CN115332102A - Semiconductor structure and method for thinning wafer - Google Patents

Semiconductor structure and method for thinning wafer Download PDF

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Publication number
CN115332102A
CN115332102A CN202210981344.XA CN202210981344A CN115332102A CN 115332102 A CN115332102 A CN 115332102A CN 202210981344 A CN202210981344 A CN 202210981344A CN 115332102 A CN115332102 A CN 115332102A
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wafer
thinning
ion implantation
atom
modified layer
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刘宇恒
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02016—Backside treatment

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  • General Physics & Mathematics (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The embodiment of the disclosure provides a semiconductor structure and a method for thinning a wafer, wherein the semiconductor structure comprises: the silicon substrate comprises a front surface and a back surface which are opposite, and the back surface of the silicon substrate is provided with a modified layer. The embodiment of the disclosure can realize at least accurate control of the thickness of the thinned wafer by thinning the silicon substrate with the modified layer.

Description

Semiconductor structure and method for thinning wafer
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a method for thinning a wafer.
Background
As integrated circuits continue to be developed to have higher density, thinner thickness, and lighter weight, wafers (wafers) are generally required to be thinned to reduce the thickness of the wafers in order to meet the development requirements.
The current wafer thinning technology comprises: grinding (grinding) process, chemical Mechanical Polishing (CMP) process, wet etching (wet etch) process, and the like. However, the above-mentioned wafer thinning technique can reduce the thickness of the wafer, but it is difficult to precisely control the thickness of the wafer.
Therefore, how to precisely control the thinned thickness of the wafer becomes an urgent problem to be solved by those skilled in the art.
Disclosure of Invention
The embodiment of the disclosure provides a semiconductor structure and a wafer thinning method, which can at least realize accurate control of wafer thinning thickness.
According to some embodiments of the present disclosure, an aspect of embodiments of the present disclosure provides a semiconductor structure, including: a silicon substrate comprising opposing front and back sides, and the back side of the silicon substrate having a modification layer.
In some embodiments, the modifying layer is doped with carbon ions or hydrogen ions, wherein the modifying layer is doped with carbon ions in a concentration range of 1 × 10 19 atom/cm 3 ～1×10 21 atom/cm 3 (ii) a Or, the modified layer is doped with hydrogen ions, and the concentration range of the hydrogen ions is 1 x 10 19 atom/cm 3 ～1×10 21 atom/cm 3 。
In some embodiments, the modifying layer has a thickness of 10nm to 100nm.
According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a method for thinning a wafer, including: providing a wafer, wherein the wafer is provided with a front surface and a back surface which are opposite; carrying out an ion implantation process on the wafer to form a modified layer in the wafer; and thinning the wafer from the back surface to the front surface to the modified layer.
In some embodiments, the performing an ion implantation process on the wafer includes: performing the ion implantation process from the front side to the back side of the wafer; after forming the modified layer, further comprising: and forming active devices and/or passive devices on the front side of the wafer.
In some embodiments, before the performing the ion implantation process on the wafer, the method further includes: forming an active device and/or a passive device on the front side of the wafer; the ion implantation process for the wafer comprises the following steps: and carrying out the ion implantation process from the back surface to the front surface.
In some embodiments, before thinning the wafer from the back side to the front side to the modified layer, the method further includes: providing a substrate; bonding the front side of the wafer to the substrate.
In some embodiments, the thinning process used to thin the wafer has a greater removal rate of the back side of the wafer than the modified layer.
In some embodiments, the hardness of the modified layer is greater than the hardness of the wafer between the modified layer and the back surface.
In some embodiments, the ions employed by the ion implantation process include carbon ions.
In some embodiments, before the ion implantation process is performed on the wafer, thinning the wafer from the back side to the front side, wherein the thinned wafer has a thickness ranging from 20um to 30um.
In some embodiments, the process parameters of the ion implantation process include: the implantation energy range is 2000 KeV-20000 KeV, and the implantation dosage range is 1 × 10 14 atom/cm 3 ～1×10 16 atom/cm 3 。
In some embodiments, the modification layer formed in the ion implantation process includes a bubble layer toward the back surface.
In some embodiments, the ions employed by the ion implantation process include hydrogen ions.
In some embodiments, the process parameters of the ion implantation process include: the implantation energy range is 2000 KeV-20000 KeV, and the implantation dosage is 1 × 10 14 atom/cm 3 ～1×10 16 atom/cm 3 。
In some embodiments, the thickness of the modified layer ranges from 10nm to 100nm, and the thickness of the thinned wafer ranges from 1um to 10um.
In some embodiments, the modification layer is doped with hydrogen ions in a concentration range of 1 × 10 19 atom/cm 3 ～1×10 21 atom/cm 3 (ii) a Or the modified layer is doped with carbon ions, and the concentration range of the carbon ions is 1 x 10 19 atom/cm 3 ～1×10 21 atom/cm 3 。
In some embodiments, the thinning process for thinning the wafer includes a chemical mechanical polishing process, and a ratio of a polishing rate of the chemical mechanical polishing process to the wafer to a polishing rate of the modification layer is greater than or equal to 3.
In some embodiments, the process parameters of the chemical mechanical polishing process include: the grinding fluid is SiO-containing 2 A grinding fluid of particles, wherein the SiO 2 The concentration range of the particles is 1 to 10 percent.
In some embodiments, the thinning process for thinning the wafer includes a wet etching process, and a ratio of an etching rate of the wet etching process to the wafer to an etching rate of the modification layer is greater than or equal to 4:1.
the technical scheme provided by the embodiment of the disclosure has at least the following advantages:
the silicon substrate is provided with the modified layer, and the modified layer is used as a terminal layer to indicate the position to which the silicon substrate needs to be thinned, so that the precision requirement on thinning of the silicon substrate can be met.
Drawings
One or more embodiments are illustrated by corresponding figures in the drawings, which are not to be construed as limiting the embodiments, unless expressly stated otherwise, and which are not to scale; in order to more clearly illustrate the embodiments of the present disclosure or technical solutions in the conventional art, the drawings required to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without inventive efforts.
Fig. 1 to fig. 3 are schematic structural diagrams corresponding to steps of a wafer thinning method;
fig. 4 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure;
fig. 5 to 11 are schematic structural diagrams corresponding to steps of a wafer thinning method according to another embodiment of the disclosure.
Detailed Description
As known from the background art, the problem that the thinning thickness of the wafer cannot be accurately controlled exists at present.
Fig. 1 to fig. 3 are schematic structural diagrams corresponding to each step of a wafer thinning method. Referring to fig. 1, a wafer 100 is provided, the wafer 100 having opposing front 101 and back 102 surfaces; performing a grinding process 11 on the back side 102 of the wafer 100 to thin the wafer 100; referring to fig. 2, performing the chemical mechanical polishing process 12 on the back side 102 of the wafer 100 further thins the wafer 100; referring to fig. 3, the wafer 100 is thinned using a wet etching process 13, i.e., the wafer 100 is thinned to a desired thickness by performing the wet etching process 13 on the backside 102 of the wafer 100.
Analysis shows that, when the wafer 100 is thinned by the grinding process 11, the chemical mechanical polishing process 12 and the wet etching process 13, the stop positions of the three processes are difficult to be precisely controlled, which results in that the thinned thickness of the wafer 100 cannot be precisely controlled, that is, the thinned thickness of the wafer 100 may not be within the required error range, and it is difficult to meet the requirement for the thinning precision of the wafer 100. Further analysis has found that the reasons why the stop positions of the three-step process are difficult to be accurately controlled include: taking the cmp process 12 as an example, the material of the wafer 100 to be removed by the cmp process 12 is the same as the material of the wafer 100 to be stopped, which results in that the removal rates of the cmp process 12 on the regions with different thicknesses of the wafer 100 are substantially the same, that is, the removal rate of the cmp process 12 on the wafer 100 to be stopped is also greater, which results in that the position of the thinning stop is difficult to be accurately controlled.
From the above analysis, if the removal rate of the wafer 100 to be thinned by the thinning process is greater than the removal rate of the wafer 100 at the thinning stop position, or the material of the wafer 100 at the thinning stop position is different from the material of the wafer 100 to be thinned, the purpose of accurately controlling the thinning stop position can be achieved, so that the thickness of the thinned wafer 100 is ensured to be within the expected range, and the thickness accuracy of the thinned wafer 100 is improved.
The embodiment of the present disclosure provides a semiconductor structure, in which a modified layer is disposed on a back surface of a silicon substrate, and the modified layer serves as a terminal layer for thinning the silicon substrate, so that a precision requirement for thinning the silicon substrate can be met.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the embodiments of the disclosure, numerous technical details are set forth in order to provide a better understanding of the disclosure. However, the claimed subject matter of the present disclosure can be practiced without these specific details and with various changes and modifications based on the following examples.
Fig. 4 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure.
Referring to fig. 4, a semiconductor structure provided in an embodiment of the present disclosure includes: a silicon substrate comprising opposing front 201 and back 202 surfaces, the back surface 202 of the silicon substrate having a modified layer 203. The modified layer 203 can be used as a grinding terminal layer, and when the silicon substrate is thinned, the silicon substrate is thinned from the back surface 202 of the silicon substrate to the modified layer 203 towards the front surface 201 of the silicon substrate, so that the requirement on the thickness reduction precision of the silicon substrate is met.
In some embodiments, the silicon substrate may be the wafer 200.
In some embodiments, the modified layer 203 is doped with carbon ions or hydrogen ions, and accordingly, the modified layer 203 is rich in carbon ions or hydrogen ions, and the doping of the carbon ions or hydrogen ions causes the property of the modified layer 203 to change, thereby ensuring that the modified layer 203 can be used as a grinding terminal layer in the thinning process, so that the thinning process can be stopped at the modified layer to control the precision of the thinning of the thickness of the silicon substrate.
Wherein, when the modified layer 203 is doped with carbon ions, the concentration range of the carbon ions is 1 × 10 19 atom/cm 3 ～1×10 21 atom/cm 3 (ii) a Alternatively, when the modified layer 203 is doped with hydrogen ions, the concentration range of the hydrogen ions is 1 × 10 19 atom/cm 3 ～1×10 21 atom/cm 3 。
In some embodiments, the thickness of the modification layer 203 is 10nm to 100nm, for example, the thickness of the modification layer 203 may be 10nm, 50nm, or 100nm.
In some embodiments, the thickness of the semiconductor structure may be 1um to 10um, for example, the thickness of the semiconductor structure may be 1um, 5um, or 10um.
Another embodiment of the present disclosure further provides a method for thinning a wafer, which provides the method for forming the semiconductor structure provided in the foregoing embodiment. The method for thinning a wafer according to the embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings, and it should be noted that the same or corresponding portions as those in the foregoing embodiment may refer to the specific description of the foregoing embodiment, and detailed description thereof will not be repeated below. Fig. 5 to 11 are schematic structural diagrams corresponding to steps of a wafer thinning method according to another embodiment of the disclosure.
Referring to fig. 5, a wafer 200 is provided, the wafer 200 having opposing front 201 and back 202 surfaces.
Wafer 200 may be Silicon, germanium, or Silicon Germanium, and wafer 200 may also be Silicon-On-Insulator (SOI), germanium-On-Insulator (GOI), and Silicon Germanium-On-Insulator (SGOI), among others.
In some embodiments, wafer 200 may be a silicon wafer.
In some embodiments, the wafer 200 is subjected to an ion implantation process to form a modified layer within the wafer 200.
In some embodiments, the wafer 200 is subjected to an ion implantation process, comprising: referring to fig. 6, an ion implantation process 21 is performed from the front side 201 to the back side 202 of the wafer 200. Referring to fig. 7, after forming the modified layer 203, the method further includes: active and/or passive devices are formed on the front side 201 of the wafer 200.
The front side 201 of the wafer 200 is a surface on which devices are to be formed, and the devices may be active devices and/or passive devices. Prior to performing the ion implantation process 21, the wafer 200 may be a bare wafer, and accordingly, the wafer 200 may be referred to as a substrate 205 (substrate). After the ion implantation process 21 is performed, a device manufacturing process is performed to form an active device and/or a passive device, where the active device may be a Transistor or a MOS Transistor (MOSFET), and the passive device may be a capacitor, a resistor, and an inductor. Specifically, a functional film layer 206 is formed on the front surface 201 of the wafer 200, and a plurality of metal wires 204 and conductive plugs electrically connecting adjacent metal wires 204 may be further formed in the functional film layer 206. In some embodiments, the functional film layer 206 may be a laminate structure including an insulating material; the metal wire 204 may be a copper wire. As such, the functional film 206 is formed after the ions are implanted from the front surface 201 so that the ion implantation process 21 does not affect the electrical performance of the devices in the functional film 206.
Compared to the solution of performing the ion implantation process 21 from the back side 202 to the front side 201, the ion implantation process 21 performed from the front side 201 to the back side 202 of the wafer 200 before the active devices and/or the passive devices are formed on the front side 201 of the wafer 200 requires a relatively shallow implantation depth, which makes the process difficulty of the ion implantation process 21 lower. By performing the ion implantation process 21 on the wafer 200, the modified layer 203 formed during the subsequent thinning process of the wafer 200 is used as a polishing end layer, which provides a basis for accurately controlling the thinned thickness of the wafer 200.
In some embodiments, the ions used in the ion implantation process 21 include carbon ions, and accordingly, the modified layer 203 is enriched with carbon ions. The hardness of the modification layer 203 can be changed by the implanted carbon ions, the hardness of the modification layer 203 is greater than the hardness of the wafer 200 between the modification layer 203 and the back surface 202, so that when the subsequent step of thinning the wafer 200 is performed, due to the difference of the hardness, the removal rate of the thinning process adopted by the thinning wafer 200 to the back surface 202 of the wafer 200 is greater than the removal rate of the modification layer 203, and the change of the removal rate can be monitored by a machine, so that the thickness of the thinned wafer 200 can be accurately controlled.
Specifically, when the ion implantation process 21 is performed using carbon ions, the process parameters of the ion implantation process 21 include: the implantation energy range is 2000KeV to 20000KeV, for example, the implantation energy can be: 2000KeV, 8000KeV or 16000KeV, and the implantation dosage is 1 × 10 14 atom/cm 3 ～1×10 16 atom/cm 3 (atoms per cubic centimeter, number of atoms contained in each cubic centimeter), the implant dose may be: 1 x 10 14 atom/cm 3 、1×10 15 atom/cm 3 Or 1X 10 16 atom/cm 3 With this arrangement, on one hand, it is ensured that the carbon ion concentration of the implanted modified layer 203 is enough to change the hardness of the modified layer 203, and on the other hand, the depth of the implanted carbon ions into the wafer 200, i.e., the position of the modified layer 203 in the wafer 200, can be controlled.
In some embodiments, the modified layer 203 is doped with carbon ions in a concentration range of 1 × 10 19 atom/cm 3 ～1×10 21 atom/cm 3 For example, the concentration of carbon ions may be 1X 10 19 atom/cm 3 、1×10 10 atom/cm 3 Or 1 × 10 21 atom/cm 3 。
In some embodiments, the ions used in the ion implantation process 21 include hydrogen ions, and accordingly, the modified layer 203 is rich in hydrogen ions. The formed modified layer 203 comprises a bubble layer facing the back surface 202, that is, the implanted hydrogen ions form a bubble layer on the surface of the modified layer 203 facing the back surface 202, and since the material of the bubble layer is different from that of the wafer 200, the machine of the bubble layer can monitor the difference, so that the bubble layer can indicate the position where thinning of the wafer 200 is stopped in the subsequent step, and the thickness of the thinned wafer 200 can be accurately controlled.
Specifically, when the ion implantation process 21 is performed by using hydrogen ions, the process parameters of the ion implantation process 21 include: the implantation energy is in the range of 2000KeV to 20000KeV, for example, 2000KeV, 8000KeV or 16000KeV, and the implantation dose is in the range of 1X 10 14 atom/cm 3 ～1×10 16 atom/cm 3 The implantation dose can be 1 × 10 14 atom/cm 3 、1×10 15 atom/cm 3 Or 1 × 10 16 atom/cm 3 With this arrangement, it is possible to ensure that hydrogen ions implanted into the modified layer 203 are sufficient to form a complete bubble layer on the surface of the modified layer 203 facing the back surface 202, and to control the depth of the hydrogen ions implanted into the modified layer 203, i.e. the position of the modified layer 203 in the wafer 200.
In some embodiments, the modification layer 203 is doped with hydrogen ions in a concentration range of 1 × 10 19 atom/cm 3 ～1×10 21 atom/cm 3 For example, hydrogen ionThe concentration of the seed may be 1X 10 19 atom/cm 3 、1×10 10 atom/cm 3 Or 1 × 10 21 atom/cm 3 。
During the ion implantation process 21, the depth and dose of the ion implantation can be controlled by the reverse implantation, so as to precisely control the thickness of the modified layer 203 and the depth of the wafer 200. In some embodiments, the thickness of the modification layer 203 ranges from 10nm to 100nm, for example, the thickness of the modification layer 203 may be: 10nm, 50nm or 100nm, so that the modified layer 203 is neither too thick nor too thin, the too thick modified layer 203 increases the process cost and the process time, and when the too thin modified layer 203 leads to a subsequent thinning process, the too thin modified layer 203 is thinned, and then the thickness of a part of the wafer 200 is continuously thinned, so that the error between the thickness of the thinned wafer 200 and the required thickness of the wafer 200 is too large, and the thickness of the thinned wafer 200 cannot be accurately controlled.
In other embodiments, before performing the ion implantation process 21 on the wafer 200, the following steps may be further included: referring to fig. 8, active and/or passive devices are formed on the front side 201 of the wafer 200; referring to fig. 9, an ion implantation process 21 is performed on the wafer 200, including: the ion implantation process 21 is performed from the back surface 202 to the front surface 201.
That is, in other embodiments, the ion implantation process 21 may be performed from the back side 202 to the front side 201, so that ions in the ion implantation process 21 may be prevented from bombarding the front side 201 of the wafer 200, thereby preventing the front side 201 of the wafer 200 from being damaged, and ions in the ion implantation process 21 may be prevented from being doped into a region between the modification layer 203 and the front side 201 of the wafer 200. It is understood that the ion implantation process 21 may be performed from the back side 202 toward the front side 201 after the active and/or passive devices are formed, or the ion implantation process 21 may be performed from the back side 202 toward the front side 201 before the active and/or passive devices are formed.
In some embodiments, before the ion implantation process 21 is performed on the wafer 200, thinning the wafer 200 from the back side 202 toward the front side 201, wherein the thinned wafer 200 may have a thickness ranging from 20um to 30um, for example, the thinned wafer 200 may have a thickness of 20um, 25um, or 30um, so that the thinner wafer 200 may reduce the difficulty of the ion implantation process 21, make the depth of the ion implantation relatively shallow, and make it easier to control the depth and dose of the ion implantation.
It is understood that in other embodiments, the ion implantation process 21 may be performed directly without thinning the wafer 200 before the ion implantation process 21 is performed.
For a detailed description of the ion implantation process 21, reference may be made to the corresponding description above, and further description thereof is omitted here.
In some embodiments, referring to fig. 10, after forming the functional film layer 206, a substrate 207 may be further provided, and the front side 201 of the wafer 202 is bonded to the substrate 207, the substrate 207 is configured to provide support for a subsequent thinning process of the wafer 200, and the substrate 207 is removed after the subsequent thinning process is completed. It is understood that the substrate 207 may also be provided with devices such as chips, i.e. the substrate 207 is a functional layer, and the substrate 207 does not need to be removed after the thinning process of the subsequent step is completed.
Specifically, the method for bonding the wafer 200 and the substrate 207 may be a wafer 200 bonding technique without an intermediate layer, a wafer 200 bonding technique with an intermediate layer, wherein the wafer 200 bonding technique without an intermediate layer may be a technique for directly bonding the wafer 200 and the substrate 207, and the wafer 200 bonding technique with an intermediate layer may be a Thermal Compression Bonding (TCB) technique or a technique for bonding by an adhesive layer.
Referring to fig. 11, the wafer 200 is thinned from the back side 202 toward the front side 201 to the modified layer 203.
In some embodiments, the thinning process 22 employed to thin the wafer 200 may be a chemical mechanical polishing process.
Specifically, the cmp process is a processing technique that combines chemical etching and mechanical removal, and global planarization (planarization) of the surface of the wafer 200 can be achieved by relative movement between the wafer 200 and the polishing head. Wherein, the ratio of the polishing rate of the chemical mechanical polishing process to the wafer 200 to the polishing rate of the modified layer 203 is greater than or equal to 3:1, the accurate thinning of the wafer 200 by the chemical mechanical polishing process can be effectively realized. The technological parameters of the chemical mechanical polishing process include: the grinding fluid is SiO-containing 2 A grinding fluid of particles in which SiO 2 The concentration of the particles is in the range of 1% to 10%, for example, siO 2 The particle concentration may be 1%, 5% or 10%, thus, siO is contained 2 The particle polishing slurry can ensure that the ratio of the polishing rate of the chemical mechanical polishing process to the wafer 200 to the polishing rate of the modified layer 203 is greater than or equal to 3:1, and the change of the polishing rate can be monitored by a CMP R2R (chemical mechanical polishing run-to-run) controller. When all the wafers 200 are removed by the chemical mechanical polishing process, i.e., the modified layer 203 is not yet encountered, the polishing speed is higher; when the CMP process is performed to polish the modified layer 203, the CMP R2R mechanism may monitor the change, so as to determine whether the CMP process is thinned to the modified layer 203, i.e., whether the CMP process needs to be finished and the precision requirement for thinning the wafer 200 is met.
In some embodiments, the thinning process 22 used to thin the wafer 200 may be a wet etch process.
Specifically, the chemical reaction between the chemical etching solution and the wafer 200 is utilized, and the wet etching process converts part of the wafer 200 into a liquid compound to be stripped off, so as to thin the wafer 200. The ratio of the etching rate of the wet etching process to the wafer 200 to the etching rate of the modification layer 203 is greater than or equal to 4:1, the accurate thinning of the wafer 200 by using the wet etching process can be effectively realized. The etching liquid adopted by the wet etching process comprises the following components: h 3 PO 4 、HNO 3 、H 2 SO 4 And mixed solution of HF or HF, HNO 3 And CH 3 A mixture of COOH. The wet etching process can determine whether the wafer 200 is thinned to the modified layer 203 or not by matching with the R2R controller, when the wafer 200 is removed by the wet etching process, namely the modified layer 203 is not touched, the etching speed is higher, and when the modified layer 203 is etched by the wet etching process, the wafer 200 is etched to have the higher etching speedThe R2R controller may monitor the change to determine whether the wet etching process has been thinned to the modification layer 203, so as to determine whether the wet etching process needs to be finished, thereby not only accurately controlling the thinned thickness of the wafer 200, but also removing contaminants, such as oil, dust, etc., on the surface of the wafer 200, and ensuring the planarization and smoothness of the surface of the wafer 200, so as to prevent the contaminants from affecting the bonding between the wafer 200 and the substrate in the subsequent step on the wafer 200.
It can also be understood that, after the thinning process 22 is performed, the modified layer 203 still remains in a partial thickness, in some embodiments, the ions used in the ion implantation process 21 are carbon ions, and accordingly, the modified layer 203 is rich in carbon ions, and since the carbon ion implantation does not cause generation of holes or electrons, performance of devices formed on the subsequent wafer 200 is not affected, and thus, removal is not needed, and process time and cost are saved; in some embodiments, the ions used in the ion implantation process 21 are hydrogen ions, and accordingly, the modified layer 203 is rich in hydrogen ions, since the hydrogen ion implantation does not cause generation of holes or electrons, and thus does not affect the performance of devices formed on the subsequent wafer 200, and the implanted hydrogen ions form a bubble layer on the surface of the modified layer 203 facing the back surface 202, the bubble layer is very easy to peel off, so that the modified layer 203 can naturally peel off without being removed.
In some embodiments, the thinned wafer 200 has a thickness of 1um to 10um, for example, the thinned wafer 200 may have a thickness of 1um, 5um, or 10um.
In some embodiments, the thinning process 22 may also be a grinding process that is performed prior to performing the chemical mechanical polishing process or the wet etching process. The grinding process has a relatively fast grinding speed compared with a chemical mechanical grinding process and a wet etching process, the grinding process can quickly thin the wafer 200 to a thinner thickness, and then the chemical mechanical grinding process or the wet etching process can accurately control the thickness of the thinned wafer 200, so that the time of the thinning process 22 is reduced, the production efficiency is improved, and the precision requirement of the thinning of the wafer 200 can be met. It is understood that in other embodiments, the wafer 200 may be directly subjected to a chemical mechanical polishing process or a wet etching process without performing a grinding process. In addition, when the thinning process 22 is a grinding process and a chemical mechanical polishing process, the grinding process and the chemical mechanical polishing process can be completed by the same machine, so that the equipment cost is reduced and the precision requirement of thinning the wafer 200 can be met.
It should be noted that, in other embodiments, the thinning process 22 may be a grinding process followed by a wet etching process, or a chemical mechanical polishing process followed by a wet etching process, or a grinding process followed by a chemical mechanical polishing process.
According to the method for thinning the wafer 200 provided by the embodiment of the disclosure, the ion implantation process 21 is performed on the wafer 200, so that the modified layer 203 is formed in the wafer 200, when the thinning process 22 is performed from the back surface 202 of the wafer 200 to the front surface 201 of the wafer 200, the modified layer 203 can serve as a terminal layer to indicate the position to which the wafer 200 needs to be thinned, the error between the thickness of the wafer 200 after the thinning process 22 and the required thickness of the wafer 200 is reduced, and the precision requirement for thinning the wafer 200 is met.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of the practice of the disclosure, and that various changes in form and detail may be made therein without departing from the spirit and scope of the disclosure. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the disclosure, and it is intended that the scope of the disclosure be limited only by the claims appended hereto.

Claims (20)

1. A semiconductor structure, comprising:
a silicon substrate comprising opposing front and back surfaces, and the back surface of the silicon substrate having a modification layer.
2. The semiconductor structure of claim 1, wherein the modifying layer is doped with dopants thereinCarbon ions or hydrogen ions are doped in the modified layer, and the concentration range of the carbon ions is 1 x 10 19 atom/cm 3 ～1×10 21 atom/cm 3 (ii) a Or, the modified layer is doped with hydrogen ions, and the concentration range of the hydrogen ions is 1 multiplied by 10 19 atom/cm 3 ～1×10 21 atom/cm 3 。
3. The semiconductor structure of claim 1, wherein the modifying layer has a thickness of 10nm to 100nm.
4. A method for thinning a wafer is characterized by comprising the following steps:
providing a wafer, wherein the wafer is provided with a front surface and a back surface which are opposite;
carrying out an ion implantation process on the wafer to form a modified layer in the wafer;
and thinning the wafer from the back surface to the front surface to the modified layer.
5. The method of claim 4, wherein the performing the ion implantation process on the wafer comprises:
performing the ion implantation process from the front side to the back side of the wafer;
after forming the modified layer, further comprising: and forming active devices and/or passive devices on the front side of the wafer.
6. The method of claim 4, wherein before the ion implantation process is performed on the wafer, the method further comprises:
forming an active device and/or a passive device on the front side of the wafer;
the ion implantation process for the wafer comprises the following steps:
the ion implantation process is performed from the back side to the front side.
7. The method of claim 5 or 6, further comprising, before thinning the wafer from the back side to the front side to the modified layer: providing a substrate; bonding the front side of the wafer to the substrate.
8. The method for thinning the wafer according to claim 4, wherein the removal rate of the back surface of the wafer by a thinning process for thinning the wafer is greater than the removal rate of the modified layer.
9. The method of claim 8, wherein the hardness of the modified layer is greater than the hardness of the wafer between the modified layer and the backside.
10. The method of claim 9, wherein the ions used in the ion implantation process comprise carbon ions.
11. The method for thinning the wafer according to claim 6, wherein before the ion implantation process is performed on the wafer, the method further comprises thinning the wafer from the back surface to the front surface, wherein the thickness of the thinned wafer ranges from 20um to 30um.
12. Method for wafer thinning according to claim 5, 10 or 11, wherein the process parameters of the ion implantation process comprise: the implantation energy range is 2000 KeV-20000 KeV, and the implantation dosage range is 1 × 10 14 atom/cm 3 ～1×10 16 atom/cm 3 。
13. The method of claim 4, wherein in the ion implantation process, the modification layer is formed to comprise a bubble layer facing the back surface.
14. The method of claim 13, wherein the ions used in the ion implantation process comprise hydrogen ions.
15. Method for wafer thinning according to claim 5, 11 or 14, wherein the process parameters of the ion implantation process comprise: the implantation energy range is 2000 KeV-20000 KeV, and the implantation dosage is 1 × 10 14 atom/cm 3 ～1×10 16 atom/cm 3 。
16. The method for thinning the wafer according to claim 4, wherein the thickness range of the modified layer is 10nm to 100nm, and the thickness of the thinned wafer is 1um to 10um.
17. The method for thinning the wafer according to claim 4, wherein the modification layer is doped with hydrogen ions, and the concentration of the hydrogen ions is in a range of 1 x 10 19 atom/cm 3 ～1×10 21 atom/cm 3 (ii) a Or the modified layer is doped with carbon ions, and the concentration range of the carbon ions is 1 x 10 19 atom/cm 3 ～1×10 21 atom/cm 3 。
18. The method for thinning the wafer according to claim 4, wherein the thinning process for thinning the wafer comprises a chemical mechanical polishing process, and the ratio of the polishing rate of the chemical mechanical polishing process to the wafer to the polishing rate of the modification layer is greater than or equal to 3.
19. The method of claim 18, wherein the process parameters of the chemical mechanical polishing process comprise: the grinding fluid is SiO-containing 2 A grinding fluid of particles, wherein the SiO 2 The concentration range of the particles is 1 to 10 percent.
20. The method for thinning the wafer according to claim 4, wherein the thinning process adopted for thinning the wafer comprises a wet etching process, and the ratio of the etching rate of the wet etching process to the wafer to the etching rate to the modification layer is greater than or equal to 4:1.
CN202210981344.XA 2022-08-16 2022-08-16 Semiconductor structure and method for thinning wafer Pending CN115332102A (en)

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