CN115331722A - Flash memory chip and programming method and testing method thereof - Google Patents

Abstract

The invention discloses a flash memory chip and a programming method and a testing method thereof. The flash memory chip comprises a controller and a flash memory array electrically connected with the controller, wherein a plurality of flash memory units in the flash memory array are arranged in an array manner; the flash memory chip further includes: a plurality of control grid lines, wherein each control grid line is connected with the first ends of a row of flash memory units; a plurality of erasing grid lines, wherein each erasing grid line is connected with the second end of one row of flash memory units; a plurality of selection grid lines, wherein each selection grid line is connected with the third ends of one row of flash memory units; the controller is used for providing a selection voltage for the ith row of flash memory units through the selection gate line, and providing a selection voltage for the jth column of flash memory units through the erasing gate line to select the flash memory units to be programmed in the ith row and jth column, and providing a preset voltage for the pth row of flash memory units through the control gate line, wherein i is more than or equal to 1, j is more than or equal to 1, p is more than or equal to 1, and p is not equal to i. The technical scheme of the embodiment of the invention can reduce the interference on the programmed flash memory unit and improve the precision of the programmed data.

Description

Flash memory chip and programming method and testing method thereof

Technical Field

The invention relates to the technical field of flash memories, in particular to a flash memory chip and a programming method and a testing method thereof.

Background

Flash Memory (Flash Memory) is a nonvolatile Memory, and has wide application range, and data cannot be lost when power is cut off.

Fig. 1 is a schematic structural diagram of a flash memory array in the prior art, and as shown in fig. 1, the flash memory array includes a plurality of flash memory units 10, and usually two rows of flash memory units 10 share one erase gate line EG, but two rows of flash memory units share one erase gate line EG, when a selected voltage is written by using the erase gate line, two rows of flash memory units 10 are selected, and one flash memory unit 10 cannot be selected independently.

In order to accurately select a certain flash memory unit, one row of flash memory units share one erasing grid line; however, when programming the selected flash memory cell, the erase gate voltage of the selected column of flash memory cells is large; therefore, during programming, certain interference exists on the programmed flash memory cells in the selected column and the unselected row, and the programmed data precision is influenced.

Disclosure of Invention

The invention provides a flash memory chip, a programming method and a testing method thereof, which are used for reducing interference on programmed flash memory units and improving the precision of programming data.

According to an aspect of the present invention, there is provided a flash memory chip including: the flash memory comprises a controller and a flash memory array electrically connected with the controller, wherein a plurality of flash memory units in the flash memory array are arranged in an array;

the flash memory chip further includes: the flash memory cell array comprises a plurality of flash memory cells, a plurality of control grid lines and a plurality of control grid lines, wherein the control grid lines extend along a first direction, the first direction is a row direction of the flash memory cell array arrangement, and each control grid line is connected with a first end of one row of the flash memory cells;

the flash memory unit array comprises a plurality of flash memory units, a plurality of erasing grid lines and a plurality of erasing grid lines, wherein the erasing grid lines extend along a second direction, the second direction is a row direction of the flash memory unit array arrangement, and each erasing grid line is connected with a second end of one row of the flash memory units;

a plurality of selection gate lines extending along the first direction, each selection gate line being connected to the third ends of a row of the flash memory cells;

the controller is used for providing a selection voltage for the flash memory units in the ith row through the selection grid line, and providing a preset voltage for the flash memory units in the pth row through the control grid line when the flash memory units in the pth row are selected by providing the selection voltage for the flash memory units in the pth column, wherein i is not less than 1, j is not less than 1, p is not less than 1, and p is not equal to i.

Optionally, the flash memory chip further comprises a plurality of drain lines and a plurality of source lines,

the plurality of source lines extend along the first direction, and each source line is connected with the fourth ends of at least one row of the flash memory units;

the plurality of drain lines extend along the second direction, and each drain line is electrically connected with a fifth end of one row of the flash memory units;

or, the plurality of drain lines extend along the first direction, and each drain line is electrically connected to the fifth end of one row of the flash memory units.

Optionally, the flash memory cell comprises a first transistor and a second transistor;

the grid electrode of the first transistor is the third end of the flash memory unit, and the drain electrode of the first transistor is the fifth end of the flash memory unit;

the control grid of the second transistor is a first end of the flash memory unit, the drain electrode of the second transistor is electrically connected with the source electrode of the first transistor, the erasing grid of the second transistor is a second end of the flash memory unit, and the source electrode of the second transistor is a fourth end of the flash memory unit; the second transistor further includes a floating gate.

Optionally, every two adjacent rows of the flash memory units form a flash memory group, each flash memory group is connected with one source line, and the source line is arranged between two rows of the flash memory units of the flash memory group;

in each flash memory group, in two flash memory units in the same column, the second transistor is arranged close to the source line, and the first transistor is arranged on one side of the source line far away from the second transistor.

Optionally, the flash memory chip further comprises a programming circuit;

the controller is electrically connected to the flash memory array through the programming circuit.

According to another aspect of the present invention, there is provided a programming method of a flash memory chip, for programming the flash memory chip according to any embodiment of the present invention, the programming method including:

providing a selection voltage for the flash memory unit in the ith row through a selection grid line, and providing a selection voltage for the flash memory unit in the jth column through an erasing grid line to select the flash memory unit to be programmed in the jth row, and providing a preset voltage for the flash memory unit in the pth row through a control grid line; wherein i is greater than or equal to 1, j is greater than or equal to 1, p is greater than or equal to 1, and p is not equal to i.

According to another aspect of the present invention, there is provided a method for testing a flash memory chip, the method for testing a flash memory chip according to any embodiment of the present invention, the method comprising:

writing an erasing voltage into the flash memory unit to be erased through the erasing grid line;

providing a selection voltage for the flash memory units in the ith row through a selection grid wire, providing a selection voltage for the flash memory units in the jth column through an erasing grid wire, selecting the flash memory units to be programmed in the jth row and the jth column, and programming the flash memory units to be programmed; wherein i is more than or equal to 1, and j is more than or equal to 1;

writing a preset voltage into a first unit to be tested through a control grid line, and determining that the flash memory chip is qualified when the parameter information of the first unit to be tested meets a first preset condition; and p is not less than 1 and is not equal to i, and the first unit to be tested is any one flash memory unit in the p-th row and the j-th column.

Optionally, a preset voltage is written into the first unit to be tested through a control gate line, and when the parameter information of the first unit to be tested meets a first preset condition, the method includes:

collecting a first initial current of the first unit to be tested, and writing a preset voltage into the first unit to be tested through a control grid line when the first initial current is smaller than a first preset current;

the method comprises the steps of collecting a first test current of a first unit to be tested, and determining that parameter information of the first unit to be tested meets a first preset condition when a difference value of the first test current and a first initial current of the first unit to be tested is within a first preset range.

Optionally, before providing the flash memory cells in the ith row with the selection voltage through the selection gate line, the method further includes:

collecting a second initial current of a second unit to be tested, and writing a preset voltage into the second unit to be tested through a control grid line when the second initial current is greater than a second preset current; the second unit to be tested is any one of the flash memory units in the p-th row and the k-th column, wherein k is more than or equal to 1, and k is not equal to j;

and collecting a second test current of the second unit to be tested, and determining that the second unit to be tested is normal when the difference value of the second test current and the second initial current is within a second difference value range.

Optionally, the parameter information of the first unit under test satisfies a first preset condition, including:

and the difference value between the erasing gate voltage and the floating gate voltage of the first unit to be tested is smaller than the tunneling threshold voltage.

According to the technical scheme of the embodiment of the invention, the flash memory unit comprises a floating gate transistor; the controller provides a selection voltage for the ith row of flash memory units through the selection gate line, and provides a preset voltage for the pth row of flash memory units through the control gate line when the selection voltage is provided for the jth column of flash memory units through the erasing gate line to select the flash memory units to be programmed in the ith row and the jth column; the voltage of the first end of the p-th row of flash memory units is coupled to the floating gates of the p-th row of flash memory units, namely, the voltage of the floating gates of the p-th row of flash memory units is increased, so that the voltage difference between the second end of the p-th row of flash memory units and the floating gates is reduced, and tunneling of the p-th row of flash memory units due to the fact that the selected voltage is written in the erasing grid lines can be avoided; therefore, the programming voltage written into the p-th row of flash memory cells can be kept, interference on the programmed flash memory cells is reduced, and the precision of programmed data is improved. The technical scheme of the embodiment of the invention solves the problem of larger interference on other programmed flash memory units when the selected voltage is written into the flash memory unit to be programmed through the erasing grid line, can avoid tunneling of the p-th row of flash memory units due to the writing of the selected voltage into the erasing grid line, reduces the interference on the programmed flash memory units and improves the precision of programmed data.

It should be understood that the statements in this section are not intended to identify key or critical features of the embodiments of the present invention, nor are they intended to limit the scope of the invention. Other features of the present invention will become apparent from the following description.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a prior art flash memory array;

fig. 2 is a schematic structural diagram of a flash memory chip according to an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of another flash memory chip according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of the structure of the jth column of flash memory cells in the pth row of FIG. 3;

FIG. 5 is a schematic diagram of the structure of the kth column of flash memory cells in the pth row of FIG. 3;

FIG. 6 is a flow chart of a programming method of a flash memory chip according to an embodiment of the present invention;

FIG. 7 is a flow chart of a method for testing a flash memory chip according to an embodiment of the present invention;

fig. 8 is a flowchart of a testing method for a flash memory chip according to another embodiment of the present invention.

Detailed Description

In order to make those skilled in the art better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 2 is a schematic structural diagram of a flash memory chip according to an embodiment of the present invention, and referring to fig. 2, the flash memory chip includes: a controller 101 and a flash memory array 102 electrically connected to the controller 101, wherein a plurality of flash memory units 1021 in the flash memory array 102 are arranged in an array; the flash memory chip further includes: a plurality of control gate lines CG ', the control gate lines CG ' extending along a first direction X, the first direction X being a row direction of the flash memory unit array 102, each control gate line CG ' being connected to a first end of a row of flash memory units 1021; a plurality of erasing gate lines EG ', the erasing gate lines EG ' extending along a second direction Y, the second direction Y being a row direction in which the flash memory unit arrays 102 are arranged, each erasing gate line EG ' being connected to a second end of one row of flash memory units 1021; a plurality of selection gate lines WL ', extending along a first direction X, each selection gate line WL' being connected to a third end of a row of flash memory units 1021; the controller 101 is configured to provide a selection voltage to the ith row of flash memory unit 1021 through the selection gate line WL ', and provide a selection voltage to the jth column of flash memory unit 1021 through the erase gate line EG ', and provide a preset voltage to the pth row of flash memory unit through the control gate line CG ', when the to-be-programmed flash memory unit in the ith row and jth column is selected, where i is greater than or equal to 1, j is greater than or equal to 1, p is greater than or equal to 1, and p is not equal to i.

The flash memory chip is, for example, a storage and computation integrated chip, that is, the flash memory chip can perform both storage and computation. The controller 101 can control the working modes of the flash memory array 102, including a calculation mode and a storage mode, when in the calculation mode, the controller 101 programs the flash memory array 102, and the calculation can be realized after the data to be processed is input into the flash memory array 102; when in the storage mode, data to be stored is input into the flash memory array 102, and the controller 101 programs the flash memory array 102 to control the flash memory array 102 to store the data. Flash memory unit 1021 includes, for example, a floating gate transistor, and the floating gate of flash memory unit 1021 can capture and store electrons, and because there is no external circuit, the electrons will not be lost even after power is off, i.e., power-off data will not be lost.

Specifically, the controller 101 may write an erase voltage to the flash memory units 1021 through erase gate lines EG', each of which may erase one column of the flash memory units 1021, to implement an erase operation. When the flash memory units to be programmed in the ith row and the jth column need to be programmed, writing a selection voltage into the flash memory units 1021 in the ith row through a selection grid line WL ', and providing a selected voltage to the flash memory units 1021 in the jth column through an erasing grid line EG', so that the flash memory units to be programmed in the ith row and the jth column are selected; the controller 101 writes a programming voltage into the selected flash memory cell to be programmed, thereby programming the flash memory cell to be programmed.

And when the ith row and the jth column of the selected flash memory cells to be programmed are selected, the voltages of the second ends of the jth column of the flash memory cells are selected voltages. Providing a preset voltage to the flash memory unit of the p-th row by controlling the grid line CG', wherein p is not equal to i, namely writing the preset voltage into the first ends of the flash memory units 1021 of the other rows except the i-th row; the voltage of the first end of the p-th row flash memory unit 1021 is coupled to the floating gate of the p-th row flash memory unit 1021, that is, the voltage of the floating gate of the p-th row flash memory unit 1021 is increased, so that the voltage difference between the second end of the p-th row flash memory unit 1021 and the floating gate is reduced, and tunneling of the p-th row flash memory unit 1021 due to the fact that the selected voltage is written in the erasing gate line EG'; therefore, the programming voltage written into the p-th row flash memory unit 1021 can be maintained, interference on the programmed flash memory unit is reduced, and the precision of the programmed data is improved.

In the technical scheme of the embodiment, the flash memory unit comprises a floating gate transistor; the controller provides a selection voltage for the ith row of flash memory cells through the selection gate line, and provides a selection voltage for the jth column of flash memory cells through the erasing gate line to select the to-be-programmed flash memory cells positioned in the jth row and the jth column of flash memory cells, and provides a preset voltage for the pth row of flash memory cells through the control gate line; the voltage of the first end of the p-th row of flash memory units is coupled to the floating gate of the p-th row of flash memory units, namely, the voltage of the floating gate of the p-th row of flash memory units is increased, so that the voltage difference between the second end of the p-th row of flash memory units and the floating gate is reduced, and tunneling of the p-th row of flash memory units due to the fact that the selected voltage is written in the erasing grid line can be avoided; therefore, the programming voltage written into the p-th row of flash memory cells can be kept, interference on the programmed flash memory cells is reduced, and the precision of the programmed data is improved. The technical scheme of the embodiment solves the problem that when the selected voltage is written into the flash memory unit to be programmed through the erasing grid line, the flash memory units programmed in other rows generate large interference, tunneling caused by the writing of the selected voltage into the erasing grid line can be avoided for the flash memory unit in the p-th row, interference on the programmed flash memory units is reduced, and the accuracy of programmed data is improved.

Fig. 3 is a schematic structural diagram of another flash memory chip according to an embodiment of the present invention, and optionally, referring to fig. 3, the flash memory chip further includes a plurality of drain lines BL 'and a plurality of source lines SL', the plurality of source lines SL 'extend along the first direction X, and each source line SL' is connected to the fourth ends of at least one row of flash memory units 1021; a plurality of drain lines BL 'extending along the second direction Y, each drain line BL' being electrically connected to a fifth terminal of one column of flash memory units 1021; alternatively, a plurality of drain lines BL 'extend along the first direction X, and each drain line BL' is electrically connected to the fifth end of one row of flash memory units 1021.

Specifically, the controller 101 may apply a programming voltage to the fourth terminal of the flash memory unit 1021 through the source line SL ', and the fifth terminal of the flash memory unit 1021 is grounded or at a low voltage through the drain line BL', and the programming voltage accelerates channel electrons to a high speed, and injects electrons into the flash memory unit 1021 by using a hot electron injection effect, thereby programming the flash memory unit 1021. The plurality of drain lines BL ' may extend along the first direction X or the second direction Y, and when the plurality of drain lines BL ' extend along the second direction Y, one row of flash memory units 1021 may share one drain line BL '; when a plurality of drain lines BL 'extend in the first direction X, one drain line BL' may be shared by one row of flash memory units 1021. Fig. 3 shows only the case where the plurality of drain lines BL' extend in the second direction Y, but the present invention is not limited thereto.

Alternatively, referring to fig. 3, the flash memory cell includes a first transistor M1 and a second transistor M2; the gate of the first transistor M1 is the third end of the flash memory unit 1021, and the drain of the first transistor M1 is the fifth end of the flash memory unit 1021; the control gate of the second transistor M2 is the first end of the flash memory unit 1021, the drain of the second transistor M2 is electrically connected to the source of the first transistor M1, the erase gate of the second transistor M2 is the second end of the flash memory unit 1021, and the source of the second transistor M2 is the fourth end of the flash memory unit 1021; the second transistor M2 further comprises a floating gate FG.

Specifically, the gate of the first transistor M1 is the third end of the flash memory unit 1021, i.e. the select gate WL of the flash memory unit; the drain of the first transistor M1 is the fifth terminal of the flash memory unit 1021, i.e. the drain BL of the flash memory unit 1021; the control gate of the second transistor M2 is a first end of the flash memory unit 1021, i.e., the control gate CG of the flash memory unit 1021, and the erase gate of the second transistor M2 is a second end of the flash memory unit 1021, i.e., the erase gate EG of the flash memory unit 1021; the source of the second transistor M2 is the fourth terminal of the flash memory cell 1021, i.e. the source SL of the flash memory cell. When the flash memory cell to be programmed in the ith row and the jth column is selected, the voltages of the erase gates EG of the flash memory cells in the jth column are selected voltages. Providing a preset voltage to the flash memory units in the p-th row through the control grid line CG', wherein p is not equal to i, namely writing the preset voltage into the control grid CG of the flash memory units 1021 in the other rows except the i-th row; the voltage of the control gate CG of the flash memory unit 1021 in the p-th row is coupled to the floating gate FG of the flash memory unit 1021 in the p-th row, that is, the floating gate voltage of the flash memory unit 1021 in the p-th row is increased, so that the voltage difference between the erasing gate EG and the floating gate FG of the flash memory unit 1021 in the p-th row is reduced, and tunneling of the flash memory unit 1021 in the p-th row due to the fact that the selected voltage is written in the erasing gate EG' can be avoided; therefore, the programming voltage written into the p-th row of flash memory cells 1021 can be maintained, interference on the programmed flash memory cells is reduced, and the accuracy of the programmed data is improved.

Fig. 4 is a schematic structural diagram of the jth column and the pth row of the flash memory cells in fig. 3, optionally, referring to fig. 4, the jth column and the pth row of the flash memory cells are flash memory cells in a selected column and an unselected row, and the voltage of the erase gate EG of the jth column and the pth row of the flash memory cells is a selected voltage, which is about 3.5V to 5V, and may be other values; the voltage of the control gate CG of the jth row and jth column of flash memory cells is a preset voltage, for example, 2.5V-5V, or other values, and may be specifically determined according to actual conditions; the voltage of the drain BL of the jth column flash memory unit in the pth row is, for example, 0.5V; then, the voltage Vfg1= Veg1 × CReg1+ Vcg1 × CRcg1+ Vwl1 × CRwl1+ Vsl1 × CRsl1+ Qfg1/Ctot _ FG1 of the floating gate FG of the jth flash memory cell in the pth row and jth column, where Veg1 is the erase gate voltage of the jth flash memory cell in the pth row and jth column, CReg1 is the coupling capacitance ratio of the erase gate to the floating gate of the jth flash memory cell in the pth row and jth column, vcg1 is the control gate voltage of the jth flash memory cell in the pth row and jth column, CRcg1 is the coupling capacitance ratio of the control gate to the floating gate of the jth flash memory cell in the pth row and jth column, vwl1 is the coupling capacitance ratio of the selection gate to the jth column, vsl1 is the source voltage of the jth column, source voltage of the jth flash memory cell in the pth row and jth column, and the floating gate charge ratio of the jth flash memory cell in the pth row and jth column, where the floating gate is the sum of the charge of the jth row and jth flash memory cell in the pth row and jth column. For example, veg1=4.5V, vcg1=5V, vfg1=4.5V 0.22+ Vcg 0.4+ Qfg1/Ctot _ fg1, then Vfg1 is about 2.5V-3.5V, and the voltage difference between Vfg1 and Veg1 is about 1V-2V; the voltage difference between the floating gate FG of the jth row and jth column of flash memory cells and the erase gate EG is small, and tunneling does not occur, so that the program voltage written into the pth row of flash memory cells 1021 can be maintained, interference to the programmed flash memory cells is reduced, and the precision of programmed data is improved.

Fig. 5 is a schematic structural diagram of the pth row and kt column flash memory cells in fig. 3, and optionally, referring to fig. 5, the pth row and kt column flash memory cells are flash memory cells in unselected rows and unselected columns; the voltage Veg2 of an erasing grid EG of the flash memory unit of the kth row and the kth column is 0V; the voltage Vcg2 of the control gate CG of the kth column flash memory cell in the pth row is a preset voltage, for example, 2.5V to 5V, or other values, and may be specifically determined according to actual conditions; the voltage of the drain BL of the kth column flash memory cell in the pth row is, for example, 0V or a power supply voltage Vdd, which can be specifically determined according to an actual situation; voltage Vfg2= Vcg2 × 0.4+ Qfg2/Ctot _ FG2 of floating gate FG of the kth column flash memory cell in the pth row, qfg2 being the charge programmed and stored in the floating gate of the kth column flash memory cell in the pth row, ctot _ FG2 being the sum of the capacitances of the floating gates of the kth column flash memory cells in the pth row. When the flash memory cell is in an erased state, taking Vcg2=4.5V as an example, and Vfg2 is about 1.8V-3V, the difference between Veg2 and Vfg2 is small, and no tunneling occurs in the kth column flash memory cell in the pth row; when the flash memory cell is in a programmed state, for example, vcg2=4.5V, vfg2 is about 0V-1.8V, and the difference between Veg2 and Vfg2 is small, the kth column flash memory cell in the p-th row will not tunnel. Therefore, when the preset voltage is written into the flash memory unit in the p-th row through the control gate line CG', the flash memory units in other columns are not affected, and interference on the flash memory unit in the p-th row and the k-th column is not generated.

It should be noted that fig. 4 and fig. 5 both show schematic structural diagrams of flash memory cells, so the structures of fig. 4 and fig. 5 are the same, but fig. 4 shows any flash memory cell in the jth row and column, fig. 5 shows any flash memory cell in the kth row and column, and the voltage conditions of the jth column flash memory cell in the pth row and column are different from those of the kth row and column.

Alternatively, referring to fig. 3, every two adjacent rows of flash memory units 1021 form a flash memory group 103, each flash memory group 103 is connected to a source line SL ', and the source line SL' is disposed between two rows of flash memory units 1021 in the flash memory group 103; in each flash memory group 103, in two flash memory units 1021 in the same column, the second transistor M2 is disposed near the source line SL ', and the first transistor M1 is disposed on the side of the source line SL' far from the second transistor M2.

Specifically, each flash memory group 103 is connected to one source line SL ', that is, each adjacent two rows of flash memory units 1021 share one source line SL ', so that the number of source lines SL ' can be reduced, and thus the number of wires in the flash memory chip is reduced, which is beneficial to reducing the volume of the flash memory chip. In addition, in the two flash memory units 1021 in the same column, the second transistor M2 is disposed close to the source line SL', so that the source electrodes of the two second transistors M2 can be connected conveniently, and the wiring is convenient.

Optionally, referring to fig. 3, the flash memory chip further includes a programming circuit 104; controller 101 is electrically coupled to flash array 102 through programming circuitry 104.

Specifically, the programming circuit 104 may write a programming voltage to the source line SL ' and the control gate line CG ' and an erasing voltage to the erasing gate line EG ', according to a control instruction of the controller 101, so as to write the programming voltage or the erasing voltage to the flash memory array 102, thereby implementing a programming or erasing operation on the flash memory array 102. The controller 101 may also write a preset voltage to the control gate line CG 'through the programming circuit 104, thereby writing a preset voltage to the control gate CG of the flash memory unit 1021 through the control gate line CG'.

Fig. 6 is a flowchart of a programming method of a flash memory chip according to an embodiment of the present invention, and referring to fig. 2 and 6, the programming method of the flash memory chip includes:

s210, providing a selection voltage for the ith row of flash memory cells through a selection grid line, and providing a preset voltage for the pth row of flash memory cells through a control grid line when the jth row of flash memory cells is selected by providing the selection voltage for the jth column of flash memory cells through an erasing grid line; wherein i is greater than or equal to 1, j is greater than or equal to 1, p is greater than or equal to 1, and p is not equal to i.

Specifically, when the flash memory unit to be programmed in the ith row and the jth column needs to be programmed, a selection voltage is written into the flash memory unit 1021 in the ith row through a selection gate line WL ', and a selected voltage is provided for the flash memory unit 1021 in the jth column through an erasing gate line EG', so that the flash memory unit to be programmed in the ith row and the jth column is selected; the controller 101 writes a programming voltage into the selected flash memory cell to be programmed, thereby programming the flash memory cell to be programmed. And when the ith row and the jth column of the selected flash memory cells to be programmed are selected, the voltages of the second ends of the jth column of the flash memory cells are selected voltages. Providing a preset voltage to the flash memory unit in the p-th row through a control grid line CG', wherein p is not equal to i, namely writing the preset voltage into the first ends of the flash memory units 1021 in the other rows except the i-th row; the voltage of the first end of the p-th row flash memory unit 1021 is coupled to the floating gate of the p-th row flash memory unit 1021, that is, the voltage of the floating gate of the p-th row flash memory unit 1021 is increased, so that the voltage difference between the second end of the p-th row flash memory unit 1021 and the floating gate is reduced, and tunneling of the p-th row flash memory unit 1021 due to the fact that the erasing gate line EG' is written with a selected voltage can be avoided; therefore, the programming voltage written into the p-th row of flash memory cells 1021 can be maintained, interference on the programmed flash memory cells is reduced, and the accuracy of the programmed data is improved.

Fig. 7 is a flowchart of a method for testing a flash memory chip according to an embodiment of the present invention, and referring to fig. 2 and fig. 7, the method for testing a flash memory chip includes:

s310, writing an erasing voltage into the flash memory unit to be erased through the erasing grid line.

Specifically, the flash memory units to be erased are, for example, all flash memory units 1021 in the flash memory array 102, and the controller 101 writes an erase voltage to the flash memory units to be erased through the erase gate line EG', that is, performs an erase operation on the entire flash memory array, so as to facilitate the operation, where the erase voltage is, for example, a voltage greater than 10V, and may also be other voltage values, thereby implementing the erase operation; testing of the flash memory chip is performed in the background of the entire flash memory array being erased.

S320, providing a selection voltage for the ith row of flash memory units through the selection grid line, providing a selection voltage for the jth column of flash memory units through the erasing grid line, selecting the to-be-programmed flash memory unit positioned in the jth row of the ith row, and programming the to-be-programmed flash memory unit; wherein i is more than or equal to 1 and j is more than or equal to 1.

Specifically, the controller 101 writes a selection voltage to the ith row of flash memory unit 1021 through the selection gate line WL ', and supplies a selected voltage to the jth column of flash memory unit 1021 through the erase gate line EG', so as to select the ith row and jth column of flash memory unit to be programmed; the controller 101 writes a programming voltage into the selected flash memory cell to be programmed, thereby programming the flash memory cell to be programmed.

S330, writing a preset voltage into the first unit to be tested through the control grid wire, and determining that the flash memory chip is qualified when the parameter information of the first unit to be tested meets a first preset condition; wherein p is not less than 1, p is not equal to i, and the first unit to be tested is any flash memory unit in the p-th row and the j-th column.

Specifically, the controller 101 provides a preset voltage to the flash memory unit in the p-th row by controlling the gate line CG', where p is not equal to i, that is, the preset voltage is written to the first ends of the flash memory units 1021 in the remaining rows except the i-th row, so as to write the preset voltage to the first unit under test; the voltage of the first end of the flash memory unit 1021 in the p-th row is coupled to the floating gate of the flash memory unit 1021 in the p-th row, that is, the voltage of the floating gate of the flash memory unit 1021 in the p-th row is increased, so that the voltage difference between the second end of the flash memory unit 1021 in the p-th row and the floating gate is reduced, and tunneling of the flash memory unit 1021 in the p-th row due to the writing of the selected voltage into the erase gate line EG'. The method comprises the steps of collecting parameter information of a first unit to be tested, wherein the parameter information comprises voltage information and current information, and when the parameter information of the first unit to be tested meets a first preset condition, for example, the voltage difference between a second end of the first unit to be tested and a floating gate is small, or the current of the first unit to be tested meets a requirement, namely the first unit to be tested does not generate tunneling, the flash memory chip can be determined to be qualified.

On the basis of the above technical solution, the parameter information of the first unit to be measured satisfies a first preset condition, including:

the difference between the erase gate voltage and the floating gate voltage of the first cell under test is less than the tunneling threshold voltage.

Specifically, referring to fig. 3, when the difference between the erase gate voltage and the floating gate voltage of the first to-be-detected unit is smaller than the tunneling threshold voltage, the first to-be-detected unit does not generate the tunneling effect and does not interfere with the programmed data, and then the voltage of the first to-be-detected unit meets the requirement, and the parameter information of the first to-be-detected unit meets the first preset condition.

Optionally, in some other embodiments, after step S310, the flash memory cells in the entire flash memory array may be programmed, then the preset voltage is written into the flash memory cells of the entire flash memory array, and then whether the flash memory chip is qualified is determined according to the parameter information of all the flash memory cells, which may facilitate operation, reduce detection time, and improve test efficiency.

Fig. 8 is a flowchart of a testing method of a flash memory chip according to an embodiment of the present invention, and optionally, referring to fig. 3 and 8, the testing method of a flash memory chip includes:

s410, writing an erasing voltage into the flash memory unit to be erased through the erasing grid line.

S420, collecting a second initial current of a second unit to be tested, and writing a preset voltage into the second unit to be tested through a control grid line when the second initial current is greater than a second preset current; the second unit to be tested is any flash memory unit in the p-th row and the k-th column, wherein k is larger than or equal to 1, and k is not equal to j.

Specifically, the second unit under test is any flash memory cell in the p-th row and the k-th column, that is, a flash memory cell in a different row and a different column from the selected unit under test to be programmed. Because the erasing operation is performed, the electrons of the flash memory unit 1021 are less, that is, the current of the flash memory unit 1021 is larger, if the second initial current is smaller than or equal to the second preset current, it indicates that the second initial current of the second unit to be tested is too small, and the flash memory chip may be abnormal, and the abnormal flash memory chip can be selected; if the second initial current is larger than the second preset current, the flash memory chip is further tested, and the preset voltage is written into the second unit to be tested through the control grid line CG', so that the interference test is carried out on the second unit to be tested.

S430, collecting a second test current of the second unit to be tested, and determining that the second unit to be tested is normal when the difference value between the second test current and the second initial current is within a second difference value range.

Specifically, after a preset voltage is written into the second unit to be tested through the control gate line CG', the current of the second unit to be tested changes, and if the difference between the second test current and the second initial current is within a second difference range, it indicates that the current change of the second unit to be tested is normal, and tunneling does not occur in the pth row and kth column flash memory units; therefore, when the preset voltage is written into the flash memory unit in the p-th row through the control gate line CG', the flash memory units in other columns are not affected, and no interference is generated on the flash memory units in the k-th row and the k-th column.

If the difference value between the second test current and the second initial current is not within the second difference value range, the second unit to be tested may be abnormal, and the abnormal flash memory chip can be selected.

S440, providing a selection voltage for the ith row of flash memory units through the selection grid line, providing a selection voltage for the jth column of flash memory units through the erasing grid line, selecting the to-be-programmed flash memory unit positioned in the jth row of the ith row, and programming the to-be-programmed flash memory unit; wherein i is more than or equal to 1 and j is more than or equal to 1.

S450, collecting a first initial current of the first unit to be tested, and writing a preset voltage into the first unit to be tested through the control grid line when the first initial current is smaller than a first preset current.

Specifically, because the programming operation is performed, the current of the first to-be-tested unit is small, and if the first initial current is greater than or equal to the first preset current, the first initial current of the first to-be-tested unit is too large, the first to-be-tested unit may be abnormal, and an abnormal flash memory chip can be selected; if the first initial current is smaller than the first preset current, the current of the first unit to be tested is normal; a preset voltage is written into the first unit to be tested through the control grid line CG', and interference testing is conducted on the first unit to be tested.

S460, collecting a first test current of the first unit to be tested, and determining that the parameter information of the first unit to be tested meets a first preset condition and the flash memory chip is qualified when the difference value of the first test current and the first initial current of the first unit to be tested is in a first preset range.

Specifically, after a preset voltage is written into the first unit to be tested through the control gate line CG', the current of the first unit to be tested changes, and if the difference between the first test current and the first initial current of the first unit to be tested is not within a first preset range, the first unit to be tested may be interfered, and if the first unit to be tested is abnormal, an abnormal flash memory chip may be selected; if the difference value between the first test current and the first initial current of the first unit to be tested is within a first preset range, the current change of the first unit to be tested is normal, and the flash memory chip can be determined to be qualified.

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present invention may be executed in parallel, sequentially, or in different orders, and are not limited herein as long as the desired result of the technical solution of the present invention can be achieved.

The above-described embodiments should not be construed as limiting the scope of the invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A flash memory chip, comprising: the flash memory comprises a controller and a flash memory array electrically connected with the controller, wherein a plurality of flash memory units in the flash memory array are arranged in an array;

the flash memory chip further includes: the flash memory cell array comprises a plurality of flash memory cells, a plurality of control grid lines and a plurality of control grid lines, wherein the control grid lines extend along a first direction, the first direction is a row direction of the flash memory cell array arrangement, and each control grid line is connected with a first end of one row of the flash memory cells;

the flash memory unit array comprises a plurality of flash memory units, a plurality of erasing grid lines and a plurality of erasing grid lines, wherein the erasing grid lines extend along a second direction, the second direction is a row direction of the flash memory unit array arrangement, and each erasing grid line is connected with a second end of one row of the flash memory units;

a plurality of selection grid lines extending along the first direction, wherein each selection grid line is connected with the third ends of a row of flash memory units;

the controller is used for providing a selection voltage for the flash memory units in the ith row through the selection grid line, and providing a preset voltage for the flash memory units in the pth row through the control grid line when the flash memory units in the pth row are selected by providing the selection voltage for the flash memory units in the pth column, wherein i is not less than 1, j is not less than 1, p is not less than 1, and p is not equal to i.

2. The flash memory chip of claim 1, further comprising a plurality of drain lines and a plurality of source lines,

the source lines extend along the first direction, and each source line is connected with the fourth ends of at least one row of the flash memory units;

the plurality of drain lines extend along the second direction, and each drain line is electrically connected with the fifth end of one column of the flash memory units;

or, the plurality of drain lines extend along the first direction, and each drain line is electrically connected to the fifth end of one row of the flash memory cells.

3. The flash memory chip of claim 2, wherein the flash memory cell comprises a first transistor and a second transistor;

the grid electrode of the first transistor is a third end of the flash memory unit, and the drain electrode of the first transistor is a fifth end of the flash memory unit;

the control gate of the second transistor is the first end of the flash memory unit, the drain of the second transistor is electrically connected with the source of the first transistor, the erasing gate of the second transistor is the second end of the flash memory unit, and the source of the second transistor is the fourth end of the flash memory unit; the second transistor further includes a floating gate.

4. The flash memory chip of claim 3 wherein every two adjacent rows of said flash memory cells form a flash memory group, each said flash memory group being connected to a said source line, said source line being disposed between two rows of flash memory cells of said flash memory group;

in each flash memory group, in two flash memory units in the same column, the second transistor is arranged close to the source line, and the first transistor is arranged on one side of the source line far away from the second transistor.

5. The flash memory chip of claim 1, further comprising a programming circuit;

the controller is electrically connected to the flash memory array through the programming circuit.

6. A programming method of a flash memory chip for programming the flash memory chip of any one of claims 1 to 5, the programming method comprising:

providing a selection voltage for the ith row of flash memory cells through a selection gate line, and providing a selection voltage for the jth column of flash memory cells through an erasing gate line to select the flash memory cells to be programmed in the jth row and the jth column of flash memory cells, and providing a preset voltage for the jth row of flash memory cells through a control gate line; wherein i is greater than or equal to 1, j is greater than or equal to 1, p is greater than or equal to 1, and p is not equal to i.

7. A method for testing a flash memory chip, for testing the flash memory chip of any one of claims 1-5, the method comprising:

writing an erasing voltage into the flash memory unit to be erased through the erasing grid line;

providing a selection voltage for the flash memory unit in the ith row through a selection grid line, providing a selection voltage for the flash memory unit in the jth column through the erasing grid line, selecting the flash memory unit to be programmed in the jth row of the ith row, and programming the flash memory unit to be programmed; wherein i is more than or equal to 1, and j is more than or equal to 1;

writing a preset voltage into a first unit to be tested through a control grid wire, and determining that the flash memory chip is qualified when the parameter information of the first unit to be tested meets a first preset condition; and p is not less than 1 and is not equal to i, and the first unit to be tested is any one flash memory unit in the p-th row and the j-th column.

8. The method of claim 7, wherein writing a predetermined voltage to the first unit under test through the control gate line, and when the parameter information of the first unit under test satisfies a first predetermined condition, the method comprises:

collecting a first initial current of the first unit to be tested, and writing a preset voltage into the first unit to be tested through a control grid line when the first initial current is smaller than a first preset current;

the method comprises the steps of collecting a first test current of a first unit to be tested, and determining that parameter information of the first unit to be tested meets a first preset condition when a difference value of the first test current and a first initial current of the first unit to be tested is within a first preset range.

9. The method of testing a flash memory chip of claim 7,

before providing the flash memory cells in the ith row with the selection voltage through the selection gate line, the method further comprises:

collecting a second initial current of a second unit to be tested, and writing a preset voltage into the second unit to be tested through a control grid line when the second initial current is greater than a second preset current; the second unit to be tested is any one of the flash memory units in the p-th row and the k-th column, wherein k is more than or equal to 1, and k is not equal to j;

and collecting a second test current of the second unit to be tested, and determining that the second unit to be tested is normal when the difference value of the second test current and the second initial current is within a second difference value range.

10. The method of claim 7, wherein the parameter information of the first unit under test satisfies a first predetermined condition, and the method comprises:

and the difference value between the erasing gate voltage and the floating gate voltage of the first unit to be tested is smaller than the tunneling threshold voltage.

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