CN115328690A

CN115328690A - Exception handling method, computer readable medium and electronic device

Info

Publication number: CN115328690A
Application number: CN202211250844.2A
Authority: CN
Inventors: 张毅
Original assignee: Hangzhou Denglin Hanhai Technology Co ltd; Beijing Denglin Technology Co ltd
Current assignee: Hangzhou Denglin Hanhai Technology Co ltd; Beijing Denglin Technology Co ltd
Priority date: 2022-10-13
Filing date: 2022-10-13
Publication date: 2022-11-11
Anticipated expiration: 2042-10-13
Also published as: CN115328690B

Abstract

The invention provides an exception handling method, a computer readable medium and an electronic device. The exception handling method comprises the following steps: in response to detecting an exception while executing a first instruction in a current program, aborting execution of the first instruction, storing a location of the first instruction, and jumping to execute an exception handler corresponding to the exception; fetching a second instruction during execution of the exception handler, wherein the second instruction is for execution in place of the first instruction; executing a second instruction in response to the exception handler ending execution; and responding to the second instruction ending execution, executing the next instruction of the first instruction in the current program so as to continue the execution of the current program. The method and the device are used for improving the efficiency of exception handling, and are particularly suitable for the multi-core processor to carry out exception handling.

Description

Exception handling method, computer readable medium and electronic device

Technical Field

The present invention relates to the field of exception handling technologies, and in particular, to an exception handling method, a computer readable medium, and an electronic device.

Background

When an exception (exception) occurs, the normal execution flow of the processor is stopped, so that the processor transfers to execute a corresponding exception handler, and there are many cases of the exception, which may be internal causes or external causes, and each case has a corresponding exception handling mode.

Some exception types need to be handled by way of an interrupt, an internal interrupt being one type of interrupt that indicates that the processor has encountered an error condition during execution of an instruction. The processor detects whether an exception occurs when executing each instruction, if a certain exception occurs, the execution of the current program is stopped to process the exception, and after the exception is processed, the interrupted program before the exception occurs is recovered.

Exceptions may include faults (faults), traps (traps), and terminations (aborts). When a processor encounters a fault (such as divide by zero, page fault, overflow, etc.), it may correct in the corresponding exception handler and re-execute the faulted instruction after the exception handler has been executed so that no further errors occur. The trap is mainly used for providing a system call interface for a user mode program so as to execute some high-priority operations by an operating system; in addition, the trap is also used for the purpose of debugging programs, such as replacing an original instruction with a breakpoint interrupt instruction, when the processor executes the breakpoint interrupt instruction, turning to execute a corresponding debugging program and replacing the breakpoint interrupt instruction with the original instruction, and returning to execute the original instruction after the execution of the debugging program. Termination is used primarily to indicate unrecoverable errors, such as double failures, and the like, and upon detection of such an exception, the current program is typically terminated.

With the widespread use of multi-core processors, when a fault or trap type exception is encountered, such as when a breakpoint interrupt instruction for a debugger is detected, if one core of the multi-core processor has replaced the breakpoint interrupt instruction back to the original instruction, some problems may be caused in the execution of the instruction by other cores. To solve these problems, additional operations are required to achieve normal operation of the program, resulting in cumbersome and inefficient operation of the program.

Disclosure of Invention

To overcome the above problems in the prior art, one aspect of the present invention provides an exception handling method, including: in response to detecting an exception while executing a first instruction in a current program, aborting execution of the first instruction, storing a location of the first instruction, and jumping to execute an exception handler corresponding to the exception; fetching a second instruction during execution of the exception handler, wherein the second instruction is for execution in place of the first instruction; executing a second instruction in response to the exception handler ending execution; and responding to the second instruction ending execution, executing the next instruction of the first instruction in the current program so as to continue the execution of the current program.

In the above method, a second instruction (hereinafter referred to as a shadow instruction) for execution in place of the first instruction in which the exception occurred when returning from the exception handler to the current program is acquired during execution of the exception handler without replacing the first instruction in which the exception occurred in the current program. For example, in the case of setting a breakpoint interruption instruction to debug the current program, the breakpoint interruption instruction does not need to be replaced in the current program by the original instruction, so that the normal execution of the current program is realized by avoiding adding extra operations. The method can improve the efficiency of exception handling without influencing the continuous execution of the current program, and is particularly suitable for the multi-core processor to carry out exception handling.

The above method may further comprise: setting a first register for storing flag bit information indicating whether to execute a first instruction in place of a second instruction; and setting a second register for storing the second instruction. The registers have very high read-write speed, so that data transmission between the registers is very fast, and the efficiency of exception handling can be improved by setting the first register and the second register to respectively store the zone bit information and the second instruction.

In the above method, the obtaining the second instruction during the execution of the exception handler includes: during the execution of an exception handling program, acquiring a preset instruction corresponding to the exception or acquiring an instruction provided by a user as a second instruction; and setting flag bit information in the first register to indicate that the first instruction needs to be executed in place of the second instruction, and storing the second instruction in the second register.

The above method may further comprise: a plurality of instructions corresponding to the exceptions are preset. And acquiring a preset instruction corresponding to the exception comprises: and selecting from a plurality of instructions corresponding to the exception according to a preset rule. The corresponding plurality of instructions are preset for the exception, so that the selection range of the second instruction (executed instead of the first instruction with the exception), for example, can be wider, and the second instruction can be flexibly selected according to actual requirements.

In the above method, executing the second instruction in response to the exception handler ending execution includes: reading flag bit information in a first register in response to the exception handler ending execution; reading a second instruction in a second register in response to the flag bit information indicating that execution of the first instruction in place of the second instruction is required; and executing the second instruction.

The above method may further comprise: in response to the second instruction ending execution, flag bit information in the first register is set to indicate that execution does not require replacement of the first instruction with the second instruction, and the second instruction in the second register is cleared.

The above method may further comprise: in response to the exception handler ending execution, a location of the first instruction stored in response to detecting the exception is retrieved, the location of the first instruction is stored in the program counter register, and the second instruction is stored in the instruction register for execution of the second instruction in the instruction register.

In the above method, executing the next instruction of the first instruction in the current program in response to the second instruction ending execution includes: responding to the end of execution of the second instruction, and enabling the program counter register to execute addition calculation to obtain the position of the next instruction of the first instruction in the current program; enabling the instruction register to read a next instruction of the first instruction in the current program according to the position in the program counter register and store the next instruction; and executing the next instruction of the first instruction in the current program in the instruction register.

The method can smoothly return to the current program from the exception handling program to continue the execution of the current program by executing some simple operations on the first and second registers, the program counter register and the instruction register, thereby improving the efficiency of exception handling.

Another aspect of the present invention provides a computer readable medium having stored thereon a computer program for implementing the above-described exception handling method when executed by a processor.

Another aspect of the invention provides an electronic device comprising a processor and a memory, the memory having stored thereon a computer program and the memory being coupled to the processor, the computer program being adapted to, when executed by the processor, cause the electronic device to carry out the above-mentioned exception handling method.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention, in which:

FIG. 1 schematically illustrates a flow diagram of an exception handling method according to one embodiment of the present invention;

fig. 2a-2e schematically show a specific example of exception handling based on the embodiment of the method shown in fig. 1.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail by embodiments with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

One aspect of the present invention provides an exception handling method for handling fault and trap type exceptions.

Referring now to FIG. 1, a flow diagram schematically illustrating an exception handling method according to one embodiment of the present invention, which is suitable for execution in a single-core, multi-core processor such as a CPU, GPU, includes the following steps S11-S16:

and S11, setting two special registers, namely a first register and a second register. The first register is a SHADOW ENABLE (SHADOW _ ENABLE) register, and the second register is a SHADOW instruction (SHADOW _ INST) register, and the SHADOW instruction register and the SHADOW ENABLE register are respectively used for storing flag bit information and a SHADOW instruction.

The SHADOW _ ENABLE register and the SHADOW _ INST register may be formed by a combination of a plurality of flip-flops having a storage function, and the register formed by the combination of the plurality of flip-flops can store a multi-bit binary code. It should be understood that either the flag bit information or the shadow instruction may be represented in a multi-bit binary code. Registers typically have very high read and write speeds, so data transfers between registers are very fast. By setting the SHADOW _ ENABLE register and the SHADOW _ INST register to respectively store the flag bit information and the SHADOW instruction, the efficiency of exception handling can be effectively improved.

The flag information is used to indicate whether to execute the SHADOW instruction stored in the SHADOW _ INST register instead of the instruction at the return position in the current program (i.e., the instruction in which the exception occurs, or the first instruction) when returning from the exception handler to the current program (i.e., jumping to the program that is being executed before the exception handler), and the initial value of the flag information is false. A shadow instruction (or second instruction) refers to an instruction that is fetched during execution of an exception handler and is executable by a processor to be executed in place of an instruction at a return position in a current program (i.e., an instruction that is excepted, or first instruction).

And step S12, executing the current program.

During execution of the current program, a Program Counter (PC) register in the processor calculates the location of the instruction to be executed in the current program, which points to the address in memory (e.g., memory, external storage, etc.) of the instruction to be executed; an instruction in processor (INST) register is used to read an instruction to be executed from memory based on a location stored in a PC register and store the instruction for execution by the processor.

Alternatively, the initial value of the PC register may be 0. The PC register will increment a count as instructions are executed during execution of the current program, which points to the address in memory of the instruction to be executed. The PC registers and the INST registers of the present invention may employ any existing PC registers and INST registers.

Step S13, in response to detecting an exception when executing a certain instruction in the current program, obtaining an instruction (first instruction) that has an exception, stopping the execution of the instruction that has an exception, storing the location of the instruction that has an exception (as described above, the location is a return location in the current program, which points to the address of the instruction that has an exception in the memory), and jumping to execute the exception handler corresponding to the detected exception.

In the execution process of the current program, when a processor detects an exception when executing a certain instruction, the execution flow of the current program is stopped, namely the execution of the instruction with the exception is stopped; subsequently, the processor stores the position of the instruction in which the exception occurred (i.e., the position in which the first instruction is stored) in an ERROR program counter (ERROR _ PC) register, and determines an exception handler corresponding to the detected exception from an Interrupt Descriptor (IDT) table, thereby jumping to execute the exception handler. Wherein, the ERROR _ PC register may be composed of a plurality of flip-flops having a storage function for storing a multi-bit binary code, and a position of the instruction in which the exception occurs may be represented by the multi-bit binary code; the IDT table associates specific exception types with their handling procedures, which are typically indexed by interrupt vector number, and looks up the corresponding exception handler based on the interrupt vector number of the various exceptions.

Specifically, the process of determining an exception handler includes: looking up the ID (interrupt vector number, usually in the range of 0-255) of the detected exception in the IDT table, then loading the base address of the IDT table, and simultaneously reading the corresponding table entry of the ID, wherein the processor can determine the exception handler by the section selector of the gate descriptor of the corresponding table entry; in addition, the process of jumping to execute the exception handler includes: the PC register in the processor stores the location of the first instruction in the exception handler, which points to the address in memory of the first instruction in the exception handler, and the INST register in the processor reads the first instruction in the exception handler from memory according to the location stored in the PC register and stores the instruction, which the processor can then execute, i.e. start executing the exception handler.

When a plurality of exceptions are detected, the exception handler corresponding to the exception with the highest priority can be executed according to the preset priority jump, and other exceptions are hung from high to low according to the priority, or even some exceptions with lower priorities can be discarded. For example, the priority of the exception of the fault type may be set to be higher than the priority of the exception of the trap type, and when the exceptions of the fault type and the trap type are detected simultaneously, the processor may jump to execute the exception handler corresponding to the exception of the fault type according to the priority, and then jump to execute the exception handler corresponding to the exception of the trap type. In addition, when the exception handling program is executed, if the exception with higher priority needs to be processed, the currently executed exception handling program is interrupted, the exception with higher priority is processed, and the interrupted exception handling program is returned to continue to execute after the exception with higher priority is processed.

In some application scenarios, many programs continuously query whether an exception occurs through a main loop program, and then process corresponding exceptions and interrupts, but in some embedded systems, because such a main loop program does not exist, the system function is usually driven by an interrupt code, when an exception or an interrupt occurs, a processor executes a corresponding function, a complex system has many interrupt sources, may have different priorities, and may face a nested interrupt situation.

Step S14. During the execution of the exception handler, a SHADOW instruction (second instruction) is fetched, stored in the SHADOW _ INST register, and the flag bit information in the SHADOW _ ENABLE register is set to indicate that the SHADOW instruction needs to be executed in place of the instruction that has the exception. Wherein the value of the flag bit information stored in the SHADOW _ ENABLE register is set to true, which indicates that when returning from the exception handler to the current program, the SHADOW instruction stored in the SHADOW _ INST register needs to be executed in place of the instruction at the return position in the current program (i.e., the instruction at which the exception occurred).

Assuming that the exception detected in step S13 is a fault-type exception, a shadow instruction may be obtained for execution in place of the instruction in which the exception occurred, in the following two ways:

1) The method includes the steps of presetting and storing shadow instructions corresponding to various faults, wherein the shadow instructions can be instructions which are preset by a user, can be executed by a processor and can be executed instead of abnormal instructions, one fault can correspond to a plurality of preset instructions (or a plurality of shadow instructions and a plurality of second instructions), and a plurality of faults can also correspond to one shadow instruction. For example, when a current program is executed by a multi-core processor, different shadow instructions may be set in advance for a fault for different cores of the processor, and when one core of the processor detects the fault, the shadow instruction specific to the core is acquired for the fault. The corresponding plurality of shadow instructions are preset for a fault, so that the selection range of the final shadow instruction (for replacing an abnormal instruction to execute) is wider, and the flexibility is higher.

After detecting the fault, searching for a preset and stored SHADOW instruction corresponding to the fault, if a plurality of corresponding SHADOW instructions exist, selecting one SHADOW instruction from the plurality of SHADOW instructions according to a preset rule (for example, according to a core of a processor), storing the searched/selected SHADOW instruction into a SHADOW _ INST register, and setting the value of the flag bit information in the SHADOW _ ENABLE register to be true. After a fault is detected, a corresponding shadow instruction can be searched immediately; the corresponding SHADOW instruction may also be looked up at any time during the execution of the exception handler, as long as the SHADOW instruction is stored to the SHADOW _ INST register and the value of the flag bit information in the SHADOW _ ENABLE register is set to true before the exception handler ends execution.

2) And interacting with a user during the execution of the exception handling program to acquire a shadow instruction provided by the user. After the SHADOW instruction provided by the user is obtained, the SHADOW instruction is stored to the SHADOW _ INST register, and the value of the flag bit information in the SHADOW _ ENABLE register is set to true.

Assuming that the exception detected in step S13 is a trap-type exception, more specifically, a breakpoint interrupt instruction is detected, an original instruction replaced by the breakpoint interrupt instruction in the current program is acquired, the original instruction is stored as a SHADOW instruction in the SHADOW _ INST register, and the value of the flag bit information in the SHADOW _ ENABLE register is set to true. Similar to fault-type exceptions, one kind of trap may also correspond to multiple shadow instructions, and multiple kinds of traps may also correspond to one shadow instruction.

Step S15, responding to the completion of the execution of the exception handler, reading the flag bit information in the SHADOW _ ENABLE register, and responding to the flag bit information in the SHADOW _ ENABLE register indicating that the execution needs to be performed by using the SHADOW instruction in the SHADOW _ INST register to replace the exception-occurring instruction, executing the SHADOW instruction in the SHADOW _ INST register.

Similar to the existing exception handling method, when the current program is returned from the exception handler, the PC register in the processor will read and store the location of the exception instruction stored in the ERROR _ PC register (which points to the address of the exception instruction in the memory, i.e. the return location in the current program); however, unlike the existing exception handling method, in the present embodiment, before the INST register reads the instruction to be executed from the memory according to the location stored in the PC register, the flag bit information stored in the SHADOW _ ENABLE register is read, and if the flag bit information is true, that is, it indicates that the SHADOW instruction stored in the SHADOW _ INST register needs to be executed instead of the instruction at the return location in the current program (i.e., the instruction in which the exception occurs), the SHADOW instruction stored in the SHADOW _ INST register is read and stored into the INST register, so that the SHADOW instruction is executed by the processor instead of the instruction in which the exception occurs.

It should be understood that the processor always executes instructions stored in the INST (instruction) register. Although the PC register now stores the location of the excepted instruction (which points to the address in memory of the excepted instruction, i.e., the return location in the current program), the processor does not execute the excepted instruction, but instead executes the shadow instruction stored in the INST instruction register. That is, the shadow instruction is executed in place of the instruction in the current program in which the exception occurred.

Step S16, responding to the end of the execution of the SHADOW instruction, clearing the SHADOW instruction in the SHADOW _ INST register, setting the flag bit information in the SHADOW _ ENABLE register to indicate that the abnormal instruction is not needed to be replaced by the SHADOW instruction for execution, and executing the next instruction of the abnormal instruction (the first instruction) in the current program to continue the execution of the current program.

As an embodiment, after the SHADOW instruction finishes executing, the value of the SHADOW _ ENABLE register may be set to false to indicate that the execution does not need to replace the exception-occurring instruction with the SHADOW instruction, and the SHADOW instruction stored in the SHADOW _ INST register may be cleared; meanwhile, the address of the instruction with the exception, which is stored in the ERROR _ PC register, needs to be cleared, so that the processing efficiency can be improved in the exception handling scene of the multi-core processor by designing a shadow instruction (One-time executed shadow instruction) which is executed at One time. As described in step S15, upon return from the exception handler to the current program, the PC register in the processor will read and store the location of the instruction where the exception occurred. Thus, after the shadow instruction finishes executing, the PC register performs addition calculation, thereby obtaining the position of the instruction next to the instruction in which the exception occurred in the current program (i.e., the position next to the return position in the current program), which points to the address in the memory of the instruction next to the instruction in which the exception occurred in the current program. An INST register in the processor reads the next instruction of the instruction in the current program that is abnormal from the memory according to the location stored in the PC register and stores the instruction so that the instruction is executed by the processor. Thus, the current program can continue to execute.

Optionally, for step S16, it may be selected not to clear the SHADOW instruction stored in the SHADOW _ INST register at this time in some scenarios (but still it is necessary to set the SHADOW _ ENABLE register to indicate that it is not necessary to replace the instruction in which the exception occurs with the SHADOW instruction here for execution), for example, it may wait until the next exception handling scenario to replace the SHADOW instruction in this scenario with the new acquired instruction, as a new SHADOW instruction for next use.

As can be seen from the above steps, by setting the SHADOW _ ENABLE register and the SHADOW _ INST register, and performing some simple operations on the SHADOW _ ENABLE register, the SHADOW _ INST register, the program counter register and the instruction register, it is possible to smoothly return to the current program from the exception handling program to continue the execution of the current program, thereby improving the efficiency of exception handling.

In the above-described embodiment, the shadow instruction for execution in place of the instruction in which the exception occurred when returning from the exception handler to the current program is acquired during execution of the exception handler, without replacing the instruction in which the exception occurred with the shadow instruction in the current program. For example, in the case of setting a breakpoint interruption instruction to debug the current program, the breakpoint interruption instruction does not need to be replaced in the current program by the original instruction, so that the normal execution of the current program is realized by avoiding adding extra operations. The method can improve the efficiency of exception handling without influencing the continuous execution of the current program, is particularly suitable for the multi-core processor to carry out exception handling, and can be applied to various exception handling scenes.

Based on the exception handling method provided by the above embodiment, fig. 2a to 2e schematically show a specific example of skipping to execute an exception handling program and returning to the current program to continue execution when the processor detects an exception:

as shown in FIG. 2a, the current program has executed to the inst2 instruction. At this point, the PC register in the processor points to the address 102 of the INST2 instruction in memory, and the INST register stores the instruction INST2 at address 102 for execution by the processor of the instruction INST2. In addition, the value of the flag bit information stored in the SHADOW _ ENABLE register is an initial value false.

Subsequently, as shown in FIG. 2b, an exception is detected when instruction INST2 in the INST register is executed. In response to detecting the exception, the excepted instruction inst2 is aborted, and the ERROR _ PC register in the processor stores the address 102 (i.e., the return location in the current program) of the excepted instruction inst2. After determining the exception handler corresponding to the detected exception, the PC register points to address 0 in the memory of the first instruction INST0 in the exception handler, and the INST register reads and stores the first instruction INST0 in the exception handler from the memory according to address 0 stored in the PC register, so that the processor jumps to execute instruction INST0 stored in the INST register.

The processor continues executing the exception handler and acquires shadow instructions during execution of the exception handler until the last instruction in the exception handler, return, is executed as shown in figure 2 c. At this point, the PC register in the processor points to address 5 of the last instruction, return, in the exception handler, and the INST register has the last instruction, return, in the exception handler stored. Since SHADOW instruction instx is obtained during execution of the exception handler, at this time, SHADOW _ INST register stores SHADOW instruction instx, and the value of the flag bit information stored in the SHADOW _ ENABLE register is set to true, which indicates that the instruction at the return position in the current program (i.e., instruction INST2 where the exception occurred) needs to be replaced with SHADOW instruction instx stored in the SHADOW _ INST register for execution.

In response to the exception handler ending execution, the current program is returned from the exception handler. As shown in FIG. 2d, the PC register in the processor reads and stores the address 102 of the excepted instruction inst2 stored in the ERROR _ PC register (i.e., the return location in the current program). Subsequently, the flag bit information stored in the SHADOW _ ENABLE register is read, and since the value of the flag bit information is true, the SHADOW instruction instx stored in the SHADOW _ INST register is read and stored to the INST register instead of storing the instruction INST2 at the address 102 pointed to by the PC register (i.e., the instruction at which the exception occurs) in the INST register, so that the processor will execute the SHADOW instruction instx stored in the INST register.

After the SHADOW instruction finishes executing, as shown in fig. 2e, clearing the SHADOW instruction instx stored in the SHADOW _ INST register, and setting the value of the SHADOW _ ENABLE register to false to indicate that the SHADOW instruction is not needed to replace the instruction with which the exception occurs for execution; at the same time, the address 102 of the instruction in which the exception occurred, which is stored in the ERROR _ PC register, is also cleared. At this time, the PC register in the processor performs an addition calculation so as to point to the address 103 of the next instruction inst3 of the instruction inst2 in the current program in which an exception occurred, and the INST register reads and stores the next instruction inst3 of the instruction inst2 in the current program in which an exception occurred from the memory according to the address 103 stored in the PC register, so that the instruction inst3 is executed by the processor. Thus, the current program can continue to execute.

It will be appreciated that those skilled in the art can set the specific contents of the corresponding registers to indicate when which type of instruction needs to be executed, based on the concepts disclosed herein and the actual requirements.

It should be noted that some exemplary methods are depicted as flowcharts. Although a flowchart may describe the operations as being performed serially, it can be appreciated that many of the operations can be performed in parallel, concurrently, or synchronously, and that the order of the operations can be rearranged. The process may terminate upon completion of the operation or may have additional steps not included in the figures or embodiments.

Another aspect of the invention provides a computer readable medium, including but not limited to: floppy disk, hard disk, magnetic tape, other magnetic media, CDROM, CDRW, DVD, other optical media, punch cards, other physical media, ROM, PROM, EEPROM, RAM, SRAM, or other media which is readable by a computer, and transmission media such as coaxial cable, fiber optic cable, carrier wave, etc. The computer readable medium may be included in the computer system described above or may be a separate medium that is not installed. The computer-readable medium is used for carrying computer instructions or programs, including computer instructions or programs for implementing the above-described exception handling method, and when the computer instructions or programs in the computer-readable medium are read and executed by a processor (e.g., a processor in the above-described computer system), the above-described embodiment of the exception handling method can be implemented (e.g., caused to be implemented by the above-described computer system), including the steps shown in fig. 1.

Another aspect of the invention provides an electronic device, such as a computer system, that may include a bus, and a processor, memory, input devices (such as a keyboard, mouse, sensors, etc.), output devices (such as a display, printer, speakers, etc.), communication interfaces (such as a parallel port, serial port, modem, network card, etc.), and other devices (such as a detachable device, a drive device, etc.) coupled to the bus.

Wherein the memory (such as ROM, PROM, EEPROM, RAM, SRAM, etc.) is used to store data as well as computer instructions or programs, including computer instructions or programs for implementing the above-described exception handling method. The processor is configured to perform a series of actions specified by the computer instructions or program, such as executing the computer instructions or program stored in the memory, which when executed by the processor, enable the computer system to implement the embodiments of the exception handling method described above, including the steps shown in fig. 1.

Although the present invention has been described by way of preferred embodiments, it is to be understood that the present invention is not limited to the embodiments described above and shown in the drawings, and that various changes and modifications may be made by one skilled in the art without departing from the scope of the invention.

Claims

1. A method of exception handling, the method comprising:

in response to detecting an exception while executing a first instruction in a current program, aborting execution of the first instruction, storing a location of the first instruction, and jumping to execute an exception handler corresponding to the exception;

fetching a second instruction during execution of the exception handler, the second instruction for execution in place of the first instruction;

in response to the exception handler ending execution, executing the second instruction; and

and responding to the second instruction ending execution, executing a next instruction of the first instruction in the current program so as to continue the execution of the current program.

2. The method of claim 1, further comprising:

setting a first register to store flag bit information indicating whether the first instruction is to be executed in place of the second instruction; and

a second register is provided for storing the second instruction.

3. The method of claim 2, wherein fetching the second instruction during execution of the exception handler comprises:

during the execution of the exception handling program, acquiring a preset instruction corresponding to the exception or acquiring an instruction provided by a user as the second instruction; and

setting flag bit information in the first register to indicate that the first instruction needs to be executed in place of the second instruction, and storing the second instruction in the second register.

4. The method of claim 3, further comprising:

presetting a plurality of instructions corresponding to the exception; and

acquiring a preset instruction corresponding to the exception comprises:

and selecting from a plurality of instructions corresponding to the exception according to a preset rule to acquire a preset instruction corresponding to the exception.

5. The method of claim 3, wherein executing the second instruction in response to the exception handler ending execution comprises:

reading flag bit information in the first register in response to the exception handler ending execution;

reading the second instruction in the second register in response to the flag bit information indicating that execution of the second instruction in place of the first instruction is required; and

executing the second instruction.

6. The method of claim 3, further comprising:

in response to the second instruction ending execution, setting flag bit information in the first register to indicate that execution does not require replacement of the first instruction with the second instruction, and clearing the second instruction in the second register.

7. The method according to any one of claims 1-6, further comprising:

in response to the exception handler ending execution, obtaining a location of the first instruction stored in response to detecting an exception, storing the location of the first instruction in a program counter register, and storing the second instruction in an instruction register to execute the second instruction in the instruction register.

8. The method of claim 7, wherein in response to the second instruction ending execution, executing a next instruction of the first instruction in the current program comprises:

responding to the end of the execution of the second instruction, and enabling the program counter register to execute addition calculation to obtain the position of the next instruction of the first instruction in the current program;

causing the instruction register to read a next instruction of the first instruction in the current program according to a position in the program counter register and store the next instruction; and

executing an instruction next to the first instruction in the current program in the instruction register.

9. A computer-readable medium, on which a computer program is stored, which, when being executed by a processor, carries out the method according to any one of claims 1-8.

10. An electronic device, comprising:

a processor; and

a memory having a computer program stored thereon and coupled to the processor, the computer program, when executed by the processor, causing the electronic device to implement the method of any of claims 1-8.