CN101042670A - Instruction exception processing method - Google Patents
Instruction exception processing method Download PDFInfo
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- CN101042670A CN101042670A CN 200710039861 CN200710039861A CN101042670A CN 101042670 A CN101042670 A CN 101042670A CN 200710039861 CN200710039861 CN 200710039861 CN 200710039861 A CN200710039861 A CN 200710039861A CN 101042670 A CN101042670 A CN 101042670A
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Abstract
This invention discloses one abnormal order process method, which is applied in order batch processor and whose hardware is mainly composed of program control unit, order code unit, register file, execution unit and transfer control bench, wherein, this invention user program control unit and register file to identify the orders and then uses the interval servo program for substitution to avoid the orders without changing hardware materials in abnormal situations of order process.
Description
Technical field:
The present invention relates to a kind of microprocessor interrupt function, that adopt the instruction flow line line structure that has.The method of instruction abnormality processing in particularly a kind of instruction set processor.
Background technology:
As everyone knows, the microprocessor general reference makes set processor (ISP, Instruction SetProcessor).ISP carries out the instruction in the pre-defined instruction set.The function of microprocessor almost completely depends on instruction set, thereby shows its executive capability by instruction set.All programs that run on the microprocessor all will be encoded based on instruction set.
The development of microprocessor also is the development of instruction collecting system to a certain extent, and from the cisc instruction set to the risc instruction set, instruction set has experienced one from simple to complexity, revert to a simple spiralling process from complexity again.
Computer organization normally develops towards more complicated direction, as bigger instruction set, more addressing mode, more special register and stronger command calculations function etc.At this moment the instruction set of Shi Yonging mainly is a cisc instruction set.Yet,, it is found that some too complicated and abstruse instructions are difficult to also seldom use when CISC develops into to a certain degree, such instruction is added to instruction set makes the design of controller become complicated on the contrary, and taken the sizable part of cpu chip area.So risc instruction set arises at the historic moment.Now existing numerous manufacturer production risc processors, although their realization means are different, the fundamental of following RISC notion is a general agree:
(1) limited simple instruction set.
(2) emphasize the use of register, or CPU is equipped with a large amount of general-purpose registers (often being called register file), or so that position paper is optimized the use of register.
(3) emphasize optimization to instruction pipelining.
Instruction pipelining overlap technique service time allows several instructions simultaneously processed, thereby improves processor performance comprehensively.Now, be used for the processor of PC/ workstation and parallel computer, the instruction flow line line structure has all been adopted in plan.
Microprocessor Design unit is according to predefined instruction set design microprocessor, before producing, flow must test designed microprocessor, but present testing mechanism can not cover all situations fully, so after flow is produced, designing unit also must have the special messenger to the microprocessor of having produced carry out for a long time, on a large scale, the test of high coverage rate.
If found certain instruction execution error this moment, general way has two kinds now:
(1) producer reminds and uses the user of assembly language not use certain instruction to the errata of user's granting to this processor.In the following example:
Program 1:AND T0, T1; T0 and T1 are done and operation, and the result is stored among the T1
OR T3, T2; With T3 and T2 work or operation, the result is stored among the T2
NOT T0; To deposit among the T0 after the data negate among the T0
XOR T1, T2; T1 and T2 are made xor operation, and the result is stored among the T2
Annotate: T0, T1, T2, T3 are temporary registers.
Make a mistake when finding in the test that the XOR instruction is carried out, continue to carry out this section program so, the programmer will can not get correct or expected result.Receive the errata of producer as the programmer after, all in just he need being write a program use the place of this instruction to replace with the program segment that can finish xor operation, shown in program 2:
Program 2:AND T0, Ti; T0 and T1 are done and operation, and the result is stored among the T1
OR T3, T2; With T3 and T2 work or operation, the result is stored among the T2
NOT T0; To deposit among the T0 after the data negate among the T0
PUSH T0; Preserve on-the-spot
PUSH T3; Preserve on-the-spot
NOT T2, T3; To deposit among the T3 after the data negate among the T2
NOT T1, T0; To deposit among the T0 after the data negate among the T1
AND T1, T3; Realize T1 T2, the result deposits among the T3
AND T0, T2; Realize T1T2, the result deposits among the T2
OR T3, T2; Realize T1 T2+ T1T2.The result deposits among the T2
POP T3; Recover on-the-spot
POP T0; Recover on-the-spot
As seen, this mode increases programmer's workload and size of code greatly, and this method is very big to programmer's dependence, does not ensure the quality of products.
(2) producer who requires compiler avoids this instruction when the program of this processor of compiling, requires constantly upgrade composing software and user platform of user to adapt to this processor then.
These two kinds of methods can be used to the user and bring inconvenience.
If it is transparent to the user that a kind of method is arranged, do not need reprogramming, allow processor itself avoid this instruction, will significantly reduce programmer's workload so, reduce the artificial wrong chance of introducing.
Summary of the invention:
The purpose of this invention is to provide the method for instruction abnormality processing in a kind of instruction set processor, it does not need upgrading hardware, does not need the user to change program, will reduce programmer's workload, reduces the artificial wrong chance of introducing.
Concrete technical scheme is as follows:
The method that instruction exception of the present invention is handled, be mainly used in the instruction set processor, it is characterized in that required hardware configuration is mainly the processor of 16 the IO registers (is example with 16 bit processors) that comprise the procedure control unit, instruction decoding unit, performance element, submission control desk and three special uses that contain the recognition instruction logic in the method; And also comprise the importing program that the user upgrades that offers; The content of described method is:
(1) processor by the coding of the recognition instruction in one of them the IO register that leaves reservation in, is discerned instruction after reading in instruction.This of this coding indication instructs us just to be called the instruction that has indicated.
(2) identify after the instruction that indicates, just enter pre-set interrupt service routine immediately, and will instruct corresponding PC address to deposit the IO register of two other reservation in.
(3) in interrupt service routine, the quilt of being stored by the IO register that reads two other reservation indicates the PC address at the instruction place that, read complete instruction, and further discern its employed operand information, with other instruction or program it is replaced then.
(4) after replacement finishes, return original program.
About employed interrupt service routine in the method and new importing program, processor chips manufacturer can offer the user together along with the errata of instruction, the user only needs it is replaced original importing program, and this interrupt service routine added in the item file, and upgrade interrupt vector table and can use.
The inventive method is owing to when realizing, the processor that requires to be moved is reserved 16 IO registers (is example with 16 bit processors) of three special uses, and adds the logic of recognition instruction in the program flow unit.Make manufacturer not need flow again to upgrade hardware like this, reduced the operation that the user participates in safeguarding, reduced to avoiding the wrong wrong chance that imports.
The present invention does not need the depended software environment when realizing, do not need the application programmer to intervene yet, and only needs to start embedded program, and user's initialization files that producer provides that upgrade in time get final product.
The present invention helps reasonably arranging data flow process of system, makes it between each performance element of microprocessor ensuring escapement from confliction and carries out smoothly.Because the method do not interrupt existing data stream and instruction stream, do not upset the executed in parallel mechanism of all devices, so microprocessor system is still in normal operation, so the intercommunication exceptional instructions has dropped to nadir to the injury of system.
Description of drawings:
Fig. 1 is the general work FB(flow block) of existing processor.
Fig. 2 adopts the later process flow diagram of exception handling of the present invention.
Embodiment:
Further set forth the present invention below in conjunction with accompanying drawing.
According to hardware in above-mentioned the inventive method that provides and software arrangements environment, it possesses and reaches processor and can carry out the function that white row is repaired to the instruction that makes mistakes.
For the ease of understanding, at first set forth the general work flow process of not using processor of the present invention to the technology of the present invention.
As shown in Figure 1, procedure control unit is given command memory by instruction address bus with instruction address, reads in instruction by the director data bus.After reading in instruction, procedure control unit is at first discerned instruction, generally will identify jump instruction supervisor steering order here, giving decoding unit with operational order then deciphers, result after will being deciphered by decoding unit again gives address-generation unit and data operation unit respectively, the storage address that the information calculations that address-generation unit is given by decoding unit need be visited, give the data-carrier store interface by address bus, then data are sent by data bus, the data operation unit is put into the result of calculated result and status register on the data bus, and procedure control unit is monitored the duty of arithmetic element by the result of data on the sampled data bus and status register.
The mechanism according to the present invention, the effect of 16 IO registers of three wherein related reservations is as follows:
IO register 1: deposit the order number that needs identification;
IO register 2: deposit a PC address high position that is replaced instruction;
IO register 3: deposit the PC address low level that is replaced instruction.
As shown in Figure 2, the microprocessor in the described method mechanism is after reading in instruction, and procedure control unit is at first discerned instruction, and at this moment, procedure control unit not only will be discerned jump instruction supervisor steering order, also will identify the instruction that has indicated.We have reserved three registers at the IO port and have used for this mechanism, and one of them is used for depositing the coding of the instruction that needs identification, and this of this coding indication instructs us just to be called the instruction that has indicated.Procedure control unit is encoded by recognition instruction and is discerned this instruction, after identifying, just enters pre-set interrupt service routine immediately, and will instruct corresponding PC address to deposit the IO register of two other reservation in.In interrupt service routine, the quilt of being stored by the IO register that reads two other reservation indicates the PC address at the instruction place that, read complete instruction, and further discern its employed operand information, with other instruction or program it is replaced then.After replacing end, return original program.Here employed interrupt service routine and new importing program, processor chips manufacturer can offer the user together along with the errata of instruction, the user only needs it is replaced original importing program, and this interrupt service routine added in the item file, and upgrade interrupt vector table and can use.
More than be one of embodiments of the present invention,, do not spend performing creative labour, on the basis of the foregoing description, can do multiple variation, can realize purpose of the present invention equally for those skilled in the art.But this variation obviously should be in the protection domain of claims of the present invention.
Claims (2)
1, a kind of method of instruction exception processing, be mainly used in the instruction set processor, it is characterized in that required hardware configuration is mainly the processor of 16 IO registers that comprise the procedure control unit, instruction decoding unit, performance element, submission control desk and three special uses that contain the recognition instruction logic in the method; And also comprise the importing program that the user upgrades that offers; The content of described method is:
(1) processor by the coding of the recognition instruction in one of them the IO register that leaves reservation in, is discerned instruction after reading in instruction.This of this coding indication instructs us just to be called the instruction that has indicated.
(2) identify after the instruction that indicates, just enter pre-set interrupt service routine immediately, and will instruct corresponding PC address to deposit the IO register of two other reservation in.
(3) in interrupt service routine, the quilt of being stored by the IO register that reads two other reservation indicates the PC address at the instruction place that, read complete instruction, and further discern its employed operand information, with other instruction or program it is replaced then.
(5) after replacement finishes, return original program.
2, the method for handling according to the instruction exception of claim 1, it is characterized in that, employed interrupt service routine and new importing program in the described method, processor chips manufacturer can offer the user together along with the errata of instruction, the user only needs it is replaced original importing program, and this interrupt service routine added in the item file, and upgrade interrupt vector table and can use.
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| CN 200710039861 CN101042670A (en) | 2007-04-24 | 2007-04-24 | Instruction exception processing method |
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| CN 200710039861 CN101042670A (en) | 2007-04-24 | 2007-04-24 | Instruction exception processing method |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270111A (en) * | 2011-08-11 | 2011-12-07 | 中国科学院声学研究所 | Command decoding method and command set simulation device |
| CN102541673A (en) * | 2010-12-27 | 2012-07-04 | 北京中电华大电子设计有限责任公司 | Security processing method and circuit for central processing unit (CPU) fetch instruction abnormity |
| CN102708013A (en) * | 2011-03-07 | 2012-10-03 | 英飞凌科技股份有限公司 | Program-instruction-controlled instruction flow supervision |
| CN103309644A (en) * | 2012-03-13 | 2013-09-18 | 辉达公司 | Translation address cache for a microprocessor |
| CN106170761A (en) * | 2012-09-27 | 2016-11-30 | 英特尔公司 | For the method and apparatus instructing across the scheduling storage of multiple atomic regions in Binary Conversion |
| US9880846B2 (en) | 2012-04-11 | 2018-01-30 | Nvidia Corporation | Improving hit rate of code translation redirection table with replacement strategy based on usage history table of evicted entries |
| US10108424B2 (en) | 2013-03-14 | 2018-10-23 | Nvidia Corporation | Profiling code portions to generate translations |
| US10241810B2 (en) | 2012-05-18 | 2019-03-26 | Nvidia Corporation | Instruction-optimizing processor with branch-count table in hardware |
| US10324725B2 (en) | 2012-12-27 | 2019-06-18 | Nvidia Corporation | Fault detection in instruction translations |
| CN115328690A (en) * | 2022-10-13 | 2022-11-11 | 北京登临科技有限公司 | Exception handling method, computer readable medium and electronic device |
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2007
- 2007-04-24 CN CN 200710039861 patent/CN101042670A/en active Pending
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102541673A (en) * | 2010-12-27 | 2012-07-04 | 北京中电华大电子设计有限责任公司 | Security processing method and circuit for central processing unit (CPU) fetch instruction abnormity |
| US10867028B2 (en) | 2011-03-07 | 2020-12-15 | Infineon Technologies Ag | Program-instruction-controlled instruction flow supervision |
| CN102708013A (en) * | 2011-03-07 | 2012-10-03 | 英飞凌科技股份有限公司 | Program-instruction-controlled instruction flow supervision |
| CN102708013B (en) * | 2011-03-07 | 2016-01-06 | 英飞凌科技股份有限公司 | For equipment, signature blocks and method that the instruction stream of program statement control controls |
| US10515206B2 (en) | 2011-03-07 | 2019-12-24 | Infineon Technologies Ag | Program-instruction-controlled instruction flow supervision |
| CN102270111A (en) * | 2011-08-11 | 2011-12-07 | 中国科学院声学研究所 | Command decoding method and command set simulation device |
| CN102270111B (en) * | 2011-08-11 | 2014-01-01 | 中国科学院声学研究所 | Command decoding method and command set simulation device |
| US10146545B2 (en) | 2012-03-13 | 2018-12-04 | Nvidia Corporation | Translation address cache for a microprocessor |
| CN103309644A (en) * | 2012-03-13 | 2013-09-18 | 辉达公司 | Translation address cache for a microprocessor |
| US9880846B2 (en) | 2012-04-11 | 2018-01-30 | Nvidia Corporation | Improving hit rate of code translation redirection table with replacement strategy based on usage history table of evicted entries |
| US10241810B2 (en) | 2012-05-18 | 2019-03-26 | Nvidia Corporation | Instruction-optimizing processor with branch-count table in hardware |
| CN106170761A (en) * | 2012-09-27 | 2016-11-30 | 英特尔公司 | For the method and apparatus instructing across the scheduling storage of multiple atomic regions in Binary Conversion |
| CN106170761B (en) * | 2012-09-27 | 2019-05-10 | 英特尔公司 | Method and apparatus for dispatching store instruction across multiple atomic regions in Binary Conversion |
| US10324725B2 (en) | 2012-12-27 | 2019-06-18 | Nvidia Corporation | Fault detection in instruction translations |
| US10108424B2 (en) | 2013-03-14 | 2018-10-23 | Nvidia Corporation | Profiling code portions to generate translations |
| CN115328690A (en) * | 2022-10-13 | 2022-11-11 | 北京登临科技有限公司 | Exception handling method, computer readable medium and electronic device |
| CN115328690B (en) * | 2022-10-13 | 2023-02-17 | 北京登临科技有限公司 | Exception handling method, computer readable medium and electronic device |
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