CN115327823A - Display panel, preparation method thereof and display device - Google Patents

Display panel, preparation method thereof and display device Download PDF

Info

Publication number
CN115327823A
CN115327823A CN202110452845.4A CN202110452845A CN115327823A CN 115327823 A CN115327823 A CN 115327823A CN 202110452845 A CN202110452845 A CN 202110452845A CN 115327823 A CN115327823 A CN 115327823A
Authority
CN
China
Prior art keywords
substrate
organic insulating
spacer
sub
pixel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110452845.4A
Other languages
Chinese (zh)
Inventor
柳泉洲
张伟
高锦成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Hefei BOE Display Lighting Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Hefei BOE Display Lighting Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Hefei BOE Display Lighting Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202110452845.4A priority Critical patent/CN115327823A/en
Publication of CN115327823A publication Critical patent/CN115327823A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The disclosure belongs to the technical field of display, and relates to a display panel, a preparation method thereof and a display device. The display panel includes: the first substrate and the second substrate are oppositely arranged; the transistor is formed on the first substrate; the organic insulating layer is formed on the first substrate and covers the transistor and comprises a first organic insulating part and a second organic insulating part, the first organic insulating part covers the wiring area, the second organic insulating part covers the pixel area, and the thickness of the first organic insulating part is larger than that of the second organic insulating part; the spacer is formed on one side of the second substrate facing the first substrate, and an orthographic projection of the spacer on the first substrate is positioned in an orthographic projection of the first organic insulating part on the first substrate. According to the scheme, the relative distance from the lower surface of the spacer to the pixel area of the array substrate is increased, and the spacer is prevented from being extruded and inclined to the pixel area to scratch a film layer of the pixel area.

Description

Display panel, preparation method thereof and display device
Technical Field
The disclosure relates to the technical field of display, in particular to a display panel, a preparation method thereof and a display device.
Background
A Liquid Crystal Display (LCD) panel is an important flat panel Display device, and has been widely applied in the fields of mobile phones, vehicles, displays, televisions, public displays and the like, and the market demand for large-sized LCD panels is increasing; at present, the liquid crystal display panel has the problems of low transmittance, easy light leakage after collision and the like.
Disclosure of Invention
An object of the embodiments of the present disclosure is to provide a display panel, a method of manufacturing the same, and a display device, thereby overcoming, at least to some extent, one or more of the problems due to the limitations and disadvantages of the related art.
The first aspect of the present disclosure provides a display panel, which includes an array substrate and a matching substrate that are oppositely disposed, wherein the array substrate includes:
a first substrate (10) including a sub-pixel region and a wiring region provided in the periphery of the sub-pixel region;
the transistor (11) is arranged on the first substrate (10) and is positioned in the wiring area;
an organic insulating layer (12) formed on the first substrate (10), including a first organic insulating portion (120) and a second organic insulating portion (121), the first organic insulating portion (120) covering the wiring region and the transistor (11), the second organic insulating portion (121) covering the sub-pixel region, a thickness of the first organic insulating portion (120) being greater than a thickness of the second organic insulating portion (121);
wherein, the involution base plate comprises:
a second substrate (20), the second substrate (20) being disposed opposite to the first substrate (10);
and the spacer (13) is formed on one side of the second substrate (20) facing the first substrate (10), and the orthographic projection of the spacer (13) on the first substrate (10) is positioned in the orthographic projection of the first organic insulating part (120) on the first substrate (10).
In an exemplary embodiment of the present disclosure, the display panel includes a plurality of the spacers (13), the spacers (13) are main spacers (1301) or auxiliary spacers (1302), and a height of the main spacers (1301) is greater than a height of the auxiliary spacers (1302) in a thickness direction of the display panel;
wherein a height difference DeltaH of the surfaces of the first organic insulating portion (120) and the second organic insulating portion (121) far away from the first substrate is larger than a height difference DeltaH of the main spacer (1301) and the auxiliary spacer (1302) ps 。
In an exemplary embodiment of the present disclosure, the array substrate further includes:
scanning lines (17) arranged on the first substrate (10) and arranged in the wiring area along a row direction;
data lines (16) provided on the first substrate (10) and arranged in the wiring region in a column direction;
common lines (18) provided on the first substrate (10) and arranged in the line direction at the wiring regions;
a pixel electrode (14) and a common electrode (15) both provided on the first substrate (10), the common electrode (15) being electrically connected to the common line (18);
the transistor (11) comprises a gate electrode, a first electrode and a second electrode, the gate electrode is electrically connected with the scanning line (17), and the first electrode is electrically connected with the data line (16); the second pole is electrically connected with the pixel electrode (14);
wherein the scanning line (17), the data line (16), the common line (18) and the transistor (11) are all positioned on one side of the organic insulating layer (12) facing the first substrate (10), and the pixel electrode (14) and the common electrode (15) are all positioned on one side of the organic insulating layer (12) far away from the first substrate (10).
In an exemplary embodiment of the present disclosure, the first organic insulating portion (120) covers the transistor (11), and an orthogonal projection of the spacer (13) on the first substrate (10) covers an orthogonal projection of the transistor (11) on the first substrate (10).
In an exemplary embodiment of the present disclosure, the first organic insulating part (120) covers the common line (18), and an orthogonal projection of the spacer (13) on the first substrate (10) covers an orthogonal projection of the common line (18) on the first substrate (10).
In an exemplary embodiment of the present disclosure, the first organic insulating part (120) covers the data lines (16) and the scan lines (17), and an orthographic projection of the spacer (13) on the first substrate (10) covers a part of the data lines (16) and/or a part of the scan lines (17) on the first substrate (10).
In an exemplary embodiment of the present disclosure, a ratio of a thickness of the first organic insulating part (120) to a thickness of the second organic insulating part (121) is 2 to 4.
In an exemplary embodiment of the present disclosure, the first organic insulating part (120) has a thickness of 2 to 4 μm; the second organic insulating portion (121) has a thickness of less than 2 [ mu ] m.
In an exemplary embodiment of the present disclosure, the second organic insulating portion (121) has a thickness of 0.
In an exemplary embodiment of the present disclosure, the first substrate (10) includes a plurality of sub-pixel regions arranged in an array along a row direction and a column direction, and the spacers (13) are disposed between two adjacent sub-pixel regions along the column direction;
at least one column of every three adjacent columns of the sub-pixel areas is provided with the spacers (13), and one spacer (13) is arranged between any two adjacent sub-pixel areas in one column provided with the spacers (13).
In an exemplary embodiment of the present disclosure, the plurality of spacers (13) includes a plurality of main spacers (1301) and a plurality of auxiliary spacers (1302), the number of the auxiliary spacers (1302) being greater than the number of the main spacers (1301);
in every three adjacent columns of the sub-pixel areas, at least one column of all the spacers (13) is the auxiliary spacer (1302).
In an exemplary embodiment of the present disclosure, a projection of the spacer (13) on the first substrate (10) is rectangular, circular or elliptical.
In an exemplary embodiment of the present disclosure, a distance between a projection of the spacer (13) on the first substrate (10) and an edge of the adjacent sub-pixel region is 15-50 μm.
In an exemplary embodiment of the present disclosure, the array substrate further includes:
and the color resistance layer (101) is arranged on the first substrate (10) and is positioned on one side, close to the first substrate (10), of the organic insulation layer (12), and the color resistance layer covers the sub-pixel area and at least part of the wiring area.
In an exemplary embodiment of the present disclosure, the color resist layer (101) has an opening (1010) at the wiring region, the organic insulating layer (12) is depressed at the opening of the color resist layer, and a projection of the spacer (13) on the first substrate (10) is located within a projection of the opening (1010) on the first substrate (10).
In an exemplary embodiment of the present disclosure, the common electrode (15) and the pixel electrode (14) are both located on a side of the organic insulating layer (12) away from the first substrate (10);
the pixel electrode (14) is provided with a plurality of first electrode strips which are arranged at intervals in the row direction;
the common electrode (15) and the pixel electrode (14) are arranged on the same layer, the common electrode (15) is provided with a plurality of second electrode strips which are arranged at intervals in the row direction, the second electrode strips and the first electrode strips are alternately arranged in the row direction, and gaps are formed between the second electrode strips and the first electrode strips; the common electrode (15) is connected to the common line (18) through a via hole.
In an exemplary embodiment of the present disclosure, the array substrate further includes:
the liquid crystal layer is arranged between the array substrate and the involutory substrate;
the first alignment layer (102) is arranged on the first substrate (10) and covers one side, away from the first substrate (10), of the common electrode (15) and the pixel electrode (14);
and the second alignment layer (22) is arranged on the second substrate (20) and is positioned between the spacer (13) and the second substrate (20).
A second aspect of the present disclosure provides a method for manufacturing a display panel, including:
providing a first substrate, wherein the first substrate is divided into a sub-pixel area and a wiring area arranged on the periphery of the sub-pixel area;
forming a transistor in a wiring region of the first substrate;
forming an organic insulating layer on the first substrate, the organic insulating layer including a first organic insulating portion and a second organic insulating portion, the first organic insulating portion covering the wiring region and the transistor, the second organic insulating portion covering the sub-pixel region; wherein a thickness of the first organic insulating portion is greater than a thickness of the second organic insulating portion;
providing a second substrate;
and forming a spacer on one side of the second substrate facing the first substrate, wherein an orthographic projection of the spacer on the first substrate is positioned in an orthographic projection of the first organic insulating part on the first substrate.
In an exemplary embodiment of the present disclosure, the forming of the organic insulating layer includes:
coating an organic insulating material on the first substrate on which the transistor is formed;
and exposing and developing the organic insulating material by adopting a half-tone mask photomask or a gray-scale tone mask photomask, so that the remaining thickness of the organic insulating material in the sub-pixel region is smaller than that of the organic insulating material in the wiring region.
A third aspect of the present disclosure provides a display device including the display panel described above.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those skilled in the art without the exercise of inventive faculty. In the drawings:
fig. 1 is a cross-sectional view showing a structural change of a display panel in the related art;
FIG. 2 illustrates a top view of a first display panel of the present disclosure;
FIG. 3 isbase:Sub>A cross-sectional view of the first display panel at positions A-A 'and B-B' of FIG. 2;
FIG. 4 illustrates a top view of a second display panel of the present disclosure;
FIG. 5 isbase:Sub>A cross-sectional view ofbase:Sub>A second display panel corresponding to the positions A-A 'and B-B' in FIG. 4;
FIG. 6 illustrates a top view of a third display panel of the present disclosure;
FIG. 7 showsbase:Sub>A cross-sectional view ofbase:Sub>A third display panel at positions A-A 'and B-B' of FIG. 6;
FIG. 8 shows a top view of a fourth display panel of the present disclosure;
FIG. 9 isbase:Sub>A cross-sectional view ofbase:Sub>A fourth display panel corresponding to A-A 'and B-B' of FIG. 8;
FIG. 10 shows a top view of a fifth display panel of the present disclosure;
FIG. 11 shows a schematic layout of the spacer of the present disclosure;
fig. 12 shows a schematic structural view of the primary and secondary spacers of the present disclosure.
Description of the reference numerals:
10. a first substrate; 11. a transistor; 110. a first pole; 111. a second pole; 112. an active layer; 114. a passivation layer; 12. an organic insulating layer; 120. a first organic insulating portion; 121. A second organic insulating portion; 13. a spacer; 1301. a primary spacer; 1302. auxiliary spacer; 14. a pixel electrode; 15. a common electrode; 16. a data line; 17. scanning lines; 18. a common line; 19. a gate insulating layer; 101. a color resist layer; 1010. an opening; 102. a first alignment layer;
20. a second substrate; 21. a shielding layer; 22. a second alignment layer; 23. a protective layer;
Detailed Description
The technical solution of the present disclosure is further specifically described by the embodiments in conjunction with the accompanying drawings. In the specification, the same or similar reference numerals denote the same or similar components. The following description of the embodiments of the present disclosure with reference to the accompanying drawings is intended to explain the general inventive concept of the present disclosure and should not be construed as limiting the present disclosure.
Furthermore, in the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details.
In the related art, the main development trend of the TFT-LCD liquid crystal panel is high resolution and high transmittance. Referring to fig. 1, the lcd panel is mainly composed of a tft array substrate, a pair of substrates, a liquid crystal layer and a column spacer PS disposed between the two substrates. The columnar spacers 13 are made of resin having a certain elasticity, and serve as a support and a buffer, and the optimal thickness of the liquid crystal layer is maintained by controlling the gap between the two substrates. However, in the Cell-forming process and the future use process of the existing liquid crystal display panel, the panel cannot be prevented from being squeezed by external force, when the external force is too large, the spacer 13 slides, the alignment film in the display area on the array substrate is scratched, and the alignment liquid crystal capability is lost, for a high-resolution product, the width of the black matrix is very small, scratches on the alignment film cannot be shielded, light leakage occurs at the scratches under a dark-state picture, and the defect of spot shape is formed.
The "spot-like" defect not only seriously affects the display effect, but also causes the reduction of the good product rate of the liquid crystal panel and the increase of the production cost. The conventional solutions are to increase the number of spacers, change the position and shape of the spacers, and increase the width of the black matrix, etc., however, these methods have insignificant improvement effect on high resolution products, sometimes have defects, and cause the transmittance of the liquid crystal panel to decrease.
When the liquid crystal panel is subjected to overlarge oblique extrusion or impact, the spacer PS slides to the pixel area of the array substrate, and the maximum length of sliding out in the thickness direction of the display panel is H shift Because the organic film protective layer has different thicknesses at different positions to form a height difference, the relative height delta H between the lower surface of the spacer and the upper surface of the display area film layer is increased, so that delta H is larger than H shift This causes the spacers PS to slip and then to lose contact with the TFT-side substrate.
In view of the foregoing, embodiments of the present disclosure provide a display panel, which can be applied to a display device, and in particular, can be applied to a liquid crystal display device. Referring to fig. 2 and 3, a display panel according to an embodiment of the present disclosure may include a first substrate 10, a sub-pixel unit, an organic insulating layer 12, a second substrate, and a spacer 13, the sub-pixel unit may include at least one transistor 11, and the transistor 11 may be formed on the first substrate 10; an organic insulating layer 12 may be formed on the first substrate 10 and cover the transistor 11; the organic insulating layer 12 includes a first organic insulating portion 120 and a second organic insulating portion 121, the first organic insulating portion 120 covers the wiring region and the transistor 11, the second organic insulating portion 121 covers the sub-pixel region, and a thickness of the first organic insulating portion 120 is greater than a thickness of the second organic insulating portion 121. The second substrate 20 is disposed corresponding to the first substrate 10, the spacer 13 may be formed on a side of the second substrate 20 facing the first substrate 10, and an orthographic projection of the spacer 13 on the first substrate 10 is located within an orthographic projection of the first organic insulating portion 120 on the first substrate. In the embodiments of the present disclosure, by using organic insulating materials, that is: compared with the scheme of covering the transistor 11 with an inorganic material such as silicon nitride, the organic insulating layer 12 covers the transistor 11, and can improve the flatness of the side of the array substrate 1, so that the spacers 13 occupy space on the array substrate 1.
Meanwhile, the thickness of the organic insulating layer 12 in the wiring area is greater than that of the pixel area, and when the spacer 13 is pressed against the wiring area of the array substrate, the relative height Δ H between the lower surface of the spacer and the upper surface of the film layer in the sub-pixel area of the array substrate can be increased, so that Δ H is greater than H shift And the spacers PS can not contact the TFT side substrate after sliding, so that the risk that the spacers deflect to the sub-pixel region to scratch the film layer of the sub-pixel region when being stressed and extruded is reduced, the defect of spots of the liquid crystal panel can be effectively solved, and the redundancy of the manufacture and use of products is improved.
In addition, due to the fact that the relative height is increased, the size (PS Shift) occupied transversely after the spacers are offset is reduced, the PS Shift area does not need to be shielded when the substrates are combined, the width of the black matrix can be further reduced, and the aperture opening ratio and the transmittance of the panel are further improved. In addition, the organic insulating layer of the sub-pixel area of the array substrate is thin, so that the loss of backlight light intensity is reduced to a certain extent, the contrast is improved, the Mura sensitivity of a lens of an exposure machine can be reduced, and the display quality is improved.
In the embodiment of the present disclosure, the sub-pixel unit may include, in addition to the aforementioned transistor 11, a common electrode 15 and a pixel electrode 14; the array substrate 1 may further include a scan line 17, a data line 16, a common line 18, and the like, in addition to the aforementioned first substrate 10, the sub-pixel unit, and the organic insulating layer 12.
The array substrate 1 according to the embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.
In the embodiment of the present disclosure, as shown in fig. 2, the first substrate 10 may have a plurality of sub-pixel regions A2 arranged in an array along a row direction X and a column direction Y, a plurality of rows of first wiring regions A1 and a plurality of columns of second wiring regions A3, where the first wiring regions A1 and the sub-pixel regions A2 are alternately arranged in the column direction Y, and the second wiring regions A3 and the sub-pixel regions A2 are alternately arranged in the row direction X, and it should be understood that there is an overlap between the first wiring regions A1 and the second wiring regions A3.
For example, the first substrate 10 may be a single layer structure, and the material of the first substrate 10 may be glass; but not limited thereto, the first substrate 10 may have a multilayer structure; and the material of the first substrate 10 is not limited to glass, but may be other materials, such as: polyimide (PI) and the like, as the case may be.
In the embodiment of the disclosure, as shown in fig. 2, the whole scan line 17 may extend in the row direction X, and the scan line 17 may be located in the first wiring area A1 for providing the scan signal to the sub-pixel unit; for example, the scan lines 17 may be disposed in a plurality of rows, wherein one row of scan lines 17 may be disposed on each first wiring area A1, but the present invention is not limited thereto, and two or more rows of scan lines 17 may be disposed.
In the embodiment of the present disclosure, as shown in fig. 2, the common line 18 may extend in the row direction X as a whole, and the common line 18 may be located in the first wiring region A1 for providing a common signal to the sub-pixel units; for example, the common lines 18 may be disposed in a plurality of rows, wherein one row of the common lines 18 may be disposed on each of the first wiring regions A1, but is not limited thereto, and two or more rows of the common lines 18 may be disposed.
The common lines 18 and the scan lines 17 can be disposed in the same layer, so as to simplify the process and reduce the cost. Note that, as shown in fig. 2, on each first wiring area A1, an orthogonal projection of the common line 18 on the first substrate 10 and an orthogonal projection of the scan line 17 on the first substrate 10 do not overlap and are spaced apart from each other, that is, an orthogonal projection of the common line 18 on the first substrate 10 and an orthogonal projection of the gate electrode of the transistor 11 on the first substrate 10 do not overlap.
Further, it should be understood that, in the present disclosure, "same layer arrangement" refers to a layer structure in which a film layer for forming a specific pattern is formed using the same film forming process and then formed by a one-time patterning process using the same mask plate. That is, one mask (also called as a photomask) is corresponding to one patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the layer structure may be continuous or discontinuous, and the specific patterns may be at different heights or have different thicknesses. Thereby simplifying the manufacturing process, saving the manufacturing cost and improving the production efficiency.
For example, the common line 18 and the scan line 17 of the embodiment of the present disclosure may be made of metal or alloy material, such as molybdenum, aluminum, titanium, etc., to ensure good conductivity, but are not limited thereto, and may also be made of other materials with good conductivity.
In the embodiment of the present disclosure, as shown in fig. 2, the data line 16 may extend in the column direction Y as a whole, and the data line 16 may be located in the second wiring region A3 for providing the data signal to the sub-pixel unit; for example, the data lines 16 may be arranged in a plurality of columns, wherein each second wiring area A3 may be provided with one row of data lines 16, but is not limited thereto, and two or more rows of data lines 16 may also be provided.
For example, the data line 16 may be located on a side of the scan line 17 and the common line 18 away from the first substrate 10, and a gate insulating layer 19 is disposed between the data line 16 and the scan line 17 and the common line 18, as shown in fig. 2, to prevent the data line 16 from contacting the scan line 17 and the common line 18, wherein the data line 16 may be made of a metal material or an alloy material, such as a metal single layer or a multi-layer structure formed by molybdenum, aluminum, titanium, and the like, wherein the multi-layer structure is a multi-metal stacked layer, such as a titanium, aluminum, titanium three-layer metal stacked layer (Ti/Al/Ti), and the like.
It should be understood that the gate insulating layer 19 mentioned in the embodiments of the present disclosure may be disposed on the array substrate 1 in a whole layer, and the gate insulating layer 19 may be made of an inorganic material, for example, silicon oxide, silicon nitride, or other inorganic materials.
In the embodiment of the present disclosure, the plurality of sub-pixel units may be arranged in an array along the row direction X and the column direction Y, only two sub-pixel units arranged along the X direction are shown in the figure, and the sub-pixel units correspond to the sub-pixel regions A2 one-to-one, that is: each sub-pixel unit is correspondingly arranged on a sub-pixel area A2; specifically, at least portions of the common electrode 15 and the pixel electrode 14 of each sub-pixel unit may be located on one sub-pixel area A2, and at least portions of the transistors 11 of each sub-pixel unit may be located on the first wiring area A1.
As shown in fig. 2 and 3, the transistor 11 may include an active layer 112, a gate, and a second pole 111 and a first pole 110 disposed in the same layer; a gate insulating layer 19 may be further disposed between the gate and the active layer 112 to insulate the gate and the active layer 112 from each other, and the thickness of the gate insulating layer 19 may be about 0.4 μm, but is not limited thereto; for example, the gate electrode of the embodiment of the present disclosure may be disposed on the same layer as the aforementioned scan line 17 and connected to the aforementioned scan line 17, in other words, the gate electrode may be a partial structure of the aforementioned scan line 17; and the second and first poles 111 and 110 may be connected to source and drain doped regions of the active layer 112, respectively.
The second electrode 111 and the first electrode 110 can be disposed on the same layer as the data line 16, so as to simplify the process and reduce the cost.
For example, the transistor 11 of the embodiment of the present disclosure may be a bottom gate type, that is: the gate electrode may be formed on the first substrate 10 first; then, forming a gate insulating layer 19 on the first substrate 10, wherein the gate insulating layer 19 covers the gate electrode; an active layer 112 is then formed on the side of the gate insulating layer 19 facing away from the first substrate 10, namely: the active layer 112 is located on a side of the gate electrode away from the first substrate 10, and the active layer 112 overlaps with an orthographic projection of the gate electrode on the first substrate 10, for example, the orthographic projection of the active layer 112 on the first substrate 10 may be located within the orthographic projection of the gate electrode on the first substrate 10; the second pole 111 and the first pole 110 may be formed after the active layer 112 is formed, a portion of the first pole 110 may overlap the drain doped region of the active layer 112, and another portion of the first pole 110 may be located on the sub-pixel region A2 to connect with the pixel electrode 14; a portion of the second electrode 111 may overlap a source doped region of the active layer 112, and another portion of the second electrode 111 may be connected to the data line 16. The first and second poles 110 and 111 are covered with a passivation layer 114.
It should be noted that the transistor 11 of the embodiment of the present disclosure is not limited to the bottom gate type mentioned above, and may also be a top gate type, that is: the gate electrode is formed after the active layer 112 is formed and before the second and first electrodes 111 and 110 are formed, and it is understood that a gate insulating layer 19 is formed between the gate electrode and the active layer 112 and between the gate electrode and the first (second) electrode, respectively; when the transistor 11 is of a top gate type, the second pole 111 and the first pole 110 can pass through via holes respectively: via holes penetrating the two gate insulating layers 19 are connected to opposite ends of the active layer 112.
In one embodiment, as shown in fig. 3, after the transistor 11 is formed, a color resist layer 101 having a red color resist block, a green color resist block, and a blue color resist block may be further formed on the transistor 11, and the color resist layer 101 covers the sub-pixel region and the wiring region. The technology is called COA technology, and is an integrated technology for directly manufacturing the color filter layer on the array substrate, the color filter layer and the TFT array are arranged on the same side, so that the deviation caused by alignment in the box aligning process of the liquid crystal display device can be effectively solved, the design width of the black matrix adopting the COA structure is further reduced, the aperture opening ratio of the liquid crystal display panel is improved, and the transmittance can be obviously improved. Of course, the color resist layer 101 may be formed on the alignment substrate.
After the color resist layer 101 is formed, the aforementioned organic insulating layer 12 may be formed, and the organic insulating layer 12 is entirely disposed on the first substrate 10 and covers the aforementioned color resist layer 101, the active layer 112, the second electrode 111, the first electrode 110, the data line 16, the scan line 17, the common line 18, and the like.
When fabricating the organic insulating layer 12, at least two organic insulating portions with different thicknesses are required to be fabricated, for example: a first organic insulating portion 120 and a second organic insulating portion 121, an orthogonal projection of the first organic insulating portion 120 on the first substrate 10 covering an orthogonal projection of the transistor 11 on the first substrate 10; an orthogonal projection of the second organic insulating part 121 on the first substrate 10 covers an orthogonal projection of the pixel electrode 14 and the common electrode 15 on the first substrate 10; wherein the thickness H1 of the first organic insulating portion 120 is greater than the thickness H2 of the second organic insulating portion 121.
For example, the ratio of the thickness H1 of the first organic insulating portion 120 to the thickness H2 of the second organic insulating portion 121 may be 2 to 4, such as: 2. 2.5, 3, 3.5, 4, etc. Here, the thickness H1 of the first organic insulating part 120 may be 1 μm to 3 μm, such as: 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, and the like; the thickness H2 of the second organic insulating part 121 may be 0.8 μm to 1.5 μm, such as: 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, and the like.
For another example, the thickness of the second organic insulating portion 121 may also be 0, that is, the second organic insulating portion 121 is not disposed in the sub-pixel region, so that the relative distance from the lower surface of the spacer 13 to the sub-pixel region may be increased to the greatest extent, and the spacer 13 may be prevented from scratching the film layer of the sub-pixel region laterally. And the film layers of the sub-pixel regions are reduced, so that the light intensity loss is reduced, and the transmittance of the panel is improved.
Note that, in order to make the organic insulating layer 12 have portions with different thicknesses, the organic insulating layer 12 may be formed by an HTM (Half Tone Mask) process or a GTM (gray Tone Mask). The thicknesses of the first and second organic insulating parts 120 and 121 may be achieved by controlling process parameters. In the embodiment of the present disclosure, in conjunction with fig. 2 and 3, the pixel electrode 14 and the common electrode 15 of each sub-pixel unit are located on the first substrate 10, and at least a portion of the pixel electrode 14 and the common electrode 15 in each sub-pixel unit is located in one sub-pixel area A2. Wherein, the orthographic projection of the pixel electrode 14 on the first substrate 10 is partially overlapped with the orthographic projection of the common electrode 15 on the first substrate 10, and the pixel electrode 14 is connected with the first pole 110 of the transistor 11; specifically, one of the pixel electrode 14 and the common electrode 15 is located on a side of the organic insulating layer 12 close to the first substrate 10, and the other is located on a side of the organic insulating layer 12 away from the first substrate 10.
For example, the common electrode 15 and the pixel electrode 14 of the embodiment of the disclosure may be located on a side of the organic insulating layer 12 away from the first substrate 10, that is: forming an organic insulating layer 12 on a first substrate 10, and then forming a pixel electrode 14 and a common electrode 22; the pixel electrode 14 may be connected to the first electrode 110 of the transistor 11 through a via structure (not shown) on the organic insulating layer 12, and the common electrode 22 may be connected to the common line through a via structure (not shown) on the organic insulating layer 12.
The common electrode 15 and the pixel electrode 14 in the embodiment of the present disclosure are transparent electrodes, and may be made of ITO (indium tin oxide), but not limited thereto, and may also be made of transparent materials such as Indium Zinc Oxide (IZO) and zinc oxide (ZnO).
As shown in fig. 2, the pixel electrode 14 may have a plurality of first electrode stripes arranged at intervals in the row direction X, and the first electrode stripes may be disposed on the sub-pixel area A2; it will be appreciated that the ends of the first electrode strips on the same side may be interconnected so that the pixel electrode as a whole has a "comb" like shape.
The first electrode strip can be integrally bent, and the bending angle alpha 1 of the first electrode strip is 150-170 degrees, specifically, the first electrode strip can comprise two parts, and the included angle alpha 1 between the two parts is 150-160 degrees; such as: 150 °, 156 °, 162 °, 166 °, 170 °, etc.; in other words, the angles α 2, α 3 between the extension direction of the two-part structure and the column direction Y are respectively 5 ° to 15 °, such as: 5 °, 7 °, 9 °, 12 °, 15 °, etc.
As shown in fig. 2 and 3, the common electrode 22 may be disposed in the same layer as the pixel electrode 14; for example, the common electrode 22 and the pixel electrode 14 may be transparent electrodes, and the common electrode 22 and the pixel electrode 14 may be made of ITO (indium tin oxide), but are not limited thereto, and may also be IZO (indium zinc oxide) or the like. It will be appreciated that there is a gap (i.e. no contact) between the common electrode 22 and the pixel electrode 14.
As shown in fig. 2, the common electrode 22 may also be configured to be in a shape similar to a "comb", that is, includes a plurality of second electrode stripes arranged at intervals in the row direction X, and the second electrode stripes may be located in the sub-pixel area A2; and the ends of the second electrode bars 220 located on the same side are connected to each other. Therefore, the sub-pixel electrode and the common electrode 22 can be In a mutually inserted state, that is, the array substrate of the embodiment of the disclosure can be In an IPS (In-Plane Switching) mode, and this design can reduce the parasitic capacitance generated between the sub-pixel electrode and the common electrode, thereby improving the pixel charging rate and the aperture ratio; but not limited thereto, the common electrode 22 and the pixel electrode 14 may be located on different layers of the array substrate and disposed opposite to each other, and one of the common electrode 22 and the pixel electrode 14 is a slit electrode having slits, and the other is a plate electrode without slits, that is, the array substrate of the embodiment of the disclosure may also be in FFS (Fringe Field Switching) mode, as the case may be.
Note that the common electrodes 22 of the respective sub-pixels may be connected to each other to form a whole.
In the embodiment of the present disclosure, the second electrode strip may be bent, and the bending angle β 1 thereof is 150 ° to 170 °, and specifically, the second electrode strip may include a two-part structure, and the included angle β 1 between the two-part structure is 150 ° to 160 °; such as: 150 °, 156 °, 162 °, 166 °, 170 °, etc.; in other words, the angles β 2, β 3 between the extension direction of the two-part structure and the column direction Y are respectively 5 ° to 15 °, such as: 5 °, 7 °, 9 °, 12 °, 15 °, and so on.
The second electrode strips and the first electrode strips may be substantially parallel, that is, the bending angle β 1 of the second electrode strips may be the same as the bending angle α 1 of the first electrode strips.
It should be noted that the first electrode stripes and the second electrode stripes in each sub-pixel are not limited to the aforementioned alternating arrangement in the row direction X, but may also be alternating arrangement in the column direction Y, depending on the actual requirement.
In the embodiment of the present disclosure, a row of scan lines 17 and a row of common lines 18 may be disposed on each first wiring area A1, and a column of data lines 16 may be disposed on each second wiring area A3, wherein each row of scan lines 17 is connected to the transistors 11 of the same row of sub-pixel units adjacent thereto; each row of the common lines 18 is overlapped with the common electrodes 15 of the sub-pixel units of the same row adjacent to the common lines; each row of data lines 16 is connected with the second pole 111 of the transistor 11 of the sub-pixel unit positioned in the even-numbered row in the sub-pixel unit of the adjacent row, and is connected with the second pole of the transistor 11 of the sub-pixel unit positioned in the odd-numbered row in the sub-pixel unit of the adjacent other row; but not limited thereto, each column of data lines 16 is connected only to the second pole 111 of the transistors 11 of the sub-pixel units in the same column of sub-pixel units adjacent thereto.
It should be noted that the array substrate 1 of the embodiment of the present disclosure may further include a jumper line (not shown) disposed on the same layer as the data line 16, and the jumper line may connect the common electrodes 15 of two adjacent sub-pixel units in the column direction Y through a via structure.
Since the pixel electrode 14 and the common electrode 15 are connected to other film layers below through the via hole, the via hole needs to be etched in the organic insulating layer 12, the organic insulating layer 12 has a certain loss during the etching process of the via hole, and since the sub-pixel region is protected by the second organic insulating portion 121, the RGB color resistance under the second organic insulating portion 121 is not damaged.
As shown in fig. 3, the array substrate 1 of the embodiment of the disclosure may further include a first alignment layer 102, and the first alignment layer 102 may be located at the topmost layer of the array substrate 1, that is: the first alignment layer 102 is disposed entirely over and covers the pixel electrode 14 and the common electrode 15.
In the embodiment of the present disclosure, the involution substrate may include a second substrate 20 and a shielding layer 21 on a side of the second substrate 20 close to the array substrate 1; the second substrate 20 may have the same structure as the first substrate 10, and the first substrate 10 is described in detail with reference to the foregoing description, but is not limited thereto, and the second substrate 20 may have a different structure from the first substrate 10 as the case may be. The orthographic projection of the blocking layer 21 on the first substrate 10 completely covers the transistors 11, the scan lines 17, the data lines 16, the common lines 18, and the spacers 13, and may also cover the edges of the common electrodes 15 and the pixel electrodes 14. The region where the shielding layer 21 is not provided may be covered with a transparent protective layer 23.
The alignment substrate 2 may further include a second alignment layer 22, and the second alignment layer 22 is disposed on a side of the transparent protective layer 23 away from the second substrate 20 and is disposed in a whole layer. The spacer 13 is formed behind the second alignment layer 22 and on a side of the second alignment layer 22 away from the second substrate 20.
In an embodiment of the present disclosure, the spacer 13 may contact the first alignment layer 102 of the array substrate. Since the height difference between the upper surfaces of the first organic insulating portion 120 and the second organic insulating portion 121 is increased, the relative distance from the lower surface of the spacer 13 to the first alignment layer 102 of the sub-pixel region is also increased, so that the spacer 13 can be prevented from laterally scratching the first alignment layer 102 of the sub-pixel region.
In the embodiment of the present disclosure, a plurality of spacers 13 may be disposed on the array substrate 1 and are divided into a main spacer 1301 and an auxiliary spacer 1302, that is, the spacers 13 of the present disclosure may be the main spacer 1301 or the auxiliary spacer 1302. When the panel does not receive external pressure, two ends of the main spacer 1301 can be respectively contacted with the array substrate 1 and the involution substrate, so that the main spacer has a supporting function; when the display panel does not receive external pressure, if the auxiliary spacer 1302 is formed on the array substrate 1, a certain distance is formed between one side of the auxiliary spacer 1302, which is far away from the first substrate 10, and the opposite substrate, that is, a step height difference exists between the main spacer 1301 and the auxiliary spacer 1302, and the thickness of the display panel can be finely adjusted by adjusting the step height difference between the main spacer 1301 and the auxiliary spacer 1302.
Illustratively, the height of the main spacer 1301 is greater than that of the auxiliary spacer 1302 in the thickness direction of the panel, and the difference between the heights is Δ H ps As shown in fig. 1. When the display panel is subjected to external pressure, the main spacer 1301 first bears all the pressure and compresses, and when the main spacer 1301 is compressed to the height difference Δ H between the main spacer 1301 and the auxiliary spacer 1302 ps When the pressure drops to 0, the main spacer 1301 and the auxiliary spacer 1302 bear the external pressure together.
Referring to fig. 1, the main spacer 1301 is easy to slide laterally under pressure, and the length of the main spacer sliding out in the thickness direction of the display panel is Hshift, which is smaller than Δ H ps . When the main spacer 1301 is not slid, the relative height Δ H between the lower surface and the upper surface of the display region film layer is the height difference Δ H between the surfaces of the first organic insulating portion 120 and the second organic insulating portion 121 far away from the first substrate, when the first organic insulating portion is formedThe height difference Δ H between the portion 120 and the surface of the second organic insulating portion 121 remote from the first substrate is larger than the height difference Δ H between the main spacer 1301 and the auxiliary spacer 1302 ps In this case, Δ H is inevitably larger than Hshift, and even if the main spacer 1301 slips, the lower surface thereof does not contact the sub-pixel region of the first substrate, and thus the display region is not damaged.
The orthographic projection of the spacer 13 on the first substrate 10 of the embodiment of the disclosure is located in the orthographic projection of the first organic insulating part 120 on the first substrate 10, and the specific position thereof may be various.
In one embodiment of the present disclosure, referring to fig. 2 and 3, the first organic insulating part 120 covers the transistor 11, and the orthographic projection of the spacer 13 on the first substrate 10 covers the orthographic projection of the transistor 11 on the first substrate 10. Since the transistor film layer is thick and the upper surface of the transistor film layer is the highest point of the thickness of the array substrate, the height difference between the upper surfaces of the first organic insulating portion 120 and the second organic insulating portion 121 can be maximized.
In another embodiment of the present disclosure, referring to fig. 4 and 5, the first organic insulating part 120 covers the common line 18, and an orthogonal projection of the spacer 13 on the first substrate 10 covers an orthogonal projection of the common line 18 on the first substrate 10. As shown, a portion of the common line 18 is not covered by an overlying film layer, and a spacer 13 can also be provided at this location.
In still another embodiment of the present disclosure, referring to fig. 6 and 7, the first organic insulating part 120 covers the data lines 16 and the scan lines 17, and the orthographic projection of the spacer 13 on the first substrate 10 covers the orthographic projection of part of the data lines 16 and/or part of the scan lines 17 on the first substrate, that is: the front projection of the spacer 13 may cover part of the data line 16, part of the scan line 17, and the overlap between the data line 16 and the scan line 17.
In an embodiment of the present disclosure, referring to fig. 8 and 9, fig. 9 isbase:Sub>A schematic cross-sectional view ofbase:Sub>A-base:Sub>A 'direction andbase:Sub>A B-B' direction in fig. 8, it should be noted that only the color-resist layer, the spacer andbase:Sub>A portion of the signal line are shown in fig. 8, andbase:Sub>A complete film structure is shown in fig. 9. The color resist layer 101 has an opening 1010 in the wiring region, and the projection of the spacer 13 on the first substrate 10 is located within the projection of the opening 1010 on the first substrate 10. Since the color resist layer 101 has the opening 1010, the organic insulating layer 12 and the first alignment layer 102 above both sink to form a notch at a position corresponding to the opening 1010, and then when the spacer 13 is pressed downward and moves toward the array substrate, the spacer extends into and abuts against the notch, and since the peripheral film layer is higher, the end of the spacer 13 can be "covered", thereby further preventing the spacer 13 from sliding laterally to the sub-pixel region. The opening 1010 may or may not penetrate the color resist layer 101.
The projection relationship between the spacer 13 and the first organic insulating section 120 is limited to at least the projection relationship between the main spacer 1301 and the first organic insulating section 120, but the projection relationship between the sub spacer 1302 and the first organic insulating section 120 may satisfy the above limitation.
Fig. 10 is a schematic structural diagram of a display panel including a plurality of spacers. As shown in the figure, the spacers 13 are sequentially arranged in the column direction, and one spacer 13 is disposed between two adjacent sub-pixel regions in the column direction. It should be noted that the spacer 13 is just located between the upper and lower two sub-pixel regions in the figure, and in the structure shown in fig. 6, the spacer 13 is located on one side between the upper and lower two sub-pixel regions, and is close to the upper and lower two sub-pixel regions in an adjacent column, and at this time, it may also be regarded as corresponding to the sub-pixel region in the column. The spacer 13 may be a main spacer 1301 or an auxiliary spacer 1302. Fig. 11 is a schematic diagram illustrating two types of spacers, where M denotes a main spacer, S denotes an auxiliary spacer, and M and S are located in sub-pixel regions, but actually indicate that the main spacer or the auxiliary spacer is located between adjacent sub-pixel regions. The main and auxiliary spacers may be arranged in different ways.
In an embodiment of the present disclosure, at least one column of every three adjacent columns of sub-pixel regions is provided with a spacer 13, and a spacer is disposed between any two adjacent sub-pixel regions in the column provided with the spacer 13. That is, all spacers are arranged between the sub-pixel regions in the column direction, whereby more spacers can be provided to provide more stable and uniform pressure.
Further, in yet another embodiment of the present disclosure, the number of the auxiliary spacers 1302 is greater than that of the main spacers 1301; in every adjacent three rows of sub-pixel regions, at least one row of all spacers 13 is the auxiliary spacer 1302. For example, in the arrangement shown in the figure, two columns of the three adjacent columns of sub-pixel regions are provided with spacers 13, such as a red sub-pixel column and a green sub-pixel column, one spacer 13 is provided between every two adjacent red sub-pixel regions in the column direction, and the spacers 13 are auxiliary spacers 1302; a spacer 13 is also arranged between every two adjacent green sub-pixel areas in the column direction, part of the spacers 13 are main spacers 1301, and the rest of the spacers 13 are auxiliary spacers 1302. No spacer 13 is provided in the blue pixel column. In the present disclosure, the density of the auxiliary spacers 1302 is higher, which can provide more support. The main spacers 1301 are arranged in the auxiliary spacers 1302 at intervals, so that the purpose of uniform distribution is achieved, and uniform supporting force can be provided.
It will be appreciated that in other embodiments, the spacers 13 may be provided in sub-pixel columns of other colours, for example red and blue, green and blue. Of course, the spacers 13 may be provided in only one color subpixel row or in all the color subpixel rows.
In the present disclosure, the projection of the spacer 13 on the first substrate 10 may be rectangular, circular, or elliptical, etc. In the embodiment shown in the figure, the projection of the main spacer 1301 or the auxiliary spacer 1302 on the first substrate 10 is rectangular, and the rectangular spacer has better pressure resistance and is convenient to position in the preparation process.
The size of the spacer may be set according to the size of the space of the wiring area, and when it is circular, its diameter may be 10-30 μm. When it is rectangular, its side length may be 10 to 40 μm. When it is oval, its short diameter may be 10 to 20 μm and its long diameter may be 15 to 30 μm.
The projection of the main spacer 1301 on the first substrate 10 and the distance between the edges of the adjacent sub-pixel regions may affect the risk of damage to the sub-pixel regions when the spacer slips laterally, if the distance is too small, the main spacer 1301 may easily slip to the sub-pixel regions when the lateral slip occurs to cause damage, and if the distance is too large, the cross-sectional area of the spacer is too small on the premise of fixing the pixel size, which makes it difficult to provide sufficient support force. Because the structure of the organic insulating layer 12 provided by the present disclosure can reduce the risk that the main spacer 1301 damages the sub-pixel region to a certain extent, the distance d between the main spacer 1301 and the adjacent sub-pixel region can be set between 15 μm and 50 μm, which can not only further prevent the spacer from damaging the sub-pixel region, but also ensure that the spacer has a sufficient cross-sectional area. In general, the spacer is disposed at a middle position between the upper and lower two sub-pixel regions, and thus is equal to the distance between the edges of the upper and lower two sub-pixel regions, for example, the distance between the spacer and the edge of the upper sub-pixel region is shown in the figure, wherein the distance d between the rectangular main spacer and the edge of the upper sub-pixel region is 42 μm, and the distance d between the rectangular auxiliary spacer and the edge of the upper sub-pixel region is 30.5 μm. Besides, the spacing between the spacer 13 and the upper and lower two adjacent sub-pixel regions can be 15 μm, 20 μm, 25 μm, 35 μm, 45 μm, 50 μm, and the like.
The embodiment of the present disclosure further provides a method for manufacturing a display panel, taking the structure shown in fig. 3 as an example, including the following steps:
step S100, providing a first substrate 10, wherein the first substrate is divided into a sub-pixel area and a wiring area arranged at the periphery of the sub-pixel area; forming a transistor 11 in a wiring region of a first substrate;
step S200, forming an organic insulating layer 12 on the first substrate 10, wherein the organic insulating layer 12 includes a first organic insulating portion 120 and a second organic insulating portion 121, such that the first organic insulating portion 120 covers the wiring region and the transistor 11, and the second organic insulating portion 121 covers the sub-pixel region; wherein the thickness of the first organic insulating portion 120 is greater than the thickness of the second organic insulating portion 121;
step S300, providing a second substrate 20, forming a spacer 13 on a side of the second substrate facing the first substrate, so that an orthographic projection of the spacer 13 on the first substrate is located within an orthographic projection of the first organic insulating portion 120 on the first substrate.
Wherein the forming of the organic insulating layer 12 may include the following substeps:
step S210 of coating an organic insulating material on the first substrate on which the transistor 11 is formed;
in step S220, the organic insulating material is exposed and developed by using a halftone mask or a gray tone mask, so that the remaining thickness of the organic insulating material in the sub-pixel region is smaller than that of the organic insulating material in the wiring region, and the thicker first organic insulating portion 120 and the thinner second organic insulating portion 121 are obtained.
The remaining structures in the figures, such as the transistor 11, the color resistance layer 101, the first alignment layer 102, the second alignment layer 22, etc., can be referred to the above description, and are not repeated herein.
The embodiment of the present disclosure further provides a display device, which includes any of the display panels mentioned in the foregoing embodiments, and repeated descriptions are omitted here. The display device may further include a liquid crystal layer (not shown) between the array substrate 1 and the opposite substrate 2, that is: the display device may be a liquid crystal display device. The liquid crystal molecules of the liquid crystal layer may be negative liquid crystal to increase transmittance, but the liquid crystal layer is not limited thereto and may also be positive liquid crystal.
According to the embodiment of the present disclosure, the specific type of the display device is not particularly limited, and the types of the display devices commonly used in the field may be any, specifically, for example, a liquid crystal display, a mobile phone, a mobile device such as a notebook computer, a wearable device such as a watch, a VR device, and the like, and those skilled in the art may select the display device according to the specific use of the display device, and details are not repeated herein.
It should be noted that the display device includes other necessary components and components besides the display panel, taking the display as an example, the display device may further include a backlight module, a housing, a main circuit board, a power line, and the like, and those skilled in the art may perform corresponding supplementation according to the specific use requirements of the display device, and details are not repeated herein.
It should be noted that "formed on" 8230, "8230" "," formed on "8230," "formed on" 8230, "provided on" 8230 "", and "provided on" may mean that one layer is directly formed or provided on the other layer, or that one layer is indirectly formed or provided on the other layer, that is, that other layers are present between the two layers.
The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.
It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, components, elements, regions, layers and/or sections, these elements, components, elements, regions, layers and/or sections should not be limited by these terms. Rather, these terms are used to distinguish one element, component, element, region, layer or section from another.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice in the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (20)

1. The display panel is characterized by comprising an array substrate and an opposite substrate which are oppositely arranged, wherein the array substrate comprises:
a first substrate (10) including a sub-pixel region and a wiring region provided in the periphery of the sub-pixel region;
the transistor (11) is arranged on the first substrate (10) and is positioned in the wiring area;
an organic insulating layer (12) formed on the first substrate (10), including a first organic insulating portion (120) and a second organic insulating portion (121), the first organic insulating portion (120) covering the wiring region and the transistor (11), the second organic insulating portion (121) covering the sub-pixel region, a thickness of the first organic insulating portion (120) being greater than a thickness of the second organic insulating portion (121);
wherein, the involution base plate comprises:
a second substrate (20), the second substrate (20) being disposed opposite to the first substrate (10);
and the spacer (13) is formed on one side of the second substrate (20) facing the first substrate (10), and the orthographic projection of the spacer (13) on the first substrate (10) is positioned in the orthographic projection of the first organic insulating part (120) on the first substrate (10).
2. The display panel according to claim 1, wherein the display panel comprises a plurality of the spacers (13), the spacers (13) are main spacers (1301) or auxiliary spacers (1302), and the height of the main spacers (1301) is larger than the height of the auxiliary spacers (1302) in the thickness direction of the display panel;
wherein a height difference DeltaH of the surfaces of the first organic insulating part (120) and the second organic insulating part (121) far away from the first substrate is larger than that of the main spacer (1301) and the auxiliary spacer (1302) ps 。
3. The display panel according to claim 2, wherein the array substrate further comprises:
scanning lines (17) arranged on the first substrate (10) and arranged in the wiring area along a row direction;
data lines (16) provided on the first substrate (10) and arranged in the wiring region in a column direction;
common lines (18) provided on the first substrate (10) and arranged in the line direction at the wiring regions;
a pixel electrode (14) and a common electrode (15) both provided on the first substrate (10), the common electrode (15) being electrically connected to the common line (18);
the transistor (11) comprises a grid electrode, a first pole and a second pole, the grid electrode is electrically connected with the scanning line (17), and the first pole is electrically connected with the data line (16); the second pole is electrically connected with the pixel electrode (14);
wherein the scanning line (17), the data line (16), the common line (18) and the transistor (11) are all positioned on one side of the organic insulating layer (12) facing the first substrate (10), and the pixel electrode (14) and the common electrode (15) are all positioned on one side of the organic insulating layer (12) far away from the first substrate (10).
4. A display panel as claimed in claim 3 characterized in that the first organic insulating part (120) covers the transistors (11) and the orthographic projection of the spacers (13) on the first substrate (10) covers the orthographic projection of the transistors (11) on the first substrate (10).
5. A display panel according to claim 3 characterized in that the first organic insulation (120) covers the common lines (18) and the orthographic projection of the spacers (13) on the first substrate (10) covers the orthographic projection of the common lines (18) on the first substrate (10).
6. The display panel according to claim 3, wherein the first organic insulating portion (120) covers the data lines (16) and the scan lines (17), and an orthogonal projection of the spacer (13) on the first substrate (10) covers a part of the data lines (16) and/or a part of the scan lines (17) on the first substrate (10).
7. The array substrate of claim 2, wherein a ratio of a thickness of the first organic insulating portion (120) to a thickness of the second organic insulating portion (121) is 2 to 4.
8. The display panel according to claim 7, wherein the first organic insulating portion (120) has a thickness of 2 to 4 μm; the second organic insulating portion (121) has a thickness of less than 2 [ mu ] m.
9. The display panel according to claim 2, wherein the second organic insulating portion (121) has a thickness of 0.
10. The display panel according to claim 2, wherein the first substrate (10) comprises a plurality of sub-pixel regions arranged in an array along a row direction and a column direction, and the spacers (13) are arranged between two adjacent sub-pixel regions along the column direction;
at least one column of the three adjacent columns of the sub-pixel areas is provided with the spacer (13), and one spacer (13) is arranged between any two adjacent sub-pixel areas in one column provided with the spacer (13).
11. The display panel according to claim 10, wherein the plurality of spacers (13) comprises a plurality of main spacers (1301) and a plurality of auxiliary spacers (1302), the number of auxiliary spacers (1302) being greater than the number of main spacers (1301);
in every three adjacent columns of the sub-pixel areas, at least one column of all the spacers (13) are the auxiliary spacers (1302).
12. A display panel as claimed in claim 1 characterized in that the projection of the spacer (13) on the first substrate (10) is rectangular, circular or elliptical.
13. A display panel as claimed in claim 12 characterized in that the spacers (13) have a projection onto the first substrate (10) with a spacing of 15-50 μm from the adjacent edges of the sub-pixel areas.
14. The display panel of claim 1, wherein the array substrate further comprises:
and the color resistance layer (101) is arranged on the first substrate (10) and is positioned on one side, close to the first substrate (10), of the organic insulation layer (12), and the color resistance layer covers the sub-pixel area and at least part of the wiring area.
15. The display panel according to claim 14, wherein the color resist layer (101) has an opening (1010) at the wiring region, the organic insulating layer (12) is depressed at the opening of the color resist layer, and a projection of the spacer (13) on the first substrate (10) is located within a projection of the opening (1010) on the first substrate (10).
16. A display panel according to claim 3, characterized in that the common electrode (15) and the pixel electrode (14) are both located on a side of the organic insulating layer (12) remote from the first substrate (10);
the pixel electrode (14) is provided with a plurality of first electrode strips which are arranged at intervals in the row direction;
the common electrode (15) and the pixel electrode (14) are arranged at the same layer, the common electrode (15) is provided with a plurality of second electrode strips which are arranged at intervals in the row direction, the second electrode strips and the first electrode strips are alternately arranged in the row direction, and gaps are formed between the second electrode strips and the first electrode strips; the common electrode (15) is connected to the common line (18) through a via hole.
17. The display panel of claim 16, wherein the array substrate further comprises:
the liquid crystal layer is arranged between the array substrate and the involutory substrate;
the first alignment layer (102) is arranged on the first substrate (10) and covers one side, away from the first substrate (10), of the common electrode (15) and the pixel electrode (14);
and the second alignment layer (22) is arranged on the second substrate (20) and is positioned between the spacer (13) and the second substrate (20).
18. A method for manufacturing a display panel, comprising:
providing a first substrate, wherein the first substrate is divided into a sub-pixel area and a wiring area arranged on the periphery of the sub-pixel area;
forming a transistor in a wiring region of the first substrate;
forming an organic insulating layer on the first substrate, the organic insulating layer including a first organic insulating portion and a second organic insulating portion, the first organic insulating portion covering the wiring region and the transistor, the second organic insulating portion covering the sub-pixel region; wherein a thickness of the first organic insulating portion is greater than a thickness of the second organic insulating portion;
providing a second substrate;
and forming a spacer on one side of the second substrate facing the first substrate, wherein an orthographic projection of the spacer on the first substrate is positioned in an orthographic projection of the first organic insulating part on the first substrate.
19. The method for manufacturing a display panel according to claim 18, wherein the forming of the organic insulating layer comprises:
coating an organic insulating material on the first substrate on which the transistor is formed;
and exposing and developing the organic insulating material by adopting a half-tone mask photomask or a gray-scale tone mask photomask to ensure that the remaining thickness of the organic insulating material in the sub-pixel area is smaller than that of the organic insulating material in the wiring area.
20. A display device characterized by comprising the display panel according to any one of claims 1 to 17.
CN202110452845.4A 2021-04-26 2021-04-26 Display panel, preparation method thereof and display device Pending CN115327823A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110452845.4A CN115327823A (en) 2021-04-26 2021-04-26 Display panel, preparation method thereof and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110452845.4A CN115327823A (en) 2021-04-26 2021-04-26 Display panel, preparation method thereof and display device

Publications (1)

Publication Number Publication Date
CN115327823A true CN115327823A (en) 2022-11-11

Family

ID=83911897

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110452845.4A Pending CN115327823A (en) 2021-04-26 2021-04-26 Display panel, preparation method thereof and display device

Country Status (1)

Country Link
CN (1) CN115327823A (en)

Similar Documents

Publication Publication Date Title
US7477345B2 (en) Liquid crystal display and method for manufacturing the same
US8400606B2 (en) Liquid crystal display apparatus and method of manufacturing the same
US7548299B2 (en) Flat display panel with a spacer unit to prevent displacement between upper and lower glass substrates
US6912024B2 (en) Array substrate of liquid crystal display device having thin film transistor on color filter structure and method of fabricating the same
US7859629B2 (en) In-plane switching mode liquid crystal display wherein the upper and lower pixel electrodes are arranged on opposite sides of the respective upper and lower pixel regions
US8390753B2 (en) Thin film transistor array panel and liquid crystal display having the same
US20060256269A1 (en) Array substrate for in-plane switching liquid crystal display device and method of fabricating the same
US20050270446A1 (en) Liquid crystal display device having structure of color filter on TFT and using in plane switching mode
US9075269B2 (en) Array substrate and liquid crystal display device including the same
JP2020532755A (en) Array boards, display panels, display devices
KR20000029318A (en) Active matrix liquid crystal display apparatus
KR20130015737A (en) Liquid crystal display device
US9857620B2 (en) Display device
CN101165581A (en) In-plane switching mode liquid crystal display device and method of fabricating the same
CN214375724U (en) Display panel and electronic device
KR101383703B1 (en) Thin film transistor array panel and manufacturung method thereof
KR20070002801A (en) Method of forming fine pattern, liquid crystal display using the same, and fabricating method thereof
US6661477B2 (en) TFT-LCD having dummy gate electrode and dummy gate insulator
US8564747B2 (en) Liquid crystal display device
US8304768B2 (en) Thin film transistor array substrate and method for manufacturing the same
US20050248700A1 (en) Substrate for liquid crystal display and liquid crystal display having the same
CN111580296B (en) Array substrate, display panel and display device
KR20070002758A (en) Method of forming fine pattern, liquid crystal display using the same, and fabricating method thereof
CN111490055B (en) Pixel array substrate
CN115327823A (en) Display panel, preparation method thereof and display device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination