CN1153274C - Method for forming semiconductor metal inner conductive wire - Google Patents
Method for forming semiconductor metal inner conductive wire Download PDFInfo
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- CN1153274C CN1153274C CNB011192348A CN01119234A CN1153274C CN 1153274 C CN1153274 C CN 1153274C CN B011192348 A CNB011192348 A CN B011192348A CN 01119234 A CN01119234 A CN 01119234A CN 1153274 C CN1153274 C CN 1153274C
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- metal interconnecting
- formation metal
- layer
- mask layer
- dielectric layer
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Abstract
The present invention relates to a method for forming semiconductor metal interconnectors, which comprises the steps: after a concave hole which has a round angle on the upper end and is tapered downwards is formed by using the great wet etching speed difference between a hydrogen silsesquioxane (HSQ) layer cured by electron beams and an HSQ cured by heat in cooperation with the wet etching technology, conductor materials, such as metal, or polysilicon, etc., are filled in the concave hole so as to form a metal interconnector structure, such as a viaplug, a contact plug, or a damascene trench structure, etc. The method of the present invention not only enables the metal filling procedure to be easily carried out, but also enables the critical dimension (CD) of the semiconductor assembly formed by the present invention to be easily controlled.
Description
The present invention relates to a kind of method that forms semiconductor subassembly, refer to a kind of method that forms metal intraconnection wire in semiconductor especially.
In the manufacture of semiconductor technology, the etch process technology is to belong to a main manufacture process now.So-called etch process; promptly be after thin film deposition and lithographic process end; with the film that deposits before the lithographic process the part that do not covered or protect by photoresist, removed with chemical reaction or physical action, shift the purpose of mask pattern to the film to finish.The etching technique of extensive use now mainly contains two kinds: a kind of is Wet-type etching (wet etch), mainly is to utilize chemical reaction to carry out the etching of film; Another kind is dry-etching (dryetch), mainly is to utilize physical action to carry out the etching of film.
With plasma reaction formula ion-etching (plasma reactive ion etch, plasma RIE) thisly compares between the dry-etching technology and the wet etching that splash etching and plasma etching, wet etching has the following advantages: (1) is because RIE utilizes plasma to carry out etching, so can cause to a certain degree injury to bottom, and Wet-type etching is to utilize chemical reaction to carry out etching, can not damage bottom.(2) selectivity of wet etching (selectivity) is far above RIE.(3) utilize Wet-type etching can cause the effect of upper end fillet (top corner rounding) automatically.
Yet, because Wet-type etching is the engraving method of a kind of isotropism (isotropic), when Wet-type etching is used in interlayer hole etching (via etching), contact hole etching (contact etching) or forms in the application of inserted irrigation canals and ditches structure metal interconnecting processing procedures such as (damascene trench structure), can be because Wet-type etching has isotropic relation, and cause its live width evenness (critical dimension, CD) unmanageable shortcoming, have influence on the carrying out of successive process, also so significantly reduced the qualification rate of producing.
The object of the present invention is to provide a kind of method that forms metal intraconnection wire in semiconductor, can make formed semiconductor subassembly have preferable live width evenness (critical dimension) control.
Another object of the present invention is to provide a kind of method that forms metal intraconnection wire in semiconductor, can form a pothole that has down reduction and a tool upper end fillet, in order to the carrying out of follow-up metal filled processing procedure.
For achieving the above object, a kind of method that forms metal intraconnection wire in semiconductor is characterized in, it comprises the following steps: that (a) forms a dielectric layer on the semiconductor device; (b) form a mask layer on described dielectric layer; (c) to partly not made cured by the described dielectric layer that described mask layer hid; (d) remove the described dielectric layer of described mask layer and some to form a pothole; And (e) conductive material is packed in the described pothole.
The conception according to the present invention, described dielectric layer is that a spin-on glasses (spin-on-glass, SOG) form by material.
The conception according to the present invention, described spin-on glasses material is that (hydrogensilsesquioxane, HSQ), its thickness is between 200 to 2000nm for half as much again oxygen silicon hydrate.
According to the present invention the conception, described dielectric layer after the formation further Celsius 300 to 500 the degree between, handle with a hot curing (thermally cure) method.
The conception according to the present invention, described mask layer is a hard mask layer (hard mask), and its thickness is between 20 to 1000nm.
The preferably, described hard mask layer is a polysilicon (poly-si), oxide layer (oxide), silicon nitride (Si
3N
4), silicon oxynitride (SiON), titanium nitride (TiN), titanium oxynitrides (TiON), aluminium oxide (Al
2O
3), carborundum (SiC) is wherein a kind of.
The conception according to the present invention, (c) is preceding in step, still comprise following steps: (b1) form a photoresist layer on described mask layer, (b2) remove a part of described mask layer, and (b3) remove described photoresist layer according to defined pattern on the described photoresist layer.
The conception according to the present invention, wherein in step (b2), removing partly, the method for described mask layer is a plasma dry-etching method (plasma etch).
The conception according to the present invention, wherein the described cured of step (c) is that an electronic beam curing (e-beamcure) is handled.
The conception according to the present invention, the substrate temperature when described electronic beam curing is handled is between 300 to 500 degree Celsius, and electron-beam dose is between 1000 to 10000 μ C/cm
2Between, electron beam energy is between 1 to 20Kev, and its value can be adjusted with the thickness of hsq layer.
The conception according to the present invention, described mask layer are to grind method (chemical-mechanicalpolishing) or a plasma reactive ion etch method (Plasma RIE) removes with a chemical machinery.
The conception according to the present invention, wherein removing a part of described dielectric layer is to remove with a wet etching (wet etch), and described wet etching is with the hydrofluoric acid (diluted HF) of a dilution or the buffered hydrofluoric acid (diluted BHF) of a dilution is the chemical solution of wet etching.
Certainly, described wet etching to through the etch-rate of the described dielectric layer behind the electronic beam curing much smaller than etch-rate to the described dielectric layer after hot curing.
According to the present invention the conception, wherein said pothole be for down reduce and have the upper end fillet.
The conception according to the present invention, wherein said pothole is to be an interlayer hole, a contact hole or an inserted irrigation canals and ditches structure (damascene trench structure).
The conception according to the present invention, described conductive material is a metal or a polysilicon.
Because the present invention utilizes HSQ to be dielectric material, and utilization different great characteristic of Wet-type etching speed difference through between the hsq layer behind hot curing and the electronic curing, the technology that cooperates Wet-type etching is to form the structure of metal interconnecting, described structure not only has the characteristic of easy filling metal material, make that more (criticaldimension CD) controls the live width evenness easily.
Be clearer understanding purpose of the present invention, characteristics and advantage, the present invention is described in detail below in conjunction with accompanying drawing.
Figure 1A to Fig. 1 D is the processing procedure of formation metal intraconnection wire in semiconductor of the present invention.
The present invention adopts with HSQ to come as dielectric material.HSQ (hydrogen silsesquioxane) is a kind of inorganic spin-on glasses (inorganic spin-on glass) material, be used at present on preceding metal dielectric layer (pre-metal dielectric) and the inner metal dielectric layer (inter-metal dielectric), HSQ does not have and need just handle and can the oneself reach splendid planarization through etch-back, and can change into the plurality of advantages of silicon dioxide after suitable temper.In addition, HSQ can be cured (e-beam cure) so that its structure is more fine and close with electron beam under the temperature that is lower than 400 degree Celsius.Can find on the experimental data that the Wet-type etching speed through the HSQ behind the electronic beam curing will be much smaller than a Wet-type etching speed through the HSQ after the hot curing, the present invention be based on utilize the etched plurality of advantages of traditional wet to cooperate will be much smaller than only through the characteristic of the Wet-type etching speed of the HSQ after the hot curing through the Wet-type etching speed of the HSQ behind the electronic beam curing, with the HSQ after the hot curing is after dielectric material imposes electronic beam curing, carry out again Wet-type etching with form one reduce downwards and have the upper end fillet pothole, like this, follow-up metal filled processing procedure will be easier to carry out, and its live width evenness also is easier to control.
See also Figure 1A-D, they are the schematic diagrames for formation metal interconnecting processing procedure of the present invention.At first, with rotary coating method (spin coating) deposition one thickness be 200 to 2000nm hsq layer 13 on semiconductor device.Described hsq layer 13 meeting self-actualization planarizations are done hot curing with the temperature of taking the photograph formula 300 to 500 degree to described hsq layer 13 afterwards and are handled, and disengage with the aqueous vapor and the solvents that will residue in the hsq layer 13.Then, depositing a layer thickness thereon is 20 to 1000nm hard mask layer (hard mask) 12.Described hard mask layer 12 can be a polysilicon (poly-si), oxide layer (oxide), silicon nitride (Si
3N
4), silicon oxynitride (SiON), titanium nitride (TiN), titanium oxynitrides (TiON), aluminium oxide (Al
2O
3), carborundum (SiC) is wherein a kind of.
Then, coating one deck photoresist 11 (photoresist) on described hard mask layer 12.The pattern that has desire formation metal interconnecting on the described photoresist 11, utilize defined pattern on the photoresist 11, with the dry-etching method that plasma etching (plasma etch) is so described hard mask layer 12 is implemented etching, and obtain the structure shown in Figure 1A.
After etching finishes, residue after photoresist 11 and the etching is removed, shown in Figure 1B, impose an electron beam 14 by the external world, hsq layer 15 structures in the zone do not contained by described hard mask layer 12 are made electronic beam curing handle, make its structure become finer and close.And substrate temperature (being about 300-500 degree Celsius), electron-beam dose when carrying out electronic beam curing (are about 1000-10000 μ C/cm
2) can adjust along with the thickness of hsq layer with electron beam energy (being about 1-20 Kev).
Moreover, with described hard mask layer 12 with chemical mechanical milling method (Chemical-mechanicalpolishing, CMP) or after plasma reaction formula ion-etching (Plasma RIE) removes, the chemical solution that is Wet-type etching with the hydrofluoric acid (diluted HF) or the buffered hydrofluoric acid (diluted BHF) of dilution of dilution is not to being imposed etching by the hsq layer of electronic beam curing.Because the etching speed of Wet-type etching differs very big between the hsq layer of hot curing and the hsq layer of electronic curing, add the isotropism speciality that Wet-type etching itself has, the side profile of formed pothole 16 (profile) will be reduction downwards, fillet can appear in its upper end simultaneously, shown in Fig. 1 C.Thus, the value of its live width evenness (CD) can be easy to Be Controlled, also can not damage bottom as plasma reaction formula ion-etching.
After etching finishes, carry out the processing procedure of metal filled then, shown in Fig. 1 D, metal or polysilicon (poly-si) etc. can be clogged in pothole by the material when conductive material in semiconductor.Have the structure of fillet because formed pothole is a reduction downwards and upper end, conductive material 17 can be entered by filling at an easy rate and be formed an interlayer connector (via plug), contact plunger (contact plug) or inserted irrigation canals and ditches structure (damascene trench structure).
Certainly, above-mentioned dielectric material is not limited to only available HSQ, and any have through the Wet-type etching speed behind the electronic beam curing much smaller than only through the SOG material of the Wet-type etching speed after the hot curing, all can be used to be used as dielectric material of the present invention.
In sum, the present invention utilizes HSQ to be dielectric material, and utilization different great characteristic of Wet-type etching speed difference through between the hsq layer behind hot curing and the electronic curing, the technology that cooperates Wet-type etching is to form the structure of metal interconnecting, described structure not only has the characteristic of easy filling metal material, make that more (criticaldimension CD) controls the live width evenness easily.
Claims (25)
1. a method that forms metal intraconnection wire in semiconductor is characterized in that it comprises the following steps:
(a) form a dielectric layer on the semiconductor device;
(b) form a mask layer on described dielectric layer, it comprises the following steps:
(b1) form a photoresist layer in described mask layer;
(b2) remove a part of described mask layer according to defined pattern on the described photoresist layer; And
(b3) remove described photoresist layer;
(c) handle partly not made electronic beam curing by the described dielectric layer that described mask layer hid;
(d) remove the described dielectric layer of described mask layer and some to form a pothole; And
(e) conductive material is packed in the described pothole.
2. the method for formation metal interconnecting as claimed in claim 1 is characterized in that, described dielectric layer by a spin-on glasses (Spin-on-glass) (SOG) material formed.
3. the method for formation metal interconnecting as claimed in claim 2 is characterized in that, described spin-on glasses material be for half as much again oxygen silicon hydrate (hydrogen silsesquioxane, HSQ).
4. the method for formation metal interconnecting as claimed in claim 3 is characterized in that, the thickness of described sesquialter oxygen silicon hydrate layer between 200 to 2000nm.
5. the method for formation metal interconnecting as claimed in claim 1 is characterized in that, (b) is preceding in described step, and described dielectric layer is further handled with a hot curing (thermally cure) method after formation.
6. the method for formation metal interconnecting as claimed in claim 5 is characterized in that, described thermal curing method is that the temperature between 300 to 500 degree Celsius is carried out.
7. the method for formation metal interconnecting as claimed in claim 1 is characterized in that, described mask layer is a hard mask layer (hard mask).
8. the method for formation metal interconnecting as claimed in claim 7 is characterized in that, the thickness of described hard mask layer is between 20 to 1000nm.
9. the method for formation metal interconnecting as claimed in claim 7 is characterized in that, described hard mask layer can be a polysilicon (poly-si), oxide layer (oxide), silicon nitride (Si
3N
4), silicon oxynitride (SiON), titanium nitride (TiN), titanium oxynitrides (TiON), aluminium oxide (Al
2O
3), carborundum (SiC) is wherein a kind of.
10. the method for formation metal interconnecting as claimed in claim 1 is characterized in that, the method that removes a part of described mask layer of described step (b2) is a plasma dry-etching method (plasma etch).
11. the method for formation metal interconnecting as claimed in claim 1 is characterized in that, the described cured of described step (c) is that an electronic beam curing (e-beam cure) is handled.
12. the method for formation metal interconnecting as claimed in claim 11 is characterized in that, the substrate temperature when described electronic beam curing is handled is between 300 to 500 degree Celsius.
13. the method for formation metal interconnecting as claimed in claim 11 is characterized in that, the electron-beam dose when described electronic beam curing is handled is between 1000 to 10000 μ C/cm
2Between.
14. the method for formation metal interconnecting as claimed in claim 11 is characterized in that, the electron beam energy when described electronic beam curing is handled is between 1 to 20Kev.
15. the method for formation metal interconnecting as claimed in claim 1 is characterized in that, described step (d), and described mask layer is to grind method (chemical-mechanical polishing) with a chemical machinery to remove.
16. the method for formation metal interconnecting as claimed in claim 1 is characterized in that, in described step (d), described mask layer is to remove with a plasma reactive ion etch method (Plasma RIE).
17. the method for formation metal interconnecting as claimed in claim 1 is characterized in that, in described step (d), removing a part of described dielectric layer is to remove with a wet etching (wet etch).
18. the method for formation metal interconnecting as claimed in claim 18 is characterized in that, described wet etching be with one the dilution hydrofluoric acid (diluted HF) or one the dilution buffered hydrofluoric acid (diluted BHF) be the chemical solution of wet etching.
19. the method for formation metal interconnecting as claimed in claim 17 is characterized in that, described wet etching to through the etch-rate of the described dielectric layer behind the electronic beam curing much smaller than etch-rate to the described dielectric layer after hot curing.
20. the method for formation metal interconnecting as claimed in claim 1 is characterized in that, described pothole be for down reduce and have the upper end fillet.
21. the method for formation metal interconnecting as claimed in claim 21 is characterized in that, described pothole is an interlayer hole.
22. the method for formation metal interconnecting as claimed in claim 21 is characterized in that, described pothole is a contact hole.
23. the method for formation metal interconnecting as claimed in claim 20 is characterized in that, described pothole is an inserted irrigation canals and ditches structure.
24. the method for formation metal interconnecting as claimed in claim 1 is characterized in that, described conductive material is a metal.
25. the method for formation metal interconnecting as claimed in claim 1 is characterized in that, described conductive material is a polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011192348A CN1153274C (en) | 2001-05-14 | 2001-05-14 | Method for forming semiconductor metal inner conductive wire |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011192348A CN1153274C (en) | 2001-05-14 | 2001-05-14 | Method for forming semiconductor metal inner conductive wire |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1385891A CN1385891A (en) | 2002-12-18 |
| CN1153274C true CN1153274C (en) | 2004-06-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011192348A Expired - Lifetime CN1153274C (en) | 2001-05-14 | 2001-05-14 | Method for forming semiconductor metal inner conductive wire |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100345276C (en) * | 2004-05-19 | 2007-10-24 | 上海宏力半导体制造有限公司 | Method for reducing leakage current between copper double inlaying processing lines |
| CN100350589C (en) * | 2005-01-18 | 2007-11-21 | 旺宏电子股份有限公司 | Shallow trench isolation method forming round corners by cleaning |
| CN100594434C (en) * | 2007-12-27 | 2010-03-17 | 中国科学院物理研究所 | Method for manufacturing nano-sized metal structure with large area covered by metal film |
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2001
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| Publication number | Publication date |
|---|---|
| CN1385891A (en) | 2002-12-18 |
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Granted publication date: 20040609 |