CN115312471A - Preparation method of ceramic substrate, chip packaging method and structure - Google Patents
Preparation method of ceramic substrate, chip packaging method and structure Download PDFInfo
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- CN115312471A CN115312471A CN202210994931.2A CN202210994931A CN115312471A CN 115312471 A CN115312471 A CN 115312471A CN 202210994931 A CN202210994931 A CN 202210994931A CN 115312471 A CN115312471 A CN 115312471A
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- 239000000919 ceramic Substances 0.000 title claims abstract description 205
- 239000000758 substrate Substances 0.000 title claims abstract description 158
- 238000000034 method Methods 0.000 title claims abstract description 35
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 24
- 238000002360 preparation method Methods 0.000 title abstract description 14
- 230000017525 heat dissipation Effects 0.000 claims abstract description 116
- 229910052751 metal Inorganic materials 0.000 claims abstract description 94
- 239000002184 metal Substances 0.000 claims abstract description 94
- 239000000945 filler Substances 0.000 claims abstract description 33
- 238000005245 sintering Methods 0.000 claims abstract description 12
- 238000009826 distribution Methods 0.000 claims description 38
- 229910052573 porcelain Inorganic materials 0.000 claims description 21
- 239000006185 dispersion Substances 0.000 claims description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 239000011733 molybdenum Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 12
- 229910010293 ceramic material Inorganic materials 0.000 description 9
- 230000008569 process Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 230000004907 flux Effects 0.000 description 5
- 238000004364 calculation method Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3731—Ceramic materials or glass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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Abstract
The invention provides a preparation method of a ceramic substrate, the ceramic substrate, a chip packaging method and a chip packaging structure. The preparation method comprises the following steps: preparing a plurality of heat dissipation through holes at a first preset position on each of the M green ceramic chips; m is a positive integer; filling each heat dissipation through hole on each green ceramic chip by using metal fillers to obtain M green ceramic substrates; and (3) superposing the M raw ceramic substrates, and sintering the superposed M raw ceramic substrates in a preset temperature environment to obtain the ceramic substrates. The ceramic substrate prepared by the preparation method of the ceramic substrate provided by the invention can effectively realize heat dissipation of a large-size chip.
Description
Technical Field
The invention relates to the technical field of chip heat dissipation, in particular to a preparation method of a ceramic substrate, the ceramic substrate, a chip packaging method and a chip packaging structure.
Background
With the increasing integration level of large-scale and very large-scale integrated circuit chips and the increasing process of chip fabrication (for example, from 130nm, 65nm, 28nm to 14 nm), the heat sources on the chips are more and more concentrated and the heat flux density is also increasing, and how to realize the heat dissipation of the chips is a hot research topic in the industry.
At present, for the heat dissipation of a chip using a ceramic package, heat dissipation is generally performed by using a metal heat sink block with higher thermal conductivity in a chip-attached region. However, as the chip area increases, for larger chip size packages, such as chip packages greater than 50mm x 50mm, the corresponding metal heatsink blocks also need to be designed to be correspondingly larger in size (e.g., greater than 50mm x 50mm). However, after the metal heat sink block with large size grade and the co-fired ceramic are welded at high temperature, the risk of thermal matching failure exists; even for chips of larger size, there is a problem that the metal heat sink cannot be directly attached to the chip-attached region.
Disclosure of Invention
The embodiment of the invention provides a preparation method of a ceramic substrate, the ceramic substrate, a chip packaging method and a chip packaging structure, and aims to solve the problem of heat dissipation of a large-size chip in the prior art.
In a first aspect, an embodiment of the present invention provides a method for preparing a ceramic substrate, including:
preparing a plurality of heat dissipation through holes at a first preset position on each of the M green ceramic chips; m is a positive integer;
filling each heat dissipation through hole on each green ceramic chip by using metal fillers to obtain M green ceramic substrates;
and (3) superposing the M raw ceramic substrates, and sintering the superposed M raw ceramic substrates in a preset temperature environment to obtain the ceramic substrates.
In a possible implementation manner, the first preset position includes a first sub-area and a second sub-area;
the first sub-area is a position determined according to a heat flow concentration area in a heat flow distribution area of a target chip, the second sub-area is a position determined according to a heat flow dispersion area in the heat flow distribution area, and the density of the heat dissipation through holes in the first sub-area is greater than that in the second sub-area.
In a possible implementation manner, after filling each heat dissipation through hole on each green ceramic sheet with a metal filler to obtain M green ceramic substrates, the method further includes:
arranging a metal layer on one side of at least one of the M green ceramic substrates to obtain at least one metal ceramic plate;
the M raw porcelain substrates are placed in an overlapping mode, and the M raw porcelain substrates after the M raw porcelain substrates are placed in the overlapping mode are sintered in a preset temperature environment to obtain the ceramic substrates, wherein the ceramic substrates comprise:
and overlapping the at least one metal porcelain plate and the rest of the green porcelain substrate, and sintering the overlapped at least one metal porcelain plate and the rest of the green porcelain substrate in a preset temperature environment to obtain the ceramic substrate.
In a possible implementation manner, the diameter of the heat dissipation through holes is less than 0.20mm, and the hole distance between every two adjacent heat dissipation through holes is between 0.50mm and 2.00mm.
In a possible implementation manner, the material of the metal filler includes tungsten or molybdenum.
In one possible implementation, the preset temperature is a temperature greater than 1500 ℃.
In a second aspect, an embodiment of the present invention provides a ceramic substrate, including: m layers of ceramic chips and metal fillers are stacked; m is a positive integer;
a plurality of heat dissipation through holes are formed in a first preset position on each ceramic chip in the M layers of ceramic chips which are stacked;
and the metal filler is filled in each heat dissipation through hole on each ceramic chip in the M layers of ceramic chips which are stacked.
In a possible implementation manner, the first preset position includes a first sub-area and a second sub-area;
the first sub-area is the position determined according to the heat flow concentration area in the heat flow distribution area of the target chip, the second sub-area is the position determined according to the heat flow dispersion area in the heat flow distribution area, and the density of the heat dissipation through holes in the first sub-area is larger than that in the second sub-area.
In one possible implementation manner, the ceramic substrate in the second aspect further includes: at least one metal layer;
for each of the at least one metal layer, the metal layer is disposed on one side of one of the M tiles.
In a possible implementation manner, the diameter of the heat dissipation through holes is less than 0.20mm, and the hole distance between every two adjacent heat dissipation through holes is between 0.50mm and 2.00mm.
In a third aspect, an embodiment of the present invention provides a chip packaging method, including:
arranging a target chip at a third preset position on the ceramic substrate;
the ceramic substrate adopts the ceramic substrate described in the second aspect and any possible implementation manner; the heat flow distribution area of the target chip corresponds to a first preset position on the ceramic substrate.
In a fourth aspect, an embodiment of the present invention provides a chip packaging structure, including: a ceramic substrate, a target chip;
the target chip is arranged at a third preset position on the ceramic substrate;
the ceramic substrate adopts the ceramic substrate described in the second aspect and any possible implementation manner; the heat flow distribution area of the target chip corresponds to a first preset position on the ceramic substrate.
The embodiment of the invention provides a preparation method of a ceramic substrate, the ceramic substrate, a chip packaging method and a chip packaging structure, wherein the preparation method comprises the following steps: preparing a plurality of heat dissipation through holes at a first preset position on each of the M green ceramic chips; wherein M is a positive integer; filling each heat dissipation through hole on each green ceramic chip by using metal fillers to obtain M green ceramic substrates; and (3) superposing the M green ceramic substrates, and sintering the superposed M green ceramic substrates in a preset temperature environment to obtain the ceramic substrates. According to the embodiment of the invention, the heat dissipation effect of the large-size chip is realized by preparing the plurality of heat dissipation through holes at the first preset position on the green ceramic chip and filling the metal filler in each heat dissipation through hole, so that the chip can be dissipated without pasting the metal heat sink block on the chip bonding area of the co-fired ceramic, and the large-size chip is dissipated without the need of the large-size metal heat sink block, so that the risk of heat matching failure caused by the large-size metal heat sink block arranged on the large-size chip is effectively reduced. Furthermore, the metal which has better heat-conducting property and is matched with the ceramic material is adopted in the chip heat flow density concentrated area, so that the heat of the chip heat flow density concentrated area can be rapidly led out to the external environment, the heat dissipation of the chip is effectively ensured, and the heat dissipation efficiency of the chip is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the embodiments or the prior art description will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings may be obtained according to these drawings without inventive labor.
Fig. 1 is a flow chart of an implementation of a method for manufacturing a ceramic substrate according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a target chip heat source distribution provided by an embodiment of the present invention;
fig. 3 is a schematic diagram of the distribution of the heat dissipating through holes at the first predetermined position according to the embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a ceramic substrate according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of another ceramic substrate according to an embodiment of the present invention;
FIG. 6 is a flowchart of an implementation of a chip packaging method according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a chip package structure according to an embodiment of the invention;
fig. 8 is a schematic diagram of thermal resistances of parts in the chip package structure according to the embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following description is made by way of specific embodiments with reference to the accompanying drawings.
Fig. 1 is a flowchart illustrating a method for manufacturing a ceramic substrate according to an embodiment of the present invention, and as shown in fig. 1, the embodiment of the present invention provides a method for manufacturing a ceramic substrate, including:
s101: preparing a plurality of heat dissipation through holes at a first preset position on each of the M green ceramic chips; m is a positive integer.
In the embodiment, a plurality of heat dissipation through holes are prepared at a first preset position on each of the M green ceramic chips, so that heat dissipation of subsequent large-size chips is facilitated; wherein, the value of M can be 1, 2, 3 or other positive integers.
In one possible implementation, the first preset position includes a first sub-area and a second sub-area.
The first sub-area is a position determined according to a heat flow concentration area in a heat flow distribution area of the target chip, the second sub-area is a position determined according to a heat flow dispersion area in the heat flow distribution area, and the density of the heat dissipation through holes in the first sub-area is larger than that of the heat dissipation through holes in the second sub-area.
In this embodiment, fig. 2 is a schematic diagram of a target chip heat source distribution provided in an embodiment of the present invention; fig. 3 is a schematic diagram of the distribution of the heat dissipation through holes at the first predetermined position according to the embodiment of the present invention; please refer to fig. 2 and fig. 3 together. In fig. 2, the position of the heat flux concentration region 22 in the heat flux distribution region of the target chip 21 is shown in fig. 2. In fig. 3, the first preset position 3 may include: a first sub-area 31 determined according to a heat flow concentration area in the heat flow distribution area of the target chip, and a second sub-area 32 determined according to a heat flow dispersion area in the heat flow distribution area of the target chip; and the density of the heat dissipation vias in the first sub-area 31 is greater than the density of the heat dissipation vias in the second sub-area 32. In this embodiment, after the values of the voltage and the current are estimated according to the usage of the gate in the target chip, the power distribution of the heat source concentration area of the target chip is estimated by using a calculation tool provided by a target chip manufacturer, so as to obtain the accurate heat flow distribution of the target chip. According to the heat flow distribution condition of the target chip, relatively dense heat dissipation through holes are prepared on the first sub-area 31 in the first preset position 3 of each raw ceramic chip correspondingly, relatively sparse heat dissipation through holes are prepared on the second sub-area 32 in the first preset position 3 of each raw ceramic chip, and therefore, the heat emitted by the target chip is led to the external environment according to the actual heating of the target chip correspondingly, so that the heat dissipation of the target chip is realized; the preparation quantity of the heat dissipation through holes is effectively reduced, and the preparation difficulty of the green ceramic substrate is effectively reduced.
S102: and filling each heat dissipation through hole on each green ceramic chip by using metal fillers to obtain M green ceramic substrates.
In this embodiment, for M green ceramic chips on which a plurality of heat dissipation through holes are prepared, metal fillers are filled into each heat dissipation through hole on each green ceramic chip to obtain M green ceramic substrates. In the embodiment, on the basis of not changing the existing ceramic material system, the metal filler which has higher heat-conducting property and is more matched with the ceramic material is utilized to rapidly lead the heat emitted by the chip out to the external environment, so that the heat dissipation of the chip is effectively ensured.
S103: and (3) superposing the M raw ceramic substrates, and sintering the superposed M raw ceramic substrates in a preset temperature environment to obtain the ceramic substrates.
In this embodiment, through stacking the M raw ceramic substrates, each two adjacent layers (i.e., upper and lower layers) of raw ceramic substrates are correspondingly overlapped, a plurality of heat dissipation through holes formed in the raw ceramic substrates are also correspondingly overlapped, and the stacked M raw ceramic substrates are integrally sintered in a preset temperature environment to obtain the ceramic substrate. In the embodiment, the large-size chip can utilize the ceramic substrate for heat dissipation; for example, the total power of the CCD large area array image sensor chip reaches 25W, the size reaches more than 120mm × 120mm, and the pixel unit is also reduced from 5.3um to 3.7um, which leads to more and more concentrated heat sources on the chip and also continuously improves the heat flow density along with the improvement of the chip process integration and the chip process technology, therefore, in the embodiment, the heat dissipation capability of the package shell is increased under the existing ceramic material system, that is, the chip dissipates heat through the ceramic substrate in the embodiment, which not only solves the problem that the large-sized chip (for example, 120mm × 120mm and more) cannot directly attach the metal heat sink block to the chip-adhering region for dissipating heat, meets the heat dissipation requirement of the large-sized chip, but also effectively reduces the risk of heat generation matching failure caused by directly attaching the metal heat sink block below the large-sized chip.
The embodiment of the invention provides a preparation method of a ceramic substrate, which comprises the following steps: preparing a plurality of heat dissipation through holes at a first preset position on each of the M green ceramic chips; wherein M is a positive integer; filling each heat dissipation through hole on each green ceramic chip by using metal fillers to obtain M green ceramic substrates; and (3) superposing the M green ceramic substrates, and sintering the superposed M green ceramic substrates in a preset temperature environment to obtain the ceramic substrates. According to the embodiment of the invention, the heat dissipation effect of the large-size chip is realized by preparing the plurality of heat dissipation through holes at the first preset position on the green ceramic chip and filling the metal filler in each heat dissipation through hole, so that the chip can be dissipated without pasting the metal heat sink block in the chip bonding area of the co-fired ceramic, and the large-size chip is dissipated without the need of the large-size metal heat sink block, so that the risk of heat matching failure caused by the large-size metal heat sink block arranged on the large-size chip is effectively reduced. Furthermore, the metal which has better heat-conducting property and is matched with the ceramic material is adopted in the heat flow density concentrated area of the chip, so that the heat in the heat flow density concentrated area of the chip can be rapidly led out to the external environment, the heat dissipation of the chip is effectively ensured, and the heat dissipation efficiency of the chip is improved.
In a possible implementation manner, after filling each heat dissipation through hole on each green ceramic sheet with a metal filler to obtain M green ceramic substrates, the method further includes:
and arranging a metal layer on one side of at least one of the M raw ceramic substrates to obtain at least one metal ceramic plate.
Placing M raw porcelain substrates in an overlapping manner, and sintering the M raw porcelain substrates after the M raw porcelain substrates are placed in the overlapping manner in a preset temperature environment to obtain a ceramic substrate, wherein the method comprises the following steps:
and (3) overlapping at least one metal porcelain plate and the rest of the green porcelain substrates, and sintering the overlapped at least one metal porcelain plate and the rest of the green porcelain substrates in a preset temperature environment to obtain the ceramic substrates.
In this embodiment, after the M raw ceramic substrates are obtained by filling the metal filler into each heat dissipation through hole on each raw ceramic sheet, a metal layer may be further disposed on one side of at least one raw ceramic substrate among the M raw ceramic substrates, so as to accelerate heat dissipation of the chip, and particularly for a chip heat flow density concentrated region, the metal layer may be disposed to effectively accelerate heat dissipation of the chip heat flow density concentrated region. Moreover, the metal ceramic plate and the green ceramic substrate without the metal layer are superposed, and when the ceramic substrate formed after high-temperature sintering is used for integrating a chip, on one hand, heat emitted by the chip can be led out to the external environment through the plurality of radiating through holes; on the other hand, for a chip with a large heat dissipation capacity, the arrangement of the metal layer can further accelerate the heat dissipation of the chip.
In a possible implementation manner, the diameter of the heat dissipation through holes is less than 0.20mm, and the hole distance between two adjacent heat dissipation through holes is between 0.50mm and 2.00mm.
In this embodiment, fig. 4 is a schematic structural diagram of a ceramic substrate according to an embodiment of the present invention, and for example, the diameter of the heat dissipation through holes 42 on the ceramic substrate may be set to be smaller than 0.20mm, and the hole pitch between two adjacent heat dissipation through holes 42 on the ceramic substrate may be set to be between 0.50mm and 2.00mm. Illustratively, the number of the heat dissipating through holes 42 may be 9 to 100 in a local range of 5.00mm × 5.00mm of a large-sized chip. Further, the height of each heat dissipating through hole 42 may be the same as the height of each green ceramic sheet 41 (or green ceramic substrate), and for example, the height of each heat dissipating through hole 42 may be set to be between 1.50mm and 5.00 mm. In the present embodiment, as shown in fig. 4, for example, the diameter of the heat dissipating through holes 42 may be 0.10mm, and the hole pitch between two adjacent heat dissipating through holes 42 may be 2.00mm. In this embodiment, the high thermal conductivity metalized heat dissipation through hole 42 is used as a heat transmission path under the region where the chip heat flow density is concentrated, so that the heat resistance of the region where the chip heat flow density is concentrated is effectively reduced.
In one possible implementation, the material of the metal filler includes tungsten or molybdenum.
In this embodiment, as shown in fig. 4, the metal filler filled in the heat dissipation through holes 42 may be tungsten or molybdenum, and the multiple heat dissipation through holes 42 prepared on each green ceramic chip 41 are filled with metal tungsten or molybdenum by utilizing the characteristic of good heat conductivity of tungsten or molybdenum, so that the problem of thermal matching failure caused by attaching a metal heat sink below a large-size chip is effectively avoided, and heat dissipation of the chip with high heat flux density in the large-size chip package is further ensured.
In one possible implementation, the preset temperature is a temperature greater than 1500 ℃.
In this embodiment, when the M green ceramic substrates that are stacked are sintered, the preset temperature may be a temperature higher than 1500 ℃. For example, the stacked M green ceramic substrates may be sintered at a temperature of 1500 ℃ or higher to obtain ceramic substrates; furthermore, elements such as chips and the like can be integrated on the ceramic substrate by adopting a thick film process, so that the use of subsequent chips can be met, and the heat dissipation of the chips can be realized.
An embodiment of the present invention further provides a ceramic substrate, including: m layers of ceramic chips and metal fillers are stacked; m is a positive integer.
A plurality of heat dissipation through holes are prepared at a first preset position on each ceramic chip in M layers of ceramic chips which are stacked.
And the metal filler is filled in each heat dissipation through hole on each ceramic chip in the M layers of ceramic chips which are arranged in an overlapping mode.
In this embodiment, the ceramic substrate includes M layers of ceramic tiles and metal filler stacked together, where M may be a positive integer such as 1, 2, or 3. For example, as shown in fig. 4, taking the ceramic substrate comprising 3 layers of tiles 41 stacked, the metal filler is filled in the heat dissipation through holes 42 prepared on each layer of tiles 41. A plurality of heat dissipation through holes 42 are prepared at a first predetermined position on each of the tiles 41 of the 3 layers of tiles 41 placed in superposition, and metal fillers are filled in each of the heat dissipation through holes 42 on each of the layers of tiles 41.
An embodiment of the present invention provides a ceramic substrate, including: m layers of ceramic chips and metal fillers are stacked; m is a positive integer; a plurality of heat dissipation through holes are formed in a first preset position on each ceramic chip in the M layers of ceramic chips which are stacked; and the metal filler is filled in each heat dissipation through hole on each ceramic chip in the M layers of ceramic chips which are arranged in an overlapping mode. According to the embodiment of the invention, the heat dissipation effect of the large-size chip is realized by preparing the plurality of heat dissipation through holes at the first preset position on the green ceramic chip and filling the metal filler in each heat dissipation through hole, so that the chip can be dissipated without pasting the metal heat sink block on the chip bonding area of the co-fired ceramic, and the large-size chip is dissipated without the need of the large-size metal heat sink block, so that the risk of heat matching failure caused by the large-size metal heat sink block arranged on the large-size chip is effectively reduced. Furthermore, the metal which has better heat-conducting property and is matched with the ceramic material is adopted in the heat flow density concentrated area of the chip, so that the heat in the heat flow density concentrated area of the chip can be rapidly led out to the external environment, the heat dissipation of the chip is effectively ensured, and the heat dissipation efficiency of the chip is improved.
In one possible implementation, the first preset position includes a first sub-area and a second sub-area.
The first sub-area is a position determined according to a heat flow concentration area in a heat flow distribution area of the target chip, the second sub-area is a position determined according to a heat flow dispersion area in the heat flow distribution area, and the density of the heat dissipation through holes in the first sub-area is larger than that of the heat dissipation through holes in the second sub-area.
In this embodiment, referring to fig. 2 and fig. 3 together, in fig. 2, the distribution of the heat concentration region 22 in the heat distribution region of the target chip 21 is shown in fig. 2. In fig. 3, the first preset position 3 may include: a first sub-area 31 determined according to a heat flow concentration area in the heat flow distribution area of the target chip, and a second sub-area 32 determined according to a heat flow dispersion area in the heat flow distribution area of the target chip; and the density of the heat dissipation vias in the first sub-area 31 is greater than the density of the heat dissipation vias in the second sub-area 32. In this embodiment, after the values of the voltage and the current are estimated according to the usage of the gate in the chip, the power distribution of the heat source concentration area of the chip is estimated by using a calculation tool provided by a chip manufacturer, so as to obtain the accurate heat flow distribution of the chip. According to the heat flow distribution condition of the chip, relatively dense heat dissipation through holes are prepared on the first sub-area in the first preset position of each raw ceramic chip correspondingly, and relatively sparse heat dissipation through holes are prepared on the second sub-area in the first preset position of each raw ceramic chip, so that the heat dissipated by the chip is guided to the external environment correspondingly according to the actual heat generated by the chip, and the heat dissipation of the chip is realized; the preparation quantity of the heat dissipation through holes is effectively reduced, and the preparation difficulty of the green ceramic substrate is effectively reduced.
In one possible implementation, the ceramic substrate further includes: at least one metal layer.
For each of the at least one metal layer, the metal layer is disposed on one side of one of the M tiles.
In this embodiment, the ceramic substrate further includes at least one metal layer. And, for each of the at least one metal layer, the metal layer is disposed on one side of one of the M layers of tiles. For example, fig. 5 is a schematic structural diagram of another ceramic substrate according to an embodiment of the present invention, and as shown in fig. 5, 2 layers of tiles are stacked in the ceramic substrate in fig. 5: the tiles 511 and 512, and the corresponding heat dissipating through holes 52 in each tile, are filled with metal filler, and a metal layer 53 is provided on the side of the tile 512 adjacent to the tile 511 (or a metal layer 53 is provided on the side of the tile 511 adjacent to the tile 512). The heat dissipation of the chip is further accelerated by arranging the metal layer 53 on one side of the tile in the ceramic substrate.
In a possible implementation manner, the diameter of the heat dissipation through holes is less than 0.20mm, and the hole distance between two adjacent heat dissipation through holes is between 0.50mm and 2.00mm.
In the present embodiment, as shown in fig. 5, for example, on the tile 511, the diameter of the heat dissipating through holes 52 may be 0.10mm, and the hole pitch between two adjacent heat dissipating through holes 52 may be 2.00mm.
The embodiment of the invention also provides a chip packaging method, which comprises the following steps:
s601: and arranging a target chip at a third preset position on the ceramic substrate.
The ceramic substrate is the ceramic substrate in the second aspect and any possible implementation manner; the heat flow distribution area of the target chip corresponds to a first preset position on the ceramic substrate.
In this embodiment, fig. 6 is a flowchart illustrating an implementation of the chip packaging method according to an embodiment of the present invention, and as shown in fig. 6, a target chip is disposed at a third preset position on a ceramic substrate to complete packaging of the target chip. For example, the target chip may be disposed at a third predetermined position on the ceramic substrate by: and arranging the target chip at a third preset position on the ceramic substrate in an adhesive manner. Illustratively, the target chip may be a chip size greater than 50mm and a concentrated heat flux density of 4W/mm 2 The above chip.
The embodiment of the invention provides a chip packaging method, which comprises the following steps: and arranging a target chip at a third preset position on the ceramic substrate. Wherein the ceramic substrate is the ceramic substrate of the second aspect and any possible implementation manner; the heat flow distribution area of the target chip corresponds to a first preset position on the ceramic substrate. According to the ceramic substrate adopted in the embodiment of the chip packaging method, the plurality of heat dissipation through holes are prepared at the first preset position on the green ceramic chip, and the metal filler is filled in each heat dissipation through hole to realize the heat dissipation effect of the large-size chip, so that the heat dissipation of the chip can be realized in a mode of not sticking the metal heat sinking block on the chip sticking area of the co-fired ceramic, and the heat dissipation of the large-size chip naturally does not need the large-size metal heat sinking block, so that the risk of heat matching failure caused by the arrangement of the large-size metal heat sinking block on the large-size chip is effectively reduced. Furthermore, the metal which has better heat-conducting property and is matched with the ceramic material is adopted in the heat flow density concentrated area of the chip, so that the heat in the heat flow density concentrated area of the chip can be rapidly led out to the external environment, the heat dissipation of the chip is effectively ensured, and the heat dissipation efficiency of the chip is improved.
An embodiment of the present invention further provides a chip packaging structure, including: ceramic substrate, target chip.
A target chip is arranged at a third preset position on the ceramic substrate;
the ceramic substrate is the ceramic substrate in the second aspect and any possible implementation manner; the heat flow distribution area of the target chip corresponds to a first preset position on the ceramic substrate.
In this embodiment, fig. 7 is a schematic structural diagram of a chip packaging structure provided in an embodiment of the present invention, as shown in fig. 7. A target chip 702 is disposed at a third predetermined position on the ceramic substrate 701. For example, the third preset position may be a position where the chip is located after the heat flow concentration area in the heat flow distribution area of the target chip 702 is set to correspond to the first sub-area of the first preset position.
Further, in this embodiment, a heat sink 703 may be further disposed on the ceramic substrate 701, so as to further smoothly introduce heat from a region where the heat flow density of the target chip 702 is concentrated and a region where the heat flow density of the target chip 702 is dispersed into an external environment in time, thereby effectively achieving heat dissipation of the target chip 702. Specifically, when the target chip is actually packaged, the package structure with the target chip 702 integrated on the ceramic substrate 701 is usually disposed on a PCB (i.e., a printed/printed circuit board), so that the heat sink 703 may be disposed below a corresponding position of the package structure on the PCB to promote the ceramic substrate 701 to rapidly extract the heat dissipated by the target chip 702 to the external environment. Fig. 8 is a schematic diagram of thermal resistances of various parts in a chip packaging structure according to an embodiment of the present invention, where in fig. 8, C denotes a target chip, R1 denotes a thermal resistance of the target chip, R2 denotes a thermal resistance of a ceramic substrate, R3 denotes a thermal resistance of a heat sink, and T denotes a temperature of an external environment, please refer to fig. 7 and fig. 8 together. On the basis of not changing the existing ceramic material system, the thermal resistance R2 of the ceramic substrate 701 is reduced by improving the thermal conductivity of the heat dissipation channel, and further high-efficiency heat dissipation of the target chip 702 is realized. Moreover, since no metal heat sink is disposed on the target chip 702, the finally formed chip package structure is light in weight. Illustratively, the target chip 702 may be a chip with a chip size between 50mm to 120mm and a total power consumption greater than 10W.
The embodiment of the invention provides a chip packaging structure, which comprises: a target chip is arranged at a third preset position on the ceramic substrate; the ceramic substrate adopts the ceramic substrate in the second aspect and any possible implementation manner; the heat flow distribution area of the target chip corresponds to a first preset position on the ceramic substrate. According to the ceramic substrate adopted in the embodiment of the chip packaging structure, the heat dissipation effect of the large-size chip is realized by preparing the plurality of heat dissipation through holes at the first preset position on the green ceramic chip and filling the metal filler in each heat dissipation through hole, so that the heat dissipation of the chip can be realized without pasting the metal heat sinking block on the chip sticking area of the co-fired ceramic, and the heat dissipation of the large-size chip naturally does not need the large-size metal heat sinking block, so that the risk of heat matching failure problem caused by arranging the large-size metal heat sinking block on the large-size chip is effectively reduced. Furthermore, the metal which has better heat-conducting property and is matched with the ceramic material is adopted in the heat flow density concentrated area of the chip, so that the heat in the heat flow density concentrated area of the chip can be rapidly led out to the external environment, the heat dissipation of the chip is effectively ensured, and the heat dissipation efficiency of the chip is improved.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
The above-mentioned embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein.
Claims (12)
1. A method for manufacturing a ceramic substrate, comprising:
preparing a plurality of heat dissipation through holes at a first preset position on each of the M green ceramic chips; m is a positive integer;
filling each heat dissipation through hole on each green ceramic chip by using metal fillers to obtain M green ceramic substrates;
and (3) superposing the M raw ceramic substrates, and sintering the superposed M raw ceramic substrates in a preset temperature environment to obtain the ceramic substrates.
2. The method according to claim 1, wherein the first predetermined position includes a first sub-area and a second sub-area;
the first sub-area is a position determined according to a heat flow concentration area in a heat flow distribution area of a target chip, the second sub-area is a position determined according to a heat flow dispersion area in the heat flow distribution area, and the density of the heat dissipation through holes in the first sub-area is greater than that in the second sub-area.
3. The method for preparing a ceramic substrate according to claim 1, wherein after filling each heat dissipating through hole of each green ceramic sheet with a metal filler to obtain M green ceramic substrates, the method further comprises:
arranging a metal layer on one side of at least one of the M raw ceramic substrates to obtain at least one metal ceramic plate;
placing M green porcelain substrates in an overlapping manner, and sintering the M green porcelain substrates after the M green porcelain substrates are placed in the overlapping manner in a preset temperature environment to obtain the ceramic substrates, which comprise:
and overlapping the at least one metal porcelain plate and the rest of the green porcelain substrate, and sintering the overlapped at least one metal porcelain plate and the rest of the green porcelain substrate in a preset temperature environment to obtain the ceramic substrate.
4. The method for preparing a ceramic substrate according to claim 1, wherein the diameter of the heat dissipation through holes is less than 0.20mm, and the hole pitch between two adjacent heat dissipation through holes is between 0.50mm and 2.00mm.
5. The method according to claim 1, wherein the metal filler comprises tungsten or molybdenum.
6. The method according to claim 1, wherein the predetermined temperature is a temperature greater than 1500 ℃.
7. A ceramic substrate, comprising: m layers of ceramic chips and metal fillers are stacked; m is a positive integer;
a plurality of heat dissipation through holes are formed in a first preset position on each ceramic chip in the M layers of ceramic chips which are stacked;
and the metal filler is filled in each heat dissipation through hole on each ceramic chip in the M layers of ceramic chips which are stacked.
8. The ceramic substrate according to claim 7, wherein the first predetermined location comprises a first sub-area and a second sub-area;
the first sub-area is a position determined according to a heat flow concentration area in a heat flow distribution area of a target chip, the second sub-area is a position determined according to a heat flow dispersion area in the heat flow distribution area, and the density of the heat dissipation through holes in the first sub-area is greater than that in the second sub-area.
9. The ceramic substrate of claim 7, further comprising: at least one metal layer;
for each of the at least one metal layer, the metal layer is disposed on one side of one of the M tiles.
10. The ceramic substrate as claimed in claim 7, wherein the diameter of the heat dissipating through holes is less than 0.20mm, and the hole pitch between two adjacent heat dissipating through holes is between 0.50mm and 2.00mm.
11. A method of chip packaging, comprising:
arranging a target chip at a third preset position on the ceramic substrate;
the ceramic substrate is the ceramic substrate of any one of the claims 7 to 10; the heat flow distribution area of the target chip corresponds to a first preset position on the ceramic substrate.
12. A chip package structure, comprising: a ceramic substrate, a target chip;
the target chip is arranged at a third preset position on the ceramic substrate;
the ceramic substrate is the ceramic substrate of any one of the claims 7 to 10; the heat flow distribution area of the target chip corresponds to a first preset position on the ceramic substrate.
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| CN202210994931.2A CN115312471A (en) | 2022-08-18 | 2022-08-18 | Preparation method of ceramic substrate, chip packaging method and structure |
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