CN115310399A - Method for wiring in integrated circuit layout based on bus topological mode - Google Patents
Method for wiring in integrated circuit layout based on bus topological mode Download PDFInfo
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- G06F30/39—Circuit design at the physical level
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Abstract
The application provides a method for wiring based on a bus topological mode in an integrated circuit layout, which comprises the following steps: a preprocessing step, namely dividing the wiring net into at least one sub-net, wherein each sub-net comprises a wiring bus and a plurality of target pins; and a pattern wiring step of creating a wiring path for each target pin in the sub-nets connected to a wiring bus in the sub-nets for each sub-net obtained through the preprocessing step, and creating the wiring path based on a first wiring pattern, a second wiring pattern and a single-source search maze wiring in response to the target pin and the wiring bus being in the same metal layer. The embodiment of the application reduces the complexity of the wiring stage.
Description
Technical Field
The application belongs to the technical field of circuits, and particularly relates to a method for wiring based on a bus topology mode in an integrated circuit layout.
Background
In a detailed wiring stage of a very large scale integrated circuit, a net often has a plurality of port patterns (such as pin patterns) waiting for connection, the port patterns waiting for connection need to be connected in the wiring stage, a plurality of design rule constraints need to be satisfied while connection is performed, and increasing process requirements lead to more and more new design constraints needing to be satisfied, thereby increasing the complexity of the wiring stage.
Disclosure of Invention
The embodiment of the application provides a method for wiring in an integrated circuit layout based on a bus topological mode, which is used for overcoming or relieving the technical problems in the prior art.
The technical scheme adopted by the application is as follows:
a method for routing based on a bus topology mode in an integrated circuit layout comprises the following steps:
a pretreatment step comprising:
collecting all pins to be connected on a wiring net of the integrated circuit layout;
determining a wiring bus for wiring by implementing the bus topology mode;
screening all the pins to be connected based on the wiring bus, and determining a target pin for wiring based on the bus topology mode;
dividing the wiring net into at least one sub-net according to the distance between the target pin and the wiring bus, wherein each sub-net comprises a wiring bus and a plurality of target pins;
a pattern wiring step including: for each sub-net obtained through the preprocessing step, executing the following steps to create a wiring path that each target pin in the sub-net is connected to a wiring bus in the sub-net:
for any target pin, judging whether the target pin and the wiring bus are in the same metal layer;
in response to the target pin and the wiring bus being in the same metal layer, setting the metal layer where the target pin is located as a wiring layer; determining a routing direction in which the target pin is connected to the routing bus; and judging whether wiring can be conducted along the wiring direction on the wiring layer;
if the wiring layer can not be wired along the wiring direction, jumping to a step of executing a second wiring mode for wiring; if the wiring layer can be wired along the wiring direction, executing a first wiring mode to perform wiring, and comprising the following steps:
a step of performing the step of creating a wiring path to create a wiring path and performing obstacle detection; if no obstacle exists, judging that the wiring path is successfully established; if the obstacle exists, executing a second wiring mode to perform wiring;
and executing a second wiring mode for wiring, comprising the following steps:
judging whether other available wiring metal layers exist in the wiring direction; if at least one other available wiring metal layer exists in the wiring direction, selecting one other wiring metal layer as a wiring layer, skipping to the wiring path creating step to create a wiring path on the wiring layer, and detecting whether an obstacle exists on the wiring path or not by the obstacle detecting step, if no obstacle exists, judging that the wiring path is created successfully, and executing the step of creating a through hole, if an obstacle exists, continuing to execute a second wiring mode for wiring, and judging whether the wiring path is created successfully or not when the second wiring mode is executed; if the wiring path is failed to be established when the second wiring mode is executed, jumping to a single-source maze searching wiring step;
the step of creating the routing path comprises the following steps: creating a routing path on the routing layer along the routing direction;
the obstacle detecting step includes: detecting obstacles on the wiring path;
the single source search maze routing step, which comprises:
and based on the single-source search maze routing, performing routing path creation on the metal layer where the target pin is located until the routing path creation is successful or failed.
Optionally, the screening, based on the wiring bus, all the pins to be connected to determine a target pin to be wired based on the bus topology mode includes: and performing projection processing on the wiring bus in the horizontal or vertical direction, determining pins covered by the projected area of the wiring bus in all the pins to be connected, and taking the pins as target pins for wiring based on the bus topology mode.
Optionally, the dividing the wiring net into at least one sub-net according to the distance between the target pin and the wiring bus includes:
calculating the linear distance between each target pin and each wiring bus;
determining a wiring bus closest to each target pin according to the linear distance;
and dividing each target pin and the wiring bus which is closest to the target pin in a straight line into one sub-net.
Optionally, the determining a wiring direction in which the target pin is connected to the wiring bus includes: if the target pin is covered by the projection area of the wiring bus in the horizontal direction, the wiring direction is longitudinal; and if the target pin is covered by the projection area of the wiring bus in the vertical direction, the wiring direction is a transverse direction.
Optionally, the creating a routing path on the routing layer along the routing direction includes:
if the wiring direction is horizontal, the starting point of the center line of the wiring path is the graphic center point of the target pin, the end point of the center line of the wiring path is the projection point of the graphic center point of the target pin on the longitudinal center line of the graphic of the bus wiring, and the width of the wiring path is the height of the graphic of the target pin;
if the wiring direction is a longitudinal direction, the starting point of the center line of the wiring path is the center point of the graph of the target pin, the end point of the center line of the wiring path is the projection point of the center point of the graph of the target pin on the transverse center line of the graph of the bus wiring, and the width of the wiring path is the width of the graph of the target pin.
Optionally, the performing obstacle detection on the wiring path includes: and carrying out outward expansion on the wiring path, and detecting whether an obstacle exists in an outward expanded area.
Optionally, the expanding the wiring path includes: and carrying out outward expansion on the wiring path based on the minimum spacing constraint numerical value of the metal layer of the wiring path.
Optionally, the determining whether there are other routing metal layers available in the routing direction includes: and sequentially judging whether other available wiring metal layers exist in the wiring direction according to the sequence of the layer numbers of the metal layers in the process from low to high.
Optionally, the step of creating a through hole includes:
if the metal layers of the wiring layer and the target pin are different, creating a through hole in an overlapping area of the metal layers of the pattern of the wiring path and the pattern of the target pin;
if the metal layer of the wiring layer is different from the metal layer of the wiring bus, creating a through hole in an overlapping area of the metal layer of the pattern of the wiring path and the metal layer of the pattern of the wiring bus;
and carrying out external expansion on the created through hole, carrying out obstacle detection in the external expansion area, judging that the through hole is successfully created if no obstacle exists, and otherwise, failing to create the through hole.
Optionally, the expanding the created through hole includes:
and respectively carrying out external expansion on the created through holes based on the minimum spacing constraint numerical value of the top metal layer of the created through hole, the minimum spacing constraint numerical value of the bottom metal layer of the created through hole and the minimum spacing constraint numerical value of the cutting layer metal layer of the created through hole to obtain three external expansion areas so as to carry out obstacle detection in each external expansion area.
In the embodiment of the present application, the preprocessing step includes: collecting all pins to be connected on a wiring net of the integrated circuit layout; determining a wiring bus for carrying out wiring according to the bus topology mode; screening all the pins to be connected based on the wiring bus, and determining a target pin for wiring based on the bus topology mode; and dividing the wiring net into at least one sub-net according to the distance between the target pin and the wiring bus, wherein each sub-net comprises a wiring bus and a plurality of target pins. A pattern wiring step including: for each sub-net obtained through the preprocessing step, executing the following steps to create a wiring path that each target pin in the sub-net is connected to a wiring bus in the sub-net: for any target pin, judging whether the target pin and the wiring bus are in the same metal layer; in response to the target pin and the wiring bus being in the same metal layer, setting the metal layer where the target pin is located as a wiring layer; determining a routing direction in which the target pin is connected to the routing bus; and judging whether wiring can be conducted along the wiring direction on the wiring layer; if the wiring layer can not be wired along the wiring direction, jumping to a step of executing a second wiring mode for wiring; if the wiring layer can be wired along the wiring direction, executing a first wiring mode to perform wiring, and comprising the following steps of: a step of performing the wiring path creation step to create a wiring path and performing obstacle detection; if no obstacle exists, the wiring path is judged to be successfully established; if the obstacle exists, executing a second wiring mode to perform wiring; and executing a second wiring mode for wiring, comprising the following steps: judging whether other available wiring metal layers exist in the wiring direction; if at least one other available wiring metal layer exists in the wiring direction, selecting one other wiring metal layer as a wiring layer, skipping to the wiring path creating step to create a wiring path on the wiring layer, and the obstacle detecting step to detect whether an obstacle exists on the wiring path, if no obstacle exists, judging that the wiring path is created successfully, executing the step of creating a through hole, if an obstacle exists, continuing to execute a second wiring mode for wiring, and judging whether the wiring path is created successfully when the second wiring mode is executed; if the wiring path is failed to be established when the second wiring mode is executed, jumping to a single-source searching maze wiring step; the routing path creating step, which comprises: creating a routing path on the routing layer along the routing direction; the obstacle detecting step includes: detecting obstacles on the wiring path; the single source search maze routing step, which comprises: and based on single-source search maze routing, performing routing path creation on the metal layer where the target pin is located until the routing path creation is successful or failed.
Drawings
Fig. 1 is a schematic flow chart of a method for wiring based on a bus topology mode in an integrated circuit layout according to an embodiment of the present application;
FIG. 2 is a schematic flow chart illustrating a pretreatment step in a second embodiment of the present application;
FIG. 3 is a schematic flow chart illustrating a pretreatment step in a third embodiment of the present application;
FIG. 4 is a diagram illustrating a projection determination of a target pin based on a wiring bus according to a fourth embodiment of the present application;
FIG. 5 is a schematic flow chart of dividing sub-nets in the fifth embodiment of the present application;
FIG. 6 is an exemplary diagram of a sub-grid in an embodiment of the present application;
FIG. 7 is a flowchart illustrating a mode wiring step in a seventh embodiment of the present application;
fig. 8 is a schematic flowchart of step S112 in the eighth embodiment of the present application;
FIG. 9 is a flowchart illustrating a first wiring pattern according to an embodiment of the present application;
FIG. 10 is a schematic diagram of a routing bus and a target pin in a ten-wire sub-network according to an embodiment of the present invention;
FIG. 11 is a diagram illustrating a routing path created according to a first routing mode in an eleventh embodiment of the present application;
fig. 12 is a schematic flow chart illustrating a wiring operation performed in the second wiring mode in the twelfth embodiment of the present application;
FIG. 13 is a flowchart illustrating steps of creating vias according to an embodiment thirteen in the present application;
FIG. 14 is a diagram illustrating a routing path created according to a second routing mode in a fourteenth embodiment of the present application;
FIG. 15 is a schematic flowchart illustrating a fifteenth implementation of a third routing mode according to an embodiment of the present application;
FIG. 16 is a schematic diagram illustrating a routing path created according to the third routing mode in a sixteenth embodiment of the present application;
FIG. 17 is another schematic diagram of a routing path created according to the third routing mode in the seventeenth embodiment of the present application;
FIG. 18 is a schematic diagram of a routing path created by routing according to the maze algorithm in eighteenth embodiment of the present application;
fig. 19 is a schematic structural diagram of an electronic device in nineteen embodiments of the application;
fig. 20 is a schematic hardware structure diagram of an electronic device according to a twentieth embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived from the embodiments in the present application by a person skilled in the art, are within the scope of protection of the present application.
The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the application may be practiced in sequences other than those illustrated or described herein, and that the terms "first," "second," and the like are generally used herein in a generic sense and do not limit the number of terms, e.g., the first term can be one or more than one. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.
In the embodiment of the present application, the preprocessing step includes: collecting all pins to be connected on a wiring net of the integrated circuit layout; determining a wiring bus for wiring by implementing the bus topology mode; screening all the pins to be connected based on the wiring bus, and determining a target pin for wiring based on the bus topology mode; and dividing the wiring net into at least one sub-net according to the distance between the target pin and the wiring bus, wherein each sub-net comprises a wiring bus and a plurality of target pins. A pattern wiring step including: for each sub-net obtained through the preprocessing step, executing the following steps to create a wiring path that each target pin in the sub-net is connected to a wiring bus in the sub-net: for any target pin, judging whether the target pin and the wiring bus are in the same metal layer; in response to the target pin and the wiring bus being in the same metal layer, setting the metal layer where the target pin is located as a wiring layer; determining a wiring direction in which the target pin is connected to the wiring bus; and judging whether or not wiring can be performed in the wiring layer along the wiring direction; if the wiring layer can not be wired along the wiring direction, jumping to a step of executing a second wiring mode for wiring; if the wiring layer can be wired along the wiring direction, executing a first wiring mode to perform wiring, and comprising the following steps of: a step of performing the step of creating a wiring path to create a wiring path and performing obstacle detection; if no obstacle exists, judging that the wiring path is successfully established; if the obstacle exists, executing a second wiring mode to perform wiring; and executing a second wiring mode for wiring, comprising the following steps: judging whether other available wiring metal layers exist in the wiring direction; if at least one other available wiring metal layer exists in the wiring direction, selecting one other wiring metal layer as a wiring layer, skipping to the wiring path creating step to create a wiring path on the wiring layer, and the obstacle detecting step to detect whether an obstacle exists on the wiring path, if no obstacle exists, judging that the wiring path is created successfully, executing the step of creating a through hole, if an obstacle exists, continuing to execute a second wiring mode for wiring, and judging whether the wiring path is created successfully when the second wiring mode is executed; if the wiring path is failed to be established when the second wiring mode is executed, jumping to a single-source maze searching wiring step; the routing path creating step, which comprises: creating a routing path on the routing layer along the routing direction; the obstacle detecting step includes: detecting obstacles on the wiring path; the single source search maze routing step, which comprises: and based on the single-source search maze routing, performing routing path creation on the metal layer where the target pin is located until the routing path creation is successful or failed. The embodiment of the application reduces the complexity of the wiring stage.
Fig. 1 is a schematic flow chart of a method for wiring based on a bus topology mode in an integrated circuit layout according to an embodiment of the present application; as shown in fig. 1, it includes:
s101, a preprocessing step, namely dividing the wiring net into at least one sub-net, wherein each sub-net comprises a wiring bus and a plurality of target pins;
s102, a pattern wiring step, namely creating a wiring path for each target pin in the sub-net to be connected to a wiring bus in the sub-net aiming at each sub-net obtained in the preprocessing step.
FIG. 2 is a schematic flow chart illustrating a pretreatment step in a second embodiment of the present application; as shown in fig. 2, the preprocessing step includes:
S111A, determining a target pin for wiring based on the bus topology mode based on the determined wiring bus;
and S121A, dividing the wiring net into at least one sub-net according to the distance between the target pin and the wiring bus.
FIG. 3 is a schematic flowchart of the pretreatment step in the third embodiment of the present application; as shown in fig. 3, the preprocessing step includes:
S111B, collecting all pins to be connected on a wiring net of the integrated circuit layout;
S121B, determining a wiring bus for implementing the bus topology mode for wiring;
S131B, screening all the pins to be connected based on the wiring bus, and determining a target pin for wiring based on the bus topology mode;
and S141B, dividing the wiring net into at least one sub-net according to the distance between the target pin and the wiring bus.
The embodiment of fig. 3 is different from the embodiment of fig. 2 in that, in consideration of the requirement of an application scenario, steps S111B and S121B are added before step S112 in the embodiment of fig. 2, and in addition, in determining target pins for wiring based on the bus topology mode based on the determined wiring bus, all the pins to be connected are screened based on the wiring bus, and the target pins for wiring based on the bus topology mode are determined from the screened target pins.
Optionally, the determining a routing bus that implements the bus topology mode for routing includes: one or more pins are provided as the wiring bus. Alternatively, in other embodiments, a wiring bus may also be created in the integrated circuit layout, and the creating manner is not particularly limited, for example, the creating is performed according to a creation instruction. The number of the wiring buses is determined according to the requirements of application scenarios.
Optionally, the screening, based on the wiring bus, all the pins to be connected, and determining a target pin to be wired based on the bus topology mode, includes: and performing projection processing on the wiring bus in the horizontal or vertical direction, determining pins covered by the projected area of the wiring bus in all the pins to be connected, and taking the pins as target pins for wiring based on the bus topology mode.
FIG. 4 is a schematic diagram illustrating a projection determination target pin based on a wiring bus according to a fourth embodiment of the present application; as shown in fig. 4, the wiring bus in fig. 4 is subjected to projection processing in the vertical direction, and the projected area (also referred to as the area where the wiring bus is projected in the vertical direction) corresponds to an open rectangular area, the pins in the rectangular area are target pins (also referred to as routable pins), and the pins outside the rectangular area are wiring pins (also referred to as non-routable pins) that do not participate in the bus topology mode.
Here, it should be noted that fig. 3 is only described by taking an example in which there is one wiring bus and a plurality of target pins, and is not limited to only one wiring bus and a fixed number of target pins.
FIG. 5 is a schematic flow chart of dividing sub-nets in the fifth embodiment of the present application; as shown in fig. 5, dividing the wiring net into at least one sub-net according to the distance between the target pin and the wiring bus includes:
s1411, calculating the linear distance between each target pin and each wiring bus;
s1412, determining a wiring bus closest to each target pin according to the linear distance;
s1413, dividing each target pin and the wiring bus which is closest to the target pin in a straight line into sub-nets.
Optionally, the linear distance of each target pin from each wiring bus is such as the distance from the center of the pattern of the target pin to the center line of each wiring bus. The straight distance may be a horizontal distance or a vertical distance, and the straight distance corresponds to a straight line that deals with the center line of the wiring bus.
FIG. 6 is an exemplary diagram of dividing sub-nets according to an embodiment of the present application; as shown in fig. 6, two wiring buses, namely a longitudinal bus wiring 1 and a transverse bus wiring 2, are assumed, and the directions of the two wiring buses are respectively the horizontal direction and the vertical direction, so that four sub-nets, namely a sub-net 1, a sub-net 2, a sub-net 3 and a sub-net 4, are obtained, and each sub-net has only one bus wiring and a plurality of target pins (also called as wiring pins).
As shown in the left side of fig. 6, there are four wiring pins, and the behavior shown in the right side of fig. 6 is that a corresponding bus is selected for each pin, where two pins select bus 1 and two pins select bus 2, resulting in four sub-nets, where the bus in two sub-nets is bus 1 and the bus in the other two sub-nets is bus 2, and there is only one bus in each of bus 1 and bus 2, two sub-nets share bus 1 and the other two sub-nets share bus 2, and the sub-net distribution diagram is shown in the right side of fig. 6.
FIG. 7 is a flowchart illustrating a mode wiring step in a seventh embodiment of the present application; as shown in fig. 7, the pattern wiring step is to create a wiring path for each target pin in the sub-net to be connected to a wiring bus in the sub-net, for each sub-net obtained by the preprocessing step, and includes:
s112, in response to the target pin and the wiring bus being in the same metal layer, executing a first wiring mode for wiring;
s122, in response to the failure of executing the first wiring mode to perform wiring and establishing a wiring path, executing a second wiring mode to perform wiring;
s133, in response to failure of executing the second wiring mode to perform wiring and create a wiring path, executing a step of searching maze wiring by a single source to perform wiring;
S143A, determining that a wiring path successfully created when a first wiring mode, a second wiring mode or a single-source maze wiring search is executed is a wiring path of a target pin connected to a wiring bus;
S143B, in response to the failure of the single-source search maze routing creation routing path, marking the corresponding target pin as a non-routable pin, and not participating in the routing based on the bus topological mode.
Fig. 8 is a schematic flowchart of step S112 in the eighth embodiment of the present application; as shown in fig. 8, step S112 may specifically include:
s1121, responding to the target pin and the wiring bus being in the same metal layer, and arranging a wiring layer;
s1122, responding to the wiring layer can be wired, executing a first wiring mode to perform wiring.
Specifically, the step S1121 may include:
for any target pin, judging whether the target pin and the wiring bus are in the same metal layer;
responding to the target pin and the wiring bus being in the same metal layer, and setting the metal layer where the target pin is located as the wiring layer;
specifically, the step S1122 may include:
determining a wiring direction in which the target pin is connected to the wiring bus;
judging whether or not wiring can be performed in the wiring layer along the wiring direction;
if routing is possible at the routing layer along the routing direction, a first routing mode is performed for routing in response to routing being possible at the routing layer.
And if the wiring layer can not be wired along the wiring direction, responding to the fact that the wiring layer can not be wired, and jumping to a step of executing a second wiring mode for wiring.
Optionally, the determining a wiring direction in which the target pin is connected to the wiring bus includes: if the target pin is covered by the projection area of the wiring bus in the horizontal direction, the wiring direction is longitudinal; and if the target pin is covered by the projection area of the wiring bus in the vertical direction, the wiring direction is the transverse direction.
FIG. 9 is a flowchart illustrating a first wiring pattern according to a ninth embodiment of the present application; as shown in fig. 9, performing the first wiring pattern for wiring includes the steps of:
s1123, creating a wiring path;
s1124, based on the created wiring path, executing obstacle detection;
S1125A, if no barrier exists, judging that the wiring path is successfully established;
S1125B, if there is an obstacle, executing a second wiring mode to perform wiring;
in this embodiment, step S1123 may specifically create a routing path on the routing layer along the routing direction by performing the step of creating a routing path;
in this embodiment, the step S1124 may specifically perform obstacle detection on the wiring path by performing an obstacle detection step;
specifically, the obstacles include existing patterns, patterns of pins of other nets, and the like.
In this embodiment, the performing obstacle detection on the wiring path includes: and carrying out outward expansion on the wiring path, and detecting whether an obstacle exists in an outward expanded area. Specifically, wherein the expanding the routing path includes: and carrying out outward expansion on the wiring path based on the minimum spacing constraint numerical value of the metal layer of the wiring path.
FIG. 10 is a schematic diagram of a routing bus and a target pin in a ten-wire sub-network according to an embodiment of the present invention; as shown in fig. 10, the wiring bus line is in a horizontal direction, and the wiring direction thereof is in a lateral direction.
Fig. 11 is a schematic diagram of a wiring path created according to the first wiring pattern in the eleventh embodiment of the present application. As shown in fig. 11, the target pin and the routing bus are in the same metal layer, and the routing direction is horizontal, the starting point of the center line of the routing path is the center point of the pattern of the target pin, and the end point of the center line of the routing path is the projection point of the center point of the pattern of the target pin on the longitudinal center line of the pattern of the bus routing.
Alternatively, if the routing direction is a horizontal direction, the width of the routing path may be the height of the pattern of the target pin. For example, if the line connecting the start point and the end point of the wiring path is parallel to the X axis, the wiring direction is the horizontal direction.
In other embodiments, if the wiring direction is vertical, the starting point of the center line of the wiring path is the center point of the pattern of the target pin, and the end point of the center line of the wiring path is the projection point of the center point of the pattern of the target pin on the horizontal center line of the pattern of the bus wiring.
Alternatively, if the routing direction is a vertical direction, the width of the routing path may be the width of the pattern of the target pin. For example, if the line connecting the start point and the end point of the wiring path is parallel to the Y axis, the wiring direction is the vertical direction.
Fig. 12 is a schematic flow chart illustrating a wiring operation performed in the second wiring mode in the twelfth embodiment of the present application; as shown in fig. 12, the second wiring pattern is performed for wiring, including the steps of:
s1221, selecting another wiring metal layer as a wiring layer, creating a wiring path on the wiring layer, and detecting whether an obstacle exists on the wiring path;
S1222A, if no obstacle exists, the wiring path is judged to be successfully established, and a step of establishing a through hole is executed;
S1222B, if an obstacle exists, continuing to execute a second wiring mode for wiring, and judging whether the wiring path is successfully created or not when the second wiring mode is executed;
if successful, jump to step S1222A, otherwise jump to perform the single source search maze routing step.
Wherein, continuously executing a second wiring mode for wiring, and judging whether the wiring path is successfully created when executing the second wiring mode is: jumping to S1221 to select another other wiring metal layer as a wiring layer, creating a wiring path on the wiring layer, and detecting whether an obstacle exists on the wiring path; if no obstacle exists, judging that the wiring path is successfully established, and executing a step of establishing a through hole; if all other wiring metal layers are traversed, and are used as wiring layers one by one, and wiring path creation and obstacle detection are carried out, if only one other wiring metal layer is used as a wiring layer and no obstacle exists, the success of wiring path creation on the wiring layer is judged, and a step of creating a through hole is executed; and denying that one other routing metal layer exists as a routing layer and all obstacles exist, judging that the routing path creation fails based on the second routing mode, namely, skipping to the step of executing the single-source search maze routing.
Specifically, before the step S1221, the method may further include:
judging whether other available wiring metal layers exist in the wiring direction;
if at least one other available routing metal layer exists in the routing direction, then step S1221 is performed to select one other routing metal layer as a routing layer;
specifically, in step S1221, a routing path is created on the routing layer by jumping to the routing path creation step, and whether an obstacle exists on the routing path is detected by jumping to the obstacle detection step.
And if no other routing metal layer is available in the routing direction, directly jumping to a single-source search maze routing step.
Optionally, the determining whether there are other routing metal layers available in the routing direction includes: and sequentially judging whether other available wiring metal layers exist in the wiring direction according to the sequence of the layer numbers of the metal layers in the process from low to high. For example, the metal layers with lower layer numbers are selected first, and then the metal layers with higher layer numbers are selected as the wiring layers in sequence.
FIG. 13 is a flow chart illustrating steps of creating a via hole according to a thirteenth embodiment of the present application; as shown in fig. 13, it includes:
s1131, creating a through hole based on the graph of the wiring path;
s1132, expanding the created through hole;
s1133, detecting obstacles in the outward-expanded area;
and if no obstacle exists, judging that the through hole is successfully established, otherwise, judging that the through hole is unsuccessfully established and judging that the wiring is unsuccessfully arranged by using the second wiring mode.
Optionally, creating a via based on the graph of the routing path may specifically include:
S1131A, if the metal layer of the wiring layer is different from the metal layer of the target pin, creating a through hole in an overlapping area of the metal layer of the pattern of the wiring path and the metal layer of the pattern of the target pin;
S1131B, if the metal layer of the wiring layer is different from the metal layer of the wiring bus, creating a through hole in an overlapping area of the metal layer of the pattern of the wiring path and the metal layer of the pattern of the wiring bus;
optionally, the expanding the created through hole includes:
because a through hole is composed of an upper metal layer, a lower metal layer and a middle cutting layer and comprises the graphs of three layers, the created through hole is respectively subjected to outward expansion based on the minimum spacing constraint value of the top metal layer of the created through hole, the minimum spacing constraint value of the bottom metal layer of the created through hole and the minimum spacing constraint value of the cutting layer metal layer of the created through hole, so that three outward expanded areas are obtained, and obstacle detection is carried out in each outward expanded area.
If no obstacles exist in all the outward-expanded areas, judging that the through holes are successfully established; and if an obstacle exists in at least one expanded region, determining that the creation of the through hole fails and determining that the wiring fails by using the second wiring mode.
And when the creation of the through hole fails and the wiring using the second wiring mode is judged to fail, jumping to a single-source searching maze wiring step can be carried out.
FIG. 14 is a diagram illustrating a routing path created according to a second routing mode in a fourteenth embodiment of the present application; as shown in the schematic view of figure 14,
the routing path is on another metal layer than the routing bus and the destination pin. The routing bus and the target pin are on the same metal layer, and for this purpose, the above steps S1131A and S1131B are performed, respectively, thereby creating two vias.
In response to the target pin not being in the same metal layer as the routing bus, a third routing mode is performed to create a routing path. It should be noted here that, in response to the target pin not being in the same metal layer as the routing bus, a routing path may also be determined in an existing routing manner that is not based on a bus topology pattern, instead of performing the third routing pattern to determine a routing path as provided in the following embodiments.
Fig. 15 is a schematic flowchart illustrating a third wiring pattern performed in fifteenth embodiment of the present application; as shown in fig. 15, it includes the following steps:
s114, setting a wiring layer and determining a wiring direction;
s124, judging whether the wiring can be conducted along the wiring direction on the wiring layer;
if the wiring layer can not be wired along the wiring direction (namely, if the wiring layer can not be wired along the wiring direction), S134 is executed, and whether the metal layer where the wiring bus is located can be used as the wiring layer or not is judged;
if the wiring layer can be wired along the wiring direction (namely, yes), jumping to a wiring path creating step and an obstacle detecting step;
if no obstacle exists (namely, no), the wiring path is successfully established;
if the obstacle exists (namely, yes), jumping to S134;
if the metal layer where the wiring bus is located can be used as a wiring layer (namely, yes), S144 is executed, the metal layer where the wiring bus is located is used as a wiring layer, and the wiring direction of the target pin connected to the wiring bus is determined again;
if the metal layer where the wiring bus is located cannot be used as a wiring layer (i.e., no), executing step S145, and skipping to judging whether there are other available wiring metal layers in the wiring direction; if at least one other available wiring metal layer exists in the wiring direction, selecting one other wiring metal layer as a wiring layer, skipping to the wiring path creating step to create a wiring path on the wiring layer, and the obstacle detecting step to detect whether an obstacle exists on the wiring path, if no obstacle exists, judging that the wiring path is created successfully, executing the step of creating a through hole, and if an obstacle exists, continuing skipping to the step of judging whether other available wiring metal layers exist in the wiring direction to judge whether the wiring path is created successfully; if so, judging that the wiring path is successfully established; if not, judging that the wiring path is failed to be established when the third wiring mode is executed, and jumping to a single-source maze searching wiring step.
Optionally, a wiring layer is set in step S114, for example: setting a metal layer where the target pin is located as a wiring layer;
optionally, the wiring direction is determined in step S114, such as: determining a routing direction in which the target pin is connected to the routing bus;
in the foregoing embodiment, the step of creating a routing path includes: creating a routing path on the routing layer along the routing direction; the obstacle detecting step includes: and detecting obstacles on the wiring path.
Optionally, in this embodiment, the step of single-source search maze routing includes: and based on single-source search maze routing, routing path creation is carried out on the metal layer where the target pin is located until the routing path creation is successful or fails.
Specifically, a target pin is used as a search source of the labyrinth algorithm wiring, a wiring bus is used as a target, the width corresponding to the outlet direction of the target pin is used as the width of a wiring path, namely if the outlet direction of the target pin is transverse, the width of the wiring path is the height of the pin, if the outlet direction of the target pin is longitudinal, the width of the wiring path is the width of the target pin, if the single-source search labyrinth wiring is successful, a result that the wiring path is successfully established is returned, and if the single-source search labyrinth wiring is failed, it is indicated that the wiring path connecting the target pin and the wiring bus cannot be pricked, a result that the wiring path is unsuccessfully established is returned.
FIG. 16 is a diagram illustrating a routing path created according to a third routing mode in a sixteenth embodiment of the present application; as shown in fig. 16, the routing bus and the target pin are in different metal layers, and the routing layer and the metal layer where the target pin is located are in the same layer, so as to successfully create a routing path and a via.
FIG. 17 is another schematic diagram of a wiring path created according to the third wiring pattern in a seventeenth embodiment of the present application; as shown in fig. 17, the wiring bus and the target pin are located in different metal layers, the wiring layer is located in a different layer from the metal layer where the target pin is located, the metal layer where the wiring bus is located has an obstacle, and the metal layer where the target pin is located has an obstacle, so that a wiring path and a through hole are successfully created.
FIG. 18 is a schematic diagram of a routing path created by routing according to the maze algorithm in eighteenth embodiment of the present application; as shown in fig. 18, the routing bus and the target pin are in the same metal layer, and there is an obstacle on the metal layer, the routing path includes a horizontal segment and a vertical segment.
In a specific application scenario, in response to the target pin and the routing bus being in the same metal layer, determining a routing path based on the first routing mode, the second routing mode, and the single-source search maze routing provided in the foregoing embodiments of the present application, and in response to the target pin and the routing bus not being in the same metal layer, executing a third routing mode to create the routing path, so that in another embodiment, the method for routing in an integrated circuit layout based on a bus topology mode may include the following steps:
a pretreatment step comprising:
collecting all pins to be connected on a wiring net of the integrated circuit layout;
determining a wiring bus for wiring by implementing the bus topology mode;
screening all the pins to be connected based on the wiring bus, and determining a target pin for wiring based on the bus topology mode;
dividing the wiring net into at least one sub-net according to the distance between the target pin and the wiring bus, wherein each sub-net comprises a wiring bus and a plurality of target pins;
a pattern wiring step including: for each sub-net obtained through the preprocessing step, executing the following steps to create a wiring path for each target pin in the sub-net to be connected to a wiring bus in the sub-net:
for any target pin, judging whether the target pin and the wiring bus are in the same metal layer;
in response to the target pin and the wiring bus being in the same metal layer, setting the metal layer where the target pin is located as a wiring layer; determining a wiring direction in which the target pin is connected to the wiring bus; and judging whether or not wiring can be performed in the wiring layer along the wiring direction;
if the wiring layer can not be wired along the wiring direction, jumping to a step of executing a second wiring mode for wiring; if the wiring layer can be wired along the wiring direction, executing a first wiring mode to perform wiring, and comprising the following steps:
a step of performing the wiring path creation step to create a wiring path and performing obstacle detection; if no obstacle exists, judging that the wiring path is successfully established; if the obstacle exists, executing a second wiring mode to perform wiring;
and executing a second wiring mode for wiring, comprising the following steps:
judging whether other available wiring metal layers exist in the wiring direction; if at least one other available wiring metal layer exists in the wiring direction, selecting one other wiring metal layer as a wiring layer, skipping to the wiring path creating step to create a wiring path on the wiring layer, and the obstacle detecting step to detect whether an obstacle exists on the wiring path, if no obstacle exists, judging that the wiring path is created successfully, executing the step of creating a through hole, if an obstacle exists, continuing to execute a second wiring mode for wiring, and judging whether the wiring path is created successfully when the second wiring mode is executed; if the wiring path is failed to be established when the second wiring mode is executed, jumping to a single-source searching maze wiring step;
in response to the target pin not being in the same metal layer as the routing bus, performing a third routing mode comprising the steps of:
setting a metal layer where the target pin is located as a wiring layer;
determining a wiring direction in which the target pin is connected to the wiring bus; and judging whether wiring can be conducted along the wiring direction on the wiring layer;
if the wiring can not be conducted on the wiring layer along the wiring direction, judging whether the metal layer where the wiring bus is located can be used as the wiring layer or not; if the wiring layer can be wired along the wiring direction, jumping to a wiring path creating step and an obstacle detecting step; if no obstacle exists, the wiring path is successfully established; if the obstacle exists, judging whether the metal layer where the wiring bus is located can be used as a wiring layer; if the metal layer where the wiring bus is located can be used as the wiring layer, the metal layer where the wiring bus is located is used as the wiring layer, and the wiring direction of the target pin connected to the wiring bus is determined again; if the metal layer where the wiring bus is located cannot be used as a wiring layer, skipping to judging whether other available wiring metal layers exist in the wiring direction; if at least one other available wiring metal layer exists in the wiring direction, selecting one other wiring metal layer as a wiring layer, skipping to the wiring path creating step to create a wiring path on the wiring layer, and the obstacle detecting step to detect whether an obstacle exists on the wiring path, if no obstacle exists, judging that the wiring path is created successfully, executing the step of creating a through hole, and if an obstacle exists, continuing skipping to the step of judging whether other available wiring metal layers exist in the wiring direction to judge whether the wiring path is created successfully; if so, judging that the wiring path is successfully established; if not, judging that the wiring path is failed to be established when the third wiring mode is executed, and jumping to a single-source search maze wiring step;
the routing path creating step, which comprises: creating a routing path on the routing layer along the routing direction;
the obstacle detecting step includes: detecting obstacles on the wiring path;
the single source search maze routing step, which comprises:
and based on single-source search maze routing, routing path creation is carried out on the metal layer where the target pin is located until the routing path creation is successful or fails.
It should be noted here that there is no strict timing relationship between determining a wiring path based on the first wiring pattern, the second wiring pattern and the single-source search maze wiring provided in the above embodiments of the present application in response to the target pin being in the same metal layer as the wiring bus, and executing the third wiring pattern to create a wiring path in response to the target pin not being in the same metal layer as the wiring bus.
Fig. 19 is a schematic structural diagram of an electronic device in nineteen embodiments of the application; as shown in fig. 19, the electronic device includes a memory 1901 for storing a computer-executable program thereon and a processor 1902 for executing the computer-executable program to implement any one of the methods according to the embodiments of the present application.
Fig. 20 is a schematic hardware structure diagram of an electronic device according to a twentieth embodiment of the present application; as shown in fig. 20, the electronic device may include: a processor (processor) 202, a communication Interface (Communications Interface) 204, a memory (memory) 206, and a communication bus 208.
Wherein:
the processor 202, communication interface 204, and memory 206 communicate with each other via a communication bus 208.
A communication interface 204 for communicating with other electronic devices or servers.
The processor 202 is configured to execute the program 2010, and may specifically perform relevant steps in the foregoing method embodiments.
Specifically, program 2010 may include program code that includes computer operating instructions.
Processor 202 may be a central processing unit CPU, or an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits configured to implement embodiments of the present Application. The intelligent device comprises one or more processors which can be the same type of processor, such as one or more CPUs; or may be different types of processors such as one or more CPUs and one or more ASICs.
Memory 206 for storing program 2010. Memory 206 may comprise high-speed RAM memory, and may also include non-volatile memory (non-volatile memory), such as at least one disk memory.
Program 2010 may be specifically configured to cause processor 202 to perform the steps in the embodiments described above.
For specific implementation of each step in the program 2010, reference may be made to corresponding steps and corresponding descriptions in units in the method embodiment, which are not described herein again. It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described devices and modules may refer to the corresponding process descriptions in the foregoing method embodiments, and are not described herein again.
The embodiment of the present application further provides a computer storage medium, on which a computer executable program is stored, and when the computer executable program runs, the wiring method according to any embodiment of the present application is executed.
The above-described methods according to the embodiments of the present application may be implemented in hardware, firmware, or as software or computer code that may be stored in a recording medium such as a CD ROM, RAM, floppy disk, hard disk, or magneto-optical disk, or as computer code downloaded through a network, originally stored in a remote recording medium or a non-transitory machine-readable medium, and to be stored in a local recording medium, so that the methods described herein may be stored in such software processes on a recording medium using a general purpose computer, a dedicated processor, or programmable or dedicated hardware such as an ASIC or FPGA. It will be appreciated that a computer, processor, microprocessor controller, or programmable hardware includes memory components (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code that, when accessed and executed by a computer, processor, or hardware, implements the methods described herein. Further, when a general-purpose computer accesses code for implementing the methods illustrated herein, execution of the code transforms the general-purpose computer into a special-purpose computer for performing the methods illustrated herein.
Those of ordinary skill in the art will appreciate that the various illustrative elements and method steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present application.
The above embodiments are only used for illustrating the embodiments of the present application, and not for limiting the embodiments of the present application, and those skilled in the relevant art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application, so that all equivalent technical solutions also belong to the scope of the embodiments of the present application, and the scope of patent protection of the embodiments of the present application should be defined by the claims.
Claims (10)
1. A method for wiring based on bus topology mode in integrated circuit layout is characterized by comprising the following steps:
a pretreatment step comprising:
collecting all pins to be connected on a wiring net of the integrated circuit layout;
determining a wiring bus for carrying out wiring according to the bus topology mode;
screening all the pins to be connected based on the wiring bus, and determining a target pin for wiring based on the bus topology mode;
dividing the wiring net into at least one sub-net according to the distance between the target pin and the wiring bus, wherein each sub-net comprises a wiring bus and a plurality of target pins;
a pattern wiring step including: for each sub-net obtained through the preprocessing step, executing the following steps to create a wiring path that each target pin in the sub-net is connected to a wiring bus in the sub-net:
for any of the target pins, the pin number is,
in response to the target pin and the wiring bus being in the same metal layer, setting the metal layer where the target pin is located as a wiring layer; determining a wiring direction in which the target pin is connected to the wiring bus; and judging whether wiring can be conducted along the wiring direction on the wiring layer;
if the wiring layer can not be wired along the wiring direction, jumping to a step of executing a second wiring mode for wiring; if the wiring layer can be wired along the wiring direction, executing a first wiring mode to perform wiring, and comprising the following steps:
a step of performing the wiring path creation step to create a wiring path and performing obstacle detection; if no obstacle exists, the wiring path is judged to be successfully established; if the obstacle exists, executing a second wiring mode to perform wiring;
and executing a second wiring mode for wiring, and comprising the following steps of:
judging whether other available wiring metal layers exist in the wiring direction; if at least one other available wiring metal layer exists in the wiring direction, selecting one other wiring metal layer as a wiring layer, skipping to the wiring path creating step to create a wiring path on the wiring layer, and detecting whether an obstacle exists on the wiring path or not by the obstacle detecting step, if no obstacle exists, judging that the wiring path is created successfully, and executing the step of creating a through hole, if an obstacle exists, continuing to execute a second wiring mode for wiring, and judging whether the wiring path is created successfully or not when the second wiring mode is executed; if the wiring path is failed to be established when the second wiring mode is executed, jumping to a single-source searching maze wiring step;
the routing path creating step, which comprises: creating a routing path on the routing layer along the routing direction;
the obstacle detecting step includes: detecting obstacles on the wiring path;
the single source search maze routing step, which comprises:
and based on the single-source search maze routing, performing routing path creation on the metal layer where the target pin is located until the routing path creation is successful or failed.
2. The method according to claim 1, wherein the screening all the pins to be connected based on the wiring bus to determine a target pin for wiring based on the bus topology mode comprises: and performing projection processing on the wiring bus in the horizontal or vertical direction, determining pins covered by the projected area of the wiring bus in all the pins to be connected, and taking the pins as target pins for wiring based on the bus topology mode.
3. The method of claim 1, comprising: dividing the wiring net into at least one sub-net according to the distance between the target pin and the wiring bus, including:
calculating the linear distance between each target pin and each wiring bus;
determining a wiring bus closest to each target pin according to the linear distance;
and dividing each target pin and the wiring bus which is closest to the target pin in a straight line into a sub-net.
4. The method of claim 1, wherein determining a routing direction in which the target pin is connected to the routing bus comprises: if the target pin is covered by the projection area of the wiring bus in the horizontal direction, the wiring direction is longitudinal; and if the target pin is covered by the projection area of the wiring bus in the vertical direction, the wiring direction is a transverse direction.
5. The method of claim 1, wherein creating a routing path on the routing layer along the routing direction comprises:
if the wiring direction is horizontal, the starting point of the center line of the wiring path is the center point of the graph of the target pin, the end point of the center line of the wiring path is the projection point of the center point of the graph of the target pin on the longitudinal center line of the graph of the bus wiring, and the width of the wiring path is the height of the graph of the target pin;
if the wiring direction is a longitudinal direction, the starting point of the center line of the wiring path is the center point of the graph of the target pin, the end point of the center line of the wiring path is the projection point of the center point of the graph of the target pin on the transverse center line of the graph of the bus wiring, and the width of the wiring path is the width of the graph of the target pin.
6. The method of claim 1, wherein the performing obstacle detection on the routing path comprises: and carrying out external expansion on the wiring path, and detecting whether an obstacle exists in an external expansion area.
7. The method of claim 6, wherein the flaring the routing path comprises: and performing outward expansion on the wiring path based on the minimum spacing constraint value of the metal layer of the wiring path.
8. The method of claim 1, wherein the determining whether there are additional routing metal layers available in the routing direction comprises: and sequentially judging whether other available wiring metal layers exist in the wiring direction according to the sequence of the layer numbers of the metal layers in the process from low to high.
9. The method of claim 1, wherein the step of creating vias comprises:
if the metal layers of the wiring layer and the target pin are different, creating a through hole in an overlapping area of the metal layers of the pattern of the wiring path and the pattern of the target pin;
if the metal layer of the wiring layer is different from the metal layer of the wiring bus, creating a through hole in an overlapping area of the metal layer of the pattern of the wiring path and the metal layer of the pattern of the wiring bus;
and expanding the created through holes, detecting obstacles in the expanded area, judging that the through holes are successfully created if no obstacle exists, and otherwise, judging that the through holes are failed to be created and the wiring is failed by using the second wiring mode.
10. The method of claim 1, wherein flaring the created via comprises:
respectively carrying out external expansion on the created through holes based on the minimum spacing constraint numerical value of the top metal layer of the created through hole, the minimum spacing constraint numerical value of the bottom metal layer of the created through hole and the minimum spacing constraint numerical value of the cutting layer metal layer of the created through hole to obtain three external expansion areas so as to carry out obstacle detection on each external expansion area.
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| US20030018947A1 (en) * | 2000-12-07 | 2003-01-23 | Steven Teig | Hierarchical routing method and apparatus that use diagonal routes |
| CN1520565A (en) * | 2000-12-07 | 2004-08-11 | 凯登斯设计系统有限公司 | Wiring method and apparatus |
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| CN115310399B (en) | 2024-06-21 |
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