CN115310396A

CN115310396A - Parasitic resistance visualization method, device, system, electronic device and storage medium

Info

Publication number: CN115310396A
Application number: CN202210784903.8A
Authority: CN
Inventors: 李索; 李嵩
Original assignee: Hangzhou Xingxin Technology Co ltd
Current assignee: Hangzhou Xingxin Technology Co ltd
Priority date: 2022-07-05
Filing date: 2022-07-05
Publication date: 2022-11-08

Abstract

The application relates to a parasitic resistance visualization method, a device, a system, an electronic device and a storage medium, wherein the parasitic resistance visualization method comprises the following steps: acquiring a preset parasitic parameter netlist, acquiring netlist nodes and parasitic resistances in the parasitic parameter netlist, and displaying the netlist nodes and the parasitic resistances; acquiring node selection information aiming at the netlist node, acquiring a first resistor matched with the node selection information from the parasitic resistor, and displaying at least the first resistor according to preset key identification information; and at least obtaining and displaying an end-to-end equivalent resistance value of the first resistor according to the first resistor. By the aid of the method, the problems of single function and low visualization efficiency of the parasitic resistance visualization method are solved, and efficient visualization of the parasitic resistance is realized.

Description

Parasitic resistance visualization method, device, system, electronic device and storage medium

Technical Field

The present application relates to the field of integrated circuit technologies, and in particular, to a parasitic resistance visualization method, apparatus, system, electronic apparatus, and storage medium.

Background

Parasitic parameters including parasitic capacitance and parasitic resistance. Parasitic resistance visualization is an important tool for users to locate layout design problems in the integrated circuit design process. In order to solve the problems existing in the layout design, a method of reversely marking the parasitic resistance on a schematic diagram for a user to inquire is generally adopted at present, so that the user can determine the problems existing in the layout design by observing the condition of the parasitic resistance in the integrated circuit.

However, as integrated circuit designs scale increasingly, parasitic resistances in the layout also increase. In the prior art, only parasitic resistance is directly inversely labeled in a layout for visualization, the function of auxiliary analysis on the parasitic resistance is lacked, meanwhile, under the conditions of huge data volume and complex connection lines, a visualization interface becomes messy, and the loading efficiency is influenced by the loaded data volume, so that the efficiency of a user for utilizing the visualization interface becomes low, and the layout design parameters are difficult to rapidly position.

Aiming at the problems of single function and low visualization efficiency of a parasitic resistance visualization method in the related technology, no effective solution is provided at present.

Disclosure of Invention

The embodiment provides a parasitic resistance visualization method, a parasitic resistance visualization device, a parasitic resistance visualization system, an electronic device and a storage medium, so as to solve the problems that the parasitic resistance visualization method in the related art is single in function and low in visualization efficiency.

In a first aspect, in this embodiment, a parasitic resistance visualization method is provided, where the method is applied to a terminal device, and includes:

acquiring a preset parasitic parameter netlist, acquiring netlist nodes and parasitic resistances in the parasitic parameter netlist, and displaying the netlist nodes and the parasitic resistances;

acquiring node selection information aiming at the netlist node, acquiring a first resistor matched with the node selection information from the parasitic resistor, and displaying at least the first resistor according to preset key identification information;

and at least obtaining and displaying an end-to-end equivalent resistance value of the first resistor according to the first resistor.

Further, the obtaining node selection information for the netlist node includes:

acquiring a graph selection instruction aiming at the netlist node and input by a user, and generating the node selection information according to the graph selection instruction;

or obtaining a netlist node name input by a user, and obtaining the node selection information according to the netlist node name.

Further, the obtaining a first resistance matched with the node selection information from the parasitic resistance and displaying at least the first resistance according to preset key identification information includes:

acquiring a starting node to be displayed and an end node to be displayed according to the node selection information;

acquiring the first resistor from the parasitic resistor according to the starting node to be displayed and the end node to be displayed;

and at least displaying the first resistor according to preset key identification information.

Further, the obtaining and displaying at least an end-to-end equivalent resistance value of the first resistor according to the first resistor includes:

obtaining an end-to-end equivalent resistance value of the first resistor according to the first resistor;

acquiring a layout file, and acquiring layer information of the first resistor according to the layout file and the parasitic parameter netlist;

acquiring a first equivalent resistance value of the first resistor according to the layer information and a first resistor contribution percentage of the first resistor corresponding to the first equivalent resistance value;

displaying the end-to-end equivalent resistance value, the layer attribute, the first equivalent resistance value, and the first resistance contribution percentage of the first resistance in a window.

Further, after at least an end-to-end equivalent resistance value of the first resistor is obtained according to the first resistor and displayed:

acquiring resistance selection information, and highlighting a second resistance according to the resistance selection information;

and at least obtaining and displaying a second equivalent resistance value of the second resistor according to the second resistor.

Further, the obtaining and displaying at least a second equivalent resistance value of the second resistor according to the second resistor includes:

acquiring and displaying a second equivalent resistance value of the second resistor according to the second resistor;

obtaining a second resistance contribution percentage of the corresponding second resistance according to the second equivalent resistance;

displaying the second equivalent resistance value and the second resistance contribution percentage of the second resistance in a window.

In a second aspect, there is provided in this embodiment a parasitic resistance visualization apparatus, including: the device comprises an acquisition module, a selection module and a display module;

the acquisition module is used for acquiring a preset parasitic parameter netlist, acquiring netlist nodes and parasitic resistances in the parasitic parameter netlist, and displaying the netlist nodes and the parasitic resistances;

the selection module is used for acquiring node selection information aiming at the netlist node, acquiring a first resistor matched with the node selection information from the parasitic resistor, and displaying at least the first resistor according to preset key identification information;

the display module is used for at least obtaining and displaying the end-to-end equivalent resistance value of the first resistor according to the first resistor.

In a third aspect, there is provided in this embodiment a parasitic resistance visualization system, comprising: a terminal device, a transmission device and a server device; the terminal equipment is connected with the server equipment through the transmission equipment;

the terminal device is used for implementing the parasitic resistance visualization method of the first aspect;

the transmission equipment is used for sending the end-to-end equivalent resistance value of the first resistor to the terminal equipment;

the server device is used for calculating an end-to-end equivalent resistance value of the first resistor.

In a fourth aspect, in this embodiment, there is provided an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the parasitic resistance visualization method according to the first aspect when executing the computer program.

In a fifth aspect, in the present embodiment, a storage medium is provided, on which a computer program is stored, which when executed by a processor, implements the parasitic resistance visualization method according to the first aspect.

Compared with the related art, the parasitic resistance visualization method, the parasitic resistance visualization device, the parasitic resistance visualization system, the parasitic resistance visualization electronic device and the storage medium are provided in the embodiment, the method is applied to terminal equipment, and the netlist node and the parasitic resistance are displayed by obtaining a preset parasitic parameter netlist and obtaining the netlist node and the parasitic resistance in the parasitic parameter netlist; acquiring node selection information aiming at the netlist node, acquiring a first resistor matched with the node selection information from the parasitic resistor, and displaying at least the first resistor according to preset key identification information; at least obtaining and displaying the end-to-end equivalent resistance value of the first resistor according to the first resistor, solving the problems of single function and low visualization efficiency of a parasitic resistor visualization method, and having the following beneficial effects:

1. the resistance is inversely marked back to the layout, a visual graphical interface is provided, and a designer is assisted in designing a circuit;

2. providing a resistance layer analysis tool, facilitating designers to quickly know the resistance between nodes in the circuit, calculating the contribution of the layer resistance, facilitating designers to know the circuit characteristics and quickly positioning the problems in layout design;

3. and a resistance local inspection tool is provided, so that a designer can conveniently study circuit details.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the application.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

FIG. 1 is a diagram illustrating an exemplary embodiment of a method for visualizing parasitic resistance;

FIG. 2 is a schematic flow chart diagram of a method for visualizing parasitic resistance in one embodiment;

FIG. 3 is a diagram of a partial layer number name interface in one embodiment;

FIG. 4 is a schematic diagram of a portion of a node information interface in one embodiment;

FIG. 5 is a schematic diagram of a portion of a resistance information interface in one embodiment;

FIG. 6 is a diagram of a display window in one embodiment;

FIG. 7 is a schematic flow chart diagram illustrating a method for visualizing parasitic resistance in another embodiment;

FIG. 8 is a block diagram of a parasitic resistance visualization device according to an embodiment;

FIG. 9 is a diagram of an internal structure of a computer device in one embodiment.

Detailed Description

For a clearer understanding of the objects, aspects and advantages of the present application, reference is made to the following description and accompanying drawings.

The parasitic resistance visualization method provided by the application can be applied to the application environment shown in fig. 1. Wherein the terminal device 102 communicates with the server device 104 over a network. The terminal device 102 acquires a preset parasitic parameter netlist, acquires netlist nodes and parasitic resistances in the parasitic parameter netlist, and displays the netlist nodes and the parasitic resistances; the terminal device 102 acquires node selection information for the netlist node, acquires a first resistor matched with the node selection information from the parasitic resistor, and displays at least the first resistor according to preset key identification information; and the terminal device 102 at least obtains and displays an end-to-end equivalent resistance value of the first resistor according to the first resistor. The server device 104 is configured to calculate an end-to-end equivalent resistance value of the first resistor. The terminal device 102 may be, but not limited to, various personal computers, notebook computers, smart phones, tablet computers, and portable wearable devices, and the server device 104 may be implemented by an independent server or a server cluster formed by a plurality of servers.

In the present embodiment, a parasitic resistance visualization method is provided, and fig. 2 is a flowchart of the parasitic resistance visualization method of the present embodiment, as shown in fig. 2, the flowchart includes the following steps:

step S202, a preset parasitic parameter netlist is obtained, netlist nodes and parasitic resistances in the parasitic parameter netlist are obtained, and the netlist nodes and the parasitic resistances are displayed.

Wherein, the parasitic parameter netlist describes the parasitic parameters of the device connection in the circuit, and the content of the parasitic parameter netlist comprises a gate-level netlist (or a register-level netlist) and the parasitic parameters; the gate-level netlist describes the connection relationship of the components; the netlist node refers to a point with a coordinate position in the parasitic parameter netlist; the parasitic parameters refer to parameters such as parasitic resistance, parasitic capacitance and parasitic inductance generated by interconnection of components on a layout.

Specifically, the terminal device 102 obtains a parasitic parameter netlist, obtains position coordinates of netlist nodes from a gate-level netlist in the parasitic parameter netlist, obtains parasitic resistances from parasitic parameters in the parasitic parameter netlist, marks the netlist nodes and the position coordinates in a layout according to the position coordinates, and connects the netlist nodes based on the connection relationship of the netlist nodes; the terminal device 102 displays the obtained netlist node and the parasitic resistor, and inversely marks the resistance value of the parasitic resistor in the layout for visual display.

Step S204, obtaining node selection information aiming at the netlist node, obtaining a first resistor matched with the node selection information from the parasitic resistor, and displaying at least the first resistor according to preset key identification information.

The node selection information is used for acquiring a first resistor required by a user from all parasitic resistors; the first resistance is matched from all parasitic resistances according to the node selection information and corresponds to the node selection information, and at least one first resistance is provided; the key identification information is preset information for highlighting the first resistor to be displayed, for example, the key identification information may be a highlight identification, and after the first resistor is obtained, the terminal device may highlight the first resistor based on the highlight identification; or, when it is detected that the key identification information is text label information, highlighting the first resistor in the form of label or the like based on the text label information; or, the key identification information may also be preset as a red identification, and the like, which is not described herein again.

Specifically, the terminal device 102 obtains node selection information for a node of the netlist, obtains at least one first node and at least one first resistor in the node selection information range according to the node selection information in the parasitic parameter netlist on the layout, and at least highlights the first resistor.

Step S206, at least obtaining and displaying an end-to-end equivalent resistance value of the first resistor according to the first resistor.

Preferably, in order to improve the efficiency of visualization of the parasitic resistor, the terminal device 102 displays the end-to-end equivalent resistance value of the first resistor calculated by the server device 104; the end-to-end equivalent resistance value refers to an equivalent resistance value from one node to another node, or an equivalent resistance value from a certain port of one device to a certain port of another device (or different ports of the same device); preferably, the end-to-end equivalent resistance value of the first resistor may be a total equivalent resistance value result of the first resistor, or may be a level equivalent resistance value result obtained by respectively calculating according to levels in the layout file.

It should be noted that, after the end-to-end equivalent resistance values of the first resistor and the first resistor are displayed and a cancel display command for canceling the first resistor input by a user is obtained, the end-to-end equivalent resistance values of the first resistor and the first resistor may be stored in a carrier such as a text document or a database, or may not be stored, and a display process of the end-to-end equivalent resistance values of the first resistor and the first resistor is released; preferably, in order to improve the efficiency of visualization of the parasitic resistance, the terminal device 102 directly releases the display process of the first resistance and the end-to-end equivalent resistance value of the first resistance after acquiring the cancel display command input by the user.

Through the steps, node selection information aiming at the netlist node is obtained, the first resistor and the end-to-end equivalent resistance value of the first resistor are displayed according to the node selection information, compared with the technical scheme that only the parasitic resistor is reversely marked in the layout in the related technology, the parasitic resistor visualization method in the embodiment can not only realize the reverse marking of the parasitic resistor in the layout, but also highlight the first node and the first resistor in the selection range according to the selection result of the netlist node by a user, and display the end-to-end equivalent resistance value of the first resistor, so that the problems of single function and low positioning efficiency of the parasitic resistor visualization method in the related technology are solved, a designer can conveniently and quickly know the resistance between nodes in a circuit, and the problem in layout design is quickly positioned.

In some embodiments, obtaining node selection information for the netlist node includes:

acquiring a graph selection instruction which is input by a user and aims at the netlist node, and generating node selection information according to the graph selection instruction;

The acquired node selection information of the netlist node refers to graphical selection information and/or parametric selection information; the graphical selection information refers to an acquired graphical selection instruction for operating a netlist node on a visual interface by a user, specifically, node selection information selected by the user on the layout file and the parasitic parameter netlist is acquired, and the user operation can be a selection operation of two netlist nodes, or a dragging check box to perform a range check operation on the layout file, or an operation of checking a netlist tree-shaped graph; the netlist tree diagram refers to circuits (net) and nodes (nodes) in a netlist which are combined into a tree structure according to layout levels, the circuits (net) and the nodes (nodes) are mainly in the form of pull-down tables, and after the net in a first-level pull-down table is selected, all the nodes on the net can be popped up for a user to select; the parameterization selection information refers to the acquired netlist node number or netlist node name input by a user; the node selection information is determined according to the larger range of the obtained graphical selection information and/or parametric selection information.

Through the steps, the end-to-end equivalent resistance value of the first resistor can be calculated by obtaining the node selection information, compared with the technical scheme that only the parasitic resistor is reversely marked in the layout in the related technology, the parasitic resistor visualization method in the embodiment not only can realize the reverse marking of the parasitic resistor in the layout, but also can obtain the node selection information of the netlist node by a user, the user can conveniently and hierarchically select the node in an imaging selection mode, the user can conveniently and rapidly find the interested node, the first node and the first resistor in the selection range are highlighted according to the node selection information, and the end-to-end equivalent resistance value of the first resistor is displayed, so that the problems that the parasitic resistor visualization method in the related technology is single in function and low in positioning efficiency are solved, a designer can conveniently and rapidly know the resistance between nodes in the circuit, and the problem in layout design is rapidly positioned.

In some embodiments, obtaining a first resistance matching the node selection information from the parasitic resistance, and displaying at least the first resistance according to preset highlight identification information includes:

acquiring the first resistor from the parasitic resistor according to the initial node to be displayed and the terminal node to be displayed;

and at least highlighting the first resistor according to preset key identification information.

And the to-be-displayed starting node and the to-be-displayed terminal node comprise respective coordinate information.

Specifically, the terminal device 102 acquires, from the node selection information, coordinate information of a start node to be displayed and coordinate information of an end node to be displayed in a maximum range; the terminal device 102 obtains at least one first node and at least one first resistor which are connected with each other between the start coordinate and the end coordinate from the parasitic parameter netlist corresponding to the parasitic resistor according to the coordinate information of the start node to be displayed and the coordinate information of the end node to be displayed; the terminal device 102 displays the start node to be displayed, the end node to be displayed, the at least one first node, and the at least one first resistor according to preset key identification information.

Through the steps, all nodes and all resistors corresponding to the node selection information are highlighted by obtaining the node selection information selected by the user, compared with the technical scheme that only the parasitic resistors are reversely marked in the layout in the related technology, the parasitic resistor visualization method in the embodiment can not only realize the reverse marking of the parasitic resistors in the layout, but also obtain the node selection information of the netlist node by the user, so that the user can conveniently and quickly find the interested nodes, highlight the first node and the first resistor in the selection range according to the node selection information, and display the end-to-end equivalent resistance value of the first resistor, thereby solving the problems of single function and low positioning efficiency of the parasitic resistor visualization method in the related technology, facilitating the designer to quickly know the resistance among the nodes in the circuit, and quickly positioning the problem in layout design.

In some embodiments, obtaining and displaying at least an end-to-end equivalent resistance value of the first resistor according to the first resistor includes:

displaying the end-to-end equivalent resistance value, the layer attribute, the first equivalent resistance value and the first resistance contribution percentage of the first resistance in a window.

The end-to-end equivalent resistance value of the first resistor may be calculated by the server device 104 according to the first resistor, or may be displayed by the terminal device 102 after obtaining and synchronously calculating the first resistor, and preferably, in order to improve the visualization efficiency of the parasitic resistor, the terminal device 102 displays the end-to-end equivalent resistance value of the first resistor calculated by the server device 104; the end-to-end equivalent resistance value refers to an equivalent resistance value from one node to another node, or an equivalent resistance value from a certain port of one device to a certain port of another device (or different ports of the same device); the layer information comprises a layout layer (layer) name, and component names, serial numbers, numerical values and the like contained in each layer; the first equivalent resistance value and the first resistance contribution percentage are calculated according to the layer information and the first resistance, and are preferably calculated by the server device 104, the terminal device 102 obtains the first equivalent resistance value sent by the server device 104, and at least one of the first equivalent resistance value and the first resistance contribution percentage corresponds to each layer in the layer information; the first equivalent resistance value refers to the equivalent resistance of the resistor on the corresponding layer to the whole circuit in the end-to-end equivalent resistance of the first resistor, namely if two nodes pass through three different layers, the circuits on the three different layers are respectively equivalent to one first resistor, and the first equivalent resistance values are three and respectively correspond to the different layers; three first resistors are connected in series, namely the three first resistors are equal to the equivalent resistance of an end-to-end circuit corresponding to the first resistors; the first resistance contribution percentage is the percentage of the first equivalent resistance value of the first resistance contributing to the whole circuit; in displaying the end-to-end equivalent resistance value of the first resistor, the layer attribute, the first equivalent resistance value, and the first resistor contribution percentage in a window, the display window may be a floating window or a pull-down window, and the display window may be located on the right side or below the display interface of the terminal device 102.

In this embodiment, a layout design with the name of EP is taken as an example, and fig. 3 is an interface schematic diagram of part layer number names in this embodiment, as shown in fig. 3, the layout design has 85 layout layers (layers), and only part layers are shown in the diagram. Fig. 4 is a schematic diagram of a partial node information interface in the embodiment, as shown in fig. 4, there are 159 netlist nodes in the layout design, which are only partially shown, where the first column of fields includes | P, | I and | S, where | P denotes a chip external port, | I denotes a device port, and | S denotes a child node; the first field in parentheses is the node name, e.g., EP:0, and XI169/MNM0@3: G, etc., and the last two fields in parentheses are the x and y coordinates of the node; the number after field $ lvl = is the number of the corresponding layer. Fig. 5 is a schematic diagram of an interface of partial resistance information in this embodiment, as shown in fig. 5, 170 resistors are provided in the layout design, which are only partial resistors, where each row of resistance information corresponds to one resistor, the first column is a resistor name (the resistor name has no specific meaning and is distinguished by a number), the second column and the third column are node names of two nodes connected by the resistor, and a number after $1v1= indicates a level of the resistor.

Fig. 6 is a schematic diagram of a display window in this embodiment, and as shown in fig. 6, the node selection information in the layout design is nodes numbered 75 and 45, where the node numbered 75 is M2: on the drawing layer, the coordinate is (100.021, 134.898); node number 45 at M3: on the drawing layer, the coordinate is (105.361, 134.646); the selection key in the window schematic diagram shown in fig. 6 may obtain an operation selection result for the corresponding node after being clicked by the user, and the calculation key may be triggered by the user after obtaining the node selection information, so as to obtain and display an equivalent resistance value result 60.7112ohms (ohms) obtained according to the node selection information, and at the same time, may obtain a command of whether to highlight the node selection information in the window interface shown in fig. 6.

Specifically, in this embodiment, an end-to-end equivalent resistance value of the first resistor is calculated according to the layout hierarchy, taking two | I in net EP as an example, node 1: XI169/MNM0@3: g, node 2: XI169/MNM0: g, an end-to-end equivalent resistance value (p 2p value) of the first resistor corresponding to the two nodes is 1847.82 Ω (ohm), the corresponding layers are

layers

13, 37, 51, 62, 68, and 73, respectively, and table 1 below is a visual example of the layer equivalent resistor and the resistor contribution in this embodiment. Wherein the expression of the resistance contribution is as follows:

the calculation expression of the equivalent contribution resistance value of each layer corresponding to the resistance contribution is as follows:

wherein R is _p2p The end-to-end equivalent resistance value of the first resistor is calculated by the server device 104 according to the connection relationship between the components in the layout file and the equivalent resistance value calculation formula of the series-parallel circuit, which is not described herein again; r _t The target resistance value refers to an object for which resistance contribution is calculated, and in this embodiment, refers to an equivalent resistance of each layer; r' _t The offset resistor is a differential unit, specifically means the ratio of the offset resistance to the offset resistance of the target resistor, and the value range is 1% -5%, and the specific value of the calculation process is determined according to the actual situation; r' _p2p The equivalent end-to-end resistance value after the offset is obtained; r _e The equivalent contribution resistance value of the target resistance in the circuit corresponding to the resistance contribution is obtained.

Table 1 graphic layer equivalent resistance and resistance contribution visualization example

Layer of a picture	Layer name	First resistance contribution	First equivalent resistance (ohm)
				13	metal1	0.02％	0.3
37	ngate_svt_fin	86.36％	1595.1
				51	npoly_svt	7.73％	142.9
62	M0G_GT	0.50％	9.2
				68	M0G_GT_npoly_svt_RC	5.3％	98.0
73	V0_M0G_GT	0.14％	2.7

In this embodiment, at least one selected first resistor in the node selection information is distributed in the 6 layers to obtain 6 first equivalent resistance values; distributed in layer 13: the first resistance contribution percentage of metal1 is 0.02%, and the first equivalent resistance value is 0.3 Ω; distribution in the layer 37: ngate _ svt _ fin has a first resistance contribution percentage of 86.36%, and a first equivalent resistance value of 1595.1 Ω; distributed in the layer 51: the first resistance contribution percentage of npoly _ svt is 7.73%, and the first equivalent resistance value is 142.9 Ω; distributed in the layer 62: the first resistance contribution percentage of M0G _ GT is 0.50%, and the first equivalent resistance value is 9.2 omega; distributed in the layer 68: the first resistance contribution percentage of M0G _ GT _ npoly _ svt _ RC is 5.3%, and the first equivalent resistance value is 98.0 Ω; distributed in the layer 73: the first resistance contribution percentage of V0_ M0G _ GT is 0.14%, and the first equivalent resistance value is 2.7 Ω.

Through the steps, the end-to-end equivalent resistance value of the first resistor and the first resistor, the first equivalent resistance value and the first resistor contribution percentage in the node selection information are visually displayed, and compared with the technical scheme that only the parasitic resistor is inversely marked in the layout in the related technology, the parasitic resistor visualization method in the embodiment solves the problems of single function and low positioning efficiency of the parasitic resistor visualization method in the related technology, provides a resistor layer analysis tool, facilitates a designer to quickly know the resistance between nodes in a circuit, calculates the layer resistor contribution, facilitates the designer to know the circuit characteristics and quickly positions the problems in layout design.

In some of these embodiments, after obtaining and displaying at least an end-to-end equivalent resistance value of the first resistor from the first resistor:

The second resistor is a resistor after the user further selects at least one first resistor, and at least one second resistor is arranged; the coordinate range of the resistance selection information is located in the node selection information, the resistance selection information only includes at least one second resistance for further selecting the at least one first resistance, and the further selection can be a full selection or a partial selection; the resistance selection information may be obtained according to the obtained graphical selection information or parameterized selection information of the first resistance in the node selection information by the user, and is not described here again.

Through the steps, the resistance selection information is obtained based on the node selection information, so that the second equivalent resistance value and the contribution percentage of the second resistance are obtained, the second resistance and the related parameters can be highlighted on the basis of highlighting the first resistance and the related parameters, the secondary selection of visualization of the parasitic resistance is realized, the problems of single function and low positioning efficiency of a visualization method of the parasitic resistance in the related technology are solved, a local resistance inspection tool is provided, a designer can conveniently research circuit details, the designer can conveniently and quickly know the resistance among nodes in a circuit, and the problem in layout design is quickly positioned.

In some embodiments, obtaining and displaying at least a second equivalent resistance value of the second resistor according to the second resistor includes:

Specifically, the resistance values of a second resistor and a second resistor are obtained according to the resistor selection information, and the resistance values of the second resistor and the second resistor are highlighted; obtaining the layer information of the second resistor according to the layer information of the first resistor; obtaining a second equivalent resistance value of the second resistor in the end-to-end equivalent resistance values and a second resistor contribution percentage of the second resistor corresponding to the second equivalent resistance value according to the second resistor; displaying the second equivalent resistance value and the second resistance contribution percentage of the second resistance in a window; the second equivalent resistance value and the second resistance contribution percentage are displayed in a window, where the display window may be a floating window or a drop-down window, and the display window may be located on the right side or below the display interface of the terminal device 102.

Preferably, the terminal device 102 obtains resistance selection information that is operated by the user on the basis of the node selection information, and the terminal device 102 highlights a resistance value of the at least one second resistance and/or second resistance selected by the user, where a highlighted attribute of the highlighted second resistance is different from a highlighted attribute of the highlighted first resistance, for example, the highlighted second resistance may be different in color or may be different in brightness, so as to display the second resistance while displaying the first resistance and distinguish the first resistance from the second resistance; the terminal device 102 obtains the layer information of the second resistor according to the layer information of the first resistor, and sends the layer information of the second resistor to the server device 104; the server device 104 obtains a resistance value of a second resistor of the resistor selection information, calculates a second equivalent resistance value according to the resistance value of the second resistor and the layer information corresponding to the second resistor, and sends a second resistor contribution percentage of the second resistor corresponding to the second equivalent resistance value to the terminal device 102; after the terminal device 102 obtains the second equivalent resistance value and the second resistance contribution percentage of the second resistance, displaying the second equivalent resistance value and the second resistance contribution percentage of the second resistance in a window; the calculation formula for the second equivalent resistance value and the second resistance contribution percentage refers to the calculation formula for the first equivalent resistance value and the first resistance contribution percentage, and details are not repeated here. Table 2 below is an example of visualizing the layer equivalent resistance and the resistance contribution corresponding to the resistance selection information based on the node selection information in this embodiment.

Table 2 visual example of layer equivalent resistance and resistance contribution corresponding to resistance selection information

Resistor (group)	Contribution of the second resistance	Second equivalent resistance (ohm)
			Group 1 (R2215098 ~ R2215117)	20.4％	378.0
Group 2 (R2215118 ~ R2215127)	20.7％	382.2
			Group 3 (R2215118 ~ R2215147)	53.0％	978.4

As shown in Table 2, the resistor selection information includes three groups, group 1 includes resistors numbered R2215098-R2215117, group 2 includes R2215118-R2215127, and group 3 includes R2215118-R2215147; the three groups of resistance selection information are mutually independent; the resistors in the above grouping may or may not be on the same layer. The second equivalent resistance of the group 1 is 378.0 omega calculated by the formula, and the contribution percentage of the second resistance is 20.4%; the second equivalent resistance of group 2 is 382.2 Ω, and the second resistance contribution percentage is 20.7%; the second equivalent resistance of group 3 is 978.4 Ω and the second resistance contribution percentage is 53.0%.

A method of visualizing parasitic resistance is also provided in this embodiment. Fig. 7 is a flowchart of another parasitic resistance visualization method according to the embodiment, and as shown in fig. 7, the flowchart includes the following steps:

step S702, a preset parasitic parameter netlist is obtained, and a netlist node and a parasitic resistance in the parasitic parameter netlist are obtained.

Step S704, displaying the netlist node and the parasitic resistance.

Step S706, node selection information for the netlist node is obtained.

Step S708, obtaining a first resistance matched with the node selection information from the parasitic resistance, and displaying at least the first resistance according to preset key identification information.

Step S710, at least obtaining and displaying an end-to-end equivalent resistance value of the first resistor according to the first resistor.

In step S712, resistance selection information is acquired.

Step S714, highlight the second resistor according to the resistor selection information, and obtain and display at least the second equivalent resistance value of the second resistor according to the second resistor.

Through the steps, node selection information for the netlist node is obtained, the first resistor and the end-to-end equivalent resistance of the first resistor are displayed according to the node selection information, compared with the technical scheme that only the parasitic resistor is reversely marked in the layout file in the related technology, the parasitic resistor visualization method in the embodiment can not only achieve reverse marking of the parasitic resistor in the layout file, but also highlight display of the first node and the first resistor in the selection range according to the selection result of the netlist node by a user, and display of the end-to-end equivalent resistance of the first resistor, so that the problems that a parasitic resistor visualization method in the related technology is single in function and low in positioning efficiency are solved, a designer can conveniently and quickly know the resistance between nodes in a circuit, and the problem in layout design is quickly positioned.

It should be understood that although the various steps in the flow diagrams of fig. 2-7 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 2-7 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.

In this embodiment, a parasitic resistance visualization apparatus is further provided, and the apparatus is used to implement the foregoing embodiments and preferred embodiments, which have already been described and are not described again. The terms "module," "unit," "sub-unit," and the like as used below may implement a combination of software and/or hardware of predetermined functions. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.

Fig. 8 is a block diagram of the structure of the parasitic resistance visualization apparatus of the present embodiment, and as shown in fig. 8, the apparatus includes: the device comprises an acquisition module 10, a selection module 20 and a display module 30;

the obtaining module 10 is configured to obtain a preset parasitic parameter netlist, obtain a netlist node and a parasitic resistance in the parasitic parameter netlist, and display the netlist node and the parasitic resistance;

the selection module 20 is configured to obtain node selection information for a node of the netlist, obtain a first resistor matched with the node selection information from the parasitic resistor, and display at least the first resistor according to preset key identification information;

the display module 30 is configured to at least obtain an end-to-end equivalent resistance value of the first resistor according to the first resistor and display the end-to-end equivalent resistance value.

For specific definition of the parasitic resistance visualization device, reference may be made to the above definition of the parasitic resistance visualization method, which is not described herein again. The respective modules in the parasitic resistance visualization device may be entirely or partially implemented by software, hardware, and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

There is also provided in this embodiment a parasitic resistance visualization system, comprising: a terminal device 102, a transmission device, and a server device 104; wherein the terminal device 102 is connected to the server device 104 through the transmission device;

the terminal device 102 is configured to implement any one of the parasitic resistance visualization methods in the above embodiments;

the transmission device is configured to send an end-to-end equivalent resistance value of the first resistor to the terminal device 102;

the server device 104 is configured to calculate an end-to-end equivalent resistance value of the first resistor.

There is also provided in this embodiment an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the above method embodiments.

Optionally, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

Optionally, in this embodiment, the processor may be configured to execute the following steps by a computer program:

s1, acquiring a preset parasitic parameter netlist, acquiring netlist nodes and parasitic resistances in the parasitic parameter netlist, and displaying the netlist nodes and the parasitic resistances.

And S2, acquiring node selection information aiming at the netlist node, acquiring a first resistor matched with the node selection information from the parasitic resistor, and displaying at least the first resistor according to preset key identification information.

And S3, at least obtaining and displaying the end-to-end equivalent resistance value of the first resistor according to the first resistor.

It should be noted that, for specific examples in this embodiment, reference may be made to the examples described in the foregoing embodiments and optional implementations, and details are not described again in this embodiment.

In addition, in combination with the parasitic resistance visualization method provided in the above embodiment, a storage medium may also be provided in this embodiment. The storage medium having stored thereon a computer program; the computer program, when executed by a processor, implements any of the parasitic resistance visualization methods of the above embodiments.

In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 9. The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a parasitic resistance visualization method. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.

Those skilled in the art will appreciate that the architecture shown in fig. 9 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), rambus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to be limiting. All other embodiments, which can be derived by a person skilled in the art from the examples provided herein without any inventive step, shall fall within the scope of protection of the present application.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the patent protection. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A parasitic resistance visualization method is applied to a terminal device and comprises the following steps:

2. The parasitic resistance visualization method according to claim 1, wherein the obtaining node selection information for the netlist node comprises:

acquiring a graph selection instruction aiming at the netlist node and input by a user, and generating node selection information according to the graph selection instruction;

3. The parasitic resistance visualization method according to claim 1, wherein the obtaining a first resistance matching the node selection information from the parasitic resistances and displaying at least the first resistance according to preset highlight identification information comprises:

acquiring the first resistor from the parasitic resistor according to the starting node to be displayed and the terminal node to be displayed;

4. The parasitic resistance visualization method according to claim 1, wherein the obtaining and displaying at least an end-to-end equivalent resistance value of the first resistance according to the first resistance comprises:

5. The parasitic resistance visualization method according to claim 1, wherein after at least an end-to-end equivalent resistance value of the first resistance is obtained from the first resistance and displayed:

6. The parasitic resistance visualization method according to claim 5, wherein the obtaining and displaying at least a second equivalent resistance value of the second resistance according to the second resistance comprises:

7. A parasitic resistance visualization device, comprising: the device comprises an acquisition module, a selection module and a display module;

the display module is used for at least obtaining and displaying an end-to-end equivalent resistance value of the first resistor according to the first resistor.

8. A parasitic resistance visualization system, comprising: a terminal device, a transmission device and a server device; the terminal equipment is connected with the server equipment through the transmission equipment;

the terminal device is used for executing the parasitic resistance visualization method of any one of claims 1 to 6;

the server device is configured to calculate an end-to-end equivalent resistance value of the first resistor.

9. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and the processor is configured to execute the computer program to perform the parasitic resistance visualization method according to any one of claims 1 to 6.

10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the parasitic resistance visualization method according to one of claims 1 to 6.