CN115308943A

CN115308943A - Array substrate and display panel

Info

Publication number: CN115308943A
Application number: CN202211117799.3A
Authority: CN
Inventors: 杨艳娜; 李荣荣
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2022-09-14
Filing date: 2022-09-14
Publication date: 2022-11-08
Anticipated expiration: 2042-09-14

Abstract

The application relates to an array substrate and a display panel. The array substrate comprises a display area and a non-display area located on the periphery of the display area, wherein the array substrate is provided with a conductive pad in the non-display area, the conductive pad comprises a metal layer, an insulating layer and a conductive layer which are sequentially formed on a first substrate, the metal layer comprises a plurality of grids which are arranged in a row-column staggered manner, the metal layer is electrically connected with a first common electrode located in the display area at the same layer, and a plurality of through holes are formed in the insulating layer so that the conductive layer is electrically connected with the first common electrode. The array substrate can improve the conductivity of conductive particles in frame glue, enhance the capability of blocking water vapor from entering, prevent the problem of abnormal picture display caused by in-plane routing corrosion, and further improve the market competitiveness of products.

Description

Array substrate and display panel

Technical Field

The present application relates to the field of display technologies, and in particular, to an array substrate and a display panel.

Background

The Liquid Crystal Display panel (LCD for short) includes an array substrate, a color filter substrate and a Liquid Crystal layer between the array substrate and the color filter substrate, which are oppositely disposed. Alignment films are respectively formed on the inner sides of the array substrate and the color film substrate and used for guiding the arrangement direction of liquid crystal molecules. In addition, the array substrate and the color film substrate are mechanically and electrically connected through the frame glue positioned in the frame area. Conductive particles are formed in the frame glue, the conductive particles are accommodated in the through holes of the conductive bonding pads on the side of the array substrate, one end of each conductive particle is electrically connected with the common electrode of the array substrate through the alignment film on the side of the array substrate, and the other end of each conductive particle is electrically connected with the common electrode of the color film substrate through the alignment film on the side of the color film substrate.

In order to completely cure the frame glue, gaps between the conductive bonding pads are generally designed to be large to increase light transmittance, but the design easily attacks water vapor, so that the problem of abnormal pictures caused by corrosion of in-plane routing lines is solved.

Disclosure of Invention

The application aims at providing an array substrate and a display panel, the array substrate can improve the conductivity of conductive particles in frame glue, enhance the capability of blocking water vapor from entering, and prevent the problem of abnormal picture display caused by in-plane wiring corrosion.

In a first aspect, an embodiment of the present application provides an array substrate, including a display area and a non-display area located at a periphery of the display area, wherein the array substrate is provided with a conductive pad in the non-display area, the conductive pad includes a metal layer, an insulating layer and a conductive layer formed on a first substrate in sequence, the metal layer includes a plurality of grids arranged in a staggered manner in rows and columns, and is electrically connected with a first common electrode located in the display area at the same layer, and the insulating layer is formed with a plurality of via holes so that the conductive layer is electrically connected with the first common electrode.

In a possible embodiment, the grids are arranged in a rectangular shape, the length a of each grid is more than or equal to 50 microns, the width b of each grid is more than or equal to 10 microns, and the line width c between every two adjacent grids is more than or equal to 10 microns; the orthographic projection of the conductive layer on the first substrate covers the orthographic projection of the metal layer on the first substrate.

In one possible embodiment, the conducting layer exceeds the single-side width d of the grid by more than or equal to 2.5 μm.

In one possible embodiment, the grid is arranged in a rectangular shape, the length a of the grid is more than or equal to 500 μm, and the width b of the grid is more than or equal to 10 μm; the conducting layer comprises a plurality of first conducting strips extending along the length direction of the grid and arranged in parallel and a plurality of second conducting strips located between two adjacent first conducting strips and distributed at intervals, and the second conducting strips of two adjacent rows are arranged in a staggered mode.

In one possible embodiment, the width f = (1/20-1/4) × a between two adjacent second conductive strips, and f ≧ 20 μm.

In one possible embodiment, the first conductive strip exceeds the single-side width d of the grid by more than or equal to 2.5 μm.

In a possible embodiment, the width of the first conductive strip is equal to the width of the second conductive strip.

In one possible embodiment, the minimum distance L between the orthographic projection edge of the conductive layer on the first substrate base plate and the via hole is more than or equal to 4.25 mu m.

In a possible embodiment, the array substrate further includes a first alignment film and a sealant, the first alignment film is located on a side of the conductive layer away from the first substrate, conductive particles are formed in the sealant, the conductive particles are accommodated in the via holes, one end of each conductive particle is electrically connected to the first common electrode through the first alignment film, and the other end of each conductive particle is electrically connected to the second common electrode through the second alignment film on the side of the color film substrate of the liquid crystal display panel.

In a second aspect, an embodiment of the present application further provides a display panel, including the array substrate as described above; the color film substrate is arranged opposite to the array substrate; and the liquid crystal layer is arranged between the array substrate and the color film substrate.

According to array substrate and display panel that this application embodiment provided, this array substrate carries out the patterning design with the electrically conductive pad in non-display area, electrically conductive pad is including forming the metal level on first substrate base plate in proper order promptly, insulating layer and conducting layer, the metal level is including being a plurality of grids of ranks crisscross setting, and with the first common electrode that is located the display area with the layer and the electricity connection, the insulating layer is formed with a plurality of via holes, so that the conducting layer is connected with first common electrode electricity, thereby can improve the conductive particle's in the frame gum conductivity, the ability of reinforcing separation steam admission, prevent that the wiring corrosion in the face from appearing the unusual problem of picture display.

Drawings

Features, advantages and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, like parts are given like reference numerals. The drawings are not necessarily to scale, and are merely intended to illustrate the relative positions of the layers, the thicknesses of the layers in some portions being exaggerated for clarity, and the thicknesses in the drawings are not intended to represent the proportional relationships of the actual thicknesses.

Fig. 1 is a schematic top view illustrating a display panel according to an embodiment of the present disclosure;

FIG. 2 shows a cross-sectional view of the display panel of FIG. 1 along the M-M direction;

fig. 3 is a schematic structural diagram illustrating a conductive pad of an array substrate according to a first embodiment of the present application;

fig. 4 is an enlarged schematic view of a region N in fig. 3;

fig. 5 is a schematic structural diagram illustrating a conductive pad of an array substrate according to a second embodiment of the present application;

FIG. 6 shows a cross-sectional view of FIG. 5 taken along the direction P-P;

fig. 7 is a schematic structural diagram illustrating a conductive pad of an array substrate according to a third embodiment of the present application.

Description of the reference numerals:

1. an array substrate; AA. A display area; NA, non-display area;

10. a conductive pad; 101. a plating layer region; 102. an edge region; 11. a first base substrate;

12. a metal layer; 121. a first common electrode;

13. an insulating layer; 13a, a gate insulating layer; 13b, a passivation layer; 131. a via hole;

14. a conductive layer; 141. a first conductive strip; 142. a second conductive strip;

16. frame glue; 161. conductive particles;

2. a color film substrate; 21. a second substrate base plate; 22. a second common electrode; 23. a light-shielding layer; 3. and a liquid crystal layer.

Detailed Description

Features of various aspects of the present application and exemplary embodiments will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof. In the drawings and the following description, at least some well-known structures and techniques have not been shown in detail in order to avoid unnecessarily obscuring the present application; also, the size of the region structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Fig. 1 is a schematic top view illustrating a display panel according to an embodiment of the present disclosure, and fig. 2 is a cross-sectional view of the display panel in fig. 1 along a direction M-M.

Referring to fig. 1 and 2, an embodiment of the present application provides a display panel, including: the liquid crystal display panel comprises an array substrate 1, a color film substrate 2 arranged opposite to the array substrate 1 and a liquid crystal layer 3 arranged between the array substrate 1 and the color film substrate 2. The liquid crystal layer 3 comprises a plurality of liquid crystal molecules, which are typically rod-shaped and both fluid like a liquid and have certain crystalline characteristics. When liquid crystal molecules are placed in an electric field, their alignment direction changes according to the change of the electric field.

The display panel comprises a display area AA and a non-display area NA positioned at the periphery of the display area AA, and a conductive bonding pad 10 is formed on the non-display area NA of the array substrate 1 along the enclosing direction. In a box-forming process of a display panel, a first alignment film and a second alignment film are usually manufactured on the opposite surfaces of the array substrate 1 and the color film substrate 2, respectively, and the first alignment film and the second alignment film are used for limiting the orientation of liquid crystal molecules in the liquid crystal layer 3, then a sealed frame glue 16 is coated on a conductive pad 10 of the array substrate 1 and liquid crystal is dripped in, then the array substrate 1 and the color film substrate 2 are attached in a vacuum state, and finally the frame glue 16 is cured through ultraviolet irradiation, so that the packaging of the array substrate 1 and the color film substrate 2 is completed.

As shown in fig. 2, the array substrate 1 includes a first common electrode 121, a conductive layer 14, and a first alignment film (not shown) sequentially formed on a first substrate 11 in a display area AA, and a conductive pad 10 disposed around a non-display area NA. The color filter substrate 2 includes a light-shielding layer 23, a second common electrode 22, and a second alignment film (not shown in the figure) sequentially formed on the second substrate 21, and the light-shielding layer 23 may be a black matrix and plays a role of light shielding. The sealant 16 is coated on one side of the color film substrate 2, and is irradiated from one side of the array substrate 1 to cure the sealant 16.

Alternatively, the sealant 16 includes an ultraviolet curable resin such as an epoxy resin, and a plurality of conductive particles 161 serving as a conductive material are dispersed and mixed, the conductive particles 161 are accommodated in the via holes 131 of the conductive pads 10 on the array substrate 1 side, and one end of each conductive particle 161 is electrically connected to the first common electrode 121 through the first alignment film, and the other end is electrically connected to the second common electrode 22 through the second alignment film on the color filter substrate 2 side.

The conductive pad 10 in the related art includes a plurality of traces disposed on the same layer as the first common electrode 121 and spaced apart from each other, an insulating layer 13 disposed on the via hole 131, and a conductive layer 14, where the insulating layer 13 is not disposed, and the conductive layer 14 covers the area where the insulating layer 13 is not disposed, so as to prevent water vapor from entering and corroding. In order to achieve the narrow frame, the width of the sealant 16 is generally narrow, for example, less than or equal to 750 μm, so the sealant 16 needs to be completely cured. Therefore, the gap between adjacent wires of the conductive pad 10 is generally designed to be relatively large to increase the light transmittance, however, the design is easy to cause vapor to attack and generate bubbles, which causes the problem of abnormal image display in the corrosion of the wires in the plane.

Therefore, the embodiment of the present application provides an array substrate 1, which can improve the conductivity of the conductive particles 161 in the sealant 16, enhance the ability of blocking the entry of water vapor, and prevent the problem of abnormal image display due to the corrosion of the trace lines in the plane.

The following describes in detail a specific structure of an array substrate provided in embodiments of the present application with reference to the accompanying drawings.

First embodiment

fig. 4 shows an enlarged structural view of the region N in fig. 3.

As shown in fig. 3 and 4, an array substrate 1 provided in a first embodiment of the present disclosure includes a display area AA and a non-display area NA located at a periphery of the display area AA, the array substrate 1 is provided with a conductive pad 10 in the non-display area NA, the conductive pad 10 includes a metal layer 12, an insulating layer 13 and a conductive layer 14 sequentially formed on a first substrate 11, the metal layer 12 includes a plurality of grids G arranged in a staggered manner, and is in the same layer and electrically connected to a first common electrode 121 located in the display area AA, and the insulating layer 13 is formed with a plurality of vias 131, so that the conductive layer 14 is electrically connected to the first common electrode 121.

Specifically, in the display area AA, the array substrate 1 includes a metal layer 12, a gate insulating layer 13a, a semiconductor layer, a source-drain metal layer, an interlayer insulating layer 13b, a conductive layer 14, and a first alignment film sequentially formed on the first substrate 11, wherein the metal layer 12 is formed with a scan line, a gate electrode of a thin film transistor, and a first common electrode 121, and the source-drain metal layer is formed with a data line, a source electrode of the thin film transistor, and a drain electrode of the thin film transistor. The conductive layer 14 may include Indium Tin Oxide (ITO), the conductive layer 14 is formed with a pixel electrode, one of the source electrode and the drain electrode is electrically connected to the data line, and the other of the source electrode and the drain electrode is electrically connected to the pixel electrode. A via hole 131 is formed between the metal layer 12 and the first common electrode 121 in a region between an outer edge of the display area AA and at least one side of the conductive pad 10 of the non-display area NA.

In order to simplify the manufacturing process, the film layers of the conductive pad 10 in the non-display area NA of the array substrate 1 are manufactured simultaneously with the display area AA. The metal layer 12 of the conductive pad 10 is in the same layer as and electrically connected to the first common electrode 121, the insulating layer 13 of the conductive pad 10 may include a gate insulating layer 13a and an interlayer insulating layer 13b, and the conductive layer 14 may be electrically connected to the first common electrode 121 by providing a via 131 on the insulating layer 13.

Alternatively, the material of the metal layer 12 of the conductive pad 10 and the first common electrode 121 may be titanium aluminum titanium (TiAlTi), for example, a titanium film having a thickness of 100nm, an aluminum film having a thickness of 300nm, and a titanium film having a thickness of 50nm are sequentially stacked. The via hole 131 is formed between the metal layer 12 of the conductive pad 10 and the first common electrode 121 at the outer edge of the display area AA, so that the electrostatic charge in the circuit can be reduced, and the circuit can be prevented from being damaged by a large current generated by the discharge of a large amount of electrostatic charge.

As shown in fig. 3 and 4, the solid line is the conductive layer 14, the dotted line is the metal layer 12, and the insulating layer 13 includes the via 131. Since the metal layer 12 of the conductive pad 10 includes a plurality of grids G arranged in a staggered manner in rows and columns, that is, the metal layers 12 are connected in a staggered manner in an i-shape to form a mesh structure, and the insulating layer 13 and the conductive layer 14 are also connected in a staggered manner in an i-shape to form a mesh structure, a meandering path surrounding the plurality of grids G is formed in the non-display area NA. There are two paths for the external water vapor to enter the display area AA from the non-display area NA: one is that the first substrate 10 bypasses a high wall composed of a metal layer 12, an insulating layer 13 and a conducting layer 14 with a certain thickness and then enters a certain grid G without continuously invading forwards, and the heat generated by the display panel is gradually dried; the other is that the heat generated by the display panel has dried along the winding path around the grid G before reaching the display area AA, thereby increasing the complexity of moisture entering the display area AA, and the capability of blocking moisture entering can be enhanced compared to the related art in which the conductive pads 10 are vertical and horizontal traces that intersect vertically.

The insulating layer 13 includes a gate insulating layer 13a and an interlayer insulating layer 13b which are sequentially stacked. Alternatively, the material of the gate insulating layer 13a includes an oxide film such as SiO2, and the material of the interlayer insulating layer 13b includes an inorganic film such as SiN. The conductive layer 14 is located on a side of the insulating layer 13 away from the metal layer 12, the insulating layer 13 is formed with a plurality of via holes 131, so that the conductive layer 14 is electrically connected to the first common electrode 121, one end of the conductive particle 161 is electrically connected to the conductive layer 14 through the first alignment film, that is, one end of the conductive particle 161 is electrically connected to the first common electrode 121, and the other end of the conductive particle 161 is electrically connected to the second common electrode 22 through the second alignment film on the color filter substrate 2 side, which can improve the conductivity of the conductive particle 161.

Since the conductive particles 161 in the sealant 16 have an anisotropic conductive function, the conductive particles are conductive in a direction perpendicular to the color filter substrate 2 and the array substrate 1, and are insulating in a direction parallel to the color filter substrate 2 and the array substrate 1, so that the conductive pad 10 is not short-circuited by the conductive particles 161.

Optionally, the shape of the via 131 is circular, rectangular, or any other shape. The smaller the number of the vias 131, the smaller the contact area between the conductive particles 161 in the sealant 16 and the metal layer 12, and the larger the resistance value, the conductivity of the conductive pad 10 may be affected. The number of the vias 131 needs to consider the size of the vias 131 and other factors, and is determined according to specific design requirements, and will not be described in detail.

According to the array substrate 1 and the display panel provided by the embodiment of the application, the array substrate 1 performs the patterning design on the conductive pad 10 of the non-display area NA, that is, the conductive pad 10 comprises the metal layer 12, the insulating layer 13 and the conductive layer 14 which are sequentially formed on the first substrate 11, the metal layer 12 comprises a plurality of grids G arranged in a staggered manner in rows and columns, and is electrically connected with the first common electrode 121 on the same layer of the display area AA, the insulating layer 13 is formed with a plurality of via holes 131, so that the conductive layer 14 is electrically connected with the first common electrode 121, thereby improving the conductivity of the conductive particles 161 in the frame glue 16, enhancing the capability of blocking water vapor from entering, and preventing the problem of abnormal picture display caused by in-plane routing corrosion.

In some embodiments, the grids G are arranged in a rectangle, the length a of each grid G is more than or equal to 50 μm, the width b of each grid G is more than or equal to 10 μm, and the line width c between every two adjacent grids G is more than or equal to 10 μm; the orthographic projection of the conductive layer 14 on the first substrate 11 covers the orthographic projection of the metal layer 12 on the first substrate 11.

Since the transmittance is higher and the curing of the sealant 16 is more complete when the resistance allows, the reliability and the quality of the display panel are better. The metal layer 12 comprises a plurality of grids G which are arranged in a row-column staggered mode, the grids G are arranged in a rectangular mode, the length a and the width b of each grid G and the line width c between every two adjacent grids G are arranged in the rectangular mode, the light transmittance of the metal layer 12 can be at least 30%, and the curing requirement of the frame glue 16 is met.

In some embodiments, the conductive layer 14 exceeds the single-sided width d of the grid G by 2.5 μm or more. With this arrangement, the conductive layer 14 can cover the metal layer 12 and protect the metal layer 12.

In some embodiments, the minimum distance L between the orthographic projected edge of the conductive layer 14 on the first substrate base plate 11 and the via 131 is ≧ 4.25 μm. With this arrangement, the conductive layer 14 can cover the area without the insulating layer 13, and moisture is prevented from entering the display area AA and corroding.

Second embodiment

Fig. 5 is a schematic structural diagram illustrating a conductive pad of an array substrate according to a second embodiment of the present application, and fig. 6 is a cross-sectional view taken along a P-P direction of fig. 5.

As shown in fig. 5, the array substrate 1 provided in the second embodiment of the present application has a similar structure to the array substrate 1 provided in the first embodiment, except that the lengths of the grids G of the metal layer 12 of the conductive pad 10 are longer, so as to further improve the light transmittance of the conductive pad 10, and further improve the curing effect of the sealant 16. Meanwhile, the conductive layer 14 includes a plurality of first conductive strips 141 extending in the length direction of the grid G and arranged in parallel, and a plurality of second conductive strips 142 distributed at intervals are further disposed between two adjacent first conductive strips 141, and the second conductive strips 142 of two adjacent rows are arranged in a staggered manner.

Specifically, the grid G is arranged in a rectangular shape, the length a of the grid G is more than or equal to 500 mu m, and the width b of the grid G is more than or equal to 10 mu m; the conductive layer 14 includes a plurality of first conductive strips 141 extending in the length direction of the grid G and arranged in parallel, and a plurality of second conductive strips 142 located between two adjacent first conductive strips 141 and distributed at intervals, and the second conductive strips 142 in two adjacent rows are arranged alternately.

As shown in fig. 6, the length a of the mesh G in the present embodiment is increased as compared with the first embodiment, so that the contact area between the conductive particles 161 and the conductive layer 14 becomes small. When the color filter substrate 2 of the liquid crystal display panel is laminated with the array substrate 1, the conductive particles 161 may gather in the gaps of the conductive pads 10 (i.e., the grid G where there is no conductive layer 14) due to the large gap and the flat topography of the conductive pads 10, so that the common electrode between the array substrate 1 and the color filter substrate 2 cannot be conducted.

For this purpose, the conductive layer 14 includes a plurality of first conductive strips 141 extending along the length direction of the grid G and arranged in parallel, and a plurality of second conductive strips 142 distributed at intervals are further disposed between two adjacent first conductive strips 141, and the second conductive strips 142 of two adjacent rows are arranged in a staggered manner.

Because the conductive layer 14 is a transparent film layer, the length a of the grid G is increased, and a plurality of second conductive strips 142 are disposed between two adjacent first conductive strips 141, so that the light transmittance of the conductive pad 10 is not affected, the contact area between the conductive particles 161 and the conductive layer 14 is increased, and the conductivity of the conductive particles 161 is effectively improved.

In some embodiments, the width f = (1/20 to 1/4) × a between two adjacent second conductive strips, and f ≧ 20 μm. If the conductive layer 14 is designed to be full, once the conductive layer 14 is partially broken, moisture can enter along the broken portion and corrode the metal layer 12 through the via hole 131 of the insulating layer 13. Therefore, the width f between two adjacent second conductive strips is greater than or equal to 20 μm, which can further enhance the capability of the conductive pad 10 for blocking the water vapor from entering while increasing the contact area between the conductive particles 161 and the conductive layer 14.

In some embodiments, the width d of the first conductive strip 141 beyond the single side of the grid G is greater than or equal to 2.5 μm. By this configuration, it is ensured that the first conductive strip 141 can cover the metal layer 12 and protect the metal layer 12.

In some embodiments, the width of first conductive strip 141 is equal to the width of second conductive strip 142. The width of the first conductive strip 141 is the sum of the line width of the grid G of the metal layer 12 and the single-side width d, and the width of the second conductive strip 142 is equal to the width of the first conductive strip 141, so that the manufacturing process of the mask plate can be simplified, and the manufacturing cost of the mask plate can be reduced.

Third embodiment

As shown in fig. 7, an array substrate 1 provided in the third embodiment of the present invention has a similar structure to the array substrate 1 provided in the second embodiment, that is, besides the conductive layer 14 includes a plurality of first conductive strips 141 extending along the length direction of the grid G and arranged in parallel, a plurality of second conductive strips 142 are arranged between two adjacent first conductive strips 141 and the second conductive strips 142 in two adjacent rows are arranged alternately, except that the metal layers 12 of the conductive pads 10 are connected alternately in a "king" shape to form a mesh structure.

Specifically, as shown in fig. 7, the solid line is the conductive layer 14, the dotted line is the metal layer 12, and the insulating layer 13 includes the via 131. Wherein two ends of two grids G formed by three rows of metal layers 12 are respectively connected in a shape like the Chinese character 'wang', the middle parts of two grids G formed by the third row of metal layers 12 and the other two adjacent rows of metal layers 12 are connected in a shape like the Chinese character 'wang', so that the whole metal layers 12 are connected in a staggered mode in a shape like the Chinese character 'wang' to form a net structure. Compared with the metal layers 12 connected in an i-shaped staggered manner to form a mesh structure, the density of the metal layers 12 in the width direction of the mesh G is reduced, and the light transmittance of the conductive pad 10 can be further improved.

Further, the conductive layer 14 includes a plurality of first conductive strips 141 extending in the length direction of the grid G and arranged in parallel, and a plurality of second conductive strips 142 located between two adjacent first conductive strips 141 and distributed at intervals, and the second conductive strips 142 of two adjacent rows are arranged in a staggered manner. Compared with the structure of the array substrate 1 provided in the second embodiment, the array substrate 1 provided in this embodiment can further improve the light transmittance of the conductive pad 10 and further improve the curing effect of the sealant 16 under the conditions that the contact area between the conductive particles 161 and the conductive layer 14 is kept unchanged and the conduction capability of the conductive particles 161 is ensured.

It can be understood that the technical solution of the array substrate 1 provided In the embodiments of the present application can be widely applied to various liquid crystal display panels, such as TN (Twisted Nematic) display panel, IPS (In-plane switching) display panel, VA (Vertical Alignment) display panel, and MVA (Multi-Domain Vertical Alignment) display panel.

It should be readily understood that "on 8230" \ 8230on "," on 82303030, and "on 82308230; \ 8230on" \ 8230, and "on 8230;" on 8230, should be interpreted in the broadest sense in this application, such that "on 8230;" on 8230not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers therebetween, and "over" \8230: \8230or \8230: \8230, above "includes not only the meaning of" over "or" on "something, but also the meaning of" over "or" on "with no intervening features or layers therebetween (i.e., directly on something).

The term "substrate" as used herein refers to a material upon which subsequent layers of material are added. The substrate base plate itself may be patterned. The material added atop the substrate base plate may be patterned or may remain unpatterned. Further, the substrate base plate may comprise a wide range of materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate base plate may be made of a non-conductive material (e.g., glass, plastic, or sapphire wafer, etc.).

The term "layer" as used herein may refer to a portion of material that includes a region having a thickness. A layer may extend over the entire underlying or overlying structure or may have a smaller extent than the underlying or overlying structure. Further, a layer may be a region of a continuous structure, homogeneous or heterogeneous, having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of lateral planes at the top and bottom surfaces. The layers may extend laterally, vertically, and/or along a tapered surface. The substrate base may be a layer, may include one or more layers therein, and/or may have one or more layers located thereon, above and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (within which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate comprises a display area and a non-display area positioned at the periphery of the display area,

the array substrate is provided with a conductive pad in the non-display area, the conductive pad comprises a metal layer, an insulating layer and a conductive layer which are sequentially formed on a first substrate, the metal layer comprises a plurality of grids which are staggered in rows and columns and is electrically connected with a first common electrode in the display area at the same layer, and a plurality of through holes are formed in the insulating layer so that the conductive layer is electrically connected with the first common electrode.

2. The array substrate of claim 1, wherein the grids are rectangular, the length a of each grid is greater than or equal to 50 μm, the width b of each grid is greater than or equal to 10 μm, and the line width c between every two adjacent grids is greater than or equal to 10 μm;

the orthographic projection of the conducting layer on the first substrate covers the orthographic projection of the metal layer on the first substrate.

3. The array substrate of claim 2, wherein the single-sided width d of the conductive layer beyond the grid is greater than or equal to 2.5 μm.

4. The array substrate of claim 1, wherein the grid is rectangular, the length a of the grid is greater than or equal to 500 μm, and the width b of the grid is greater than or equal to 10 μm;

the conducting layer comprises a plurality of first conducting strips extending along the length direction of the grid and arranged in parallel and a plurality of second conducting strips located between two adjacent first conducting strips and distributed at intervals, and the second conducting strips in two adjacent rows are arranged in a staggered mode.

5. The array substrate according to claim 4, wherein a width f = (1/20-1/4) × a between two adjacent second conductive strips, and f ≧ 20 μm.

6. The array substrate as claimed in claim 4, wherein the first conductive stripe exceeds the single-side width d of the grid by 2.5 μm or more.

7. The array substrate of claim 6, wherein the width of the first conductive strip is equal to the width of the second conductive strip.

8. The array substrate of claim 1, wherein the minimum distance L between the orthographic projection edge of the conductive layer on the first substrate base plate and the via hole is more than or equal to 4.25 μm.

9. The array substrate according to claim 1, further comprising a first alignment film and a sealant, wherein the first alignment film is located on a side of the conductive layer away from the first substrate, conductive particles are formed in the sealant, the conductive particles are accommodated in the via holes, and one end of each conductive particle is electrically connected to the first common electrode through the first alignment film, and the other end of each conductive particle is electrically connected to the second common electrode through a second alignment film on a side of a color film substrate of the liquid crystal display panel.

10. A display panel, comprising:

an array substrate according to any one of claims 1 to 9;

the color film substrate is arranged opposite to the array substrate;

and the liquid crystal layer is arranged between the array substrate and the color film substrate.