CN115296632A - Automatic gain control circuit with dual-mode continuous gain adjustment and high robustness - Google Patents
Automatic gain control circuit with dual-mode continuous gain adjustment and high robustness Download PDFInfo
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Abstract
The invention provides an automatic gain control circuit with dual-mode continuous gain adjustment and high robustness, which comprises at least one stage of variable gain amplifier unit and a current bias circuit. The variable gain amplifier unit comprises two input differential tubes and two shunt differential tubes connected in parallel, and the adjusting voltage Vc adjusts the current flowing through the input differential tubes by controlling the current flowing through the shunt differential tubes. The load circuit comprises two NMOS load tubes which share a grid electrode and have drain electrodes connected to power supply voltage, and two load shunt branches which are connected in parallel and are composed of PMOS. The current bias circuit is connected with the PMOS load tube in each load shunt branch, and controls the load shunt ratio K of each load shunt branch to adjust the current flowing through the corresponding NMOS load tube. The variable gain amplifier unit forms a dual-mode continuous gain adjustment based on a differential main circuit and a load circuit by controlling the adjusting voltage and the current bias circuit.
Description
Technical Field
The present invention relates to the field of wireless communication technologies, and in particular, to an automatic gain control circuit with dual-mode continuous gain adjustment and high robustness.
Background
AGC (automatic Gain Control) is a part of signal processing circuitry in the field of wireless communications, which utilizes an effective combination of linear amplification and linear attenuation to adjust the output signal. A VGA (variable gain amplifier) is an integral part of the AGC loop to provide adjustable gain. For an open-loop VGA, the single-stage gain is:
wherein the content of the first and second substances,
is the transconductance of the input tube in the VGA, and
is the transconductance of the load tube in the VGA.
To achieve a large gain, on the one hand, the size ratio of the input tubes is required
/
Much larger than the size ratio of the load tube
/
. However, the device is not limited to the specific type of the deviceDue to the current flowing through the input tube
Less than the total current flowing through the load tube
To ensure that both the input tube and the load tube are in saturation state, the maximum can be achieved by
/
)/(
/
) = 4, whereby the maximum gain of the VGA would be limited; in addition, the increase of the size difference between the input tube and the load tube can also greatly weaken the robustness of the VGA to the process; on the other hand based on load current
The gain adjustment of (a) may also be limited by bandwidth. Therefore, for architectural reasons, it is difficult to achieve a high gain of more than 14dB with the gain of the existing open-loop VGA, and the gain adjustment range is very limited, usually only 45dB.
Disclosure of Invention
The present invention provides an automatic gain control circuit with dual-mode continuous gain adjustment and high robustness to overcome the disadvantages of the prior art.
To achieve the above object, the present invention provides an automatic gain control circuit with two-mode continuous gain adjustment and high robustness, which includes at least one stage of a variable gain amplifier unit and a current bias circuit. The variable gain amplifier unit includes a differential main circuit and a load circuit. The differential main circuit comprises two groups of transistors, wherein the first group of transistors comprises two input differential tubes of which the grid electrodes are respectively connected to positive and negative input signals; the second group of transistors comprises two shunt differential tubes, grid electrodes of the two shunt differential tubes are connected with the adjusting voltage respectively, the two shunt differential tubes are connected with the two input differential tubes in parallel correspondingly, and the adjusting voltage Vc adjusts the current flowing through the input differential tubes by controlling the current flowing through the shunt differential tubes. The load circuit comprises two NMOS load tubes sharing a grid electrode and two load shunt branches consisting of PMOS, the two NMOS load tubes are respectively connected with the two input differential tubes in series, the drain electrode of each NMOS load tube is connected to a power supply voltage, and the two load shunt branches are respectively connected with the two NMOS load tubes in parallel to shunt. The current bias circuit is connected with the grid electrode of a PMOS load tube in each load shunt branch on the variable gain amplifier, and controls the load shunt ratio K of each load shunt branch to adjust the current flowing through the NMOS load tube corresponding to the load shunt branch; the variable gain amplifier unit forms a dual-mode continuous gain adjustment based on a differential main circuit and a load circuit by controlling the adjusting voltage and the current bias circuit.
According to an embodiment of the present invention, each load shunt branch comprises two PMOS load transistors connected in series, a source of the first PMOS load transistor is connected to a power voltage, a drain of the first PMOS load transistor is connected to a source of the second PMOS load transistor, and a drain of the second PMOS load transistor is connected to a drain of the input differential transistor.
According to an embodiment of the present invention, the current bias circuit includes a current mirror circuit and a bias current source, the current mirror circuit is symmetrically mirrored with the load shunt branch, and the bias current source is connected between the current mirror circuit and the ground.
According to an embodiment of the invention, the automatic gain control circuit with dual-mode continuous gain adjustment and high robustness further comprises a control circuit for generating adjustment voltage, wherein the control circuit comprises a total current analog branch, a control main circuit, a mirror image differential branch mirrored with the differential main circuit and two operational amplifiers;
the first operational amplifier is connected between the total current analog branch and the control main circuit, and copies the total current on the total current analog branch to a reference tube of the control main circuit;
the second operational amplifier is connected between the main control circuit and the mirror image differential branch circuit, current generated by a control tube of the main control circuit is copied to the mirror image differential branch circuit, and the output of the second operational amplifier forms an adjusting voltage Vc;
based on a control circuit, the current of an input differential tube related to gain adjustment and the total current I of a branch circuit 0 The ratio of (A) to (B) varies exponentially with the difference in control voltages on the reference and control tubes.
According to an embodiment of the invention, on the control main circuit, the reference tube and the control tube are both NMOS tubes working in a sub-threshold region, drain electrodes of the reference tube and the control tube are respectively connected to a power supply voltage through two pull-up resistors, and source electrodes of the reference tube and the control tube are both connected to the ground through a current tail tube;
the reverse input end of the first operational amplifier is connected to the output of the total current analog branch circuit, the same-direction input end of the first operational amplifier is connected with the drain electrode of the reference tube, and the output end of the first operational amplifier is connected to the grid electrode of the current tail tube;
the reverse input end of the second operational amplifier is connected to the drain electrode of the mirrored input differential tube on the mirrored differential branch, the same-direction input end of the second operational amplifier is connected to the drain electrode of the control tube, and the output end of the second operational amplifier forms the adjusting voltage Vc and outputs the adjusting voltage Vc to the grid electrodes of the two mirrored differential tubes on the differential main circuit and the grid electrodes of the two mirrored differential tubes on the mirrored differential branch.
According to an embodiment of the present invention, the automatic gain control circuit with dual-mode continuous gain adjustment and high robustness further comprises a peak detection circuit, an integration circuit and an error amplification circuit connected to the output terminal of the last stage of the variable gain amplifier unit, wherein the peak detection circuit detects the peak voltage outputted from the last stage of the variable gain amplifier unit, and outputs a voltage V proportional to the amplitude of the peak voltage after integration by the integration circuit PD And input to an error amplifier circuit, and amplified to form a gain control voltage V related to the regulated voltage Vc CTL 。
According to an embodiment of the present invention, the peak detection circuit has the same structure as the variable gain amplifier unit, two output voltages of the last stage of the variable gain amplifier unit form two input voltages of the peak detection circuit, and a source of the input differential transistor on the peak detection circuit forms an output terminal and is connected to the integrator circuit.
According to an embodiment of the present invention, the automatic gain control circuit with dual-mode continuous gain adjustment and high robustness further comprises a temperature compensation circuit and a dc mismatch subtraction circuit, wherein the temperature compensation circuit is connected between the error amplification circuit and the control circuit; the direct current mismatch subtraction circuit is connected to the input end of the variable gain amplifier unit.
According to an embodiment of the present invention, the automatic gain control circuit with dual-mode continuous gain adjustment and high robustness includes multiple stages of variable gain amplifier units connected in sequence and having the same structure, the main differential circuit of each variable gain amplifier unit is connected to the adjustment voltage Vc, and the load circuit is connected to the current bias circuit.
According to an embodiment of the present invention, the automatic gain control circuit with dual-mode continuous gain adjustment and high robustness further comprises clamping the dc output voltage of each stage of the variable gain amplifier unit to a fixed voltage V CM The common mode voltage control circuit of (1); the common-mode voltage control circuit comprises a common-mode main circuit and a common-mode negative feedback amplifier, the circuit structure of the common-mode main circuit is the same as that of the variable gain amplifier unit, and two input ends of the common-mode main circuit are connected to a fixed voltage V CM Two output ends of the common mode negative feedback amplifier are connected to the reverse input end of the common mode negative feedback amplifier; the common-mode negative feedback amplifier has its common-mode input connected to a fixed voltage V CM The output end of the common-mode circuit and the grids of two NMOS load tubes form a feedback voltage V together FB And outputs the output to the grids of two NMOS load tubes on a load circuit in the variable gain amplifier unit.
In summary, the present invention provides an automatic gain control circuit with dual-mode continuous gain adjustment and high robustness, wherein the core variable gain amplifier unit is a current steering architecture. The gain adjustment is realized by adjusting the current flowing through the shunt differential tube on the differential main circuit, the NMOS tube is used as the active load and is connected in parallel with a load shunt branch formed by the PMOS tube, and the total current I of the load shunt branch to the branch is adjusted 0 The load split ratio K of the variable gain amplifier is used for improving the maximum gain of the variable gain amplifier and further expanding the adjustment range of the gain; and the adjustment of the gain is divided along with the current and the load of the divided differential tubeThe current on the branch circuit is continuously changed, so that dual-mode continuous gain adjustment is realized. In addition, the introduction of the load split ratio K enables the variable gain amplifier unit to adopt a small input differential tube to load tube size ratio to realize high gain control, and has good process robustness. And the NMOS is used as an active load, so that the influence of the power voltage acting on the drain end of the NMOS load tube on the transconductance of the NMOS load tube can be almost ignored, and the robustness of the power voltage can be realized.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic block diagram of an automatic gain control circuit with dual-mode continuous gain adjustment and high robustness according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of the variable gain amplifier unit, the current bias circuit and the common mode voltage control circuit in fig. 1.
Fig. 3 is a circuit symbol representation of the variable gain amplifier unit of fig. 2.
Fig. 4 is a detailed schematic diagram of the control circuit of fig. 1.
Fig. 5 is a detailed schematic diagram of the peak detection, integration circuit and error amplification circuit of fig. 1.
Fig. 6 is a detailed schematic diagram of the temperature compensation circuit of fig. 1.
Fig. 7 is a graph showing a simulation of the gain of an automatic gain control circuit with dual-mode continuous gain adjustment and high robustness, which includes a three-stage variable gain amplifier.
FIG. 8 shows Δ V CTL And when the value is not less than 0, the gain is changed along with the change of the shunt ratio K under different process conditions.
FIG. 9 shows the gain and linearity error with Δ V for different process conditions with K =0.5 CTL Simulation schematic of the variations.
Fig. 10 shows the gain and linearity error with Δ V for different supply voltages when K =0.5 CTL Simulation schematic of the variations.
Interpretation of terms:
VGA, variable-gain amplifier;
AGC, automatic gain control;
process, voltage, temperature Process, supply voltage and temperature;
dB is Decibel Decibel.
Detailed Description
As shown in fig. 1 and fig. 2, the present embodiment provides an automatic gain control circuit with dual-mode continuous gain adjustment and high robustness, which includes at least one stage of variable gain amplifier unit (hereinafter abbreviated as VGA unit) 1 and a current bias circuit 2. The VGA unit 1 comprises a differential main circuit 11 and a load circuit 12. The differential main circuit 11 comprises two groups of transistors, the first group of transistors comprising gates connected to the positive and negative input signals V, respectively in+ ，V in- Two input differential tubes M11. The second group of transistors comprises two shunt differential tubes M12 with grid electrodes connected with a regulated voltage Vc, the two shunt differential tubes M12 are respectively connected with the two input differential tubes M11 in parallel correspondingly, and the regulated voltage Vc regulates the current flowing through the input differential tubes M11 by controlling the current flowing through the shunt differential tubes M12. The load circuit 12 includes two common-gate NMOS load tubes M13 and two load shunt branches formed by PMOS, the two NMOS load tubes M13 are respectively connected in series with the two input differential tubes M11, and the drain of each NMOS load tube M13 is connected to the power supply voltage VDD. The two load shunt branches are respectively connected in parallel to the two NMOS load tubes M13 for shunting. The current bias circuit 2 is connected to the gate of the PMOS load transistor in each load shunt branch of the variable gain amplifier 1, and controls the load shunt ratio K of each load shunt branch to regulate the current flowing through the NMOS load transistor M13 corresponding to the load shunt ratio K. The variable gain amplifier forms a dual-mode continuous gain adjustment based on the differential main circuit 11 and the load circuit 12 by controlling the adjustment voltage Vc and the current bias circuit 2.
In this embodiment, as shown in fig. 2, each load shunt branch includes two PMOS load transistors M14 and M15 connected in series, a source of the first PMOS load transistor M15 is connected to the power voltage VDD, a drain thereof is connected to a source of the second PMOS load transistor M14, and a drain of the second PMOS load transistor M14 is connected to a drain of the input differential transistor M11. The gates of the two PMOS load transistors M14, M15 are connected to the current bias circuit 2, respectively. The load shunt branch based on the first PMOS load tube M15 and the second PMOS load tube M14 not only effectively improves the copying accuracy of the current mirror in the current bias circuit 2, and prevents the dB linearity of gain from deteriorating. Meanwhile, the two PMOS load tubes also increase the output impedance of the load shunt branch, and the load of the whole VGA unit 1 is prevented from being influenced by the branch load in the current change process, so that the accuracy of the gain simplification formula is influenced. Specifically, in the load circuit, the load of the VGA unit 1 is 1/gm3 (RN) in parallel with the output impedance (RP) of the load shunt branch formed by the two PMOS load tubes M14 and M15. When the load split ratio K is changed, both RN and RP will change; but only changes in RN are required for gain adjustment. Therefore, in the present embodiment, two PMOS load tubes are used to form a load shunt branch to increase RP as much as possible (if only a single PMOS tube M14 is used to shunt, the output impedance is only ro 14), so that RP// RN ≈ RN exists in the whole variation range of the load shunt ratio K, thereby avoiding the influence of RP on the gain of the VGA unit 1. In this embodiment, RP = gm14 × ro15, where gm14 is the transconductance of the second PMOS load transistor M14 and ro14 is the channel resistance thereof; ro15 is the channel resistance of the first PMOS load transistor M15.
As shown in FIG. 2, the VGA unit 1 is a current steering structure, providing a current shunt I 0 =I 1 +I 2 In which I 0 Is the total current, I, of a branch composed of an input differential tube M11 and a shunt differential tube M12 connected in parallel with the input differential tube in the VGA unit 1 1 For the current flowing through the input differential tube M11, I 2 The total current of the VGA unit 1 is 2I for the current flowing through the shunt differential tube M12 0 . A regulating voltage V connected to the grid of the shunt differential tube M12 C Controlling the current I of the shunt differential tube M12 2 Thereby influencing the current I input to the differential tube M11 1 And further realize the adjustment of the gain. The automatic gain control circuit with dual-mode continuous gain adjustment and high robustness provided by the embodiment adds a load shunt structure on the basis of a current rudder architecture to form I 0 =I 1 +I 2 =I 3 +I 4 . Wherein, I 3 And I 4 The currents respectively flowing through the two PMOS load tubes M14 and M15 on one of the NMOS load tubes M13 and the corresponding load shunt branch. Because the grids of the two PMOS load tubes M14 and M15 on the load shunt branch are connected to the current bias circuit 2, the current bias circuit 2 is based on the bias current I CTL Can change the current I of the load shunt branch 4 Further influencing the current I flowing through the NMOS load tube M13 3 . In this embodiment, the voltage V is regulated C And a bias current I CTL A dual-mode continuous gain adjustment is formed and the gain adjustment by the two is independent, thereby greatly expanding the gain adjustment range of the VGA unit 1.
Specifically, for load splitting, a load splitting ratio K (0) is set< K <1) Let I 4 =K*I 0 ，I 3 = (1-K)*I 0 . Thus, the unipolar gain of the VGA unit 1 can be calculated as:
Wherein, g m1 Transconductance of the input differential tube M11; g m3 Is transconductance of an NMOS load tube M13; w is a group of 1 /L 1 The width-to-length ratio of the input differential pipe M11; w is a group of 3 /L 3 The width-to-length ratio of the NMOS load tube M13. In the circuit provided in this embodiment, set (W) 1 /L 1 )/(W 3 /L 3 ) = 2, the single-stage gain of the VGA-enabled unit 1 can be simplified as follows:
For the size ratio of the input differential transistor M11 and the NMOS load transistor M13, the present embodiment is only (W) 1 /L 1 )/(W 3 /L 3 ) = 2 the typical condition of good process robustness is an example to illustrate the performance of the VGA unit 1, which the present invention is not limited in any way.
From equation 2, under the condition that the sizes of the input differential transistor M11 and the NMOS load transistor M13 are determined, the gain of the VGA unit 1 is only subject to the load shunt ratio K and I 1 /I 0 Independent of other process parameters (such as substrate doping concentration); and the introduction of the load split ratio K greatly weakens the influence of the size ratio of the input differential tube M11 and the NMOS load tube M13 on gain adjustment, so that the method has good process robustness. Besides good process robustness, the automatic gain control circuit provided by the embodiment also has high power supply voltage robustness. Specifically, as shown in fig. 2, the power supply voltage VDD is applied to two NMOS load transistors M13 and two load shunt branches including PMOS load transistors M14 and M5 on the load circuit 12. Combining equations 1 and 2, it can be seen that, for the load circuit 12 and the power supply voltage VDD, the influence on the gain is mainly reflected in the load shunt ratio K and the transconductance g of the NMOS load tube m3 . For the load shunt ratio K, in the present embodiment, the current bias circuit 2 is a current mirror structure, which includes a current mirror circuit 21 and a bias current source 22, and the load shunt ratio K is influenced by the bias current I of the bias current source 22 CTL Is controlled and transmitted to the VGA unit 1 via the current mirror circuit 21, so that the load split ratio K is independent of the supply voltage VDD. And transconductance g for NMOS load tube M13 m3 Supply voltage VDD to transconductance g acting on drain terminal of NMOS load tube M3 m3 Is also substantially negligible, whereby a high robustness of the supply voltage can be achieved.
In this embodiment, the gain of the VGA unit 1 can be controlled by controlling the load split ratios K and I 1 /I 0 To be implemented. For the load split ratio K, it is controlled by the current bias circuit 2. In the present embodiment, as shown in fig. 2, the current bias circuit 2 has two bias current sources 22 therein, and the current mirror circuit 21 includes three PMOS transistors M21, M22, M23; the source of the PMOS transistor M21 is connected to the power voltage VDD, and the drain, the gate and the gate of the PMOS transistor M22 are connected together to one of the bias current sources 22 and connected as the output to the gate of the second PMOS load transistor M14 in the VGA unit 1. The drain of the PMOS transistor M22 is connected to another bias current source 22, and the source thereof is connected to the drain of the PMOS transistor M23. Source electrode of PMOS tube M23 is connectedThe gate of the PMOS transistor M22 is connected to another bias current source 22 and outputs the bias current source to the gate of the first PMOS load transistor M15 in the VGA unit 1. In the current bias circuit 2, PMOS transistors M22, M23 form a mirror image with two PMOS loads M14, M15 in the VGA unit 1, and two bias current sources 22 control bias currents I of the PMOS transistors M22, M23 CTL To realize the current I flowing through the two PMOS load tubes M14 and M15 in the VGA unit 1 4 And further realizing the adjustment of the load split ratio K. However, the present invention does not limit the specific circuit structure of the current bias circuit. Other circuit structures based on NMOS load and load shunting to realize a high robustness VGA unit are within the scope of the present invention. For example, in other embodiments, when there is only one PMOS load transistor in the load shunt branch, only one mirror PMOS transistor may be provided in the corresponding current bias circuit to form the control of the bias current.
And for I 1 /I 0 Which is then regulated by a regulating voltage V C And (5) controlling. In this embodiment, the voltage V is regulated C From the control circuit 3. As shown in fig. 4, the control circuit 3 includes a total current analog branch 31, a control main circuit 32, a mirror differential branch 33 which mirrors the differential main circuit 11, and two operational amplifiers A1 and A2. The first operational amplifier A1 is connected between the total current analog branch 31 and the main control circuit 32, and simulates the total current I on the total current analog branch 31 0 Is copied to the reference tube M35 of the control main circuit 32. The second operational amplifier A2 is connected between the main control circuit 32 and the mirror image differential branch 33, and copies the current on the control tube M36 of the main control circuit 32 to the mirror image differential branch 33, and the output of the second operational amplifier A2 forms the regulated voltage Vc. Based on the control circuit 3, a differential tube current I is input 1 And branch total current I 0 Is dependent on the control voltage difference Δ V between the gates of the reference transistor M35 and the control transistor M36 CTL And the gain is exponentially changed, namely, the exponential adjustment (dB linear adjustment) of the VGA gain is realized.
Fig. 4 is a schematic diagram showing a specific structure of the control circuit. The total current analog branch 31 includes two NMOS transistors M33, M34 connected in series in sequence. Wherein the NMOS transistor M33Via a pull-up resistor R 0 The source electrode of the transistor 2 is connected with the drain electrode of the NMOS transistor M34; the NMOS transistor M34 acts as a tail pipe for the branch, and its source is grounded. In the total current analog branch 31, the current flowing through the NMOS transistor M34 is 2I based on the control of the bias on the NMOS transistor M34 0 . For the control main circuit 32, the reference transistor M35 and the control transistor M36 are NMOS transistors, and the drains of the two transistors pass through two pull-up resistors R respectively 0 To supply voltage VDD, and both sources are connected to ground via the current tail M37 of the branch. The grid of the reference tube M35 inputs a reference voltage V REF The grid of the control tube M36 inputs the regulated voltage V CTL . For the mirror image differential branch 33, the structure thereof is mirror image of the structure of the differential main circuit 11 in the VGA unit 1, and the input differential tubes M31 of the two mirror images pass through two pull-up resistors R respectively 0 Connected to a supply voltage VDD; the two mirrored split differential pipes M32 are connected in parallel with the two mirrored input differential pipes M31, respectively. The sources of the four transistors are all connected to ground via the footer M30 of the mirrored differential branch.
The inverting input terminal of the first operational amplifier A1 is connected to the drain of the NMOS transistor M33 in the total current analog branch 31, the inverting input terminal thereof is connected to the drain of the reference transistor M35, and the output thereof is connected to the gate of the current tail pipe M37 of the main control circuit 32. For the second operational amplifier A2, the inverting input terminal thereof is connected to the drains of the two mirrored input differential transistors M31 on the mirrored differential branch 33, the inverting input terminal thereof is connected to the drain of the control transistor M36, and the output terminal thereof forms the regulated voltage Vc through negative feedback.
In the circuit structure, the reference tube M35 and the control tube M36 are sub-threshold tubes, and the I-V characteristics are as follows:
wherein
Is a parameter that is related to both process and temperature;
thermal voltage for sub-threshold tubes;
is a reference voltage connected to the gate of the reference tube M35, n is a sub-threshold slope parameter,
is a control voltage connected to the gate of control tube M36.
In the total current analog branch 31, the voltage of the drain of the NMOS transistor M33 (the voltage connected to the inverting input terminal of the first operational amplifier A1) is:
VDD-2I 0 * R 0 /2=VDD- I 0 * R 0 ；
based on the virtual short circuit characteristic of the first operational amplifier A1, the voltage of the equidirectional input end of the first operational amplifier A1 is as follows:
VDD- I 0 * R 0 ；
the current flowing through the reference tube M35:
I M35 =[VDD- (VDD -I 0 * R 0 )]/R 0 = I 0 ；
similarly, the virtual short circuit characteristic I based on the second operational amplifier A2 M36 = I 1 (ii) a And since the reference tube M35 and the control tube M36 have the same size, the above-described formula of the I-V characteristic can be:
this gives: i is 1 /I 0 With control of the voltage difference
=
And exponentially changes, so that exponential adjustment, namely dB linear adjustment, of the gain of the VGA unit 1 is realized.
In the present embodiment, as shown in fig. 1, the agc circuit with dual-mode continuous gain adjustment and high robustness includes three stages of VGA units 1 connected in sequence and having the same structure, a differential main circuit 11 of each VGA unit 1 is connected to the adjustment voltage Vc, and a load circuit 12 is connected to the current bias circuit 2. However, the present invention is not limited in this respect. In other embodiments, the automatic gain control circuit with dual-mode continuous gain adjustment and high robustness may also include only one or two stages of VGA units.
Substituting equation 3 into equation 2 for calculating the gain of the three-stage variable gain amplifier can obtain the total gain after the three-stage variable gain amplifier is cascaded as follows:
It can also be intuitively obtained from equation 4: total gain A after cascade connection of three-stage variable gain amplifier Vtotal (dB) dependent control voltage difference DeltaV CTL And (4) linear adjustment.
In this embodiment, the control circuit 3 adopts a copy bias technique, and the tail pipe currents of the current analog branch 31, the control main circuit 32 and the mirror image differential branch 33 are all the same as the current of the tail pipe M10 in the VGA unit 1, and are all 2I 0 . In this embodiment, the control circuit 3 further implements the dB linear adjustment of the VGA gain on the basis of generating the adjustment voltage Vc and the load split ratio K to form the dual-mode gain continuous adjustment, thereby further improving the performance of the VGA unit. However, the present invention is not limited to the specific structure of the control circuit. In other embodiments, the control circuit may only output the adjustment voltage Vc to realize I 1 /I 0 Without compromising the dB linearity of the VGA gain. Further, based on the expression of formula 4, it can be seen that: the adjustment of the VGA gain is only based on the load split ratio K and the control voltage difference DeltaV CTL Related, not by the total current I of the branch 0 The influence of (a); in a variable gain amplifier, the total current I of the branch circuit can be adjusted 0 To achieve bandwidth adjustment. Therefore, the automatic gain control circuit with dual-mode continuous gain adjustment and high robustness provided by the embodiment also realizes independent adjustment of gain and bandwidthSection; i.e. adjusting the bandwidth while keeping the gain constant.
Fig. 7 and fig. 8 are gain simulation diagrams of the automatic gain control circuit with two-mode continuous gain adjustment and high robustness provided by the present embodiment. In fig. 7, the ordinate is the variation of Gain (Gain), and the abscissa is the load split ratio K and the control voltage difference Δ V, respectively CTL Which reflects the gain-dependent current divider K and the control voltage difference DeltaV CTL The trend of change of (c). The automatic gain control circuit provided in this embodiment is (W) 1 /L1)/(W 3 /L 3 ) And when = 2 and K =0.75, the maximum three-level cascade gain of 27.1dB can be realized by the three-level VGA unit according to the calculation of formula 2. The introduction of the load shunt ratio K expands the adjustment range of VGA gain, and the simulation of figure 7 shows that the gain adjustment range of the design is 68.2dB (-41.4 dB-26.8 dB); it will have a higher gain and a wider gain adjustment range than existing variable gain amplifiers.
FIG. 8 is a graph of the control voltage difference Δ V CTL Graph of gain versus load split ratio K at 0V. According to the difference of electron drift speeds in P doping and N doping, three typical process deviations of S (slow), T (typical) and F (fast) exist, processes SS, TT and FF (for example, SS represents slow NMOS slow PMOS; TT represents typical typical, FF represents fast NMOS fast PMOS) under three limit conditions are selected, and the influence of process changes on gain is compared. Meanwhile, the influence of different power supply voltages (2.25V, 2.5V and 2.75V) on the gain under the same process condition is also compared. From fig. 8, it can be seen that nine curves are substantially overlapped, which proves that the influence of the change of the process condition and the power supply voltage on the gain is very small, and the change of the gain is basically only changed by the load-shunt ratio K; i.e. with good process and supply voltage robustness.
Fig. 9 compares the effect of three limiting process variations on gain and its dB linearity for K = 0.5. The three gain curves in fig. 9 are substantially coincident and have very good linearity, which not only indicates that the automatic gain control circuit provided by this embodiment has a dB gain with Δ V CTL Linearly and it has further been demonstrated that the variation in gain is little affected by the process conditions, i.e.Has good process robustness. Three error curves indicate that the automatic gain control circuit is at delta V CTL The maximum linearity error in the adjusting range is only +/-0.4 dB, and the dB linearity is good.
Fig. 10 compares the effects of three supply voltages VDD on gain and its dB linearity for K = 0.5. The three gain curves in FIG. 10 are substantially coincident and have very good linearity, again indicating dB gain with Δ V CTL The linear variation and further proves that the variation of the gain is little influenced by the power supply voltage VDD, i.e. the robustness of the power supply voltage is good. Three error curves also indicate that the automatic gain control circuit is at delta V CTL The maximum linearity error in the adjusting range is only +/-0.5 dB, and the dB linearity is good.
The automatic gain control circuit with the dual-mode continuous gain adjustment and the high robustness is additionally provided with a load shunt structure on the basis of a current rudder architecture to achieve the dual-mode gain continuous adjustment, so that the adjustment range of the gain is further expanded while the upper limit of the gain is improved. At the same time, the introduction of the load split ratio K also greatly weakens (W) 1 /L 1 )/(W 3 /L 3 ) The influence of the process condition on the gain adjustment reduces the size difference of the input differential tube M11 and the load tube M13, thereby optimizing the process robustness. And the PMOS load shunt on the load shunt branch further improves the robustness of the drain end of the NMOS load tube to the change of the power supply voltage VDD. In addition, the control circuit 3 generates the adjustment voltage Vc to control I 1 /I 0 And further realizes the dB linear control of the VGA gain, so that the gain adjustment and the bandwidth adjustment are independent.
As shown in fig. 1 and fig. 5, the automatic gain control circuit with dual-mode continuous gain adjustment and high robustness provided in this embodiment further includes a peak detection circuit 4, an integration circuit 5 and an error amplification circuit 6 sequentially connected to the output terminal of the third stage variable gain amplifier 1, wherein the peak detection circuit 4 detects the peak voltage output by the third stage variable gain amplifier 3, and outputs a voltage V proportional to the amplitude of the peak voltage after being integrated by the integration circuit 5 PD And input to the error amplifying circuitA circuit 6 for amplifying to form a gain control voltage V related to the regulated voltage Vc CTL . In this embodiment, the gain control voltage V CTL Is the voltage output to the gate of the control tube M36 on the control circuit 3. As shown in FIG. 5, the peak detection circuit 4 has the same structure as the VGA unit 1, and the two output voltages V of the VGA unit 1 in the third stage VGA_out+ And V VGA_out- Two input voltages of the peak detection circuit 4 are formed, and the source of the input differential tube M41 on the peak detection circuit 4 forms an output and is connected to the integration circuit 5. The integrating circuit is an RC integrating circuit and comprises a resistor R1 and a capacitor C1. In the error amplifying circuit 6, V REF0 Is the error reference voltage. In the present embodiment, the structure of the peak detection circuit 4 based on the variable gain amplifier unit (VGA unit) can further optimize the process and voltage robustness of the AGC loop.
Due to the variation of the currents in the input differential transistor M11 and the NMOS load transistor M13, the dc output voltage of the VGA unit 1 will also vary. In order not to affect the performance of the cascaded VGA, the DC output voltage of the VGA unit 1 needs to be fixed to V CM . In the present embodiment, as shown in fig. 2, the common mode voltage control circuit 7 includes a common mode main circuit 71 having the same circuit structure as the VGA unit 1 and a common mode negative feedback amplifier 72, wherein two input terminals of the common mode main circuit 71 are connected to the fixed voltage V CM And both outputs thereof are commonly connected to the inverting input of the common mode negative feedback amplifier 72. The common-mode negative feedback amplifier 72 has its common-mode input connected to a fixed voltage V CM The output end of the common mode main circuit 71 and the grids of the two NMOS load tubes form a feedback voltage V FB And outputs to the gates of two NMOS load tubes M13 of the VGA unit 1. That is, the common mode main circuit 71 based on VGA structure and the common mode negative feedback amplifier 72 jointly generate the feedback voltage V FB Feedback voltage V FB Simultaneously clamping the DC output voltage of the three-level VGA unit 1 to V CM Therefore, the input common-mode voltage of the VGA unit at the next stage is not influenced by the current change of the VGA unit at the previous stage any more, and a large-area blocking capacitor between cascade circuits is saved.
In this embodiment, the reference tube M35 and the control tube M36 in the control circuit 3 are both sub-threshold tubes, and the formula3 and equation 4 there is a temperature dependent thermal voltage V T In order to make the dB linear gain of the VGA independent of the temperature, the automatic gain control circuit with dual-mode continuous gain adjustment and high robustness provided by the present embodiment further includes a temperature compensation circuit 8. The gain control voltage V output from the error amplifying circuit 6 CTL And a reference voltage V applied to the gate of a reference transistor M35 of the control circuit 3 REF Are input to the temperature compensation circuit 8 for temperature compensation to improve the robustness of the temperature. FIG. 6 shows a form of temperature compensation circuit in which the temperature independent current I B And I PTAT May be generated using a bandgap reference circuit. However, the present invention does not limit the specific structure of the temperature compensation circuit.
In this embodiment, the agc circuit with dual-mode continuous gain adjustment and high robustness further comprises a dc mismatch subtraction circuit (DCOC) 9 connected to the input of the VGA unit 1 for removing dc mismatch, thereby cancelling the dc mismatch caused by the differential structure in the VGA unit 1.
In summary, the present invention provides an automatic gain control circuit with dual-mode continuous gain adjustment and high robustness, wherein the core variable gain amplifier unit is a current steering architecture. The gain adjustment is realized by adjusting the current flowing through the shunt differential tube on the differential main circuit, the NMOS tube is used as the active load and is connected in parallel with a load shunt branch formed by the PMOS tube, and the total current I of the load shunt branch to the branch is adjusted 0 The load split ratio K of the variable gain amplifier is used for improving the maximum gain of the variable gain amplifier and further expanding the adjustment range of the gain; and the adjustment of the gain is continuously changed along with the current of the shunt differential tube and the current on the load shunt branch, so that dual-mode continuous gain adjustment is realized. In addition, the introduction of the load split ratio K enables the variable gain amplifier to adopt a small input differential tube to load tube size ratio to realize high gain control, and has good process robustness. And the NMOS is used as an active load, so that the influence of the power voltage acting on the drain end of the NMOS load tube on the transconductance of the NMOS load tube can be almost ignored, and the robustness of the power voltage can be realized.
Although the present invention has been described with reference to the preferred embodiments, it should be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.
Claims (10)
1. An automatic gain control circuit with dual-mode continuous gain adjustment and high robustness is characterized by comprising at least one stage of variable gain amplifier unit and a current bias circuit;
the variable gain amplifier unit includes:
the differential main circuit comprises two groups of transistors, wherein the first group of transistors comprises two input differential tubes of which the grid electrodes are respectively connected to positive and negative input signals; the second group of transistors comprises two shunt differential tubes, grid electrodes of which are connected with a regulating voltage Vc, the two shunt differential tubes are respectively connected with the two input differential tubes in parallel correspondingly, and the regulating voltage Vc regulates the current flowing through the input differential tubes by controlling the current flowing through the shunt differential tubes;
the load circuit comprises two NMOS load tubes sharing a grid electrode and two load shunt branches consisting of PMOS, wherein the two NMOS load tubes are respectively connected with the two input differential tubes in series, the drain electrode of each NMOS load tube is connected to a power supply voltage, and the two load shunt branches are respectively connected with the two NMOS load tubes in parallel to shunt;
the current bias circuit is connected with the grid electrode of the PMOS load tube in each load shunt branch on the variable gain amplifier unit and controls the load shunt ratio K of each load shunt branch to adjust the current flowing through the NMOS load tube corresponding to the load shunt branch; the variable gain amplifier unit forms dual-mode continuous gain adjustment based on a differential main circuit and a load circuit by controlling and adjusting a voltage and a current bias circuit.
2. The automatic gain control circuit with dual-mode continuous gain adjustment and high robustness of claim 1, wherein each load shunt branch comprises two PMOS load tubes connected in series, a source of the first PMOS load tube is connected to a power supply voltage, a drain of the first PMOS load tube is connected to a source of the second PMOS load tube, and a drain of the second PMOS load tube is connected to a drain of the input differential tube.
3. The automatic gain control circuit with dual-mode continuous gain adjustment and high robustness of claim 2 wherein the current bias circuit comprises a current mirror circuit and a bias current source, the current mirror circuit is symmetrically mirrored with the load shunt branch, and the bias current source is connected between the current mirror circuit and ground.
4. The automatic gain control circuit with dual-mode continuous gain adjustment and high robustness of claim 1, further comprising a control circuit generating an adjustment voltage, wherein the control circuit comprises a total current analog branch, a control main circuit, a mirror differential branch mirrored from the differential main circuit, and two operational amplifiers;
the first operational amplifier is connected between the total current analog branch and the control main circuit, and copies the total current on the total current analog branch to a reference tube of the control main circuit;
the second operational amplifier is connected between the main control circuit and the mirror image differential branch circuit, current generated by a control tube of the main control circuit is copied to the mirror image differential branch circuit, and the output of the second operational amplifier forms a regulated voltage Vc;
based on the control circuit, the input differential tube current and the branch total current I related to gain adjustment 0 The ratio of (A) to (B) varies exponentially with the difference in control voltages on the reference and control tubes.
5. The automatic gain control circuit with dual-mode continuous gain adjustment and high robustness according to claim 4, wherein on the control main circuit, the reference transistor and the control transistor are both NMOS transistors working in a sub-threshold region, the drains of the reference transistor and the control transistor are connected to a power supply voltage through two pull-up resistors respectively, and the sources of the reference transistor and the control transistor are connected to the ground through a current tail pipe;
the reverse input end of the first operational amplifier is connected to the output of the total current analog branch circuit, the same-direction input end of the first operational amplifier is connected with the drain electrode of the reference tube, and the output end of the first operational amplifier is connected to the grid electrode of the current tail tube;
the reverse input end of the second operational amplifier is connected to the drain electrode of the input differential tube of the mirror image on the mirror image differential branch, the same-direction input end of the second operational amplifier is connected to the drain electrode of the control tube, and the output end of the second operational amplifier forms the adjusting voltage Vc and outputs the adjusting voltage Vc to the grid electrodes of the two shunt differential tubes on the differential main circuit and the grid electrodes of the two shunt differential tubes of the mirror image on the mirror image differential branch.
6. The automatic gain control circuit with dual-mode continuous gain adjustment and high robustness as claimed in claim 1 or 4, wherein the automatic gain control circuit with dual-mode continuous gain adjustment and high robustness further comprises a peak detection circuit, an integration circuit and an error amplification circuit connected to the output terminal of the last stage of the variable gain amplifier unit, the peak detection circuit detects the peak voltage output by the last stage of the variable gain amplifier unit, and the peak detection circuit outputs a voltage V proportional to the amplitude of the peak voltage after being integrated by the integration circuit PD And input to an error amplifier circuit, and amplified to form a gain control voltage V related to the regulated voltage Vc CTL 。
7. The automatic gain control circuit with dual-mode continuous gain adjustment and high robustness according to claim 6, wherein the peak detection circuit has the same structure as the variable gain amplifier unit, two output voltages of the last stage of the variable gain amplifier unit form two input voltages of the peak detection circuit, and a source of the input differential transistor on the peak detection circuit forms an output terminal and is connected to the integration circuit.
8. The automatic gain control circuit with dual-mode continuous gain adjustment and high robustness of claim 6, further comprising a temperature compensation circuit and a dc mismatch subtraction circuit, the temperature compensation circuit being connected between the error amplification circuit and the control circuit; the direct current mismatch subtraction circuit is connected to the input end of the variable gain amplifier unit.
9. The automatic gain control circuit with dual-mode continuous gain adjustment and high robustness according to claim 1, wherein the automatic gain control circuit with dual-mode continuous gain adjustment and high robustness comprises a plurality of sequentially connected variable gain amplifier units with the same structure, a main differential circuit of each variable gain amplifier unit is connected to the adjustment voltage Vc, and a load circuit is connected to the current bias circuit.
10. The automatic gain control circuit with dual-mode continuous gain adjustment and high robustness of claim 9 wherein the automatic gain control circuit with dual-mode continuous gain adjustment and high robustness further comprises clamping the dc output voltage of each stage of the variable gain amplifier unit to a fixed voltage V CM The common mode voltage control circuit of (1); the common-mode voltage control circuit comprises a common-mode main circuit and a common-mode negative feedback amplifier, wherein the circuit structure of the common-mode main circuit is the same as that of the variable gain amplifier unit, and two input ends of the common-mode main circuit are connected to a fixed voltage V CM Two output ends of the common mode negative feedback amplifier are connected to the reverse input end of the common mode negative feedback amplifier; the common-mode negative feedback amplifier has its common-mode input connected to a fixed voltage V CM The output end of the common-mode circuit and the grids of two NMOS load tubes form a feedback voltage V together FB And outputs the output to the grids of two NMOS load tubes on a load circuit in the variable gain amplifier unit.
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