CN115295435A - Interposer structure and method of manufacturing the same - Google Patents

Interposer structure and method of manufacturing the same Download PDF

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Publication number
CN115295435A
CN115295435A CN202211021381.2A CN202211021381A CN115295435A CN 115295435 A CN115295435 A CN 115295435A CN 202211021381 A CN202211021381 A CN 202211021381A CN 115295435 A CN115295435 A CN 115295435A
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layer
bonding
substrate
metal
metal layer
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陆路
胡胜
叶国梁
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention relates to an interposer structure and a manufacturing method thereof. The manufacturing method comprises the steps of firstly forming a first bonding substrate comprising at least one first metal layer and a first bonding layer and a second bonding substrate comprising at least one second metal layer and a second bonding layer, then enabling the first bonding substrate and the second bonding substrate to be opposite and bonded, and then removing the second substrate to form an interconnection layer formed by bonding the first metal layer and the second metal layer through the first bonding layer and the second bonding layer on the first substrate, wherein the number of at least one of the first metal layer and the second metal layer is larger than 1, and the number of the metal layers in the interconnection layer is larger than 5, so that the wiring abundance degree of the interposer structure is improved, and compared with a mode of forming the same number of metal layers through a multi-time single-layer stacking method, the production efficiency can be improved, the stress of the interposer structure is reduced, and the risk of peeling of the film layer is reduced. The interposer structure may be formed using the fabrication methods described above.

Description

Interposer structure and method of manufacturing the same
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to an interposer structure and a method for fabricating the same.
Background
As the demand for small, light and highly integrated semiconductor devices increases, a technology of forming a three-dimensional integrated circuit (3D-IC) using a wafer level packaging process is widely used. Currently, some three-dimensional integrated circuits employ interposer structures (interposers) fabricated on the basis of semiconductor substrates (e.g., silicon wafers), the circuit line widths and node pitches of the interposer structures are smaller than those of conventional circuit boards, and the interposer structures can be used to achieve higher-density interconnections between chips and/or between chips and package substrates. Generally, the interposer structure includes stacked multi-layer dielectric layers, and dielectric vias and metal layers formed in the stacked multi-layer dielectric layers, and the addition of the metal layers is advantageous for designing a rich circuit network and solving the problem of routing congestion. Each of the metal layers is typically made thicker (e.g., greater than or equal to 2 μm) to reduce the resistance of the circuit network in the interposer structure and reduce power consumption.
When multiple metal layers in the intermediate layer structure are manufactured, a method of stacking multiple metal layers in a single layer is usually adopted, that is, the metal layers are manufactured layer by layer on the same substrate from bottom to top, a dielectric layer and a dielectric via hole penetrating through the corresponding dielectric layer are formed between two adjacent metal layers, and the two adjacent metal layers are connected with each other by using the dielectric via hole. However, the method of multiple single layer stacking has low production efficiency, and multiple stacking causes a plurality of materials to remain on the edge and the back of the substrate, the remaining materials are prone to cause peeling (peeling), and in the process of stacking metal layers on the same substrate layer by layer, the stress on the substrate is gradually accumulated, when the number of stacked metal layers exceeds a certain number, the stress risk is high, and the reliability of the interposer structure is affected, and in order to ensure the reliability of the interposer structure, the number of stacked metal layers in the interposer structure is currently limited (usually below 5 layers), so that the degree of abundance of wiring is limited, and the problem of wiring congestion is easily generated.
Disclosure of Invention
In order to obtain an interposer structure with more metal layers, to improve the routing margin, avoid routing congestion, improve the production efficiency, and reduce the risk of stress and film peeling, the present invention provides a method for manufacturing the interposer structure, and further provides an interposer structure.
In one aspect, the present invention provides a method for fabricating an interposer structure, the method comprising:
forming a first bonding substrate, wherein the first bonding substrate comprises a first substrate, at least one first metal layer and a first bonding layer, the first metal layer is sequentially overlapped on the first substrate, the first bonding layer is positioned on the at least one first metal layer, when more than one first metal layer is arranged, two adjacent first metal layers are separated by a first interlayer dielectric layer and are connected through a first dielectric via hole penetrating through the first interlayer dielectric layer, a first bonding pad is formed in the first bonding layer, and the first bonding pad is connected with the first metal layer which is positioned farthest away from the first substrate;
forming a second bonding substrate, wherein the second bonding substrate comprises a second substrate, at least one second metal layer and a second bonding layer, the second metal layer is sequentially overlapped on the second substrate, the second bonding layer is positioned on the at least one second metal layer, when more than one second metal layer is arranged, two adjacent second metal layers are separated by a second interlayer dielectric layer and are connected through a second dielectric via hole penetrating through the second interlayer dielectric layer, a second bonding pad is formed in the second bonding layer, and the second bonding pad is connected with the second metal layer which is positioned farthest away from the second substrate;
a first bonding layer in the first bonding substrate and a second bonding layer in the second bonding substrate are opposite to each other and bonded, wherein the first bonding pad and the second bonding pad are in bonding connection;
removing the second substrate to form an interconnection layer on the first substrate, wherein the interconnection layer is formed by bonding the at least one first metal layer and the at least one second metal layer through the first bonding layer and the second bonding layer, the number of layers of at least one of the first metal layer and the second metal layer is greater than 1, and the number of layers of metal layers in the interconnection layer is greater than 5.
Optionally, after removing the second substrate, the manufacturing method further includes:
and forming a metal pad on one side of the second metal layer far away from the first substrate, wherein the metal pad is connected with the second metal layer far away from the first substrate.
Optionally, the first bonding substrate includes a TSV via, one end of the TSV via is buried in the first substrate, and the other end of the TSV via is connected to the first metal layer on the first substrate, which is located closest to the first substrate.
Optionally, after removing the second substrate, the manufacturing method further includes:
and thinning the first substrate to expose one end of the TSV conducting hole, which is far away from the first metal layer.
Optionally, the thickness of each of the first metal layers and the second metal layers is in a range of 2 μm to 5 μm.
Optionally, before bonding, the number of the first metal layers on the first bonding substrate is less than or equal to 5, and the number of the second metal layers on the second bonding substrate is less than or equal to 5.
Optionally, a first bonding layer in the first bonding substrate and a second bonding layer in the second bonding substrate are bonded by hybrid bonding.
In one aspect, the present invention provides an interposer structure comprising:
a first substrate;
the first metal layers are sequentially overlapped on the first substrate, and when more than one first metal layer is arranged, two adjacent first metal layers are separated by a first interlayer dielectric layer and are connected by a first dielectric via hole penetrating through the first interlayer dielectric layer;
a first bonding layer on the at least one first metal layer, the first bonding layer having first bonding pads formed therein, the first bonding pads being connected to the first metal layer located farthest from the first substrate;
the second bonding layer is positioned on the first bonding pad and bonded with the first bonding pad, a second bonding pad is formed in the second bonding layer, and the second bonding pad is bonded and connected with the first bonding pad; and the number of the first and second groups,
the at least one layer of second metal layer is sequentially superposed on the second bonding layer, and when more than one layer of second metal layer is arranged, two adjacent layers of second metal layers are separated by a second interlayer dielectric layer and are connected by a second dielectric via hole penetrating through the second interlayer dielectric layer;
the at least one first metal layer and the at least one second metal layer are bonded through the first bonding layer and the second bonding layer to jointly form an interconnection layer, the number of layers of at least one of the first metal layer and the second metal layer is greater than 1, and the number of layers of metal layers in the interconnection layer is greater than 5.
Optionally, the interposer structure further includes:
and the metal pad is positioned on the plurality of second metal layers and is connected with the second metal layer farthest from the first substrate.
Optionally, the number of the first metal layers is less than or equal to 5, and the number of the second metal layers is less than or equal to 5.
In the manufacturing method of the interposer structure provided by the invention, a first bonding substrate and a second bonding substrate are formed, the first bonding substrate comprises at least one first metal layer and a first bonding layer, the second bonding substrate comprises at least one second metal layer and a second bonding layer, then the first bonding layer in the first bonding substrate and the second bonding layer in the second bonding substrate are opposite and bonded, then the second substrate is removed, an interconnection layer formed by bonding at least one first metal layer and at least one second metal layer through the first bonding layer and the second bonding layer is formed on the first substrate, in addition, the number of layers of at least one of the first metal layer and the second metal layer is more than 1, the number of layers of the metal layers in the interconnection layer is more than 5, the sum of the number of layers of the first metal layer and the second metal layer (the first bonding layer and the second bonding layer are not included) is increased, the manufacturing method of the invention can reduce the number of times of the via layers and the manufacturing efficiency of the interposer structure, and can also reduce the risk of the dielectric layer manufacturing by adopting the method of the invention.
The interposer structure provided by the invention comprises a first substrate, and at least one first metal layer and at least one second metal layer which are sequentially superposed on the first substrate, wherein the at least one first metal layer and the at least one second metal layer are bonded through a first bonding layer and a second bonding layer to jointly form an interconnection layer, the number of layers of at least one of the first metal layer and the second metal layer is greater than 1, and the number of layers of the metal layers in the interconnection layer is greater than 5, so that the interposer structure has more metal layers under the condition of reducing stress risk and film peeling risk, and the interposer structure is favorable for designing a sufficient circuit network and avoiding wiring congestion.
Drawings
Fig. 1 is a flow chart illustrating a method for manufacturing an interposer structure according to an embodiment of the invention.
Fig. 2A to 2F are schematic cross-sectional views illustrating a method for manufacturing an interposer structure during a process of forming a first bonding substrate according to an embodiment of the invention.
Fig. 3 is a schematic cross-sectional view of a second bonded substrate formed by a method for manufacturing an interposer structure according to an embodiment of the invention.
Fig. 4 is a schematic cross-sectional view of a first bonding substrate and a second bonding substrate bonded by using the interposer structure manufacturing method according to an embodiment of the invention.
FIG. 5 is a cross-sectional view of the interposer structure after removal of the second substrate according to one embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of a first metal layer after forming metal pads thereon by using a method for manufacturing an interposer structure according to an embodiment of the invention.
Description of reference numerals:
100-a first bonded substrate; 101-a first substrate; 102-a bottom insulating layer; 103-a first insulating layer; 110 — a first metal layer; 120-a first interlayer dielectric layer; 130-first dielectric via; 140-a first bonding layer; 141-first bond pads; 200-a second bonded substrate; 201-a second substrate; 210-a second metal layer; 220-a second interlayer dielectric layer; 230-second dielectric via hole; 240-a second bonding layer; 241-second bond pads; 300-metal pads; 150-TSV via.
Detailed Description
The interposer structure and the method of fabricating the same according to the present invention are further described in detail below with reference to the accompanying drawings and the embodiments. It is noted that the terms "first," "second," and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances. Similarly, if a method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, some of the described steps may be omitted, and/or some other steps not described herein may be added to the method.
It is to be understood that the drawings in the specification are in simplified form and are not to scale, the drawings being for the purpose of facilitating clarity and aiding in the description of embodiments of the invention. Furthermore, spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation of the device depicted in the figures. For example, if the structure in the figures is inverted or otherwise positioned (e.g., rotated) in a different manner, the exemplary term "above … …" may also include "below … …" and other orientation relationships. Although elements in the drawings may be readily apparent from the drawings as they are illustrated and described, in order to make the description of the elements more clear, not all of the elements will be labeled and described.
Interconnections between chips and/or between chips and package substrates may be achieved using interposer structures (interposers), such as may be used to form power supply networks that meet the power requirements of the chips. In the interposer structure, the patterned metal layer can serve as a lead. When designing a circuit network of an interposer structure, a single metal layer often cannot meet the requirement of circuit layout, and the circuit layout often requires multiple layers of lead wires formed by stacked multiple layers of metal layers, and the multiple layers of lead wires are interconnected. Increasing the number of metal layers can improve the degree of abundance of wiring, avoid wiring congestion, reduce the wiring difficulty of a single metal layer, and also improve the flexibility of the wiring of the metal layers. In addition, in order to reduce the resistance of the circuit network in the interposer structure and reduce the power consumption, each of the metal layers is usually made thicker, for example, it can be made greater than or equal to 2 μm, and further, the thickness of each of the metal layers is, for example, in the range of 2 μm to 5 μm.
In order to obtain an interposer structure including a plurality of metal layers, so as to increase the degree of routing margin, avoid routing congestion, increase the production efficiency, and reduce the risk of stress and film peeling, a method for manufacturing the interposer structure according to an embodiment of the present invention is first described, and the method for manufacturing the interposer structure according to an embodiment of the present invention is further described with reference to the accompanying drawings.
Referring to fig. 1 and 2F, a first step S1 of the method for manufacturing an interposer structure according to an embodiment of the present invention includes: forming a first bonded substrate 100, wherein the first bonded substrate 100 comprises a first substrate 101, at least one first metal layer 110 sequentially stacked on the first substrate 101, and a first bonding layer 140 located on the at least one first metal layer 110, when more than one first metal layer 110 is provided, two adjacent first metal layers 110 are separated by a first interlayer dielectric layer 120 and connected by a first dielectric via 130 penetrating through the first interlayer dielectric layer 120, a first bonding pad 141 is formed in the first bonding layer 140, and the first bonding pad 141 is connected with the first metal layer 110 located farthest from the first substrate 101.
The first substrate 101 is, for example, a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium substrate, an SOI (Silicon On Insulator) substrate, a GOI (Germanium On Insulator) substrate, or the like. Illustratively, the first substrate 101 is a silicon substrate here. Depending on the specific design of the interposer structure, electronic components (at least one of MOS devices, sensing devices, memory devices, passive devices, etc.) may or may not be formed in the silicon substrate.
Fig. 2A is a schematic cross-sectional view illustrating a bottom insulating layer and TSV via holes formed on a first substrate by using a method for manufacturing an interposer structure according to an embodiment of the invention. Fig. 2B is a schematic cross-sectional view of a first metal layer closest to a first substrate formed on the first substrate by a method for manufacturing an interposer structure according to an embodiment of the invention. Fig. 2C is a schematic cross-sectional view illustrating a first interlayer dielectric layer and a first dielectric via hole formed on a first metal layer closest to a first substrate by using a method for manufacturing an interposer structure according to an embodiment of the invention. Fig. 2D is a schematic cross-sectional view of a method for fabricating an interposer structure according to an embodiment of the present invention after forming two first metal layers. Fig. 2E is a schematic cross-sectional view of a 5-metal layer stack formed by the method of manufacturing an interposer structure according to an embodiment of the invention. Fig. 2F is a schematic cross-sectional view illustrating a first bonding layer formed by a method for manufacturing an interposer structure according to an embodiment of the invention. The first step S1 is further described below with reference to fig. 2A to 2F.
Referring to fig. 2A, before the first metal layer 110 is formed on the first substrate 101, a bottom insulating layer 102 may be formed on the first substrate 101, and the bottom insulating layer 102 is used to isolate the first substrate 101 from the first metal layer 110 to be formed later. The bottom insulating layer 102 may comprise silicon oxide, silicon nitride, silicon oxynitride, or other suitable material. In this embodiment, the bottom insulating layer 102 includes a silicon oxide layer covering the front surface of the first substrate 101.
Further, after the bottom insulating layer 102 is formed, at least one blind via penetrating through the bottom insulating layer 102 and a portion of the first substrate 101 may be formed by using a photolithography and etching process, then a barrier layer (not shown, for example, comprising silicon oxide) may be formed along an inner surface of the blind via, and the blind via may be filled with a conductive material (for example, copper or other suitable material) by using an electroplating or electroless plating process, and then the conductive material covering the upper surface of the bottom insulating layer 102 may be removed by using a planarization process (for example, chemical mechanical polishing, CMP), where the blind via and the conductive material filled therein form a TSV via 150, and one end of the TSV via 150 is buried in the first substrate 101 and the other end of the TSV via is located on the upper surface of the bottom insulating layer 102. The end of the TSV via 150 buried in the first substrate 101 may be coupled to an electronic component in the first substrate 101, but is not limited thereto, in this embodiment, in the first step, the end of the TSV via 150 buried in the first substrate 101 is not coupled to the electronic component in the first substrate 101, or no electronic component is disposed in the first substrate 101, so that the end of the TSV via 150 buried in the first substrate 101 is not coupled to any electronic component. The TSV via 150 is located at one end of the upper surface of the bottom insulating layer 102 for connecting with the first metal layer 110 located closest to the first substrate 101 on the first substrate 101 to be formed later.
For example, the forming of the first metal layer 110, the first interlayer dielectric layer 120 and the first dielectric via 130 on the first substrate 101 may include the following steps:
first, referring to fig. 2B, a first layer of a first metal layer 110 (i.e., a second metal layer 110 on the first substrate 101 located closest to the first substrate 101) is formed on the bottom insulating layer 102. In this embodiment, the first metal layer 110 is used for a first layer of wiring on the first substrate 101, and is made of, for example, copper, and has a thickness of, for example, 2 μm to 5 μm; specifically, a first insulating layer 103 may be formed on the bottom insulating layer 102, then a trench corresponding to the first layer of wiring is formed in the first insulating layer 103 through photolithography and etching processes, the trench exposes the TSV via 150, copper is filled in the trench through an electroplating or chemical plating process, and a planarization process (such as chemical mechanical polishing, CMP) is used to remove the copper on the upper surface of the first insulating layer 103, where the copper in the trench serves as the first layer of the first metal layer 110;
next, referring to fig. 2C, a first interlayer dielectric layer 120 is formed on the insulating layer 103 and the first metal layer 110 (the first interlayer dielectric layer 120 may include a silicon nitride layer and a silicon oxide layer on the silicon nitride layer), a through hole is formed in the first interlayer dielectric layer 120, the through hole exposes a set region of the first metal layer 110, and then a conductive material (e.g., copper) is filled in the through hole by using an electroplating or chemical plating process, and the conductive material on the upper surface of the first interlayer dielectric layer 120 is removed by using a planarization process, and the through hole and the conductive material filled therein form a first dielectric via 130;
then, referring to fig. 2D, a second layer of the first metal layer 110 is formed on the first interlayer dielectric layer 120 and the first dielectric via 130, where "first layer" and "second layer" refer to the sequence from the direction close to the first substrate 101 to the direction away from the first substrate 101. The second layer of the first metal layer 120 is used for performing a second layer of wiring on the first substrate 101, and the second layer of the first metal layer 110 may be manufactured by the same process as the first layer of the first metal layer 110, that is, a corresponding first insulating layer 103 is formed first, a trench corresponding to the second layer of wiring is formed in the first insulating layer 103, copper is filled in the trench corresponding to the second layer of wiring by using an electroplating or electroless plating process, and the copper on the upper surface of the first insulating layer 103 is removed by using a planarization process, and the copper in the trench corresponding to the second layer of wiring is used as the second layer of the first metal layer 110;
using the above-described process of stacking the first metal layers 110, at least one first metal layer 110 may be sequentially stacked on the first substrate 101, as shown in fig. 2E. In this embodiment, the first insulating layer 103 and the first interlayer dielectric layer 120 each include a silicon nitride layer that helps prevent copper diffusion and a silicon oxide layer on the silicon nitride layer.
Optionally, the conductive material (here, for example, copper) in the first dielectric via 130 and the first metal layer 110 located above the conductive material may be formed by using the same electroplating process or the same chemical plating process, at this time, after a first interlayer dielectric layer 120 is formed, a through hole may not be formed first, but the first insulating layer 103 is deposited and a corresponding trench is formed in the first insulating layer 103, then a photolithography and etching process is performed to form a through hole penetrating through the lower first interlayer dielectric layer 120 in the trench, then an electroplating or chemical plating process is performed to fill copper in the trench of the first insulating layer 103 and the through hole in the lower first interlayer dielectric layer 120, and then a planarization process is performed to remove the copper located on the upper surface of the first insulating layer 103, so that the first dielectric via 130 and the first metal layer 110 located above the corresponding first dielectric via 130 and connected to the corresponding first dielectric via 130 may also be obtained.
The wiring pattern corresponding to each first metal layer 110 formed on the first substrate 101 may be provided according to the specific design of the circuit network of the interposer structure to be fabricated. The wiring patterns corresponding to the first metal layers 110 may be the same or different. In addition, the position of the first dielectric via 130 formed on each first metal layer 110 may be adjusted as necessary by using the wiring extension pattern of the first metal layer 110.
Research shows that when the first metal layer 110 is formed on the first substrate 101 by the above method, as the number of layers of the first metal layer 110 increases, stress on the first substrate 101 is accumulated, and if the accumulated stress exceeds a safe range, the reliability of the interposer structure is reduced; furthermore, as the number of layers of the first metal layer 110 increases, the amount of residual material (which may include silicon oxide, silicon nitride, copper, or other reactants, for example) on the side and the back of the first substrate 101 increases, increasing the probability of peeling off the film, which also reduces the reliability of the interposer structure. Therefore, when the first bonding substrate 100 is formed in the first step S1, the number of the first metal layers 110 is set in consideration of the stress risk and the peeling risk, and is not more than a certain value as much as possible, so as to ensure that the stress risk and the peeling risk are within a safe range and avoid affecting the reliability of the interposer structure to be manufactured. In this embodiment, the number of layers of the first metal layer 110 in the first bonding substrate 100 is less than or equal to 5, and the statistics on the number of layers do not include the first bonding layer 140 formed subsequently. As shown in fig. 2E, in the present embodiment, 5 layers of the first metal layer 110 are formed on the first bonding substrate 110.
In order to make the interposer structure to be manufactured include more metal layers, so as to increase the routing margin of the interposer structure and avoid routing congestion, in the embodiment of the invention, the first step S1 further forms a first bonding layer 140 on the stacked at least one first metal layer 110, so as to perform a bonding process, and superimposes at least one metal layer formed on the basis of another substrate (hereinafter, referred to as a second substrate) on the first bonding substrate 100.
Referring to fig. 2F, for example, forming the first bonding layer 140 on the first metal layer 110 may include the following processes:
first, a dielectric layer (for example, including a silicon nitride layer and a silicon oxide layer on the silicon nitride layer) is deposited on the uppermost first metal layer 110 on the first substrate 101;
then, a through hole exposing the uppermost first metal layer 110 is formed in the dielectric layer through a first photolithography and etching process, and then an opening is formed in the dielectric layer through a second photolithography and etching process, wherein the depth of the opening is smaller than that of the through hole formed through the first photolithography and etching process, the radial dimension of the opening is larger than that of the through hole, the opening can be formed at a position corresponding to the through hole, so as to be communicated with the through hole at a corresponding position, but not limited thereto, a part of the opening can also be formed in a region outside the through hole;
next, an electroplating or chemical plating process is performed to deposit a conductive material (e.g., copper or other suitable material) in the through hole and the opening formed in the dielectric layer, a planarization process is performed to remove the conductive material on the upper surface of the dielectric layer, the conductive material filled in the through hole and the opening that are communicated with each other is connected to the first metal layer 110 located farthest from the first substrate 101 to form a first bonding pad 141, and only the conductive material formed in the opening forms a dummy bonding pad (not shown), where the first bonding layer 140 may include the dielectric layer and the first bonding pad 141 and the dummy bonding pad disposed in the dielectric layer.
Referring to fig. 1 and 3, the second step S2 of the method for manufacturing an interposer structure according to the embodiment of the present invention includes: forming a second bonded substrate 200, wherein the second bonded substrate 200 includes a second substrate 201, at least one second metal layer 210 sequentially stacked on the second substrate 201, and a second bonding layer 240 located on the at least one second metal layer 210, when there are more than one second metal layers 210, two adjacent second metal layers 210 are separated by a second interlayer dielectric layer 220 and connected by a second dielectric via 230 penetrating through the second interlayer dielectric layer 220, a second bonding pad 241 is formed in the second bonding layer 240, and the second bonding pad 241 is connected with the second metal layer 210 located farthest from the second substrate 201.
In the second step S2, the second bonded substrate 200 is formed based on the second substrate 201, and the second bonded substrate 200 does not need to be manufactured based on the first step S1, so that the second step S2 may be performed before or after the first step S1, or may be performed simultaneously with the first step S1 as long as the first bonded substrate 100 and the second bonded substrate 200 are formed before the third step S3.
In this embodiment, at least one second metal layer 210 stacked sequentially is formed on the second substrate 201, so as to avoid the problems of low production efficiency, high stress risk and high peeling risk when a metal layer is formed on the first substrate 101 by a single layer too many times. Here, the second substrate 201 is equivalent to a carrier plate, and is removed later. The second substrate 201 is, for example, a silicon substrate, on which electronic components and dielectric via holes penetrating into the second substrate 201 are not required to be formed.
In the second step S2, the forming of the at least one second metal layer 210 sequentially stacked on the second substrate 201 may be performed with reference to the method of the first step S1 for forming the at least one first metal layer 110 sequentially stacked on the first substrate 101, and the forming of the second bonding layer 240 on the at least one second metal layer 210 may be performed with reference to the method of the first step S1 for forming the first bonding layer 140 on the at least one first metal layer 110, which is not described herein again.
Similar to the first bonding substrate 100, when the second bonding substrate 200 is formed in the second step S2, the number of the second metal layers 210 is set to take the stress risk and the peeling risk into consideration, and should not exceed a certain value as much as possible, so as to ensure that the stress risk and the peeling risk are within a safe range and avoid affecting the reliability of the interposer structure to be manufactured. In this embodiment, in the second bonding substrate 200, the number of layers of the second metal layer 210 is less than or equal to 5, and the statistics on the number of layers do not include the second bonding layer 240. As shown in fig. 3, in the present embodiment, the second bonding substrate 200 includes 4 second metal layers 210 stacked on the second substrate 201 in a direction from near the second substrate 201 to far from the second substrate 201. In order to reduce the resistance and the power consumption of the interposer structure, each second metal layer 210 of the second bonding substrate 200 is made thicker, and the thickness thereof is, for example, in the range of 2 μm to 5 μm.
Referring to fig. 1 and 4, a third step S3 of the method for manufacturing an interposer structure according to the embodiment of the present invention includes: the first bonding layer 140 in the first bonding substrate 100 and the second bonding layer 240 in the second bonding substrate 200 are opposed to each other and bonded, wherein the first bonding pad 141 and the second bonding pad 241 are bonded.
In performing the third step S3, the second bonding substrate 200 may be turned over such that the side of the first bonding substrate 100 on which the first metal layer 110 is formed and the side of the second bonding substrate 200 on which the second metal layer 210 is formed are opposite to each other, and bonded together after being aligned. As an example, the bonding method of the first and second bonding substrates 100 and 200 is hybrid bonding (hybrid bonding). When the hybrid bonding is performed, the first and second bonding pads 141 and 241, whose positions correspond to each other, are aligned and bonded. If dummy bonding pads are formed on the first and second bonding substrates 100 and 200, the dummy bonding pads corresponding to each other may be aligned and bonded. In addition, the dielectric layer in the first bonding layer 140 and the dielectric layer in the second bonding layer 240 may also be bonded together. The invention is not limited in this regard and in other embodiments, the at least one first bond pad 141 and the at least one second bond pad 241 are, for example, offset from each other but have portions thereof bonded together. Since the first bonding pad 141 is connected to the first metal layer 110 formed on the first substrate 101 and the second bonding pad 241 is connected to the second metal layer 210 formed on the second substrate 201, the first metal layer 110 and the second metal layer 210 are electrically conducted to each other after the first bonding pad 141 and the second bonding pad 241 are bonded.
Referring to fig. 1 and 5, a fourth step S4 of the method for manufacturing an interposer structure according to the embodiment of the present invention includes: the second substrate 201 is removed. For example, grinding, etching, or a combination of grinding and etching may be used.
Through the above steps, at least one first metal layer 110 and at least one second metal layer 210 sequentially stacked on the first substrate 101 are obtained, and an interconnection layer formed by bonding the first metal layer 110 and the second metal layer 210 through the first bonding layer 140 and the second bonding layer 240 is formed on the first substrate 101, where the number of metal layers in the interconnection layer is the sum of the number of layers of the first metal layer 110 and the number of layers of the second metal layer 210.
In this embodiment, in order to increase the number of metal layers in the interposer structure, the number of layers of at least one of the first metal layer 110 on the first bonding substrate 100 and the second metal layer 210 on the second bonding substrate 200 is greater than 1, and the number of layers of metal layers in the interconnection layer is greater than 5 (the statistics on the number of layers do not include the first bonding layer 140 and the second bonding layer 240). The number of layers of the first metal layer 110 formed on the basis of the first substrate 101 may be the same as or different from the number of layers of the second metal layer 210 formed on the basis of the second substrate 201.
As an example, if the number of layers of the first metal layer 110 formed on the basis of the first substrate 101 is set to M and the number of layers of the second metal layer 210 formed on the basis of the second substrate 201 is set to N, the values of M and N may be set to any one of the following settings:
m =1 and N =5, or M =2 and N =4, or M =3 and N =3, or M =4 and N =2, or M =5 and N =1, respectively, the number of layers of metal layers in the interconnect layer is 6;
m =2 and N =5, or M =3 and N =4, or M =4 and N =3, or M =5 and N =2, respectively, the number of layers of metal layers in the interconnect layer is 7;
m =3 and N =5, or M =4 and N =4, or M =5 and N =3, respectively, the number of metal layers in the interconnection layer is 8;
m =4 and N =5, or M =5 and N =4, and accordingly, the number of metal layers in the interconnection layer is 9;
m =5 and N =5, and accordingly, the number of metal layers in the interconnection layer is 10, which is a preferable solution to obtain an interconnection layer having up to 10 metal layers on the basis of ensuring that the stress risk and the peeling risk of the first bonded substrate 100 and the second bonded substrate 200 are within a safe range.
After removing the second substrate 201, a second metal layer 210 may be formed on the first metal layer 110 in the manner described above, and another bonding substrate may be bonded on the second metal layer 210 farthest from the first substrate 101 to stack more metal layers, as needed. Specifically, the method for manufacturing an interposer structure according to an embodiment of the present invention may further include the following steps: forming at least two of the second bonded substrates 200; after removing the second substrate 201 of the second bonding substrate 200 bonded to the first bonding substrate 100, sequentially bonding the remaining second bonding substrates 200 to the previous second bonding substrate 200, and removing the second substrate 201 of the second bonding substrate 200 that is currently bonded, so as to obtain an interposer structure with a required number of metal layers. For example, on the basis of obtaining a bonding substrate 200 including 10 metal layers on the first substrate 101 by the above setting of M =5 and N =5, the number of metal layers in the interconnection layer can be made to be 11, 12, 13, 14, 16, 17, 18, 19, 20 or more layers in a similar manner by further stacking and bonding a second bonding substrate 200 including 5 second metal layers 210.
By forming a plurality of metal layers on the first substrate 101 by using the above-described manufacturing method, not only can the wiring margin of the interposer structure be increased, but also the production efficiency can be increased by using the manufacturing method described in the embodiments of the present invention, compared to a method in which the same number of metal layers are formed by a method of stacking a plurality of single layers, and in the manufacturing method described in the embodiments of the present invention, the number of times of depositing an insulating material, forming a dielectric via hole, and forming a metal layer on the same substrate is reduced, so that the stress of the resulting interposer structure can be reduced, and the risk of peeling off the film can be reduced.
In order to facilitate the connection between the interposer structure and the external chip or package substrate, referring to fig. 6, after removing the second substrate 201, the method for manufacturing the interposer structure according to the embodiment of the present invention may further include the following steps: a metal pad is formed on the side of the second metal layer 210 away from the first substrate 101, and the metal pad is connected to the second metal layer 210 farthest away from the first substrate 101.
For example, an insulating layer may be formed on the surface obtained after the second substrate 201 is removed (or an insulating bottom layer in the second bonding substrate 200 is used, where the insulating bottom layer may be left after the second substrate 201 is removed), then a photolithography and etching process may be performed on the insulating layer by using a photolithography process to form an opening that exposes the second metal layer 210 farthest from the first substrate 101, then a conductive material (such as aluminum, an alloy including aluminum, or other suitable materials) is deposited, a conductive layer that covers the insulating layer and fills the opening is formed, then the conductive layer is etched, then a protective layer 301 that covers the conductive layer and the insulating layer is formed, and the protective layer 301 is etched to expose a portion of the conductive layer, where the exposed portion of the conductive layer is the metal pad 300. The position of the metal pad 300 in a plane parallel to the upper surface of the first substrate 101 may be set as desired.
Alternatively, in order to connect the interposer structure with an external chip or package substrate on the back side of the first substrate 101 (i.e., the side of the first substrate 101 away from the first metal layer 110 and the second metal layer 210), after forming the metal pads 300, the method for manufacturing the interposer structure according to an embodiment may further include the following steps: the first substrate 101 is thinned, so that one end of the TSV via 150, which is far away from the first metal layer 110, is exposed. A redistribution layer connected to the TSV vias 150 and metal pads (not shown) connected to the redistribution layer for connecting the interposer structure to an external chip or package substrate on the back side of the first substrate 101 may then be formed on the back side of the first substrate 101.
Embodiments of the present invention also relate to an interposer structure that can be formed using the fabrication methods described in the above embodiments. Referring to fig. 6, the interposer structure includes:
a first substrate 101;
at least one first metal layer 110 sequentially superposed on the first substrate 101, wherein when more than one first metal layer 110 is provided, two adjacent first metal layers 110 are separated by a first interlayer dielectric layer 120 and connected by a first dielectric via 130 penetrating through the first interlayer dielectric layer 120;
a first bonding layer 140 located on the at least one first metal layer 110, wherein a first bonding pad 141 is formed in the first bonding layer 140, and the first bonding pad 141 is connected to the first metal layer 110 located farthest from the first substrate 101;
a second bonding layer 240 located on the first bonding layer 140 and bonded to the first bonding layer 140, wherein a second bonding pad 241 is formed in the second bonding layer 240, and the second bonding pad 241 is bonded to the first bonding pad 141; and the number of the first and second groups,
at least one second metal layer 210 sequentially stacked on the second bonding layer 240, and when more than one second metal layer 210 is provided, two adjacent second metal layers 210 are separated by a second interlayer dielectric layer 220 and connected by a second dielectric via 230 penetrating through the second interlayer dielectric layer 220;
the at least one first metal layer 110 and the at least one second metal layer 210 are bonded together through the first bonding layer 140 and the second bonding layer 240 to form an interconnection layer, the number of layers of at least one of the first metal layer 110 and the second metal layer 210 is greater than 1, and the number of layers of metal layers in the interconnection layer is greater than 5.
In some embodiments, the interposer structure further comprises a metal pad 300, the metal pad 300 being located on the at least one second metal layer 210, the metal pad 300 being connected to the second metal layer 210 that is farthest from the first substrate 101.
In order to reduce the resistance of the circuit network provided by the interposer structure and reduce power consumption, each of the first metal layers 110 and each of the second metal layers 210 is preferably formed to be thicker, for example, each of them has a thickness ranging from 2 μm to 5 μm.
The interposer structure of the embodiment of the invention includes a first substrate 101 and at least one first metal layer 110 and at least one second metal layer 210 sequentially stacked on the first substrate 101, and a first bonding layer 140 and a second bonding layer 240 bonded to each other are provided between the first metal layer 110 and the second metal layer 210, the at least one first metal layer 110 and the at least one second metal layer 210 jointly form an interconnection layer by bonding the first bonding layer 140 and the second bonding layer 240, the number of layers of at least one of the first metal layer 110 and the second metal layer 210 is greater than 1, and the number of layers of metal layers in the interconnection layer is greater than 5 (the statistics on the number of layers does not include the first bonding layer 140 and the second bonding layer 240). The first metal layer 110 and the second metal layer 210 in the interposer structure are stacked and interconnected by bonding, so that the interposer structure has more metal layers under the condition of reducing the risk of stress and the risk of film peeling, the degree of routing is increased, a sufficient circuit network is designed, and routing congestion is avoided.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
The above description is only for the purpose of describing preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art may make possible variations and modifications of the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modifications, equivalent changes and modifications of the above embodiments according to the technical essence of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims (10)

1. A method of fabricating an interposer structure, comprising:
forming a first bonding substrate, wherein the first bonding substrate comprises a first substrate, at least one first metal layer and a first bonding layer, the first metal layer is sequentially overlapped on the first substrate, the first bonding layer is positioned on the at least one first metal layer, when more than one first metal layer is arranged, two adjacent first metal layers are separated by a first interlayer dielectric layer and are connected through a first dielectric via hole penetrating through the first interlayer dielectric layer, a first bonding pad is formed in the first bonding layer, and the first bonding pad is connected with the first metal layer which is positioned farthest away from the first substrate;
forming a second bonding substrate, wherein the second bonding substrate comprises a second substrate, at least one second metal layer and a second bonding layer, the second metal layer is sequentially overlapped on the second substrate, the second bonding layer is positioned on the at least one second metal layer, when more than one second metal layer is arranged, two adjacent second metal layers are separated by a second interlayer dielectric layer and are connected through a second dielectric via hole penetrating through the second interlayer dielectric layer, a second bonding pad is formed in the second bonding layer, and the second bonding pad is connected with the second metal layer which is positioned farthest away from the second substrate;
a first bonding layer in the first bonding substrate and a second bonding layer in the second bonding substrate are opposite to each other and bonded, wherein the first bonding pad and the second bonding pad are in bonding connection;
removing the second substrate to form an interconnection layer on the first substrate, wherein the interconnection layer is formed by bonding the at least one first metal layer and the at least one second metal layer through the first bonding layer and the second bonding layer, the number of layers of at least one of the first metal layer and the second metal layer is greater than 1, and the number of layers of metal layers in the interconnection layer is greater than 5.
2. The manufacturing method according to claim 1, wherein after removing the second substrate, the manufacturing method further comprises:
and forming a metal pad on one side of the second metal layer far away from the first substrate, wherein the metal pad is connected with the second metal layer far away from the first substrate.
3. The method of manufacturing according to claim 1, wherein the first bonded substrate includes a TSV via, one end of the TSV via is buried in the first substrate, and the other end is connected to the first metal layer on the first substrate that is located closest to the first substrate.
4. The manufacturing method of claim 3, wherein after removing the second substrate, the manufacturing method further comprises:
and thinning the first substrate to expose one end of the TSV conducting hole far away from the first metal layer.
5. The manufacturing method according to claim 1, wherein each of the first metal layers and each of the second metal layers has a thickness in a range of 2 μm to 5 μm.
6. The manufacturing method according to claim 1, wherein the number of layers of the first metal layer on the first bonding substrate is 5 or less, and the number of layers of the second metal layer on the second bonding substrate is 5 or less, before bonding.
7. The manufacturing method according to claim 1, wherein the first bonding layer in the first bonding substrate and the second bonding layer in the second bonding substrate are bonded using hybrid bonding.
8. An interposer structure, comprising:
a first substrate;
the first metal layers are sequentially overlapped on the first substrate, and when more than one first metal layer is arranged, two adjacent first metal layers are separated by a first interlayer dielectric layer and are connected by a first dielectric via hole penetrating through the first interlayer dielectric layer;
a first bonding layer on the at least one first metal layer, the first bonding layer having a first bonding pad formed therein, the first bonding pad being connected to the first metal layer located farthest from the first substrate;
the second bonding layer is positioned on the first bonding pad and bonded with the first bonding pad, a second bonding pad is formed in the second bonding layer, and the second bonding pad is bonded and connected with the first bonding pad; and the number of the first and second groups,
the at least one layer of second metal layer is sequentially superposed on the second bonding layer, and when more than one layer of second metal layer is arranged, two adjacent layers of second metal layers are separated by a second interlayer dielectric layer and are connected by a second dielectric via hole penetrating through the second interlayer dielectric layer;
the at least one first metal layer and the at least one second metal layer are bonded through the first bonding layer and the second bonding layer to jointly form an interconnection layer, the number of layers of at least one of the first metal layer and the second metal layer is greater than 1, and the number of layers of metal layers in the interconnection layer is greater than 5.
9. The interposer structure of claim 8, further comprising:
a metal pad on the at least one second metal layer, the metal pad being connected to the second metal layer furthest from the first substrate.
10. The interposer structure of claim 8, wherein the number of layers of the first metal layer is less than or equal to 5 and the number of layers of the second metal layer is less than or equal to 5.
CN202211021381.2A 2022-08-24 2022-08-24 Interposer structure and method of manufacturing the same Pending CN115295435A (en)

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