CN114783984A - Three-dimensional integrated device and manufacturing method thereof - Google Patents

Three-dimensional integrated device and manufacturing method thereof Download PDF

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CN114783984A
CN114783984A CN202210432164.6A CN202210432164A CN114783984A CN 114783984 A CN114783984 A CN 114783984A CN 202210432164 A CN202210432164 A CN 202210432164A CN 114783984 A CN114783984 A CN 114783984A
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bonding
substrate
wafer
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pad
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薛晓晨
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

The invention relates to a three-dimensional integrated device and a manufacturing method thereof. The three-dimensional integrated device comprises three bonding layers which are sequentially overlapped along the thickness direction, each bonding layer comprises a substrate and an interconnection structure arranged on the front side of the corresponding substrate, and a via hole arranged on the back side of one bonding layer is bonded with a bonding pad arranged on the front side of the other bonding layer on a bonding interface. The three-dimensional integrated device can be manufactured by the manufacturing method, can save working procedures and shorten the manufacturing period while realizing three-dimensional integration, can adopt a circulating mode to carry out wafer stacking and bonding, is convenient to realize integration of a plurality of wafers by adopting an automatic working procedure, and can save cost.

Description

Three-dimensional integrated device and manufacturing method thereof
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a three-dimensional integrated device and a method for manufacturing the three-dimensional integrated device.
Background
The three-dimensional integration technology can realize high-performance integrated interconnection circuits, and is a new technology for obtaining high-performance chips. When a chip is manufactured by using a three-dimensional integration technology, different wafers are used to manufacture a part of circuits respectively, then the wafers with the circuits are bonded together, and the circuits on the wafers are connected with each other to form a complete circuit system.
Disclosure of Invention
In order to shorten the manufacturing period and reduce the process cost while realizing three-dimensional integration, the invention provides a three-dimensional integrated device and a manufacturing method of the three-dimensional integrated device.
In one aspect, the present invention provides a three-dimensional integrated device, including a first bonding layer, a second bonding layer, and a third bonding layer sequentially stacked along a thickness direction, where the first bonding layer, the second bonding layer, and the third bonding layer each include a substrate and an interconnection structure disposed on a front surface of the corresponding substrate, a first bonding interface is formed between the first bonding layer and the second bonding layer, and a second bonding interface is formed between the second bonding layer and the third bonding layer; the first bonding interface is provided with a first through hole which is arranged on the first bonding layer and penetrates through the corresponding substrate from the back side, and a first bonding pad which is arranged on the second bonding layer and is positioned on the front side of the corresponding substrate; and at the second bonding interface, a second via hole which is arranged on the second bonding layer and penetrates through the corresponding substrate from the back surface is bonded with a second bonding pad which is arranged on the third bonding layer and is positioned on the front surface of the corresponding substrate.
Optionally, the three-dimensional integrated device further includes a fourth bonding layer, a fifth bonding layer, a second bonding layer, and an mth bonding layer, which are sequentially stacked on a side of the third bonding layer away from the second bonding layer, each bonding layer including a substrate and an interconnection structure disposed on a front surface of the substrate, and an (N-1) th bonding interface is formed between the (N-1) th bonding layer and the nth bonding layer; and in the (N-1) th bonding interface, a (N-1) th via hole which is arranged in the (N-1) th bonding layer and penetrates through the corresponding substrate from the back side is bonded with a (N-1) th bonding pad which is arranged in the Nth bonding layer and is positioned on the front side of the corresponding substrate, M is an integer greater than or equal to 4, and N is greater than or equal to 2 and less than or equal to M.
Optionally, the first bonding layer includes a first substrate, a first interconnection structure disposed on a front surface of the first substrate, and a first dielectric layer disposed on a back surface of the first substrate, and the first via hole penetrates through the first dielectric layer and the first substrate and is electrically connected to the first interconnection structure; the second bonding layer comprises a second substrate, a second interconnection structure arranged on the front surface of the second substrate, a second dielectric layer and the first bonding pad, and the first bonding pad penetrates through the second dielectric layer and is electrically connected with the second interconnection structure.
Optionally, a first virtual bonding pad is disposed on a surface of the first dielectric layer facing the first bonding interface, a second virtual bonding pad is disposed on a surface of the second dielectric layer facing the first bonding interface, and the first virtual bonding pad is bonded to the second virtual bonding pad.
Optionally, the second interconnect structure includes a top metal layer disposed toward the first bonding interface, the second dielectric layer is located between the top metal layer and the first bonding interface, and the first bonding pad penetrates through the second dielectric layer and is electrically connected to the top metal layer.
Optionally, the second bonding layer includes a third dielectric layer disposed on the back surface of the second substrate, and the second via hole penetrates through the third dielectric layer and the second substrate and is electrically connected to the second interconnection structure; the third bonding layer comprises a third substrate, a third interconnection structure arranged on the front surface of the third substrate, a fourth dielectric layer and a second bonding pad, and the second bonding pad penetrates through the fourth dielectric layer and is electrically connected with the third interconnection structure.
Optionally, the three-dimensional integrated device further includes a lead-out pad, where the lead-out pad is disposed on a side of the first bonding layer away from the first bonding interface, and is electrically connected to the first interconnection structure.
Optionally, the three-dimensional integrated device comprises a wafer-level or chip-level longitudinal stacking structure.
In one aspect, the present invention provides a method for fabricating a three-dimensional integrated device, the method comprising a first step and a second step performed in sequence; the first step comprises: providing a first wafer, wherein the first wafer comprises a first substrate, a first interconnection structure formed on the front surface of the first substrate and a first dielectric layer formed on the back surface of the first substrate; forming a first via hole penetrating through the first dielectric layer and the first substrate on the back of the first substrate; providing a second wafer, wherein the second wafer comprises a second substrate, a second interconnection structure formed on the front surface of the second substrate and a first bonding pad connected with the second interconnection structure; bonding the first wafer and the second wafer to form a first bonding interface, wherein the first through hole is bonded with the first bonding pad at the first bonding interface; the second step includes: forming a third dielectric layer and a second via hole penetrating through the third dielectric layer and the second substrate on the back surface of the second wafer; providing a third wafer, wherein the third wafer comprises a third substrate, a third interconnection structure formed on the front surface of the third substrate and a second bonding pad connected with the third interconnection structure; and bonding the second wafer and a third wafer to form a second bonding interface, wherein the second via hole is bonded with the second bonding pad at the second bonding interface.
Optionally, the manufacturing method further includes: and circularly executing the second step, and bonding at least one wafer on the side, far away from the second wafer, of the third wafer in a stacking way, wherein each wafer comprises a substrate and an interconnection structure arranged on the front surface of the corresponding substrate.
Optionally, in the first step, when the first via hole is formed on the back surface of the first substrate, a first dummy bonding pad is further formed on the back surface of the first dielectric layer; when the first bonding pad is formed on the front surface of the second wafer, a second virtual bonding pad is further formed on the surface of the second dielectric layer; and at the first bonding interface, the second virtual bonding pad is bonded with the second virtual bonding pad.
Optionally, in the first step, the step of forming the first via hole and the first dummy bonding pad on the back surface of the first wafer includes: carrying out photoetching and etching processes on the back of the first substrate, forming at least one groove on the surface of the first dielectric layer, and forming at least one opening in the first wafer, wherein the opening penetrates through the first dielectric layer and the first substrate and exposes the first interconnection structure; and filling a conductive material in the opening and the groove, wherein the conductive material in the opening is electrically connected with the first interconnection structure to form the first via hole, and the conductive material in the groove forms the first dummy bonding pad.
Optionally, in the first wafer, the front surface of the first substrate is bonded to a carrier substrate, and after the second wafer is bonded to the third wafer, the manufacturing method further includes: removing the bearing substrate; and forming a lead-out pad on the front surface of the first substrate, wherein the lead-out pad is electrically connected with the first interconnection structure.
Optionally, after the forming of the extraction pad, the manufacturing method further includes: and cutting the wafer-level longitudinal stacking structure comprising the first wafer, the second wafer and the third wafer to obtain a plurality of chips.
The three-dimensional integration device provided by the invention has a simpler structure while realizing three-dimensional integration, is convenient for realizing more layers of stacking bonding, is beneficial to saving working procedures, shortens the manufacturing period, is convenient to realize by adopting an automatic working procedure, and can save the cost.
The manufacturing method of the three-dimensional integrated device provided by the invention has the advantages that the three-dimensional integration is realized, meanwhile, the process flow is shortened compared with the prior art, the manufacturing period can be shortened, the wafer stacking and bonding can be carried out in a circulating mode, the integration of a plurality of wafers is conveniently realized by adopting an automatic process, and the cost can be saved.
Drawings
Fig. 1 is a schematic cross-sectional view of a three-dimensional integrated device.
Fig. 2 is a schematic flow chart illustrating a method for manufacturing a three-dimensional integrated device according to an embodiment of the present invention.
Fig. 3A to fig. 3F are schematic cross-sectional views illustrating a manufacturing method of a three-dimensional integrated device according to an embodiment of the invention during a manufacturing process.
Description of reference numerals:
10-a first bonding layer; 11. 101-a carrier substrate; 12. 110-a first substrate; 12. 120-a first interconnect structure; 14-via holes; 15-rewiring layer; 16. 230-a first bond pad; 20-a second bonding layer; 21. 210-a second substrate; 22. 220-a second interconnect structure; 23. 330-second bond pad; 100-a first wafer; 130-a first dielectric layer; 100 a-grooves; 100 b-open pore; 140 — a first via hole; 150-a first dummy bond pad; 200-a second wafer; 240-a second dielectric layer; 250-a second dummy bond pad; 260-a third dielectric layer; 270-a second via hole; 280-a third dummy bond pad; 300-a third wafer; 310-a third substrate; 320-a third interconnect structure; 340-a fourth dielectric layer; 350-fourth dummy bond pads; 160-lead-out pad.
Detailed Description
The three-dimensional integrated device and the method for manufacturing the same according to the present invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be understood that the drawings in the specification are in simplified form and are not to be taken in a precise scale, for the purpose of facilitating and distinctly claiming the embodiments of the present invention. It should be noted that the order of steps in the methods presented herein is not necessarily the only order in which the steps are performed, some of the described steps may be omitted and/or some other steps not described herein may be added to the methods.
Fig. 1 is a schematic cross-sectional view of a three-dimensional integrated device. Referring to fig. 1, the three-dimensional integrated device includes a first bonding Layer 10 and a second bonding Layer 20 bonded to each other, the first bonding Layer 10 includes a carrier substrate 11 and a first substrate 12 on the carrier substrate 11, a first interconnection structure 13 is disposed on a front surface of the first substrate 12, a via hole 14 connected to the first interconnection structure 13, a Redistribution Layer (RDL) 15 and a first bonding pad 16 are disposed on a rear surface of the first substrate 12, the second bonding Layer 20 includes a second substrate 21 and a second interconnection structure 22 disposed on a front surface of the second substrate 21 and a second bonding pad 23 connected to the second interconnection structure 22, and the first bonding pad 16 of the first bonding Layer 10 and the second bonding pad 23 of the second bonding Layer 20 are bonded together at a bonding interface of the first bonding Layer 10 and the second bonding Layer 20. It can be seen that the three-dimensional integrated device shown in fig. 1 has a complex structure, and the first bonding layer 10 needs to undergo multiple photolithography processes before bonding, and if different photomasks are needed to fabricate the redistribution layer 15 and the portions of different depths of the first bonding pad 16 on the back surface of the first substrate 12, the process is complex, the cost is high, and it is not favorable for bonding more than three bonding layers. Further, in the three-dimensional integrated device, when the position of the first bonding pad 16 is set, it is necessary to avoid overlapping (overlap) of the longitudinal portion of the first bonding pad 16 with the orthographic projection of the via hole 14 on the rear surface of the first substrate 12 to reduce stress accumulation, which limits the design flexibility of the via hole 14.
Compared with the three-dimensional integrated device and the manufacturing process thereof shown in the figure 1, the embodiment of the invention can simplify the structure of the three-dimensional integrated device, save the process, shorten the manufacturing period, facilitate the automatic realization, be conductive to reducing the process cost for manufacturing the three-dimensional integrated device and realize the integration of more bonding layers on the basis of realizing the three-dimensional integration of each bonding layer.
Fig. 2 is a schematic flow chart illustrating a method for manufacturing a three-dimensional integrated device according to an embodiment of the invention. Referring to fig. 2, the method for fabricating a three-dimensional integrated device according to the embodiment of the present invention includes a first step S1 and a second step S2, which are sequentially performed, wherein the first step S1 completes bonding of a first wafer and a second wafer, and the second step S2 completes bonding of the second wafer and a third wafer based on the first step S1. Fig. 3A to 3F are schematic cross-sectional views illustrating a manufacturing method of a three-dimensional integrated device according to an embodiment of the invention during a manufacturing process. The following describes a method for fabricating a three-dimensional integrated device according to an embodiment of the invention with reference to fig. 2 and fig. 3A to 3F.
Referring to fig. 2 and 3A, the first step S1 of the method for manufacturing a three-dimensional integrated device according to the embodiment of the present invention includes: a first wafer 100 is provided, the first wafer 100 including a first substrate 110, a first interconnect structure 120 formed on a front surface of the first substrate 110, and a first dielectric layer 130 formed on a back surface of the first substrate 110.
The first wafer 100 is, for example, a silicon wafer or other semiconductor substrate. The first wafer 100 may perform various semiconductor processing and the first wafer 100 may be formed with one or more electronic components. The electronic components are formed on the first substrate 110, for example, and the first interconnect structure 120 is formed over the electronic components, where the side where the electronic components and the first interconnect structure 120 are formed is a front side of the first substrate 110, and the other side opposite to the front side is a back side of the first substrate 110. The first substrate 110 may be a semiconductor substrate, and for example, may be a Silicon substrate, a Germanium (Ge) substrate, a Germanium-Silicon substrate, an SOI (Silicon On Insulator) substrate, a GOI (Germanium On Insulator) substrate, or the like. The electronic component may include at least one of a MOS device, a sensing device, a storage device, and a passive device, the sensing device may be a photosensitive device, the storage device may include a nonvolatile memory or a random access memory, the nonvolatile memory may include a floating gate field effect transistor such as a NOR flash memory or a NAND flash memory, a ferroelectric memory or a phase change memory, and the passive device may include a resistor or a capacitor. The electronic component may be a planar device or a three-dimensional device, such as a Fin-FET (Fin field effect transistor) or a three-dimensional memory. The electronic component may be covered by a dielectric material, the dielectric material may be a stacked structure and may include silicon oxide, silicon nitride, silicon oxynitride, or the like, the first interconnect structure 120 is formed in the dielectric material, the first interconnect structure 120 may include at least one of a via plug, a via hole, and a wiring layer, the wiring layer may be one or more layers, and the first interconnect structure 120 may include a metal material and may include at least one of metals such as tungsten, aluminum, and copper. For simplicity, the structure of the first interconnect structure 120 is illustrated in fig. 3A to show the metal layers required for electrical extraction in the first interconnect structure 120, and other portions of the first interconnect structure 120 are not shown.
In some embodiments, the first wafer 100 further includes a carrier wafer 101, the carrier wafer 101 being opposite to and bonded to the front surface of the first substrate 110. The carrier substrate 101 may play a role of a carrier when a semiconductor process is performed on the rear surface of the first substrate 110. The carrier substrate 101 may be a wafer or other type of substrate, and no circuit structures are disposed on the carrier substrate 101 or the disposed circuit structures are not connected to the first wafer 100. The carrier substrate 101 may be bonded to the front surface of the first substrate 110 by adhesive bonding or fusion bonding (fusion bonding). In another embodiment, the first wafer 100 is another wafer in which the circuit structures on the other wafer are interconnected with the first wafer 100, and the position of the carrier substrate 101 in fig. 3A is set. The following description will be given by taking this point as an example of the carrier substrate 101.
Due to the bonding of the carrier substrate 101, the back side of the first wafer 100 (i.e., the back side of the first substrate 110) can be turned upward for back side operation. For example, the first dielectric layer 130 may be formed on the back surface of the first substrate 110 by thinning the back surface of the first substrate 110 and depositing a dielectric material. The first dielectric layer 130 may be a single-layer structure formed by the same deposition process or a stacked structure obtained by multiple deposition processes, and the first dielectric layer 130 may include one or more of Silicon oxide, Silicon nitride, and NDC (Nitrogen doped Silicon Carbide) dielectric materials. In this embodiment, the first dielectric layer 130 includes an oxide layer and an NDC layer covering the oxide layer, and the thickness of each layer is set according to specific conditions.
Referring to fig. 2, 3B and 3C, the first step of the method for manufacturing a three-dimensional integrated device according to the embodiment of the present invention further includes: a first via hole 140 penetrating the first dielectric layer 130 and the first substrate 110 is formed on the back surface of the first substrate 110.
The first via hole 140 may be formed by a TSV (through silicon via) process. In some embodiments, when the first via hole 140 is formed on the back surface of the first substrate 110, a first dummy bond pad 150(dummy pad) is also formed on the back surface of the first substrate 110, which may specifically adopt the following process steps: first, as shown in fig. 3B, performing photolithography and etching processes on the back surface of the first substrate 110, forming at least one groove 100a on the surface of the first dielectric layer 130, and forming at least one opening 100B in the first wafer 100, where the opening 100B penetrates through the first dielectric layer 130 and the first substrate 110 and exposes the first interconnection structure 120; then, as shown in fig. 3C, the recess 100a and the opening 100b are filled with a conductive material, the conductive material in the opening 100b is electrically connected to the first interconnect structure 120 to form a first via hole 140, and the conductive material in the recess 100a forms a first dummy bond pad 150. The first via 140 and the first dummy bond pad 150 are used for subsequent bonding with corresponding bond pads on another wafer. In the embodiment of the present invention, the rewiring layer 15 and the first bonding pad 16 in the device shown in fig. 1 are not manufactured by using a special process before bonding, which saves the process steps and enables the position of the first via hole 140 to be flexibly set.
The recess 100a and the opening 100b may be formed by photolithography and etching processes more than once. In an example, first, a photolithography process is performed on a surface of the first dielectric layer 130, which is far away from the first substrate 110, by using a first photomask to form a mask layer, then, the first dielectric layer 130 is etched by using the mask layer, a plurality of grooves 100a are formed on a back surface of the first dielectric layer 130, then, a photolithography process is performed on a back surface of the first dielectric layer 130 by using a second photomask to form another mask layer, then, the first dielectric layer 130, the first substrate 110 below and the dielectric material burying the first interconnection structure 120 are etched by using the another mask layer, the opening 100b is opened from the back surface of the first dielectric layer 130, and the opening 100b is used for manufacturing a TSV (through silicon via). The recess 100a is used for providing a dummy bond pad that does not need to be connected to an electrical component in the first wafer 100, and thus the recess 100a does not need to be deep, e.g. does not penetrate the first dielectric layer 130, and the depth of the recess 100a is, e.g. in the region of the first dielectric layer 130
Figure BDA0003611207050000081
The shape of the groove 100a is, for example, a square or a circle of 2 μm to 3 μm square. In an embodiment, the positions of the recess 100a and the opening 100b are different from each other, but not limited thereto, in this embodiment, when the plurality of recesses 100a are formed by using the first mask, a part (number) of the recesses 100a is located in a region where the opening 100b is to be formed, so that the first dielectric layer 130 in the opening region can be etched in advance to reduce the thickness of the first dielectric layer 130 in a part of the opening region, and the etching time for forming the opening 100b can be saved.
The conductive material filled in the recess 100a and the opening 100b is, for example, copper or other suitable material. The copper can be deposited by an electroplating process or an electroless plating process, and the specific process of the electroplating process or the electroless plating process can adopt the method disclosed in the field. The conductive material may fill the recess 100a and the opening 100b, and may also extend to cover the back surface of the first dielectric layer 130, so that after the recess 100a and the opening 100b are filled with the conductive material, the back surface of the first dielectric layer 130 may be planarized (e.g., by a Chemical Mechanical Polishing (CMP) process) to improve the flatness of the top surface of the conductive material in the recess 100a and the opening 100b and the back surface of the first dielectric layer 130 outside the recess 100a and the opening 100 b.
Referring to fig. 2 and 3D, the first step of the method for manufacturing a three-dimensional integrated device according to the embodiment of the present invention further includes: providing a second wafer 200, wherein the second wafer 200 comprises a second substrate 210, a second interconnection structure 220 formed on the front surface of the second substrate, and a first bonding pad 230 connected to the second interconnection structure 220; then, the first wafer 100 and the second wafer 200 are bonded to form a first bonding interface a1, where the first via 140 on the first wafer 100 and the first bonding pad 230 on the second wafer 200 are bonded to each other at the first bonding interface a 1.
The second wafer 200 is, for example, a silicon wafer or other semiconductor substrate. The second wafer 200 may perform a plurality of semiconductor processes, so that the second wafer 200 may have electronic components of the same type or different type as those of the first wafer 100, and may be configured according to specific situations. For example, the electronic components and the second interconnect structure 220 are sequentially formed on the second substrate 210, one side where the electronic components and the second interconnect structure 120 are formed is a front surface of the second substrate 210, and the other side opposite to the front surface is a back surface of the second substrate 210. For simplicity, the structure of the second interconnect structure 220 is illustrated in fig. 3D to show the metal layers required for electrical extraction in the second interconnect structure 220, and other parts of the second interconnect structure 220 are not shown.
Referring to fig. 3D, the second interconnect structure 220 has a top metal layer, for example, the second wafer 200 has a second dielectric layer 240 formed on the top metal layer, the second dielectric layer 240 is also formed on the front surface of the second substrate 210, the first bonding pad 230 penetrates through the second dielectric layer 240 and is electrically connected to the top metal layer of the second interconnect structure 220, and the bonding positions of the first bonding pad 230 and the first via hole 140 can be adjusted by using the pattern design of the top metal layer and the first bonding pad 230.
The second wafer 200 may also be formed with a second dummy bonding pad 250, and the second dummy bonding pad 250 may be formed on the surface of the second dielectric layer 240 during the formation of the first bonding pad 230. The second dummy bonding pad 250 is embedded on the surface of the second dielectric layer 240, for example, and the second dummy bonding pad 250 and the first dummy bonding pad 150 formed on the first wafer 100 are configured to enhance bonding connection, reduce surface pit defects caused by a load effect of a Chemical Mechanical Polishing (CMP) process, and ensure reliability of a subsequent process. The second dummy bond pads 250 may not be connected to any circuit structures in the second wafer 200. The upper surfaces of the first and second dummy bond pads 230 and 250 and the upper surface of the second dielectric layer 240 are subjected to CMP processing, for example, to improve planarity. The second wafer 200 includes a first bonding pad 230 and a second dummy bonding pad 250 disposed on a surface of a second dielectric layer 240, and a first bonding interface a1 formed between the first wafer 100 and the second wafer 200, and the first dummy bonding pad 150 and the second dummy bonding pad 250 are bonded together, for example.
The first wafer 100 and the second wafer 200 are bonded, for example, by Hybrid Bonding (HB). Through the first step, a plurality of first via holes 140 and a plurality of first dummy bonding pads 150 to be bonded are formed on the first wafer 100, and a plurality of first bonding pads 230 corresponding to the first via holes 140 and a plurality of second dummy bonding pads 250 corresponding to the first dummy bonding pads 150 are formed on the second wafer 200, wherein the first via holes 140 and the first bonding pads 230 corresponding to each other form a group and are bonded. During bonding, each set of the first via holes 140 and the first bonding pads 230 corresponding to each other are aligned to each other (e.g., aligned) and bonded together (the first bonding pads 230 may be formed to have a size capable of completely covering the corresponding first via holes 140 during bonding to avoid a small contact area caused by misalignment), and each set of the first dummy bonding pads 150 and the second dummy bonding pads 250 are aligned to each other. The invention is not so limited and in other embodiments, at least one first dummy bond pad 150 and at least one second dummy bond pad 250 may be offset from each other but have portions bonded together; alternatively, the at least one first dummy bond pad 150 and each second dummy bond pad 250 are not aligned or partially misaligned and thus are not bonded to the second dummy bond pads 250. In addition, the first dielectric layer 130 on the first wafer 100 and the second dielectric layer 240 on the second wafer 200 may also be bonded together, and when a heterogeneous interface such as the first bonding pad 230 and the first dielectric layer 130, and the second dummy bonding pad 250 and the first dielectric layer 130 is formed due to a size or position deviation, materials on both sides of the heterogeneous interface may also be bonded.
Referring to fig. 2 and 3E, the second step of the method for fabricating a three-dimensional integrated device according to the embodiment of the present invention includes:
first, a third dielectric layer 260 and a second via hole 270 penetrating through the third dielectric layer 260 and the second substrate 210 are formed on the back surface of the second wafer 200, a process similar to the process for forming the first via hole 140 on the back surface of the first wafer 100 can be adopted for forming the second via hole 270 on the back surface of the second wafer 200, the second via hole 270 is electrically connected with the second interconnection structure 220 on the front surface of the second wafer 200, and in addition, a third dummy bonding pad 280 arranged on the surface of the third dielectric layer 260 can be formed on the back surface of the second wafer 200 similarly to the first dummy bonding pad 150 formed on the back surface of the first wafer 100;
then, a third wafer 300 is provided, where the third wafer 300 includes a third substrate 310, a third interconnect structure 320 formed on the front surface of the third substrate 310, and a second bonding pad 330 connected to the third interconnect structure 320, the front surface of the third wafer 300 may further be formed with a fourth dielectric layer 340 and a fourth dummy bonding pad 350, the second bonding pad 330 is electrically connected to the third interconnect structure 320 through the fourth dielectric layer 340, and the fourth dummy bonding pad 350 is embedded on the surface of the fourth dielectric layer 340, for example;
next, the second wafer 200 is bonded to the third wafer 300 to form a second bonding interface a2, and at the second bonding interface a2, the second via 270 on the second wafer 200 is bonded (e.g., aligned) to the second bonding pad 330 on the third wafer 300, and in addition, the third dummy bonding pad 280 on the second wafer 200 and the fourth dummy bonding pad 350 on the third wafer 300 can also be bonded (e.g., aligned), and the third dielectric layer 260 on the back side of the second wafer 200 and the fourth dielectric layer 340 on the third wafer 300 can also be bonded together. In further embodiments, the at least one third dummy bond pad 280 and the at least one fourth dummy bond pad 350 may be offset from each other but have a portion bonded together; alternatively, the at least one third dummy bond pad 280 and each fourth dummy bond pad 350 are neither aligned nor partially misaligned and thus are not bonded to the fourth dummy bond pads 350.
Through the above steps, a wafer level vertical stack structure including the first wafer 100, the second wafer 200, and the third wafer 300 is formed. In some embodiments, by performing the second step in a cyclic manner, at least one wafer, including the first wafer 100, the second wafer 200, and the third wafer 300, may be stacked and bonded on a side of the third wafer 300 away from the second wafer 200, where each of the wafers includes a substrate and an interconnect structure disposed on a front surface of the corresponding substrate, and by performing the second step in a cyclic manner (for example, forming a via hole on a back surface of the corresponding wafer and bonding the via hole to a bonding pad disposed on a front surface of another wafer), a wafer-level longitudinal stacked structure in which more than four wafers are stacked and bonded may be obtained, where the interconnect structure of each wafer forms a longitudinal through connection, for example, in a thickness direction of the wafer. To avoid stress accumulation, the vias formed in different wafers can be staggered, for example, the relative positions of the vias in different wafers can be adjusted to make their orthographic distances on the back surface of the first substrate 110 larger than a predetermined value (for example, by making the lateral distance between the first via 140 and the second via 270 in fig. 3E larger than a predetermined value, the overlap is reduced).
In the embodiment, the first wafer 100 includes a carrier substrate 101 on the front surface of the first substrate 110, and the carrier substrate 101 may be removed after the semiconductor process performed on the back surface of the first wafer 100 is completed. Referring to fig. 3F, in some embodiments, the method for fabricating a three-dimensional integrated device further includes a step of removing the carrier substrate 101 and then a step of forming a lead-out pad 160 on the front surface of the first wafer 100 (i.e., the front surface of the first substrate 110). For example, an insulating layer may be formed on the front surface of the first wafer 100 after the carrier substrate 101 is removed, and then a mask layer is formed on the insulating layer by using a photolithography process and an etching process is performed to form openings penetrating to corresponding extraction positions of the first interconnect structures 120, and then a conductive material (e.g., aluminum) is deposited in the openings to form a conductive layer, and then the conductive layer is etched to form the extraction pads 160 for electrically extracting the first interconnect structures 120 from the front surface of the first substrate 110. The extraction pad 160 may serve as an input and/or output terminal for a wafer level vertical stack structure formed using the above-described method. Through the above steps, the formed wafer-level vertical stack structure may include a plurality of chips. The method for manufacturing the three-dimensional integrated device according to the embodiment of the present invention may further include a step of cutting the wafer-level vertical stack structure formed by the above method to obtain a plurality of chips. The three-dimensional integrated device formed by the method for manufacturing the three-dimensional integrated device in the embodiment of the invention may include a wafer-level longitudinal stacking structure obtained by the method before separation, or may include a chip-level longitudinal stacking structure obtained after further cutting the wafer-level longitudinal stacking structure, and the chip-level longitudinal stacking structure is a three-dimensional integrated chip.
In the manufacturing method of the three-dimensional integrated device according to the embodiment of the present invention, the first via hole 140 formed on the back surface of the first wafer 100 is bonded to the first bonding pad 230 formed on the front surface of the second wafer 200, and the second via hole 270 formed on the back surface of the second wafer 200 is bonded to the second bonding pad 330 formed on the front surface of the third wafer 300, compared with the manufacturing process of the structure shown in fig. 1, the manufacturing method according to the embodiment of the present invention does not use a special mask to respectively manufacture the through holes of the redistribution layer and the bonding pads between the bonding interface and the via hole, and when the three-dimensional integration is realized, the process flow is shortened compared with the prior art, the manufacturing period can be shortened, and the wafer stacking bonding can be performed in a cyclic manner, so that the integration of multiple wafers can be realized by using an automatic process, and the cost can be saved. In addition, the embodiment of the invention utilizes the through holes formed on the back surface of the wafer to carry out bonding, thereby reducing stress accumulation, and the through holes 140 and 270 and the bonding pads correspondingly bonded are more flexible in design.
The three-dimensional integrated device of the embodiment of the present invention further includes a three-dimensional integrated device, and referring to fig. 3F, the three-dimensional integrated device of the embodiment of the present invention includes a first bonding layer (which may be formed by a first wafer 100), a second bonding layer (which may be formed by a second wafer 200), and a third bonding layer (which may be formed by a third wafer 300) that are sequentially stacked in a thickness direction, where the first bonding layer, the second bonding layer, and the third bonding layer each include a substrate and an interconnection structure disposed on a front surface of the substrate, a first bonding interface a1 is formed between the first bonding layer and the second bonding layer, and a second bonding interface a2 is formed between the second bonding layer and the third bonding layer; wherein, at the first bonding interface a1, the first via hole 140 disposed on the first bonding layer and penetrating through the corresponding substrate from the back surface is bonded to the first bonding pad 230 disposed on the second bonding layer and located on the front surface of the corresponding substrate, and at the second bonding interface a2, the second via hole 270 disposed on the second bonding layer and penetrating through the corresponding substrate from the back surface is bonded to the second bonding pad 330 disposed on the third bonding layer and located on the front surface of the corresponding substrate.
The three-dimensional integrated device according to the embodiment of the present invention can be obtained by using the manufacturing method shown in fig. 3A to 3F described in the embodiment of the present invention. The first bonding layer, the second bonding layer and the third bonding layer in the three-dimensional integrated device may be wafer-scale or chip-scale, and thus the three-dimensional integrated device may include a wafer-level or chip-level vertical stack structure, and the three-dimensional integrated device may be a wafer-level vertical stack structure obtained by the above method, or may include at least one three-dimensional integrated chip obtained by the above method.
In the three-dimensional integrated device of some embodiments, the first bonding layer may include a first substrate 110, a first interconnection structure 120 disposed on a front surface of the first substrate 110, and a first dielectric layer 130 disposed on a back surface of the first substrate 110, and the first via hole 140 penetrates through the first dielectric layer 130 and the first substrate 110 and is electrically connected to the first interconnection structure 120; the second bonding layer includes a second substrate 210, a second interconnect structure 220 disposed on the front surface of the second substrate 210, a second dielectric layer 240, and the first bonding pad 230 penetrates through the second dielectric layer 240 and is electrically connected to the second interconnect structure 220. Optionally, the second interconnect structure 220 in the second bonding layer may include a top metal layer disposed toward the first bonding interface a1, the second dielectric layer 240 is located between the top metal layer and the first bonding interface a1, and the first bonding pad 230 penetrates through the second dielectric layer 240 and is electrically connected to the top metal layer.
In some embodiments of the three-dimensional integrated device, the surface of the first dielectric layer 130 facing the first bonding interface a1 may be provided with a first dummy bond pad 150, and the surface of the second dielectric layer 240 facing the first bonding interface a1 may be provided with a second dummy bond pad 250. In the first bonding interface a1, not only the first via hole 140 and the first bonding pad 230, but also the first dummy bonding pad 150 and the second dummy bonding pad 250 may be bonded. In addition, the first dielectric layer 130 in the first bonding layer and the second dielectric layer 240 in the second bonding layer may also be bonded to each other.
In the three-dimensional integrated device of some embodiments, the second bonding layer may include a third dielectric layer 260 disposed on the back surface of the second substrate 210, and the second via hole 270 penetrates through the third dielectric layer 260 and the second substrate 210 and is electrically connected to the second interconnect structure 220. The third bonding layer includes a third substrate 310, a third interconnect structure 320 disposed on the front surface of the third substrate 310, a fourth dielectric layer 340, and the second bonding pad 330 penetrates through the fourth dielectric layer 340 and is electrically connected to the third interconnect structure 320. In addition, a surface of the third dielectric layer 260 facing the second bonding interface a2 may be provided with a third dummy bonding pad 280, a surface of the fourth dielectric layer 340 facing the second bonding interface a2 is provided with a fourth dummy bonding pad 350, and at the second bonding interface a2, not only the second via hole 270 and the second bonding pad 330 are bonded, but also the third dummy bonding pad 280 and the fourth dummy bonding pad 350 may be bonded. In addition, the third dielectric layer 260 in the second bonding layer and the fourth dielectric layer 340 in the third bonding layer may also be bonded to each other.
In some embodiments, the three-dimensional integrated device may further include a fourth bonding layer, a fifth bonding layer, an as bonding layer, and an mth bonding layer, which are sequentially stacked on a side of the third bonding layer away from the second bonding layer, where M is an integer greater than or equal to 4, and the specific number of layers is set according to actual circumstances. In all bonding layers of the three-dimensional integrated device comprising the first bonding layer, the second bonding layer and the third bonding layer, each bonding layer comprises a substrate and an interconnection structure arranged on the front surface of the corresponding substrate, and an (N-1) th bonding interface is formed between the (N-1) th bonding layer and the Nth bonding layer; and in the (N-1) th bonding interface, an (N-1) th via hole which is arranged on the (N-1) th bonding layer and penetrates through the corresponding substrate (namely the (N-1) th substrate) from the back side is bonded with an (N-1) th bonding pad which is arranged on the Nth bonding layer and is positioned on the front side of the corresponding substrate (namely the Nth substrate), wherein N is more than or equal to 2 and less than or equal to M. In addition, bonding between virtual bonding pads and bonding between dielectric layers can be formed on a bonding interface between two adjacent bonding layers, and the interconnection structure on the front surface of each substrate in the three-dimensional integrated device can be longitudinally communicated, so that the three-dimensional integrated device is simple in structure and good in reliability.
Referring to fig. 3F, the three-dimensional integrated device of some embodiments may further include a draw pad 160, the draw pad 160 being disposed on a side of the first bonding layer away from the first bonding interface a1, the draw pad 160 being electrically connectable with the first interconnect structure 120 in the first bonding layer.
Compared with the bonding structure shown in fig. 1, the three-dimensional integrated device provided by the embodiment of the invention has the advantages that the structure is simpler while the three-dimensional integration is realized, the multilayer stacking bonding is convenient to realize, the process is saved, the manufacturing period is shortened, the implementation by adopting an automatic process is convenient, and the cost can be saved. In addition, the embodiment of the invention directly utilizes the through hole formed on the back surface of the substrate to carry out bonding, thereby reducing stress accumulation and enabling the design of the through hole and the bonding pad bonded with the through hole to be more flexible.
It should be noted that the embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts in various embodiments are referred to each other. For the structure disclosed in the embodiment, the description is relatively simple because the structure corresponds to the method disclosed in the embodiment, and the relevant points can be referred to the description of the method part.
The above description is only for the purpose of describing preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art may make possible variations and modifications of the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modifications, equivalent changes and modifications of the above embodiments according to the technical essence of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims (14)

1. A three-dimensional integrated device, comprising a first bonding layer, a second bonding layer and a third bonding layer sequentially stacked along a thickness direction, wherein the first bonding layer, the second bonding layer and the third bonding layer each comprise a substrate and an interconnection structure disposed on a front surface of the corresponding substrate, a first bonding interface is formed between the first bonding layer and the second bonding layer, and a second bonding interface is formed between the second bonding layer and the third bonding layer, wherein:
at the first bonding interface, a first via hole which is arranged on the first bonding layer and penetrates through the corresponding substrate from the back side is bonded with a first bonding pad which is arranged on the second bonding layer and is positioned on the front side of the corresponding substrate;
and at the second bonding interface, a second via hole which is arranged on the second bonding layer and penetrates through the corresponding substrate from the back side is bonded with a second bonding pad which is arranged on the third bonding layer and is positioned on the front side of the corresponding substrate.
2. The three-dimensional integrated device according to claim 1, further comprising a fourth bonding layer, a fifth bonding layer, an mth bonding layer and a plurality of bonding layers sequentially stacked on a side of the third bonding layer away from the second bonding layer, wherein each bonding layer comprises a substrate and an interconnection structure disposed on a front side of the corresponding substrate, and an (N-1) th bonding interface is formed between the (N-1) th bonding layer and the nth bonding layer; and in the (N-1) th bonding interface, an (N-1) th via hole which is arranged in the (N-1) th bonding layer and penetrates through the corresponding substrate from the back side is bonded with an (N-1) th bonding pad which is arranged in the Nth bonding layer and is positioned on the front side of the corresponding substrate, M is an integer greater than or equal to 4, and 2 < N < M.
3. The three-dimensional integrated device of claim 1, wherein the first bonding layer comprises a first substrate, a first interconnect structure disposed on a front side of the first substrate, and a first dielectric layer disposed on a back side of the first substrate, wherein the first via hole penetrates through the first dielectric layer and the first substrate and is electrically connected to the first interconnect structure; the second bonding layer comprises a second substrate, a second interconnection structure arranged on the front surface of the second substrate, a second dielectric layer and the first bonding pad, and the first bonding pad penetrates through the second dielectric layer and is electrically connected with the second interconnection structure.
4. The three-dimensional integrated device of claim 3, wherein a surface of the first dielectric layer facing the first bonding interface is provided with a first dummy bond pad, wherein a surface of the second dielectric layer facing the first bonding interface is provided with a second dummy bond pad, and wherein the first dummy bond pad is bonded to the second dummy bond pad.
5. The three-dimensional integrated device of claim 3, wherein the second interconnect structure includes a top metal layer disposed toward the first bonding interface, the second dielectric layer is between the top metal layer and the first bonding interface, and the first bonding pad passes through the second dielectric layer and is electrically connected to the top metal layer.
6. The three-dimensional integrated device of claim 3, wherein the second bonding layer comprises a third dielectric layer disposed on a back side of the second substrate, the second via hole penetrating the third dielectric layer and the second substrate and electrically connecting to the second interconnect structure; the third bonding layer comprises a third substrate, a third interconnection structure arranged on the front surface of the third substrate, a fourth dielectric layer and the second bonding pad, and the second bonding pad penetrates through the fourth dielectric layer and is electrically connected with the third interconnection structure.
7. The three-dimensional integrated device of claim 3, further comprising a landing pad disposed on a side of the first bonding layer away from the first bonding interface and electrically connected to the first interconnect structure.
8. The three-dimensional integrated device according to any of claims 1 to 7, wherein the three-dimensional integrated device comprises a wafer-level or chip-level vertical stack structure.
9. A manufacturing method of a three-dimensional integrated device comprises a first step and a second step which are executed in sequence;
the first step comprises: providing a first wafer, wherein the first wafer comprises a first substrate, a first interconnection structure formed on the front surface of the first substrate and a first dielectric layer formed on the back surface of the first substrate; forming a first via hole penetrating through the first dielectric layer and the first substrate on the back surface of the first substrate; providing a second wafer, wherein the second wafer comprises a second substrate, a second interconnection structure formed on the front surface of the second substrate and a first bonding pad connected with the second interconnection structure; bonding the first wafer and the second wafer to form a first bonding interface, wherein the first via hole is bonded with the first bonding pad at the first bonding interface;
the second step includes: forming a third dielectric layer and a second via hole penetrating through the third dielectric layer and the second substrate on the back surface of the second wafer; providing a third wafer, wherein the third wafer comprises a third substrate, a third interconnection structure formed on the front surface of the third substrate and a second bonding pad connected with the third interconnection structure; and bonding the second wafer and a third wafer to form a second bonding interface, wherein the second through hole is bonded with the second bonding pad at the second bonding interface.
10. The method of manufacturing of claim 9, further comprising:
and circularly executing the second step, and bonding at least one wafer on the side of the third wafer far away from the second wafer in a stacking mode, wherein each wafer comprises a substrate and an interconnection structure arranged on the front surface of the corresponding substrate.
11. The method of claim 9, wherein in the first step, when the first via hole is formed on the back surface of the first substrate, a first dummy bonding pad is further formed on the back surface of the first dielectric layer; when the first bonding pad is formed on the front surface of the second wafer, a second virtual bonding pad is further formed on the surface of the second dielectric layer; and at the first bonding interface, the second virtual bonding pad is bonded with the second virtual bonding pad.
12. The method of claim 11, wherein the step of forming the first via and the first dummy bond pad on the first wafer backside in the first step comprises:
carrying out photoetching and etching processes on the back surface of the first substrate, forming at least one groove on the surface of the first dielectric layer, and forming at least one opening in the first wafer, wherein the opening penetrates through the first dielectric layer and the first substrate and exposes the first interconnection structure; and the number of the first and second groups,
and filling a conductive material in the opening and the groove, wherein the conductive material in the opening is electrically connected with the first interconnection structure to form the first via hole, and the conductive material in the groove forms the first dummy bonding pad.
13. The method of claim 9, wherein the first wafer has the front surface of the first substrate bonded to a carrier substrate, and wherein after bonding the second wafer to the third wafer, the method further comprises:
removing the bearing substrate; and (c) a second step of,
and forming a lead-out pad on the front surface of the first substrate, wherein the lead-out pad is electrically connected with the first interconnection structure.
14. The method of manufacturing of claim 13, further comprising, after forming the extraction pad:
and cutting the wafer-level longitudinal stacking structure comprising the first wafer, the second wafer and the third wafer to obtain a plurality of chips.
CN202210432164.6A 2022-04-22 2022-04-22 Three-dimensional integrated device and manufacturing method thereof Pending CN114783984A (en)

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