CN115295399A - Structure with back sealing layer, preparation method thereof and preparation method of semiconductor structure - Google Patents

Structure with back sealing layer, preparation method thereof and preparation method of semiconductor structure Download PDF

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CN115295399A
CN115295399A CN202210988631.3A CN202210988631A CN115295399A CN 115295399 A CN115295399 A CN 115295399A CN 202210988631 A CN202210988631 A CN 202210988631A CN 115295399 A CN115295399 A CN 115295399A
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layer
wafer
etching
silicon nitride
oxide layer
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张延鲁
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GTA Semiconductor Co Ltd
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GTA Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

The invention provides a structure with a back sealing layer and a preparation method thereof, wherein the method comprises the following steps: providing a wafer, wherein the wafer comprises a doped layer; forming oxide layers for coating the front surface, the back surface and the side surfaces of the wafer; sequentially forming a silicon nitride layer and a polysilicon layer on the surface of the oxide layer; then removing the polysilicon layer, the silicon nitride layer and the oxide layer on the front surface of the wafer in sequence; the structure with the back sealing layer can reduce the generation of granular byproducts and the occurrence of self-doping reaction in subsequent processes, and reduce the phenomena of abnormal adsorption of a wafer on the surface of an electronic chuck and device damage caused by microcosmic charging and discharging in the process of the wafer process. The invention also provides a preparation method of the semiconductor structure, wherein an epitaxial film layer grows on the front side of the structure with the back seal layer, grows along the surface of the polycrystalline silicon layer and covers the etching interfaces of the polycrystalline silicon layer, the silicon nitride layer and the silicon oxide layer, and the generation of self-doping or granular byproducts can be further reduced.

Description

Structure with back sealing layer, preparation method thereof and preparation method of semiconductor structure
Technical Field
The invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a structure with a back sealing layer, a preparation method of the structure and a preparation method of a semiconductor structure.
Background
In order to improve or change the electrical characteristics and other performance of the semiconductor device, it is generally necessary to dope various impurity elements with different concentrations to the semiconductor substrate to meet the application of the semiconductor device in different fields, which are classified into light doping, medium doping and heavy doping according to the doping concentration.
At present, a doped substrate is generally adopted for a silicon wafer for epitaxial deposition of a power device, and in order to prevent diffusion escape of doped elements in the substrate and a self-doping phenomenon generated under a high-temperature condition in a subsequent epitaxial process, a back-sealing structure needs to be formed on the back of the wafer, and then subsequent processes such as epitaxial layer growth and the like are performed.
Silicon dioxide is generally selected as a back sealing material in silicon wafer production factories, and a silicon dioxide film is grown on the back of a silicon substrate by adopting a plasma enhanced chemical vapor deposition technology to serve as a back sealing structure. However, before entering a subsequent process machine, the silicon substrate with the silicon dioxide film back sealing structure needs to be polished and cleaned, and at this time, the oxide film can cause damage and even completely remove, so that the doped substrate is exposed again, and ions doped in the substrate are separated out to cause pollution.
Therefore, it is an important technical problem to be solved by those skilled in the art how to provide a structure with a back sealing layer, a method for fabricating the same, and a method for fabricating a semiconductor structure, so as to avoid or reduce the generation of granular byproducts and the occurrence of self-doping reactions in the subsequent processes, thereby reducing the machine maintenance frequency and the wafer yield.
It should be noted that the above background description is only for the convenience of clear and complete description of the technical solutions of the present application and for the understanding of those skilled in the art. These solutions are not considered to be known to the person skilled in the art merely because they are set forth in the background section of the present application.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a structure with a back sealing layer, a method for manufacturing the same, and a method for manufacturing a semiconductor structure, which are used to solve the problem in the prior art that the yield of wafer production is affected due to the self-doping phenomenon caused by diffusion and escape of doping elements or the generation of granular byproducts in the back sealing layer in the subsequent process.
To achieve the above and other related objects, the present invention provides a method for manufacturing a structure having a back seal layer, comprising the steps of:
providing a wafer, wherein the wafer comprises a doped layer;
forming an oxide layer, wherein the oxide layer coats the front surface, the back surface and the side surface of the wafer;
forming a silicon nitride layer on the surface of the oxide layer;
forming a polycrystalline silicon layer on the surface of the silicon nitride layer;
removing the polysilicon layer on the front side of the wafer;
removing the silicon nitride layer on the front surface of the wafer;
and removing the oxide layer on the front surface of the wafer.
Optionally, the method of forming the oxide layer includes at least one of a dry oxygen method, a wet oxygen method, an ethyl orthosilicate decomposition method, and a silane decomposition method.
Alternatively, the oxidation temperature range of the method of forming the oxide layer is 500 ℃ to 1300 ℃, and the oxidation time range of the method of forming the oxide layer is 0.5 hours to 6 hours.
Optionally, the method for removing the polysilicon layer on the front side of the wafer includes at least one of dry etching and wet etching; the method for removing the silicon nitride layer on the front surface of the wafer comprises at least one of dry etching and wet etching; the method for removing the oxide layer on the front surface of the wafer comprises at least one of dry etching and wet etching.
Optionally, the wet etching for removing the polysilicon layer is single-sided etching, and the adopted etching solution comprises phosphoric acid; the dry etching for removing the polysilicon layer comprises at least one of ion etching and chemical reaction etching; the wet etching for removing the silicon nitride layer is single-sided etching, and the adopted etching liquid comprises phosphoric acid; the dry etching for removing the silicon nitride layer comprises at least one of ion etching and chemical reaction etching; the wet etching for removing the oxide layer is single-sided etching, and the adopted etching liquid comprises phosphoric acid; the dry etching for removing the oxide layer comprises at least one of ion etching and chemical reaction etching.
The invention also provides a structure with the back sealing layer, which comprises a wafer, wherein the wafer comprises a doping layer, and the side surface and the back surface of the wafer are sequentially coated with an oxide layer, a silicon nitride layer and a polycrystalline silicon layer from inside to outside.
Optionally, the doped layer is P-type or N-type, and a resistivity of the doped layer ranges from 0.01 milli-ohms per centimeter to 100 milli-ohms per centimeter.
Optionally, the wafer further includes a P-type or N-type preset epitaxial layer, and the preset epitaxial layer is located on the front side of the doped layer.
Optionally, the thickness of the oxide layer ranges from 50 angstroms to 32000 angstroms, the thickness of the silicon nitride layer ranges from 5 angstroms to 5000 angstroms, and the thickness of the polysilicon layer ranges from 1000 angstroms to 20000 angstroms.
The invention also provides a preparation method of the semiconductor structure, which provides the structure with the back seal layer, and an epitaxial film layer is grown on the front surface of the structure with the back seal layer, grows along the surface of the polycrystalline silicon layer and covers the etching interfaces of the polycrystalline silicon layer, the silicon nitride layer and the silicon oxide layer.
As described above, the structure having a back-sealing layer and the method for fabricating the same according to the present invention are achieved by sequentially forming an oxide layer and silicon nitride (Si) on a wafer including a doped layer 3 N 4 ) The back sealing layer adopting the oxide layer-silicon nitride layer-polycrystalline silicon layer laminated structure can reduce the generation of granular byproducts and the risk of self-doping reaction in the subsequent process, and reduce the phenomena of abnormal adsorption of a wafer on the surface of an electronic chuck and damage of a device caused by microcosmic charging and discharging in the process of the wafer. The preparation method of the semiconductor structure forms the epitaxial film layer based on the structure with the back seal layer, the epitaxial film layer can grow along the surface of the polycrystalline silicon layer and cover the etching interface of the polycrystalline silicon layer, the silicon nitride layer and the silicon oxide layer, and the phenomenon that the doping elements in the wafer diffuse and overflow from the etching interface can be effectively controlled, so that the semiconductor structure is prepared by the methodFurther reducing the generation of self-doping or granular by-products, reducing the maintenance frequency of the machine and increasing the production yield.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a structure with a back sealing layer according to the present invention.
Fig. 2 to 8 are schematic structural diagrams of steps in a first embodiment of a method for manufacturing a structure with a back sealing layer according to the present invention, wherein fig. 8 is a schematic cross-sectional structural diagram of a second embodiment of the structure with a back sealing layer according to the present invention.
Fig. 9 is a schematic top view of a structure with a back sealing layer according to a second embodiment of the invention.
Fig. 10 is a schematic cross-sectional view of a structure with a back sealing layer according to a third embodiment of the invention.
Fig. 11 is a schematic top view of a structure with a back sealing layer according to a third embodiment of the invention.
Fig. 12 is a schematic cross-sectional view illustrating a semiconductor structure according to a fourth embodiment of the invention.
Description of the element reference
1. Wafer
2. Oxide layer
3. Silicon nitride layer
4. Polycrystalline silicon layer
5. Doped layer
6. Preset epitaxial layer
7. Epitaxial film layer
S1 to S7
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 12. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The inventor finds in the working practice that the wafer can be ensured to have a back sealing structure and not to influence the normal growth epitaxial layer on the front surface of the wafer by forming a silicon dioxide layer on the whole surface of the wafer and then depositing a silicon nitride layer and then removing the two-layer structure on the front surface of the wafer by adopting a dry etching process. However, in the dry etching process, the phenomenon that the electric charge on the silicon nitride film layer cannot be released or led out in time, so that the electronic chuck fails to release the wafer, and further mechanical collision occurs to cause wafer fragments, thereby causing wafer scrap is easily caused. Secondly, in the actual production process, the inventor also finds that after the silicon dioxide layer and the silicon nitride layer on the front surface of the doped substrate are removed by the dry etching process, rough interfaces of all film layers can appear at the edge of the wafer, and special gas of the front surface process enters the back surface from an oblique angle interface and reacts easily during the epitaxial process to generate granular byproducts, and the byproducts can contaminate and scatter at various positions such as a machine equipment base, a mechanical arm and the like, so that various defects are formed on the front surface of the wafer, the subsequent device process of the epitaxial layer is seriously influenced, and meanwhile, the doping elements in the substrate can diffuse to generate a self-diffusion phenomenon during the epitaxial process. In addition, in some back sealing layer forming processes, charge transfer from the back sealing film layer to the substrate film layer can also occur to cause a micro-phenomenon of charge and discharge, and further, the functional structure of the device is influenced and even damaged. The invention improves the problems by an improved preparation method of the back sealing layer, and the specific scheme is as follows.
Example one
The present embodiment provides a method for manufacturing a structure having a back sealing layer, referring to fig. 1, which is a schematic flow chart of the method in the present embodiment, and includes the following steps:
s1: providing a wafer, wherein the wafer comprises a doped layer;
s2: forming an oxide layer, wherein the oxide layer coats the front surface, the back surface and the side surface of the wafer;
s3: forming a silicon nitride layer on the surface of the oxide layer;
s4: forming a polysilicon layer on the surface of the silicon nitride layer;
s5: removing the polysilicon layer on the front side of the wafer;
s6: removing the silicon nitride layer on the front surface of the wafer;
s7: and removing the oxide layer on the front surface of the wafer.
First, referring to fig. 2, the step S1 is performed to provide a wafer 1, where the wafer 1 includes a doped layer 5.
Specifically, the wafer 1 includes a front surface, a back surface and a side surface, and the front surface of the wafer 1 is a surface used for manufacturing a device in a subsequent production process.
Specifically, the material of the wafer 1 may be silicon, germanium, or other semiconductor materials such as trivalent elements.
Specifically, the wafer 1 may be the entire doped layer 5, and may further include an epitaxial film layer, where the doping element of the doped layer 5 includes, but is not limited to, elements commonly used in the current semiconductor industry, such As phosphorus (P), boron (B), arsenic (As), and antimony (Sb), and the doping concentration of the doped layer 5 includes light-concentration doping, medium-concentration doping, and heavy-concentration doping. In this embodiment, the doping concentration of the doping layer 5 is high-concentration doping, and in this case, the resistivity of the doping layer 5 ranges from 0.01 milli-ohm per centimeter to 100 ohm per centimeter.
Referring to fig. 3, the step S2 is performed to form an oxide layer 2, and the oxide layer 2 covers the front surface, the back surface and the side surface of the wafer 1.
As an example of this, the following is given, the method of forming the oxide layer 2 includes a dry oxygen method a wet oxygen method,Decomposition method of Tetraethoxysilane (TEOS), silane (SiH) 4 ) At least one of decomposition methods. The gas source for forming the oxide layer 2 comprises at least one of oxygen, water vapor, tetraethoxysilane and silane or other special oxygen-containing and silicon-oxygen-containing gas. In this embodiment, the oxide layer 2 is formed in the furnace tube or the thin film cavity under normal pressure or low pressure.
As an example, the oxidation temperature range of forming the oxide layer 2 is 500 to 1300 ℃, and the oxidation time range of the method of forming the oxide layer 2 is 0.5 to 6 hours.
Referring to fig. 4, the step S3 is performed to form a silicon nitride layer 3 on the surface of the oxide layer 2.
By way of example, the silicon nitride layer 3 is formed by a Low Pressure Chemical Vapor Deposition (LPCVD) method or other suitable method, wherein a gas source of the LPCVD method includes tetraethoxysilane, silane, and ammonia (NH) 3 ) Hydrogen (H) 2 ) And oxygen (O) 2 ) Or other nitrogen (N) -containing compound.
Referring to fig. 5, step S4 is performed to form a polysilicon layer 4 on the surface of the silicon nitride layer 3.
As an example, the thickness of the polysilicon layer 4 ranges from 1000 angstroms to 20000 angstroms, the polysilicon layer 4 may be formed by a low pressure chemical vapor deposition method or other suitable methods, and the gas source may be silane or other suitable gases.
Referring to fig. 6 again, the step S5 is performed to remove the polysilicon layer 4 on the front side of the wafer 1.
As an example, the method for removing the polysilicon layer 4 on the front surface of the wafer 1 includes at least one of dry etching and wet etching. The wet etching is single-sided etching, and etching liquid adopted by the single-sided etching comprises phosphoric acid or a mixture containing phosphoric acid; the dry etching includes at least one of ion etching and chemical reaction etching.
Referring to fig. 7, the step S6 is performed to remove the silicon nitride layer 3 on the front surface of the wafer 1.
As an example, the method for removing the silicon nitride layer 3 on the front surface of the wafer 1 includes at least one of dry etching and wet etching. The wet etching is single-sided etching, and etching liquid adopted by the single-sided etching comprises phosphoric acid or a mixture containing phosphoric acid; the dry etching includes at least one of ion etching and chemical reaction etching.
Referring to fig. 8, the step S7 is performed to remove the oxide layer 2 on the front surface of the wafer 1.
As an example, the method for removing the oxide layer 2 on the front surface of the wafer 1 includes at least one of dry etching and wet etching. The wet etching is single-sided etching, and etching liquid adopted by the single-sided etching comprises phosphoric acid or a mixture containing phosphoric acid; the dry etching includes at least one of ion etching and chemical reaction etching.
According to the preparation method of the structure with the back sealing layer, the oxide layer 2, the silicon nitride layer 3 and the polycrystalline silicon layer 4 are sequentially formed on the wafer 1, and then the polycrystalline silicon layer 4, the silicon nitride layer 3 and the oxide layer 2 on the front side of the wafer 1 are sequentially etched, so that the structure with the back sealing layer is formed, the preparation process is simple, the operability is high, and large-scale production can be realized.
Example two
Referring to fig. 8 and 9, fig. 8 is a schematic cross-sectional view illustrating a structure with a back sealing layer according to an embodiment of the present invention, and fig. 9 is a top view illustrating the structure with the back sealing layer, where the structure with the back sealing layer includes a wafer 1, the wafer 1 includes a doped layer 5, and a side surface and a back surface of the wafer 1 are sequentially coated with an oxide layer 2, a silicon nitride layer 3, and a polysilicon layer 4 from inside to outside.
In this embodiment, the entire wafer 1 is the doped layer 5, and compared with the front surface and the back surface of the doped layer 5, the front surface is smoother and smoother, and in this embodiment, the front surface of the doped layer 5 is the front surface of the wafer 1.
As an example, the doped layer 5 is P-type or N-type, the doping concentration of the doped layer 5 includes light concentration doping, medium concentration doping and heavy concentration doping, and the doping element of the doped layer 5 includes, but is not limited to, elements commonly used in the current semiconductor industry, such As phosphorus element (P), boron element (B), arsenic element (As), antimony element (Sb), and the like. In this embodiment, the doping concentration of the doped layer 5 is high-concentration doping, and in this case, the resistivity of the doped layer 5 may be, but is not limited to, 0.01 milli-ohm per centimeter to 100 ohm per centimeter.
As an example, the thickness of the oxide layer 2 ranges from 50 angstroms to 32000 angstroms, the thickness of the silicon nitride layer 3 ranges from 5 angstroms to 5000 angstroms, and the thickness of the polysilicon layer 4 ranges from 1000 angstroms to 20000 angstroms, which can be set reasonably according to practical application scenarios during production.
The structure with the back sealing layer can reduce the generation of granular byproducts and the occurrence of self-doping reaction in the subsequent process, and can reduce the phenomena of abnormal adsorption of the wafer on the surface of the electronic chuck and device damage caused by microscopic charging and discharging in the wafer process.
EXAMPLE III
The present embodiment provides a structure having a back-sealing layer, which is different from the second embodiment in that the entire wafer 1 in the second embodiment is the doped layer 5, and the wafer 1 in the present embodiment includes the doped layer 5 and the pre-epitaxial layer 6.
Referring to fig. 10 and 11, in which fig. 10 is a schematic cross-sectional structure diagram of the structure with the back sealing layer of the present embodiment, fig. 11 is a top view of the structure with the back sealing layer, the structure with the back sealing layer includes a wafer 1, the wafer 1 includes a doping layer 5 and a preset epitaxial layer 6, the preset epitaxial layer 6 is located on a front surface of the doping layer 5, and a side surface and a back surface of the wafer 1 are sequentially coated with an oxide layer 2, a silicon nitride layer 3 and a polysilicon layer 4 from inside to outside.
In this embodiment, the wafer 1 includes the doping layer 5 and the preset epitaxial layer 6, and the preset epitaxial layer 6 is located on the front surface of the doping layer 5, so that one surface of the preset epitaxial layer 6 away from the doping layer 5 in this embodiment is the front surface of the wafer 1.
As an example, the doped layer 5 is P-type or N-type, the doping concentration of the doped layer 5 includes light concentration doping, medium concentration doping and heavy concentration doping, the doping element of the doped layer 5 includes, but is not limited to, elements commonly used in the current semiconductor industry, such As phosphorus element (P), boron element (B), arsenic element (As), antimony element (Sb), and the like, in this embodiment, the doping concentration of the doped layer 5 is high concentration doping, and in this case, the resistivity of the doped layer 5 may be, but is not limited to, in a range of 0.01 milli-100 ohms per centimeter.
As an example, the pre-epitaxial layer 6 is P-type or N-type, and the doping concentration range of the pre-epitaxial layer 6 may be determined according to practical situations.
As an example, the thickness of the oxide layer 2 ranges from 50 angstroms to 32000 angstroms, the thickness of the silicon nitride layer 3 ranges from 5 angstroms to 5000 angstroms, and the thickness of the polysilicon layer 4 ranges from 1000 angstroms to 20000 angstroms, which can be set reasonably according to practical application scenarios during production.
The structure with the back sealing layer reduces the generation of granular byproducts in subsequent process workers, reduces the maintenance frequency of a machine table, reduces the risk of self-doping reaction, reduces the adsorption abnormality of a wafer on an electronic chuck, and can effectively reduce the damage phenomenon of devices caused by microcosmic charging and discharging in the process of the wafer process.
Example four
In this embodiment, a method for manufacturing a semiconductor structure is provided, where a structure having a back seal layer is provided as in the second embodiment or the third embodiment, an epitaxial film layer 6 is grown on the front surface of the structure having the back seal layer, and the epitaxial film layer 6 is further grown along the surface of the polysilicon layer 4 and covers the etching interfaces of the polysilicon layer 4, the silicon nitride layer 3 and the silicon oxide layer 2, as shown in fig. 12, which is a schematic cross-sectional structure diagram of the semiconductor structure of this embodiment.
The preparation method of the semiconductor structure of the embodiment is based on the front growth of the epitaxial film layer 6 with the back sealing layer structure, the epitaxial film layer 6 also grows along the surface of the polycrystalline silicon layer 4 and covers the etching interfaces of the polycrystalline silicon layer 4, the silicon nitride layer 3 and the silicon oxide layer 2, and the phenomenon that the doping elements in the wafer 1 diffuse and overflow from the etching interfaces can be effectively controlled, so that the generation of self-doping or granular byproducts is further reduced, the maintenance frequency of a machine is reduced, and the production yield is improved.
In the invention, on one hand, because the outermost layer of the back sealing structure of the wafer is the polycrystalline silicon layer, even if a small amount of charged particles enter the silicon nitride layer due to good conductivity of the polycrystalline silicon, the part of charges can be released out along with micro current generated by the polycrystalline silicon layer in the process of removing the voltage of the electronic card disk in the subsequent etching process, and the phenomenon of wafer fragments on the electronic card disk due to the fact that the charges are not released out can not be caused. On the other hand, because the back sealing film layer of the wafer is of a multilayer structure comprising a silicon oxide layer, a silicon nitride layer, a polysilicon layer and the like which are sequentially laminated on the wafer bottom, even if the outermost polysilicon layer occasionally has an inward charge transfer phenomenon, charges cannot reach the wafer through the middle dense insulating silicon nitride layer and the innermost oxide layer to form a charging and discharging microscopic phenomenon, and the functional structure of a device cannot be influenced or damaged. In addition, when the polysilicon layer, the silicon nitride layer and the oxide layer on the front surface of the wafer are sequentially removed, the relative integrity of the polysilicon layer remained at each rough interface of the film layers at the edge of the wafer can be controlled through process parameters, in the subsequent epitaxial process, because the atomic compositions of the epitaxial film layer and the wafer are almost the same and are all silicon compositions, and the remained polysilicon is also silicon compositions, the epitaxial film layer can grow along the remained polysilicon layer under the action of interatomic bonds, so that each rough interface of the film layers at the edge of the wafer can be covered, and doping elements in the wafer can not diffuse and escape from the rough interfaces of the film layers to generate self-doping reaction or react at other places of the wafer to generate granular byproducts to cause the pollution of the wafer and the machine and the surface defect of the wafer, thereby reducing the maintenance frequency of the machine and improving the production yield.
In summary, according to the structure with the back sealing layer and the preparation method thereof of the present invention, the oxide layer, the silicon nitride layer and the polysilicon layer are sequentially formed on the wafer including the doped layer, and then the polysilicon layer, the silicon nitride layer and the oxide layer on the front surface of the substrate are sequentially removed, so as to form the structure with the back sealing layer. The preparation method of the semiconductor structure of the invention forms the epitaxial film layer based on the structure with the back sealing layer, the epitaxial film layer can grow along the surface of the polycrystalline silicon layer and cover the etching interface of the polycrystalline silicon layer, the silicon nitride layer and the silicon oxide layer, and can effectively control the phenomenon that the doping elements in the wafer diffuse and overflow from the etching interface, thereby further reducing the generation of self-doping or granular by-products, reducing the maintenance frequency of a machine and improving the production yield. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. A preparation method of a structure with a back sealing layer is characterized by comprising the following steps:
providing a wafer, wherein the wafer comprises a doped layer;
forming an oxide layer, wherein the oxide layer coats the front surface, the back surface and the side surface of the wafer;
forming a silicon nitride layer on the surface of the oxide layer;
forming a polycrystalline silicon layer on the surface of the silicon nitride layer;
removing the polysilicon layer on the front side of the wafer;
removing the silicon nitride layer on the front surface of the wafer;
and removing the oxide layer on the front surface of the wafer.
2. The method of manufacturing a structure having a back seal layer as claimed in claim 1, wherein: the method for forming the oxide layer includes at least one of a dry oxygen method, a wet oxygen method, an ethyl orthosilicate decomposition method, and a silane decomposition method.
3. The method of manufacturing a structure having a back seal according to claim 2, wherein: the oxidation temperature range of the method of forming the oxide layer is 500 to 1300 ℃, and the oxidation time range of the method of forming the oxide layer is 0.5 to 6 hours.
4. The method of manufacturing a structure having a back seal according to claim 1, wherein: the method for removing the polycrystalline silicon layer on the front surface of the wafer comprises at least one of dry etching and wet etching; the method for removing the silicon nitride layer on the front surface of the wafer comprises at least one of dry etching and wet etching; the method for removing the oxide layer on the front surface of the wafer comprises at least one of dry etching and wet etching.
5. The method of claim 4, wherein the step of forming the structure with the back seal layer comprises: the wet etching for removing the polycrystalline silicon layer is single-sided etching, and the adopted etching liquid comprises phosphoric acid; the dry etching for removing the polycrystalline silicon layer comprises at least one of ion etching and chemical reaction etching; the wet etching for removing the silicon nitride layer is single-sided etching, and the adopted etching liquid comprises phosphoric acid; the dry etching for removing the silicon nitride layer comprises at least one of ion etching and chemical reaction etching; the wet etching for removing the oxide layer is single-sided etching, and the adopted etching liquid comprises phosphoric acid; the dry etching for removing the oxide layer comprises at least one of ion etching and chemical reaction etching.
6. A structure with a back seal layer, characterized in that: the structure with the back sealing layer comprises a wafer, the wafer comprises a doping layer, and the side face and the back face of the wafer are sequentially coated with an oxide layer, a silicon nitride layer and a polycrystalline silicon layer from inside to outside.
7. The structure with a back seal layer of claim 6, wherein: the doped layer is of a P-type or N-type, and the resistivity of the doped layer ranges from 0.01 milli-ohms per centimeter to 100 milli-ohms per centimeter.
8. The structure with a back seal layer of claim 6, wherein: the wafer further comprises a P-type or N-type preset epitaxial layer, and the preset epitaxial layer is located on the front side of the doped layer.
9. The structure with a back seal layer of claim 6, wherein: the thickness of the oxide layer ranges from 50 angstroms to 32000 angstroms, the thickness of the silicon nitride layer ranges from 5 angstroms to 5000 angstroms, and the thickness of the polysilicon layer ranges from 1000 angstroms to 20000 angstroms.
10. A method for manufacturing a semiconductor structure is characterized in that: providing the structure with the back sealing layer according to any one of claims 6 to 9, wherein an epitaxial film layer is grown on the front surface of the structure with the back sealing layer, and the epitaxial film layer is further grown along the surface of the polysilicon layer and covers the etching interface of the polysilicon layer, the silicon nitride layer and the silicon oxide layer.
CN202210988631.3A 2022-08-17 2022-08-17 Structure with back sealing layer, preparation method thereof and preparation method of semiconductor structure Pending CN115295399A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117766378A (en) * 2023-12-22 2024-03-26 上海领矽半导体有限公司 Preparation method of silicon epitaxial material for low-capacitance TVS

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117766378A (en) * 2023-12-22 2024-03-26 上海领矽半导体有限公司 Preparation method of silicon epitaxial material for low-capacitance TVS

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