CN115293082A

CN115293082A - Training and predicting method, device, equipment and storage medium of time sequence prediction model

Info

Publication number: CN115293082A
Application number: CN202211205570.5A
Authority: CN
Inventors: 冯春阳; 田培杰
Original assignee: Shenzhen Hongxin Micro Nano Technology Co ltd
Current assignee: Shenzhen Hongxin Micro Nano Technology Co ltd
Priority date: 2022-09-30
Filing date: 2022-09-30
Publication date: 2022-11-04
Anticipated expiration: 2042-09-30
Also published as: CN115293082B

Abstract

The invention provides a training and predicting method, a training and predicting device and a storage medium of a time sequence prediction model, and relates to the technical field of data processing. The method comprises the following steps: carrying out conversion processing on sample circuit structures of a plurality of sample integrated circuits to obtain a sample graph structure; performing feature extraction processing according to each sample circuit structure to obtain sample graph feature information; predicting by adopting an initial time sequence prediction model according to the sample graph structure and the sample graph characteristic information to obtain predicted time sequence information corresponding to the sample integrated circuit; calculating a loss function value according to the predicted timing information and the real timing information of the plurality of sample integrated circuits; and continuing model training by adopting the loss function value according to the sample graph structure, the sample graph characteristic information and the real time sequence information until the loss function value reaches a preset iteration stop condition to obtain a time sequence prediction model. The timing sequence prediction model obtained by training can predict the timing sequence information of any circuit structure, and the application range is widened.

Description

Training and predicting method, device, equipment and storage medium of time sequence prediction model

Technical Field

The invention relates to the technical field of data processing, in particular to a training and predicting method, a training and predicting device and a training and predicting equipment of a time sequence prediction model and a storage medium.

Background

An Integrated Circuit (IC) is a type of microelectronic device or component. In the manufacture of ICs, a certain process is used to interconnect the required elements such as transistors, resistors, capacitors and inductors in a circuit and wiring, and the interconnection is made on one or more small semiconductor chips or dielectric substrates, which are then packaged in a package to form a microstructure having the required circuit function.

In the related art, the Bigram (Bigram) structure is used to predict the timing information of the devices in the integrated circuit, but when the Bigram (Bigram) structure is used to predict, the prediction cannot be performed on the integrated circuit with a partial structure, for example, the integrated circuit with only two devices, i.e., a start register and a tail register, and the integrated circuit with an even number of path passing points cannot be predicted.

In the related art, a Bigram (Bigram) structure is adopted for prediction, partial integrated circuits cannot perform prediction, and the application range is small.

Disclosure of Invention

The present invention aims to provide a training and predicting method, device, apparatus and storage medium for a timing prediction model, so as to solve the problem that in the related art, a Bigram (binary model) structure is adopted for prediction, and a part of integrated circuits cannot perform prediction, so that the application range is small.

In order to achieve the above purpose, the embodiment of the present invention adopts the following technical solutions:

in a first aspect, an embodiment of the present invention provides a method for training a time sequence prediction model, including:

carrying out conversion processing on sample circuit structures of a plurality of sample integrated circuits to obtain a plurality of sample graph structures of the sample integrated circuits, wherein nodes in the sample graph structures are used for representing pins of each device in the sample integrated circuits, and connecting lines of the nodes in the sample graph structures are used for representing the connection relation among the pins;

performing feature extraction processing according to each sample circuit structure to obtain sample graph feature information of the sample graph structure;

predicting by adopting an initial time sequence prediction model according to the sample graph structure and the sample graph characteristic information to obtain predicted time sequence information corresponding to the sample integrated circuit;

calculating a loss function value according to the predicted timing information and the real timing information of the plurality of sample integrated circuits;

and continuing model training according to the sample graph structure, the sample graph characteristic information and the real time sequence information by adopting the loss function value until the loss function value reaches a preset iteration stop condition to obtain a time sequence prediction model.

Optionally, the performing feature extraction processing according to each sample circuit structure to obtain sample graph feature information of the sample graph structure includes:

performing feature extraction processing according to each sample circuit structure to obtain feature values of a plurality of nodes in the sample circuit structure and feature values of a plurality of node connecting lines;

respectively generating eigenvectors of the plurality of nodes and eigenvectors of the plurality of node connecting lines according to the eigenvalues of the plurality of nodes and the eigenvalues of the plurality of node connecting lines;

wherein, the sample graph characteristic information comprises: the node characteristic matrix is composed of characteristic vectors of the nodes, and the edge characteristic vector matrix is composed of characteristic vectors of connecting lines of the nodes.

Optionally, the performing feature extraction processing according to each sample circuit structure to obtain feature values of a plurality of nodes in the sample circuit structure and feature values of a plurality of node connecting lines includes:

performing feature extraction processing according to each sample circuit structure to obtain feature values of the plurality of nodes;

and determining the characteristic values of the plurality of node connections according to the characteristic values of the plurality of nodes.

Optionally, the feature values of the multiple nodes include: whether the node is on the path, the arrival time, the conversion time, the maximum capacitance of the node, the maximum effective capacitance and the characteristic conversion time ratio;

the determining the characteristic values of the plurality of node connections according to the characteristic values of the plurality of nodes comprises:

subtracting the arrival time of the starting node from the arrival time of the tail node to obtain the delay of the node connecting line;

taking the conversion time ratio on the starting node as the conversion time ratio of the node connecting line, wherein the characteristic values of the plurality of node connecting lines comprise: a delay of the node connection line and a transition time ratio of the node connection line.

Optionally, the calculating a loss function value according to the predicted timing information and the real timing information of the plurality of sample integrated circuits includes:

calculating a mean square error from the predicted timing information and the true timing information for a plurality of the sample integrated circuits;

calculating a penalty item according to the predicted time sequence information and the real time sequence information of a plurality of sample integrated circuits;

and calculating the loss function value according to the mean square error, the penalty item and a preset weight.

Optionally, the calculating a penalty term according to the predicted timing information and the real timing information of the plurality of sample integrated circuits includes:

calculating an absolute value of predicted timing information for each of the sample integrated circuits, and a negative first sum of the predicted timing information, and calculating a square of each of the first sums;

calculating an average value of squares of the plurality of first sum values to obtain a first average value;

calculating a difference value of the predicted timing information and the true timing information for each of the sample integrated circuits, and calculating an absolute value of the difference value and a square of a second sum of the difference values;

calculating an average value of squares of the plurality of second sum values to obtain a second average value;

and calculating the penalty item according to the first average value and the second average value.

Optionally, the sample graph feature information includes: first predicted timing information, the method further comprising:

dividing the sample graph structure, the sample graph feature information and the real time sequence information of the sample integrated circuit into a plurality of types of sample data sets according to the first prediction time sequence information, wherein the first prediction time sequence information is graph-based time sequence prediction information;

respectively carrying out graph neural network model training according to the multi-class sample data sets to obtain a plurality of target time sequence prediction models;

the target time sequence prediction models are used for predicting the integrated circuits to be predicted corresponding to different first prediction time sequence information to obtain second prediction time sequence information, and the second prediction time sequence information is time sequence prediction information based on paths.

Optionally, if the actual timing information of the sample integrated circuit is: if the difference value between the first predicted time sequence information and the target real time sequence information is smaller than the preset time sequence information, the time sequence prediction model is used for predicting the difference value between the first predicted time sequence information and the second predicted time sequence information of the integrated circuit to be predicted;

or, the real timing information of the sample integrated circuit is: and the time sequence prediction model is used for predicting second predicted time sequence information of the integrated circuit to be predicted according to the target real time sequence information.

In a second aspect, an embodiment of the present invention further provides a time sequence prediction method, including:

performing conversion processing on a circuit structure to be predicted of an integrated circuit to be predicted to obtain a graph structure to be predicted of the integrated circuit to be predicted, wherein nodes in the graph structure to be predicted are used for representing pins of each device in the integrated circuit to be predicted, and node connecting lines in the graph structure to be predicted are used for representing the connection relation between the pins;

performing feature extraction processing according to the circuit structure to be predicted to obtain feature information of the graph to be predicted of the graph structure to be predicted;

and performing prediction processing according to the structure of the graph to be predicted and the characteristic information of the graph to be predicted by using a preset time sequence prediction model to obtain the predicted time sequence information of the integrated circuit to be predicted, wherein the preset time sequence prediction model is obtained by training by using any one of the methods of the first aspect.

In a third aspect, an embodiment of the present invention provides a training apparatus for a time sequence prediction model, including:

the conversion processing module is used for performing conversion processing on sample circuit structures of a plurality of sample integrated circuits to obtain a plurality of sample graph structures of the sample integrated circuits, wherein nodes in the sample graph structures are used for representing pins of each device in the sample integrated circuits, and connecting lines of the nodes in the sample graph structures are used for representing the connection relation among the pins;

the characteristic extraction module is used for carrying out characteristic extraction processing according to each sample circuit structure to obtain sample graph characteristic information of the sample graph structure;

the training module is used for predicting by adopting an initial time sequence prediction model according to the sample graph structure and the sample graph characteristic information to obtain the corresponding predicted time sequence information of the sample integrated circuit; calculating a loss function value according to the predicted time sequence information and the real time sequence information of a plurality of sample integrated circuits; and continuing model training according to the sample graph structure, the sample graph characteristic information and the real time sequence information by adopting the loss function value until the loss function value reaches a preset iteration stop condition to obtain a time sequence prediction model.

Optionally, the feature extraction module is further configured to perform feature extraction processing according to each sample circuit structure, so as to obtain feature values of a plurality of nodes in the sample circuit structure and feature values of a plurality of node connecting lines; respectively generating eigenvectors of the plurality of nodes and eigenvectors of the plurality of node connecting lines according to the eigenvalues of the plurality of nodes and the eigenvalues of the plurality of node connecting lines; wherein, the sample graph characteristic information comprises: the node characteristic matrix is composed of characteristic vectors of the nodes, and the edge characteristic vector matrix is composed of characteristic vectors of connecting lines of the nodes.

Optionally, the feature extraction module is further configured to perform feature extraction processing according to each sample circuit structure to obtain feature values of the plurality of nodes; and determining the characteristic values of the plurality of node connections according to the characteristic values of the plurality of nodes.

Optionally, the feature values of the plurality of nodes include: whether the node is on the path, the arrival time, the conversion time, the maximum capacitance of the node, the maximum effective capacitance and the characteristic conversion time ratio;

the characteristic extraction module is also used for subtracting the arrival time of the starting node from the arrival time of the tail node to obtain the delay of the node connecting line; taking the conversion time ratio on the starting node as the conversion time ratio of the node connecting line, wherein the characteristic values of the plurality of node connecting lines comprise: a delay of the node connection line and a transition time ratio of the node connection line.

Optionally, the training module is further configured to calculate a mean square error according to the predicted timing information and the real timing information of the plurality of sample integrated circuits; calculating a penalty item according to the predicted time sequence information and the real time sequence information of a plurality of sample integrated circuits; and calculating the loss function value according to the mean square error, the penalty item and a preset weight.

Optionally, the training module is further configured to calculate an absolute value of predicted timing information of each of the sample integrated circuits, and a negative first sum of the predicted timing information, and calculate a square of each of the first sums; calculating an average value of squares of the plurality of first sum values to obtain a first average value; calculating a difference value of the predicted timing information and the true timing information for each of the sample integrated circuits, and calculating an absolute value of the difference value and a square of a second sum of the difference values; calculating an average value of squares of the plurality of second sum values to obtain a second average value; and calculating the penalty item according to the first average value and the second average value.

Optionally, the sample graph feature information includes: first predicted timing information, the apparatus further comprising:

a dividing module, configured to divide the sample graph structure, the sample graph feature information, and the real timing information of the sample integrated circuit into multiple types of sample data sets according to the first predicted timing information, where the first predicted timing information is graph-based timing prediction information;

the acquisition module is used for respectively carrying out graph neural network model training according to the multi-class sample data sets to obtain a plurality of target time sequence prediction models; the target time sequence prediction models are used for predicting the integrated circuits to be predicted corresponding to different first prediction time sequence information to obtain second prediction time sequence information, and the second prediction time sequence information is time sequence prediction information based on paths.

or, the real time sequence information of the sample integrated circuit is: and the time sequence prediction model is used for predicting second predicted time sequence information of the integrated circuit to be predicted according to the target real time sequence information.

In a fourth aspect, an embodiment of the present invention further provides a time sequence prediction apparatus, including:

the device comprises a conversion processing module, a prediction processing module and a prediction processing module, wherein the conversion processing module is used for converting a circuit structure to be predicted of an integrated circuit to be predicted to obtain a graph structure to be predicted of the integrated circuit to be predicted, nodes in the graph structure to be predicted are used for representing pins of each device in the integrated circuit to be predicted, and node connecting lines in the graph structure to be predicted are used for representing the connection relation among the pins;

the characteristic extraction module is used for carrying out characteristic extraction processing according to the circuit structure to be predicted to obtain the characteristic information of the graph to be predicted of the graph structure to be predicted;

the prediction module is configured to perform prediction processing according to the structure of the to-be-predicted graph and the feature information of the to-be-predicted graph by using a preset time sequence prediction model, so as to obtain predicted time sequence information for the to-be-predicted integrated circuit, where the preset time sequence prediction model is obtained by training using any one of the methods described in the first aspect.

In a fifth aspect, an embodiment of the present invention further provides a processing device, including: a memory storing a computer program executable by the processor, and a processor implementing the method of any one of the first and second aspects when the processor executes the computer program.

In a sixth aspect, the present invention further provides a computer-readable storage medium, where the storage medium stores a computer program, and when the computer program is read and executed, the computer program implements the method according to any one of the first and second aspects.

The beneficial effects of the invention are: the embodiment of the invention provides a training method of a time sequence prediction model, which comprises the following steps: carrying out conversion processing on sample circuit structures of a plurality of sample integrated circuits to obtain sample graph structures of the plurality of sample integrated circuits, wherein nodes in the sample graph structures are used for representing pins of each device in the sample integrated circuits, and node connecting lines in the sample graph structures are used for representing the connection relation among the pins; performing feature extraction processing according to each sample circuit structure to obtain sample graph feature information of the sample graph structure; predicting by adopting an initial time sequence prediction model according to the sample graph structure and the sample graph characteristic information to obtain predicted time sequence information corresponding to the sample integrated circuit; calculating a loss function value according to the predicted timing information and the real timing information of the plurality of sample integrated circuits; and continuing model training by adopting the loss function value according to the sample graph structure, the sample graph characteristic information and the real time sequence information until the loss function value reaches a preset iteration stop condition to obtain a time sequence prediction model. The nodes of the sample graph structure represent pins of devices in the sample integrated circuit, the node connecting lines are used for representing the connection relation among the pins, the information represented by the sample graph structure and the sample graph characteristic information is more detailed and abundant, the representation form of the sample circuit structure is more flexible and simpler, and the time sequence prediction model obtained based on the sample graph structure, the sample graph characteristic information and the real time sequence information of the sample integrated circuit through training can predict the time sequence information of any circuit structure, so that the application range is expanded.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a schematic structural diagram of a first circuit according to an embodiment of the present invention;

fig. 2 is a schematic flowchart of a training method of a first timing prediction model according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a second circuit according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a first diagram structure provided in accordance with an embodiment of the present invention;

FIG. 5 is a schematic diagram of a second diagram structure provided in accordance with an embodiment of the present invention;

fig. 6 is a flowchart illustrating a training method of a second timing prediction model according to an embodiment of the present invention;

FIG. 7 is a flowchart illustrating a third method for training a timing prediction model according to an embodiment of the present invention;

fig. 8 is a flowchart illustrating a fourth method for training a timing prediction model according to an embodiment of the present invention;

fig. 9 is a flowchart illustrating a fifth training method for a time series prediction model according to an embodiment of the present invention;

fig. 10 is a schematic diagram illustrating a relationship between predicted timing information and actual timing information according to an embodiment of the present invention;

fig. 11 is a flowchart illustrating a training method of a sixth time series prediction model according to an embodiment of the present invention;

fig. 12 is a flowchart illustrating a seventh training method for a time series prediction model according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of an experimental result provided by an embodiment of the present invention;

fig. 14 is a flowchart illustrating a timing prediction method according to an embodiment of the present invention;

FIG. 15 is a schematic structural diagram of a training apparatus for a timing prediction model according to an embodiment of the present invention;

fig. 16 is a schematic structural diagram of a timing prediction apparatus according to an embodiment of the present invention;

fig. 17 is a schematic structural diagram of a processing apparatus according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that if the terms "upper", "lower", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which is usually arranged when the product of the application is used, the description is only for convenience of describing the application and simplifying the description, but the indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation and operation, and thus, cannot be understood as the limitation of the application.

Furthermore, the terms "first," "second," and the like in the description and in the claims, as well as in the drawings, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.

In the related art, the Bigram structure is adopted to predict the timing information of the devices in the integrated circuit, but when the Bigram structure is adopted to predict, the prediction cannot be performed on the integrated circuit with a partial structure, for example, the integrated circuit with only two devices, namely a start register and a tail register, and the integrated circuit with an even number of path passing points cannot be predicted. The method adopts a Bigram structure for prediction, partial integrated circuits cannot perform prediction, and the application range is small.

Fig. 1 is a schematic structural diagram of a first circuit according to an embodiment of the present invention, and as shown in (a) of fig. 1, the circuit may include: the first register FF1, the first device and the last register FF2 are connected in sequence, wherein D represents an input end, and Q represents an output end. As shown in fig. 1 (a), a Bigram structure requires at least one device for a path, and since a Bigram contains two devices and a path can be predicted with at least one Bigram structure, a predictable path can contain at least two devices.

In addition, since the start register contains all the features required for a data point, it can be handled by one device, so at least one device is required, and the end register is not one of the devices. However, in practical designs, there are many paths, as shown in fig. 1 (b), which have only two devices, namely, a start register and an end register, and are unpredictable.

Moreover, each device has an input pin and an output pin, namely two points on a path, and an input pin of a tail register is added (the arrival time of the path only reaches the input pin of the tail register, so the output pin is not needed), and the number of the pins passing through each path is odd. However, in many designs, the number of points through which the path passes may be even for some reasons. In this case, a normal Bigram structure cannot be constructed, so such a path is also unpredictable, which further cuts down the number of predictable paths.

In view of the above technical problems in the related art, an embodiment of the present application provides a training method for a timing prediction model, where nodes of a sample graph structure represent pins of devices in a sample integrated circuit, and node connection lines are used to represent connection relationships between the pins, information represented by the sample graph structure and sample graph feature information is more detailed and abundant, and a representation form of the sample circuit structure is more flexible and simpler, and a timing prediction model trained based on the sample graph structure, the sample graph feature information, and real timing information of the sample integrated circuit can predict timing information of any circuit structure, thereby improving an application range.

Fig. 2 is a schematic flowchart of a training method of a first timing prediction model according to an embodiment of the present invention, and as shown in fig. 2, the method may include:

s201, converting the sample circuit structures of the plurality of sample integrated circuits to obtain the sample graph structures of the plurality of sample integrated circuits.

The nodes in the sample graph structure are used for representing pins of each device in the sample integrated circuit, and the node connecting lines in the sample graph structure are used for representing the connection relation between the pins.

In the embodiment of the present application, the sample integrated circuit is formed by devices and connections between the devices, the devices in the circuit correspond to each node of the sample graph structure, and the connections between the devices correspond to the connections between the nodes of the sample graph structure. The sample integrated circuit is dissected in more detail, pins on each device are taken as a node, and the connecting lines between the pins correspond to the connecting lines of all nodes in the sample graph structure.

In addition, because different attributes and information are provided among the pins, the connection line from the input pin to the output pin can be represented by a time sequence arc, and the existence of the time sequence arc and the influence caused by the time sequence arc are represented. The direction of the nodes in the directed graph can be used for representing the signal propagation direction in the sample integrated circuit, and the physical composition of the sample integrated circuit and the relation between the connecting lines of the pins can be presented to the greatest extent.

S202, performing feature extraction processing according to each sample circuit structure to obtain sample graph feature information of the sample graph structure.

The sample diagram feature information of the sample diagram structure can be used for characterizing feature information of devices in the sample integrated circuit, and feature information corresponding to connecting lines between the devices.

In some embodiments, a preset tool or a preset algorithm may be used to perform feature extraction processing on each sample circuit structure, so as to directly or indirectly obtain sample graph feature information of the sample graph structure.

It should be noted that the feature extraction processing may be performed on a plurality of sample circuit structures simultaneously, or may also be performed on a plurality of sample circuit structures sequentially in a preset order, which is not specifically limited in the embodiment of the present application.

Similarly, a plurality of sample circuit structures may be simultaneously subjected to conversion processing, or a preset sequence may also be adopted to sequentially perform conversion processing on a plurality of sample circuit structures, and the embodiment of the present application does not specifically limit this.

And S203, predicting by adopting an initial time sequence prediction model according to the sample graph structure and the sample graph characteristic information to obtain the corresponding predicted time sequence information of the sample integrated circuit.

The sample graph structure and the sample graph feature information are input into an initial timing prediction model, and the initial timing prediction model can output the predicted timing information corresponding to the sample integrated circuit.

S204, calculating a loss function value according to the predicted time sequence information and the real time sequence information of the plurality of sample integrated circuits.

In the embodiment of the present application, a predetermined formula is adopted to calculate the loss function value according to the predicted timing information and the real timing information of the plurality of sample integrated circuits.

And S205, continuing model training by adopting the loss function value according to the sample graph structure, the sample graph characteristic information and the real time sequence information until the loss function value reaches a preset iteration stop condition to obtain a time sequence prediction model.

The timing prediction model can be used for predicting the timing information of the integrated circuit to be predicted.

In some embodiments, a graph neural network model is trained according to a sample graph structure, sample graph feature information, and real time sequence information of a sample integrated circuit, and when model parameters meet preset conditions, a time sequence prediction model is obtained. In addition, if the model parameters do not meet the preset conditions, continuing to train the graph neural network model until the model parameters meet the preset conditions to obtain the time sequence prediction model.

Alternatively, the neural network on which the time sequence prediction model is based may be an information-passing neural network (NNConv), and data input into the information-passing neural network can output useful characteristic information through a series of transmission and calculation.

The convolution formula for NNConv is as follows:

wherein, the first and the second end of the pipe are connected with each other,

represents a starting nodeThe weight on the edge to the target node,

represents a neural network, so the term means that a neural network is used to train on-edge information. NNConv is a nested neural network, and a neural network is also arranged in the neural network. The number of neurons of the input layer of the neural network is 2, namely the number of neurons of the hidden layer is 32 corresponding to two features of an edge, and the number of neurons of the output layer is the number of node features multiplied by the number of neurons of the outer hidden layer.

Is the output of one convolutional layer.

In addition, the information of the edge is multiplied by the characteristic value of the neighbor node after passing through the neural network

And finally adding the obtained results to obtain the information item of the side.

Is the characteristic value of the central node

Multiplying by a weight

And adding the information items of the edges to obtain the value of the center node after convolution.

It should be noted that the graph neural network may use two layers of NNConv as convolution layers, the number of neurons in the convolution layers is 64, each convolution layer is layered with one standard layer, the middle is connected by a ReLU (Linear rectification) activation function, then the global pooling layer is connected, and finally the small full connection layer is connected. The small-sized full-connection layer is composed of three hidden layers, and the number of neurons of each hidden layer is 64. Optionally, the loss function is a custom loss function, the learning rate is 0.003, the optimizer is Adam (an optimizer), and the number of iterations is preset for each training, where the preset number may be 100.

In the examples of the application, graphConv, GCNConv, GATConv, etc. can be used as the convolution layer. In addition, the number of the adopted convolutional layers is not limited, the number of neurons of the convolutional layers is not limited, the selection of an activation function is not limited, the selection of a global pooling layer is not limited, and the scale of an output conversion full-connection layer of the model is not limited. The graph neural network architecture may also be other architectures.

In summary, an embodiment of the present invention provides a training method for a time sequence prediction model, where the method includes: carrying out conversion processing on sample circuit structures of a plurality of sample integrated circuits to obtain sample graph structures of the plurality of sample integrated circuits, wherein nodes in the sample graph structures are used for representing pins of each device in the sample integrated circuits, and node connecting lines in the sample graph structures are used for representing the connection relation among the pins; performing feature extraction processing according to each sample circuit structure to obtain sample graph feature information of the sample graph structure; predicting by adopting an initial time sequence prediction model according to the sample graph structure and the sample graph characteristic information to obtain predicted time sequence information corresponding to the sample integrated circuit; calculating a loss function value according to the predicted timing information and the real timing information of the plurality of sample integrated circuits; and continuing model training by adopting the loss function value according to the sample graph structure, the sample graph characteristic information and the real time sequence information until the loss function value reaches a preset iteration stop condition to obtain a time sequence prediction model. The nodes of the sample graph structure represent pins of devices in the sample integrated circuit, the node connecting lines are used for representing the connection relation among the pins, the information represented by the sample graph structure and the sample graph characteristic information is more detailed and abundant, the representation form of the sample circuit structure is more flexible and simpler, and the time sequence prediction model obtained based on the sample graph structure, the sample graph characteristic information and the real time sequence information of the sample integrated circuit through training can predict the time sequence information of any circuit structure, so that the application range is expanded.

Fig. 3 is a schematic structural diagram of a second circuit according to an embodiment of the present invention, as shown in fig. 3, in the sample integrated circuit, a path starts from a start register FF1, passes through a second device and gate, then passes through a third device or gate, and finally ends at a last register FF2. The device pins through which it passes are from the CLK pin of FF1 through to the D pin of FF2, as shown by the dashed lines in fig. 3.

Fig. 4 is a schematic diagram of a first diagram structure provided by an embodiment of the present invention, and the diagram structure in fig. 4 can be obtained by performing conversion processing on the circuit in fig. 3, as shown in fig. 4, each circle in the diagram structure is a node and represents a corresponding pin, where node 0 represents a CLK pin of the start register FF1, node 1 represents a Q pin of the start register FF1, node 2 represents an a pin of a second device and gate, and so on, and node 3 and node 6 represent a branch pin B of the second device and gate and a branch pin a of a third device or gate, respectively.

Fig. 5 is a schematic diagram of a second diagram structure provided by an embodiment of the present invention, and the diagram structure in fig. 5 can be obtained by performing conversion processing on the circuit in fig. 2 (b), as shown in fig. 5, each circle in the diagram structure is a node and represents a corresponding pin, where a node 0 represents a CLK pin of the start register FF1, a node 1 represents a Q pin of the start register FF1, and a node 2 represents a Q pin of the end register FF2. The circuit diagram is represented by a diagram structure, which is completely different from the Bigram structure in the prior art and can represent paths that cannot be represented by the Bigram structure.

Optionally, fig. 6 is a schematic flowchart of a training method of a second time sequence prediction model according to an embodiment of the present invention, and as shown in fig. 6, the process of performing feature extraction processing according to each sample circuit structure in S201 to obtain sample diagram feature information of the sample diagram structure may include:

s601, feature extraction processing is carried out according to each sample circuit structure, and feature values of a plurality of nodes in the sample circuit structure and feature values of a plurality of node connecting lines are obtained.

S602, respectively generating eigenvectors of the plurality of nodes and eigenvectors of the plurality of node connecting lines according to the eigenvalues of the plurality of nodes and the eigenvalues of the plurality of node connecting lines.

Wherein, the sample graph characteristic information comprises: the node feature matrix is composed of feature vectors of a plurality of nodes, and the edge feature vector matrix is composed of feature vectors of a plurality of node connecting lines.

Optionally, fig. 7 is a flowchart of a training method of a third time series prediction model according to an embodiment of the present invention, and as shown in fig. 7, the process of performing feature extraction processing according to each sample circuit structure in S601 to obtain feature values of a plurality of nodes in the sample circuit structure and feature values of a plurality of node connecting lines may include:

and S701, performing feature extraction processing according to each sample circuit structure to obtain feature values of a plurality of nodes.

S702, determining the characteristic values of the wiring of the plurality of nodes according to the characteristic values of the plurality of nodes.

In some embodiments, feature extraction processing is performed according to each sample circuit structure to obtain a maximum value TR _ MAX among a plurality of paths, all pins passing through each path, devices passing through the paths, all branch pins of the devices, and conversion time on all input pins of the devices _gba 。

in this embodiment of the present application, for all pins through which a path passes and all branch pins of a device, characteristic values of the pins, that is, characteristic values of a plurality of nodes, may be recorded, including: whether it is on the path (is _ on _ path), arrival time (arrival _ time), transition time (TR _ time, TR) _gba ) Pin (node) maximum capacitance (pin _ max _ cap) and maximum effective capacitance (max _ effect _ cap). A characteristic conversion time ratio (TR _ ratio).

Where is _ on _ path indicates whether the node, i.e., the pin, is on the path. The boolean value may be converted to a floating point value as a weight, with a value of 1 if the pin is on the path and 0 otherwise. An is _ on _ path of 1 indicates that the information on the node is important, and the information should be considered with attention; an is _ on _ path of 0 indicates that the information on the node is not so important, but certain considerations are needed. The arrival time is the arrival time of the corresponding pin of the node. The conversion time is the conversion time of the corresponding pin of the node. The pin maximum capacitance (pin _ max _ cap) and the maximum effective capacitance (max _ effect _ cap) are both the values on the corresponding pin of the node.

In addition, the transition time ratio (TR _ ratio) is the transition Time (TR) on the current input pin _gba ) Divided by the maximum transition time (TR _ MAX) on all input pins _gba ) The ratio is then subtracted from 1 and is formulated as follows:

it should be noted that, taking TR _ ratio as a relatively complex feature, it is difficult to be extracted by the time sequence prediction model spontaneously, or even if the time sequence prediction model recognizes that this feature has an influence on the final result, it may not give too much weight to this feature, and it is advantageous to use this data as a feature to better match the time sequence prediction model.

Optionally, fig. 8 is a flowchart illustrating a fourth method for training a time series prediction model according to an embodiment of the present invention, and as shown in fig. 8, the process of determining the eigenvalue of the connection line of the multiple nodes according to the eigenvalue of the multiple nodes in S702 may include:

and S801, subtracting the arrival time of the initial node from the arrival time of the final node to obtain the delay of the node connecting line.

Where the delay represents the time that elapses from the node to the next node. The node connecting lines may also be referred to as edges.

S802, taking the conversion time ratio on the initial node as the conversion time ratio of the node connecting line.

Wherein, the characteristic value of a plurality of node connections includes: the delay of the node connection line and the ratio of the transition time of the node connection line. In addition, the ratio of the transition times of the node connecting lines can be expressed as TR _ ratio.

Optionally, fig. 9 is a flowchart illustrating a fifth method for training a timing prediction model according to an embodiment of the present invention, and as shown in fig. 9, the step of calculating a loss function value according to the predicted timing information and the real timing information of the multiple sample integrated circuits in S204 may include:

s1001, calculating a mean square error according to the predicted timing information and the actual timing information of the plurality of sample ics.

Wherein the predicted timing information of the plurality of sample integrated circuits may be expressed as:

(ii) a The true timing information for multiple sample integrated circuits can be expressed as:

. The mean square error can be expressed as:

。

s1002, calculating a penalty item according to the predicted time sequence information and the real time sequence information of the plurality of sample integrated circuits.

And S1003, calculating a loss function value according to the mean square error, the penalty term and the preset weight.

And the mean square error and the penalty term have corresponding preset weights.

It should be noted that there are two Analysis methods in static timing Analysis, one is Graph-Based timing Analysis GBA (Graph-Based Analysis) and the other is Path-Based timing Analysis PBA (Path-Based Analysis). The GBA analysis speed is high, but the precision is low, and the result is pessimistic, and the PBA analysis speed is low, but the precision is high, and the result is optimistic. The PBA runtime is more than an order of magnitude larger than the GBA runtime for the same number of paths, so running PBA on all paths in the entire integrated circuit design is impractical.

In addition, the timing prediction model can predict GBA-PBA or directly predict PBA, and both GBA-PBA and PBA can be prediction timing information.

It should be noted that the selected target value is not the arrival time gain of each Bigram structure in the related art, but the GBA-PBA arrival time difference of the whole path. The fundamental reason is that with graph neural networks, predictions are made on the entire graph hierarchy, and each graph should have only one prediction value.

In the embodiment of the application, the time sequence prediction model can predict the GBA-PBA, and the predicted GBA-PBA arrival time difference is mostly between the real difference and zero, so that the ratio of an over-optimistic result is reduced.

Notably, the reason for using the custom loss function is as follows:

it should be noted that the penalty function degradation in the static timing analysis is somewhat different from the normal penalty function degradation. In general, the MSE is used as a loss function when training the model, i.e. it is desirable to predict the point as close to the true value as possible, regardless of whether the point is above or below the true value. But not exactly the same in the specific case of predicting the GBA-PBA arrival time difference, two points need to be noted.

The first condition is as follows: since the final goal of prediction is to reduce the pessimism of GBA, which is obtained by subtracting the GBA-PBA arrival time prediction difference from the GBA arrival time, if the prediction timing information is smaller than zero, it is not valid to indicate that the prediction is invalid, rather than using the GBA arrival time directly as a result of subtracting the GBA arrival time from the GBA arrival time.

Case two: it is optimistic if the GBA-PBA arrival time prediction difference is larger than the GBA-PBA arrival time true difference, and this should be avoided as much as possible. Since when using this model, the chip designer wants to have a slightly happy value to avoid spending too much effort on repair. However, if this value is too optimistic, the violations that should actually be fixed are not fixed because of the too optimistic value, and as a result, it becomes very difficult to fix the violations that should be fixed when the PBA is actually used later in the process. The designer therefore does not want to have an optimistic value over the true value.

Optionally, fig. 10 is a schematic diagram of a relationship between predicted timing information and real timing information according to an embodiment of the present invention, as shown in fig. 10, a relationship between a GBA-PBA arrival time prediction difference (prediction difference for short) and a GBA-PBA arrival time real difference (real difference for short) and zero is shown, where the real difference and zero are shown by black solid lines, and the prediction difference is shown by a dashed line. When the predicted difference is below the true difference and above zero, it is acceptable to indicate that the prediction is correct, the closer this value is to the true difference the better. When the prediction difference is smaller than zero, the prediction error, unlike direct GBA, corresponds to the case one mentioned above. When the predicted difference is larger than the true difference, the prediction is wrong and is too optimistic, corresponding to case two mentioned above.

Optionally, fig. 11 is a flowchart illustrating a training method of a sixth timing prediction model according to an embodiment of the present invention, and as shown in fig. 11, the step of calculating a penalty term according to the predicted timing information and the real timing information of the multiple sample integrated circuits in the step S1002 may include:

s1201, the absolute value of the prediction timing information of each sample integrated circuit and the first sum of the negative prediction timing information are calculated, and the square of each first sum is calculated.

S1202, an average value of squares of the plurality of first sum values is obtained to obtain a first average value.

In some embodiments, the first average may be represented as follows:

(ii) a n represents the number of sample integrated circuits.

S1203, a difference between the predicted timing information and the true timing information of each sample integrated circuit is calculated, and an absolute value of the difference and a square of a second sum of the differences are calculated.

And S1204, calculating an average value of squares of the plurality of second sum values to obtain a second average value.

In some embodiments, the second average may be expressed as follows:

and n represents the number of sample integrated circuits.

And S1205, calculating a penalty item according to the first average value and the second average value.

In the embodiment of the present application, the penalty term may be expressed as:

+

+

in addition, the loss function can be expressed as:

wherein the content of the first and second substances,

，

and

may be a preset weight, and may also be referred to as a penalty term coefficient.

In the embodiment of the present application, an MSE plus a penalty term is used as a loss function, where the MSE term is necessary to make the value of the predicted difference as close as possible to the true difference, otherwise, the predicted value will not converge.

Second, the second term is to prevent the prediction result from being invalid, and when the prediction difference is negative, the term becomes twice the absolute value of the prediction difference, and the more negative the prediction difference is, the larger the penalty term is. When the predicted difference is positive, the term is zero and no penalty is imposed.

Finally, the third term is to prevent from being too optimistic, when the predicted difference is larger than the true difference, the term becomes twice the predicted difference minus the true difference, and the penalty term is larger if the predicted difference is larger than the true difference. When the prediction difference is smaller than the true value, the penalty item is zero, and no penalty is given. Front face

，

And

the penalty term coefficient is used as the weight for adjusting the penalty term. Generally, an overoptimistic situation is more difficult to tolerate, because once an overoptimistic path occurs, post-repair is very difficult, so the overoptimistic situation should be minimized, so the penalty factor of the second term

Should be large. Secondly, the negative prediction is acceptable because even if the prediction is negative, then the GBA arrival time is used directly, although it does reduce the model effect, but the overall ratio is too optimistic, so the coefficient of the term

Should not be so large. Finally, penalty factor of MSE term

It is sufficient to keep a moderate reasonable value, which cannot be too large or too small. If too large, the penalty term effect will be small, resulting in many points being too optimistic. If it is too small, the model will not converge and the prediction will be poor or even ineffective.

Optionally, the sample graph feature information includes: optionally, fig. 12 is a flowchart illustrating a training method of a seventh timing prediction model according to an embodiment of the present invention, as shown in fig. 12, the method may further include:

and S1301, dividing the sample graph structure, the sample graph characteristic information and the real time sequence information of the sample integrated circuit into a plurality of types of sample data sets according to the first prediction time sequence information.

The first predicted timing information may be timing prediction information based on a graph, and the first predicted timing information may be GBA.

In addition, each type of sample data set may include: sample graph structure, sample graph feature information, and true timing information for the sample integrated circuit.

S1302, training a graph neural network model according to the multi-class sample data sets respectively to obtain a plurality of target time sequence prediction models;

and S1303, the multiple target time sequence prediction models are used for predicting the integrated circuits to be predicted corresponding to different first prediction time sequence information to obtain second prediction time sequence information.

The second predicted timing information may be path-based timing prediction information, and the second predicted timing information may be PBA or GBA-PBA.

In some embodiments, a first class sample data set of which the first prediction timing information is smaller than a first threshold value is counted; the first prediction time sequence information is greater than or equal to a first threshold value and smaller than a second type sample data set of a second threshold value; and the first prediction time sequence information is greater than or equal to a third sample data set of a second threshold value. Carrying out graph neural network model training by adopting a first type of sample data set to obtain a first target time sequence prediction model; performing graph neural network model training by adopting a second type of sample data set to obtain a second target time sequence prediction model; and carrying out graph neural network model training by adopting the third type of sample data set to obtain a third target time sequence prediction model.

It should be noted that, if the GBA of the integrated circuit to be predicted is smaller than the first threshold, the PBA or GBA-PBA of the integrated circuit to be predicted may be predicted by using the first target timing prediction model; if the GBA of the integrated circuit to be predicted is larger than or equal to the first threshold and smaller than the second threshold, the PBA or GBA-PBA of the integrated circuit to be predicted can be predicted by adopting a second target time sequence prediction model; if the GBA of the integrated circuit to be predicted is larger than or equal to the second threshold, the PBA or GBA-PBA of the integrated circuit to be predicted can be predicted by adopting a third target time sequence prediction model. Wherein, the GBA of the integrated circuit to be predicted can be carried in the graph characteristic information of the integrated circuit to be predicted.

The prediction method can be a three-step prediction method, the time sequence prediction model provided by the embodiment of the application adopts a custom loss function, and a three-step prediction method is adopted, so that the prediction result can be limited to be too optimistic to a great extent, and the prior art does not consider the prediction result.

Fig. 13 is a schematic diagram of an experimental result provided by an embodiment of the present invention, as shown in fig. 13, clearly showing the effect of the three-step prediction method. Two vertical lines in the graph separate the prediction results of the first step, the second step and the third step, so that faults with obvious prediction difference at the separation position can be obviously seen, and the prediction results on the left side and the right side of the separation position are from different time sequence prediction models. Points that should be mostly too optimistic are more likely to be distributed below the true difference because they are less optimistic to train and predict using a new timing prediction model. The difference ratio of the second step model and the third step model is greatly reduced, and the three-step time sequence prediction model plays a strong role in limiting optimism.

Optionally, if the real timing information of the sample integrated circuit is: if the difference value between the first predicted time sequence information and the target real time sequence information is smaller than the preset threshold value, the time sequence prediction model is used for predicting the difference value between the first predicted time sequence information and the second predicted time sequence information of the integrated circuit to be predicted;

or, the real timing information of the sample integrated circuit is: and the time sequence prediction model is used for predicting second prediction time sequence information of the integrated circuit to be predicted according to the target real time sequence information.

In the embodiment of the present application, if the actual timing information of the sample integrated circuit is: and predicting the GBA-real PBA, wherein the time sequence prediction model can output the GBA-PBA predicted by the integrated circuit to be predicted, and the predicted PBA of the predicted integrated circuit can be obtained according to the GBA in the graph characteristic information of the circuit to be predicted. If the real timing information of the sample integrated circuit is: and the real PBA, the time sequence prediction model can output the PBA predicted by the integrated circuit to be predicted.

Table 1 is a data comparison table of the prior art and the embodiment of the present application, where table 1 shows a specific degree of pessimism of the time sequence prediction model provided in the prior art and the embodiment of the present application, and indexes of the time sequence prediction model provided in the prior art and the embodiment of the present application cannot be directly used as comparison due to differences in design of the time sequence prediction model, but because the generalization capability of the model is strong, the performance of the model on different designs does not differ too much, and thus indirect comparison can be performed. Compared with the prior art, the time sequence prediction model provided by the embodiment of the application reduces the mean index, the 99p index and the max index by 72.8%,66.0% and 55.0%, and is improved in comparison with the 61.8%,47.6% and 29.1% in the prior art. The model proposed by the inventor can achieve better effect than the prior art.

TABLE 1

Also, as can be seen from table 1, the optimistic ratio of the time sequence model proposed in the present application is only 10.5%, and the optimistic ratio of the prior art is only 0.8%, which further represents the limit of the three-step prediction method on the optimistic ratio.

Moreover, the time sequence prediction model provided by the embodiment of the application can be applied to wider paths, is better than the prior art in terms of GBA pessimistic reduction, and has smaller proportion of over-optimistic results in prediction results.

In summary, the timing prediction model provided in the embodiment of the present application can predict the timing information of the PBA from the timing information of the GBA, and the prediction result can significantly reduce the pessimism of the GBA, and can be reduced to a greater extent than the prior art. Meanwhile, the method adopts a graph structure, so that the method can be applied to wider paths. According to the method, the custom loss function is adopted in the graph neural network model, so that the too optimistic result in the prediction result is less. When the prediction is carried out, a three-step (not limited to three-step) prediction method is adopted, so that partial over-optimistic results can be over-optimistic, and the over-optimistic result ratio in the prediction results is further reduced.

Fig. 14 is a flowchart illustrating a timing prediction method according to an embodiment of the present invention, as shown in fig. 14, the method may include:

s1501, converting the to-be-predicted circuit structure of the to-be-predicted integrated circuit to obtain the to-be-predicted graph structure of the to-be-predicted integrated circuit.

The node in the graph structure to be predicted is used for representing the pins of each device in the integrated circuit to be predicted, and the node connecting line in the graph structure to be predicted is used for representing the connection relation among the pins.

And S1502, performing feature extraction processing according to the circuit structure to be predicted to obtain feature information of the graph to be predicted of the graph structure to be predicted.

The above processes of S1501 and S1502 may refer to the relevant contents corresponding to S201 and S202, which are not described herein again.

And S1503, performing prediction processing according to the graph structure to be predicted and the graph characteristic information to be predicted by adopting a preset time sequence prediction model to obtain prediction time sequence information for the integrated circuit to be predicted.

The preset time sequence prediction model is obtained by training by adopting the method.

It should be noted that the prediction timing information of the integrated circuit to be predicted may be PBA or GBA-PBA.

In summary, according to the timing prediction method provided in the embodiments of the present invention, the nodes of the graph structure to be predicted represent the pins of the device in the integrated circuit to be predicted, the node connection lines are used to represent the connection relationships between the pins, the information represented by the graph structure to be predicted and the feature information of the graph to be predicted is more detailed and richer, the representation form of the circuit structure to be predicted is also more flexible and simpler, and the timing prediction model is adopted to predict the timing information of any circuit structure, thereby increasing the application range.

The following describes a device, a processing device, a storage medium, and the like for executing the training of the timing prediction model and the timing prediction method provided in the present application, and specific implementation processes and technical effects thereof are referred to the relevant contents of the above methods, and will not be described again below.

Fig. 15 is a schematic structural diagram of a training apparatus for a time series prediction model according to an embodiment of the present invention, as shown in fig. 15, the apparatus may include:

a conversion processing module 1601, configured to perform conversion processing on sample circuit structures of a plurality of sample integrated circuits to obtain sample graph structures of the plurality of sample integrated circuits, where a node in the sample graph structure is used to characterize a pin of each device in the sample integrated circuit, and a node connection line in the sample graph structure is used to characterize a connection relationship between the pins;

a feature extraction module 1602, configured to perform feature extraction processing according to each sample circuit structure to obtain sample graph feature information of the sample graph structure;

a training module 1603, configured to perform graph neural network model training according to the sample graph structure, the sample graph feature information, and the real time sequence information of the sample integrated circuit, to obtain a time sequence prediction model.

Optionally, the feature extraction module 1602 is further configured to perform feature extraction processing according to each sample circuit structure, so as to obtain feature values of a plurality of nodes in the sample circuit structure and feature values of a plurality of node connecting lines; respectively generating eigenvectors of the plurality of nodes and eigenvectors of the plurality of node connecting lines according to the eigenvalues of the plurality of nodes and the eigenvalues of the plurality of node connecting lines; wherein, the sample graph characteristic information comprises: the node characteristic matrix is composed of characteristic vectors of the nodes, and the edge characteristic vector matrix is composed of characteristic vectors of connecting lines of the nodes.

Optionally, the feature extraction module 1602 is further configured to perform feature extraction processing according to each sample circuit structure to obtain feature values of the plurality of nodes; and determining the characteristic values of the plurality of node connections according to the characteristic values of the plurality of nodes.

the feature extraction module 1602 is further configured to subtract the arrival time of the start node from the arrival time of the end node to obtain the delay of the node connection line; taking the conversion time ratio on the starting node as the conversion time ratio of the node connecting line, wherein the characteristic values of the plurality of node connecting lines comprise: a delay of the node connection line and a transition time ratio of the node connection line.

Optionally, the training module 1603 is further configured to perform prediction by using an initial timing prediction model according to the sample graph structure and the sample graph feature information, so as to obtain prediction timing information corresponding to the sample integrated circuit; calculating a loss function value according to the predicted timing information and the real timing information of a plurality of the sample integrated circuits; and continuing model training according to the sample graph structure, the sample graph characteristic information and the real time sequence information by adopting the loss function value until the loss function value reaches a preset iteration stop condition to obtain the time sequence prediction model.

Optionally, the training module 1603 is further configured to calculate a mean square error according to the predicted timing information and the real timing information of the plurality of sample integrated circuits; calculating a penalty item according to the predicted time sequence information and the real time sequence information of a plurality of sample integrated circuits; and calculating the loss function value according to the mean square error, the penalty item and a preset weight.

Optionally, the training module 1603 is further configured to calculate an absolute value of predicted timing information of each sample integrated circuit and a negative first sum of the predicted timing information, and calculate a square of each first sum; calculating an average value of squares of the plurality of first sum values to obtain a first average value; calculating a difference value of the predicted timing information and the true timing information for each of the sample integrated circuits, and calculating an absolute value of the difference value and a square of a second sum of the difference values; calculating an average value of squares of the plurality of second sum values to obtain a second average value; and calculating the penalty item according to the first average value and the second average value.

Optionally, if the real timing information of the sample integrated circuit is: if the difference value between the first predicted time sequence information and the target real time sequence information is smaller than the preset time sequence information, the time sequence prediction model is used for predicting the difference value between the first predicted time sequence information and the second predicted time sequence information of the integrated circuit to be predicted;

Fig. 16 is a schematic structural diagram of a timing prediction apparatus according to an embodiment of the present invention, and as shown in fig. 16, the apparatus may include:

a conversion processing module 1701, configured to perform conversion processing on a to-be-predicted circuit structure of an integrated circuit to be predicted to obtain a to-be-predicted graph structure of the integrated circuit to be predicted, where a node in the to-be-predicted graph structure is used to represent a pin of each device in the integrated circuit to be predicted, and a node connection line in the to-be-predicted graph structure is used to represent a connection relationship between the pins;

a feature extraction module 1702, configured to perform feature extraction processing according to the circuit structure to be predicted, so as to obtain feature information of the graph to be predicted of the graph structure to be predicted;

a prediction module 1703, configured to perform prediction processing according to the structure of the to-be-predicted graph and the feature information of the to-be-predicted graph by using a preset time sequence prediction model, so as to obtain predicted time sequence information for the to-be-predicted integrated circuit, where the preset time sequence prediction model is a model obtained by training using any one of the above methods.

The above-mentioned apparatus is used for executing the method provided by the foregoing embodiment, and the implementation principle and technical effect are similar, which are not described herein again.

These above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs), among others. For another example, when one of the above modules is implemented in the form of a Processing element scheduler code, the Processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

Fig. 17 is a schematic structural diagram of a processing apparatus according to an embodiment of the present invention, and as shown in fig. 17, the processing apparatus includes: a processor 1801, a memory 1802.

The memory 1802 is used for storing a program, and the processor 1801 calls the program stored in the memory 1802 to execute the above method embodiment. The specific implementation and technical effects are similar, and are not described herein again.

Optionally, the present invention also provides a program product, for example a computer-readable storage medium, comprising a program which, when being executed by a processor, is adapted to carry out the above-mentioned method embodiments.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is only a logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or in the form of hardware plus a software functional unit.

The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) or a processor (in english: processor) to execute some steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for training a time series prediction model, comprising:

predicting by adopting an initial time sequence prediction model according to the sample graph structure and the sample graph characteristic information to obtain prediction time sequence information corresponding to the sample integrated circuit;

2. The method according to claim 1, wherein the performing a feature extraction process according to each of the sample circuit structures to obtain sample graph feature information of the sample graph structure comprises:

wherein, the sample graph characteristic information comprises: the node characteristic vector matrix is composed of characteristic vectors of the nodes, and the edge characteristic vector matrix is composed of characteristic vectors of the connecting lines of the nodes.

3. The method of claim 2, wherein the performing the feature extraction process according to each of the sample circuit structures to obtain feature values of a plurality of nodes and feature values of a plurality of node lines in the sample circuit structure comprises:

4. The method of claim 3, wherein the eigenvalues of the plurality of nodes comprise: whether the node is on the path, the arrival time, the conversion time, the maximum capacitance of the node, the maximum effective capacitance and the characteristic conversion time ratio;

5. The method of claim 1, wherein calculating a loss function value based on predicted timing information and real timing information for a plurality of the sample integrated circuits comprises:

calculating a penalty item according to the predicted timing information and the real timing information of a plurality of sample integrated circuits;

6. The method of claim 5, wherein calculating a penalty term based on the predicted timing information and the true timing information for a plurality of the sample integrated circuits comprises:

7. The method of claim 1, wherein the sample map feature information comprises: first predicted timing information, the method further comprising:

8. The method of claim 7, wherein if the true timing information of the sample integrated circuit is: if the difference value between the first predicted time sequence information and the target real time sequence information is smaller than the preset time sequence information, the time sequence prediction model is used for predicting the difference value between the first predicted time sequence information and the second predicted time sequence information of the integrated circuit to be predicted;

9. A method of timing prediction, comprising:

and performing prediction processing according to the graph structure to be predicted and the graph characteristic information to be predicted by adopting a preset time sequence prediction model to obtain the predicted time sequence information of the integrated circuit to be predicted, wherein the preset time sequence prediction model is obtained by training by adopting the method of any one of claims 1 to 8.

10. An apparatus for training a time series prediction model, the apparatus comprising:

the training module is used for predicting by adopting an initial time sequence prediction model according to the sample graph structure and the sample graph characteristic information to obtain the prediction time sequence information corresponding to the sample integrated circuit; calculating a loss function value according to the predicted timing information and the real timing information of the plurality of sample integrated circuits; and continuing model training according to the sample graph structure, the sample graph characteristic information and the real time sequence information by adopting the loss function value until the loss function value reaches a preset iteration stop condition to obtain a time sequence prediction model.

11. A timing prediction apparatus, comprising:

the characteristic extraction module is used for carrying out characteristic extraction processing according to the circuit structure to be predicted to obtain characteristic information of the graph to be predicted of the graph structure to be predicted;

a prediction module, configured to perform prediction processing according to the structure of the graph to be predicted and the feature information of the graph to be predicted by using a preset time sequence prediction model, so as to obtain predicted time sequence information for the integrated circuit to be predicted, where the preset time sequence prediction model is a model obtained by training according to any one of the methods in claims 1 to 8.

12. A processing device, comprising: a memory storing a computer program executable by the processor, and a processor implementing the method of any of the preceding claims 1-9 when executing the computer program.

13. A computer-readable storage medium, characterized in that a computer program is stored on the storage medium, which computer program, when read and executed, implements the method of any of the preceding claims 1-9.