CN115291664A

CN115291664A - Low dropout regulator circuit with automatically adjustable static power consumption

Info

Publication number: CN115291664A
Application number: CN202211188219.XA
Authority: CN
Inventors: 方狄; 吴献; 许江; 鲁翔; 李炜
Original assignee: Shenzhen Apt Microelectronics Co ltd
Current assignee: Shenzhen Apt Microelectronics Co ltd
Priority date: 2022-09-28
Filing date: 2022-09-28
Publication date: 2022-11-04
Anticipated expiration: 2042-09-28
Also published as: CN115291664B

Abstract

The invention provides a low dropout regulator circuit with automatically adjustable static power consumption, which comprises an LDO main circuit and an LDO output current detection circuit connected with the LDO main circuit, wherein the LDO main circuit comprises an error amplifier and an output stage circuit, and the LDO output current detection circuit is used for detecting the output current of the LDO main circuit and adjusting the current of the error amplifier according to the change of the output current. The LDO output current detection circuit detects the magnitude of the LDO output current, the magnitude of the output current of the main LDO circuit can be tracked in real time, the current of the error amplifier can be adjusted, the gear of the detection current can be freely adjusted according to different modes of the digital circuit, and the gear can be adjusted if the current changes greatly in the same mode; by detecting the magnitude of the output current of the LDO, the magnitude of the input current of the LDO can be tracked in real time, and then the current of the error amplifier is adjusted.

Description

Low dropout regulator circuit with automatically adjustable static power consumption

Technical Field

The invention relates to the technical field of circuits, in particular to a low dropout regulator circuit with automatically adjustable static power consumption.

Background

In the SOC chip, a Low-dropout regulator (LDO) is often used as a power supply of a digital circuit. A commonly used LDO architecture (shown in fig. 1) consists of a reference Voltage (VREF), an error amplifier, and an output stage circuit. The current consumed may vary when the digital circuit is operating in different modes (e.g., run mode/sleep mode/standby mode, etc.). In general, the current consumed by the operation mode > the current consumed by the sleep mode > the current consumed by the standby mode varies greatly from a few microamperes to a few tens of milliamperes. For the LDO, the corresponding driving currents are different, and when the driving current changes, the position of the output pole of the LDO also changes greatly, which affects the stability of the circuit. And when the digital circuit works in an ultra-low power consumption mode, the LDO is not expected to consume excessive current, so that the overall power consumption is influenced. When the LDO driving current is large, it is not particularly sensitive to the current consumed by the error amplifier.

In view of the above situation, a general method is to control and adjust the current of the error amplifier by using a control word under different digital circuit operating modes, increase the operating current of the error amplifier when the LDO outputs a large current, and decrease the operating current of the error amplifier as much as possible when the LDO outputs a small current or even has no load. Present LDOs often do not have an off-chip capacitor, and the dominant pole is typically located at the output of the error amplifier. When the LDO is fully loaded, the pole of the output stage is transferred to high frequency, so that the current of the error amplifier can be increased, the response speed is improved, and the stability is not influenced. When the LDO is idle (standby mode), it is sensitive to the power consumption of the LDO error amplifier, so its operating current must be reduced. In this mode, the output stage pole can move inward at a low frequency, so that the power consumption of the error amplifier is reduced, the frequency of the main pole can be reduced, and the circuit is kept stable.

As shown in fig. 2, in the normal operation MODE of the digital circuit, MODE1/MODE2= L, I1/I2/I3 is simultaneously used as a bias current of the error amplifier, so that the operation current of the error amplifier is increased, and the response speed is improved. When the sleep MODE is operated, MODE1= H/MODE2= L, I2/I3 is used as a bias current of the error amplifier. In the standby MODE, MODE1= H/MODE2= H, and only I3 is used as the bias current of the error amplifier. The number of I1/I2/I3 can be deleted or increased to adapt to different working modes, and the size of the I1/I2/I3 can be adjusted according to the working current of the digital circuit in different modes respectively. However, in this case, an additional external input pin is required to control the current of the error amplifier, and even when the digital circuit operates in a mode, the current becomes large, for example, the current varies from several mA to several tens of mA in the operation mode, and the circuit cannot be adjusted in real time according to the actual current variation of the digital circuit.

Based on this, a new solution is needed.

Disclosure of Invention

The invention aims to provide a low dropout regulator circuit with automatically adjustable static power consumption, aiming at the problem that the current of an error amplifier cannot be adjusted in real time according to the actual current change condition of a digital circuit because an additional external input pin is needed by the current of the low dropout regulator circuit.

According to an aspect of the present invention, a low dropout regulator circuit with automatically adjustable static power consumption is provided, which includes an LDO main circuit and an LDO output current detection circuit connected to the LDO main circuit, where the LDO main circuit includes an error amplifier and an output stage circuit, and the LDO output current detection circuit is configured to detect an output current of the LDO main circuit, and adjust a current of the error amplifier according to a change of the output current.

In the low dropout regulator circuit with automatically adjustable static power consumption, the output stage circuit comprises an output MOS tube M0, a resistor R1 and a capacitor CL, the grid electrode of the output MOS tube M0 is connected with the output end of the error amplifier and the LDO output current detection circuit, the source electrode of the output MOS tube M0 is connected with a voltage VDD, the drain electrode of the output MOS tube M0 is connected with the first end of the resistor R0 and the first end of the capacitor CL, the second end of the resistor R0 is connected with the first end of the resistor R1 and the forward input end of the error amplifier, the reverse input end of the error amplifier is connected with a voltage VREF, and the second end of the resistor R1 and the second end of the capacitor CL are grounded.

In the low dropout regulator circuit with automatically adjustable static power consumption, the LDO output current detection circuit comprises a plurality of current detection units which are connected in parallel.

In the low dropout regulator circuit with automatically adjustable static power consumption provided by the invention, each current detection unit comprises an output current detection MOS tube M1, an output current detection resistor R2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a level shifter and an inverter, wherein the grid electrode of the output current detection MOS tube M1 is connected with the output end of an error amplifier, the source electrode of the output current detection MOS tube M1 is connected with the source electrode of the output MOS tube M0, the drain electrode of the output current detection MOS tube M1 is grounded through the output current detection resistor R2, the grid electrode of the third MOS tube M3 is connected with the drain electrode of the output current detection MOS tube M1, a source electrode of the third MOS transistor M3 and a source electrode of the fourth MOS transistor M4 are connected to the first current source, a gate electrode of the fourth MOS transistor M4 is connected to the voltage VREF, a drain electrode of the third MOS transistor M3 is connected to a drain electrode of the fifth MOS transistor M5, a gate electrode of the fifth MOS transistor M5, a drain electrode of the seventh MOS transistor M7 and a gate electrode of the sixth MOS transistor M6, a drain electrode of the fourth MOS transistor M4 is connected to a drain electrode of the eighth MOS transistor M8, a gate electrode of the eighth MOS transistor M8, a drain electrode of the sixth MOS transistor M6, a gate electrode of the seventh MOS transistor M7 and an input end of the level shifter, a source electrode of the fifth MOS transistor M5, a source electrode of the sixth MOS transistor M6, a source electrode of the seventh MOS transistor M7 and a source electrode of the eighth MOS transistor M8 are grounded, an input end of the phase inverter is connected to an output end of the level shifter, and an output end of the phase inverter is connected to the error amplifier.

According to another aspect of the invention, a chip is further provided, which includes the low dropout regulator circuit with the automatically adjustable static power consumption as described above.

The low dropout regulator circuit with the automatically adjustable static power consumption has the following beneficial effects: the low dropout regulator circuit with automatically adjustable static power consumption, provided by the invention, comprises an LDO main circuit and an LDO output current detection circuit for detecting the output current of the LDO main circuit, wherein the LDO output current detection circuit is used for detecting the output current of the LDO, so that the input current of the LDO main circuit can be tracked in real time, and then the current of an error amplifier is adjusted, further, the gear of the detected current can be freely adjusted according to different modes of a digital circuit, and in the same mode, if the current changes greatly, the adjustment can be carried out; the magnitude of the LDO input current can be tracked in real time by detecting the magnitude of the LDO output current, and then the current of the error amplifier is adjusted; the gear of the detection current can be freely adjusted according to different modes of the digital circuit, and if the current change is large in the same mode, the adjustment can be carried out through adjusting the resistor; through setting up a plurality of output voltage detecting element, according to actual conditions, can increase the number of output voltage detecting element, the current of segmentation error amplifier reaches the purpose of accurate control electric current.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts:

FIG. 1 shows a conventional LDO structure in the prior art;

FIG. 2 shows an error amplifier structure of the LDO;

fig. 3 is a circuit diagram of a low dropout regulator circuit with automatically adjustable static power consumption according to an embodiment of the present invention.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully hereinafter with reference to the accompanying drawings. Exemplary embodiments of the invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

The general idea of the invention is as follows: aiming at the problem that the current of an error amplifier cannot be adjusted in real time according to the actual current change condition of a digital circuit because an additional external input pin is needed by the current of the current low dropout regulator circuit, the invention provides a structure for automatically adjusting the current of the error amplifier according to the LDO driving current, more current working gears can be added on the basis of the circuit without introducing additional control bits, and the working current of the error amplifier is accurately controlled according to the output current of the LDO, so that the aims of reducing power consumption, increasing stability and improving response speed are fulfilled.

In order to better understand the technical solutions, the technical solutions will be described in detail below with reference to the drawings and the specific embodiments of the specification, and it should be understood that the embodiments and specific features of the embodiments of the present invention are detailed descriptions of the technical solutions of the present application, and are not limited to the technical solutions of the present application, and the technical features of the embodiments and examples of the present invention may be combined with each other without conflict.

Fig. 3 is a circuit diagram of a low dropout regulator circuit with automatically adjustable static power consumption according to an embodiment of the present invention. As shown in fig. 3, the low dropout regulator circuit with automatically adjustable quiescent power consumption of the present invention includes an LDO main circuit 10 and an LDO output current detection circuit 20, wherein the LDO output current detection circuit 20 is electrically connected to the LDO main circuit 10 for detecting the output current of the LDO main circuit 10. The size of the output current of the LDO is detected by the LDO output current detection circuit, the size of the input current of the main circuit of the LDO can be tracked in real time, then the current of the error amplifier is adjusted, and further the gear of the detection current can be freely adjusted according to different modes of the digital circuit, and under the same mode, if the current changes greatly, the adjustment can be carried out.

Further, the LDO output current detection circuit 20 includes a plurality of current detection units (two current detection units are included in the embodiment shown in fig. 3) connected in parallel, each current detection unit can independently detect the magnitude of the output current of the LDO main circuit, and generate a control signal for controlling the current of the error amplifier according to the change of the output current of the LDO main circuit, so that the number of current detection units can be increased to increase the control gear according to the actual situation, and the current of the error amplifier can be subdivided, thereby achieving the purpose of accurately controlling the current.

Further, in an embodiment of the invention, the LDO main circuit 10 includes an error amplifier AMP, an output MOS transistor M0, a resistor R1, and a capacitor CL. The grid electrode of the output MOS tube M0 is connected to the output end of the error amplifier and the LDO output current detection circuit, the source electrode of the output MOS tube M0 is connected with the voltage VDD, the drain electrode of the output MOS tube M0 is connected with the first end of the resistor R0 and the first end of the capacitor CL, the second end of the resistor R0 is connected with the first end of the resistor R1 and the forward input end of the error amplifier, the reverse input end of the error amplifier is connected with the voltage VREF, and the second end of the resistor R1 and the second end of the capacitor CL are grounded.

Further, in an embodiment of the present invention, each current detecting unit includes an output current detecting MOS transistor M1, an output current detecting resistor R2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a level shifter and a phase inverter, a gate of the output current detecting MOS transistor M1 is connected to the output terminal of the error amplifier, a source of the output current detecting MOS transistor M1 is connected to the source of the output MOS transistor M0, a drain of the output current detecting MOS transistor M1 is grounded via the output current detecting resistor R2, a gate of the third MOS transistor M3 is connected to the drain of the output current detecting MOS transistor M1, a source of the third MOS transistor M3 and a source of the fourth MOS transistor M4 are connected to a first current source, a gate of the fourth MOS transistor M4 is connected to a voltage VREF, a drain of the third MOS transistor M3 is connected to a drain of the fifth MOS transistor M5, a gate of the fifth MOS transistor M5, a source of the seventh MOS transistor M7, a source of the sixth MOS transistor M6, a drain of the eighth MOS transistor M8 is connected to the gate of the output terminal of the error amplifier, a level shifter, a drain of the eighth MOS transistor M8 and a level shifter, a gate of the eighth MOS transistor M8.

Specifically, as shown in fig. 3, the LDO output current detection circuit includes two current detection units connected in parallel for explanation. As shown in fig. 3, the first current detection unit includes an output current detection MOS transistor M1, an output current detection resistor R2, an MOS transistor M3, an MOS transistor M4, an MOS transistor M5, an MOS transistor M6, an MOS transistor M7, an MOS transistor M8, a first level shifter, and a first inverter; the second current detection unit comprises an output current detection MOS tube M2, an output current detection resistor R3, an MOS tube M9, an MOS tube M10, an MOS tube M11, an MOS tube M12, an MOS tube M13, an MOS tube M14, a second level shifter and a second phase inverter.

Further, as shown in fig. 3, in the first current detection unit, the gate of the output current detection MOS transistor M1 is connected to the output terminal of the error amplifier, the source of the output current detection MOS transistor M1 is connected to the source of the output MOS transistor M0, the drain of the output current detection MOS transistor M1 is grounded via the output current detection resistor R2, the gate of the MOS transistor M3 is connected to the drain of the output current detection MOS transistor M1, the source of the MOS transistor M3 and the source of the MOS transistor M4 are connected to the first current source, the gate of the MOS transistor M4 is connected to the voltage VREF, the drain of the MOS transistor M3 is connected to the drain of the MOS transistor M5, the gate of the MOS transistor M5, the drain of the MOS transistor M7 and the gate of the MOS transistor M6, the drain of the MOS transistor M4 is connected to the drain of the MOS transistor M8, the gate of the MOS transistor M8, the drain of the MOS transistor M6, the gate of the MOS transistor M7 and the input terminal of the first level shifter, the source of the MOS transistor M5, the source of the MOS transistor M7 and the source of the first level shifter are connected to the output terminal of the first level shifter, and the first level shifter are connected to the output terminal of the error amplifier. Therefore, the first current detection unit can independently detect the magnitude of the output current of the LDO main circuit, and generate the control signal MODE1 for controlling the current of the error amplifier according to the change of the output current of the LDO main circuit.

Further, as shown in fig. 3, in the second current detection unit, the gate of the output current detection MOS transistor M2 is connected to the output terminal of the error amplifier, the source of the output current detection MOS transistor M2 is connected to the source of the output MOS transistor M0, the drain of the output current detection MOS transistor M2 is grounded via the output current detection resistor R3, the gate of the MOS transistor M9 is connected to the drain of the output current detection MOS transistor M2, the source of the MOS transistor M9 and the source of the MOS transistor M10 are connected to the second current source, the gate of the MOS transistor M10 is connected to the voltage VREF, the drain of the MOS transistor M9 is connected to the drain of the MOS transistor M11, the gate of the MOS transistor M11, the drain of the MOS transistor M13 and the gate of the MOS transistor M12, the drain of the MOS transistor M10 is connected to the drain of the MOS transistor M14, the gate of the MOS transistor M14, the drain of the MOS transistor M12, the gate of the MOS transistor M13 and the input terminal of the second level shifter, the source of the MOS transistor M11, the source of the MOS transistor M12, the source of the MOS transistor M13 and the source of the second level shifter are connected to the second output terminal of the second level shifter, and the second level shifter is connected to the output terminal of the error amplifier. Therefore, the second current detection unit can independently detect the magnitude of the output current of the LDO main circuit, and generate the control signal MODE2 for controlling the current of the error amplifier according to the change of the output current of the LDO main circuit.

In the embodiment shown in fig. 3, M0 is an output tube of the main LDO circuit, M1 and M2 are LDO output current detection MOS tubes, the width-to-length ratio W/L of the LDO output current detection MOS tube may be 1/100, even 1/200, the consumed current of the LDO output current detection MOS tube is almost negligible compared with the current of the main LDO circuit itself, and the selection of the specific width-to-length ratio may be adjusted according to practical applications. Taking 1/100 as an example, taking R3> R2, idrv as LDO output current, current flowing through M1/M2 as Idrv/100, M3 gate voltage as Idrv/100 × R2, when Idrv current is small, idrv/100 × R2 is restricted to Idrv/100 × R3 and is not in vref, current of current source I1 flows through M3, no current flows in M4, current of current source I2 flows through M9, no current flows in M10, MODE1= H, MODE2= H, and the error amplifier operates at minimum current. As the LDO output current becomes larger, idrv/100 × r2<vref </100 × r3, I2 all flow through M10, M9 has no current flow, and then MODE1= H, MODE2= L, and the error amplifier current is increased by one step. As Idrv continues to increase, VREF < Idrv/100 + r2 and Idrv/100 + r3, mode1= l, mode2= l, the error amplifier current comes to a maximum. The value of R2/R3 can be adjusted according to the size of Idrv and VREF to obtain the required gear of corresponding Idrv. Meanwhile, the detection current can be increased by the number of paths to achieve more accurate control.

In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be construed to reflect the intent: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

Moreover, those of skill in the art will appreciate that while some embodiments herein include some features included in other embodiments, not others, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

Claims

1. The low dropout regulator circuit with the automatically adjustable static power consumption is characterized by comprising an LDO main circuit and an LDO output current detection circuit connected to the LDO main circuit, wherein the LDO main circuit comprises an error amplifier and an output stage circuit, and the LDO output current detection circuit is used for detecting the output current of the LDO main circuit and adjusting the current of the error amplifier according to the change of the output current.

2. The low dropout regulator circuit of claim 1, wherein the output stage circuit comprises an output MOS transistor M0, a resistor R1, and a capacitor CL, a gate of the output MOS transistor M0 is connected to the output terminal of the error amplifier and the LDO output current detection circuit, a source of the output MOS transistor M0 is connected to the voltage VDD, a drain of the output MOS transistor M0 is connected to the first terminal of the resistor R0 and the first terminal of the capacitor CL, a second terminal of the resistor R0 is connected to the first terminal of the resistor R1 and the forward input terminal of the error amplifier, a reverse input terminal of the error amplifier is connected to the voltage VREF, and a second terminal of the resistor R1 and the second terminal of the capacitor CL are grounded.

3. The low dropout regulator circuit of claim 2 wherein the LDO output current detection circuit comprises a plurality of current detection units connected in parallel.

4. The low dropout regulator circuit with automatically adjustable static power consumption according to claim 3, wherein each current detection unit comprises an output current detection MOS transistor M1, an output current detection resistor R2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a level shifter and an inverter, wherein the gate of the output current detection MOS transistor M1 is connected to the output terminal of the error amplifier, the source of the output current detection MOS transistor M1 is connected to the source of the output MOS transistor M0, the drain of the output current detection MOS transistor M1 is grounded via the output current detection resistor R2, the gate of the third MOS transistor M3 is connected to the drain of the output current detection MOS transistor M1, the source of the third MOS transistor M3 and the source of the fourth MOS transistor M4 are connected to a first current source, the gate of the fourth MOS transistor M4 is connected to a voltage VREF, the drain of the third MOS transistor M3 is connected to the drain of the fifth MOS transistor M5, the gate of the fifth MOS transistor M5, the drain of the seventh MOS transistor M7 and the gate of the sixth MOS transistor M6, the drain of the fourth MOS transistor M4 is connected to the drain of the eighth MOS transistor M8, the gate of the eighth MOS transistor M8, the drain of the sixth MOS transistor M6, the gate of the seventh MOS transistor M7 and the input of the level shifter, the source of the fifth MOS transistor M5, the source of the sixth MOS transistor M6, the source of the seventh MOS transistor M7 and the source of the eighth MOS transistor M8 are grounded, the input of the phase inverter is connected to the output of the level shifter, and the output of the phase inverter is connected to an error amplifier.

5. A chip, characterized by comprising the low dropout linear regulator circuit with automatically adjustable static power consumption as claimed in any one of claims 1 to 4.