CN115278910A

CN115278910A - Method and device used in node of wireless communication

Info

Publication number: CN115278910A
Application number: CN202110500364.6A
Authority: CN
Inventors: 胡杨; 张晓博
Original assignee: Shanghai Langbo Communication Technology Co Ltd
Current assignee: Shanghai Langbo Communication Technology Co Ltd
Priority date: 2021-04-30
Filing date: 2021-05-08
Publication date: 2022-11-01

Abstract

A method and apparatus in a node used for wireless communication is disclosed. A first receiver to receive a first information block, the first information block being used to determine a first pool of empty resources; a first transmitter to transmit a first signal, the first signal being used to carry a first bit block, the first bit block comprising at least one control information bit; the air interface resource occupied by the first signal belongs to the first air interface resource pool, and the number of the physical resource blocks occupied by the first signal in the frequency domain is equal to a first number; the number of bits comprised by the first block of bits is used to determine the first number; the second bit block comprises at least one control information bit; a second number is related to the second block of bits, the second number being used to determine a starting physical resource block occupied by the first signal in the frequency domain.

Description

Method and apparatus in a node used for wireless communication

Technical Field

The present application relates to a transmission method and apparatus in a wireless communication system, and more particularly, to a transmission method and apparatus for a wireless signal in a wireless communication system supporting a cellular network.

Background

In a 3GPP (3 rd Generation Partner Project) NR (New Radio, new air interface) system, in order to support URLLC (Ultra Reliable and Low Latency Communication) service with higher requirements (e.g., higher reliability, lower Latency, etc.), the NR Release 16 version protocol has supported various enhancements for uplink transmission.

Work Item (WI) continues to be enhanced for URLLC over the 3GPP RAN congress by NR Release 17. Among them, multiplexing (Multiplexing) of different services in a UE (User Equipment) (Intra-UE) is a major point to be researched.

Disclosure of Invention

In the above background, how to handle multiplexing of UCI (Uplink Control Information) with different priorities is a key issue that must be solved.

In view of the above, the present application discloses a solution. In the above description, UCI reporting in an UpLink (UpLink) is taken as an example; the present application is also applicable to other scenarios, such as Downlink (Downlink) or SideLink (SL), etc., and achieves similar technical effects. Furthermore, the adoption of a unified solution for different scenarios (including but not limited to uplink, downlink, sidelink) also helps to reduce hardware complexity and cost. It should be noted that, in case of no conflict, the embodiments and features of the embodiments in the user equipment of the present application may be applied to the base station, and vice versa. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

As an example, the term (telematics) in the present application is explained with reference to the definition of the specification protocol TS36 series of 3 GPP.

As an example, the terms in this application are explained with reference to the definitions of the 3GPP specification protocol TS38 series.

As an example, the terms in the present application are explained with reference to the definitions of the 3GPP specification protocol TS37 series.

As an example, the terms in this application are explained with reference to the definition of the specification protocol of IEEE (Institute of electrical and electronics Engineers).

The application discloses a method in a first node used for wireless communication, characterized by comprising:

receiving a first information block, the first information block being used to determine a first pool of empty resources;

transmitting a first signal, the first signal being used to carry a first block of bits, the first block of bits including at least one control information bit;

the air interface resources occupied by the first signal belong to the first air interface resource pool, the number of the physical resource blocks occupied by the first signal in the frequency domain is equal to a first number, and the first number is not greater than the number of the physical resource blocks included by the first air interface resource pool in the frequency domain; the number of bits comprised by the first block of bits is used to determine the first number, the first number being a positive integer; the second bit block comprises at least one control information bit, and the category of the control information bit contained in the first bit block is different from that of the control information bit contained in the second bit block; a second number is related to the second block of bits, the second number being used to determine a starting physical resource block occupied by the first signal in the frequency domain, the second number being a non-negative integer.

As an embodiment, the problem to be solved by the present application includes: the problem of how to determine the initial physical resource block occupied by the first signal in the frequency domain.

As an embodiment, the problem to be solved by the present application includes: the problem of how to determine the starting physical resource block occupied by the first signal in the frequency domain in one PUCCH, based on the second number related to the second bit block.

As an embodiment, the problem to be solved by the present application includes: the problem of how to determine the starting physical resource block occupied by one PUCCH in the frequency domain based on the second number related to the second bit block.

As an embodiment, the problem to be solved by the present application includes: the problem of how to determine the total number of physical resource blocks in one PUCCH resource for carrying UCI of different priorities.

As an example, the benefits of the above method include: the transmission performance of high-priority (such as URLLC) UCI can be guaranteed.

As an example, the benefits of the above method include: the method is favorable for multiplexing the UCIs corresponding to different priority indexes on the same PUCCH in a mode of respectively coding.

As an embodiment, the benefits of the above method include: the method is favorable for reducing the influence of multiplexing of the low-priority UCI on the high-priority UCI.

As an example, the benefits of the above method include: the problem that the understanding of the PUCCH resources by the two communication parties is inconsistent is relieved.

As an embodiment, the benefits of the above method include: the blind detection performance aiming at the PUCCH is improved.

According to one aspect of the application, the above method is characterized in that,

the second number is equal to the number of bits carried by the first signal and related to the second bit block, or the second number is equal to the number of bits included in one bit block generated by the second bit block.

According to one aspect of the application, the method described above is characterized in that,

the second number belongs to one of a plurality of numerical intervals, any one of the plurality of numerical intervals including at least one non-negative integer; the plurality of numerical intervals comprise a first numerical interval and a second numerical interval; any two value intervals in the plurality of value intervals are orthogonal to each other; when the second number belongs to the first numerical interval, the index of the initial physical resource block occupied by the first signal in the frequency domain is a first physical resource block index; when the second number belongs to the second numerical interval, the index of the initial physical resource block occupied by the first signal in the frequency domain is equal to the index of the first physical resource block plus a first offset; the plurality of value intervals are predefined or configurable, the first physical resource block index is predefined or configurable, and the first offset is predefined or configurable.

As an embodiment, the characteristics of the above method include: and determining the index of the initial physical resource block occupied by the first signal in the frequency domain according to the numerical value interval to which the second quantity belongs.

at least the former of both the first bit block and the second bit block is used to generate a first output bit sequence comprising a positive integer number of bits greater than 1; the number of bits comprised by the first output bit sequence and the first number are linearly related, the first output bit sequence being used for generating the first signal.

the number of bits comprised by the first bit block and a first parameter value are jointly used for determining the first number; the first parameter value is a predefined or configurable non-negative number or the first parameter value is related to the second block of bits.

As an embodiment, the characteristics of the above method include: limiting the number of bits carried in the first signal that relate to the second block of bits to a fixed value or to one of a plurality of predefined or configurable values.

As an example, the benefits of the above method include: the influence of the multiplexing of the priority UCI on the transmission performance of the high-priority UCI is reduced.

the priority index of the control information bits included in the first bit block is equal to a first index, the priority index of the control information bits included in the second bit block is equal to a second index, the first index is a non-negative integer, and the second index is a non-negative integer; the first index and the second index are not equal; the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block is greater than 2.

a size relationship between a number of bits comprised by the second block of bits and a first threshold is used to determine a manner in which the second block of bits is used to generate the first sequence of output bits, the first threshold being a non-negative integer; the first threshold is predefined, or the first threshold is configurable, or the first threshold is related to a first parameter value.

As an embodiment, the characteristics of the above method include: when the number of bits comprised by the second block of bits is greater than the first threshold, the first sequence of output bits carries only partial information indicated by the second block of bits; when the number of bits comprised by the second block of bits is not greater than the first threshold, the first sequence of output bits carries all information indicated by the second block of bits.

As an example, the benefits of the above method include: the method is favorable for optimizing the reporting performance of the low-priority UCI on the premise of ensuring the transmission performance of the high-priority UCI.

The application discloses a method in a second node used for wireless communication, which is characterized by comprising the following steps:

transmitting a first information block, the first information block being used to determine a first pool of empty resources;

receiving a first signal, the first signal being used to carry a first block of bits, the first block of bits including at least one control information bit;

the air interface resources occupied by the first signal belong to the first air interface resource pool, the number of physical resource blocks occupied by the first signal in the frequency domain is equal to a first number, and the first number is not greater than the number of physical resource blocks included by the first air interface resource pool in the frequency domain; the number of bits comprised by the first block of bits is used to determine the first number, the first number being a positive integer; the second bit block comprises at least one control information bit, and the category of the control information bit contained in the first bit block is different from that of the control information bit contained in the second bit block; a second number is related to the second block of bits, the second number being used to determine a starting physical resource block occupied by the first signal in the frequency domain, the second number being a non-negative integer.

the second number belongs to one of a plurality of numerical intervals, any one of the plurality of numerical intervals including at least one non-negative integer; the plurality of value intervals comprise a first value interval and a second value interval; any two value intervals in the plurality of value intervals are orthogonal to each other; when the second number belongs to the first value interval, the index of the initial physical resource block occupied by the first signal in the frequency domain is a first physical resource block index; when the second number belongs to the second numerical interval, the index of the initial physical resource block occupied by the first signal in the frequency domain is equal to the index of the first physical resource block plus a first offset; the plurality of value intervals are predefined or configurable, the first physical resource block index is predefined or configurable, and the first offset is predefined or configurable.

the number of bits comprised by the first block of bits and a first parameter value are used together to determine the first number; the first parameter value is a predefined or configurable non-negative number or the first parameter value is related to the second block of bits.

The application discloses a first node device used for wireless communication, characterized by comprising:

a first receiver to receive a first information block, the first information block being used to determine a first pool of empty resources;

a first transmitter to transmit a first signal, the first signal being used to carry a first block of bits, the first block of bits including at least one control information bit;

The present application discloses a second node device used for wireless communication, comprising:

a second transmitter to transmit a first information block, the first information block being used to determine a first pool of empty resources;

a second receiver to receive a first signal, the first signal being used to carry a first block of bits, the first block of bits including at least one control information bit;

As an example, the method in the present application has the following advantages:

-to facilitate ensuring transmission performance (e.g., reliability) for high priority (e.g., URLLC) UCI;

-facilitating multiplexing UCI corresponding to different priority indices onto the same PUCCH in a separately coded manner;

-facilitating a reduction of the impact of multiplexing of low priority UCI on high priority UCI;

the problem of inconsistent understanding of the PUCCH resources by both communication parties, which may occur, is alleviated;

-to facilitate optimizing reporting performance of low priority (e.g., eMBB) UCI while guaranteeing high priority UCI transmission performance;

advantageously improving the performance of blind detection performed by the receiving end.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of the non-limiting embodiments with reference to the following drawings in which:

FIG. 1 illustrates a process flow diagram of a first node according to one embodiment of the present application;

FIG. 2 shows a schematic diagram of a network architecture according to an embodiment of the present application;

figure 3 shows a schematic diagram of a radio protocol architecture of a user plane and a control plane according to an embodiment of the present application;

FIG. 4 shows a schematic diagram of a first communication device and a second communication device according to an embodiment of the present application;

FIG. 5 shows a signal transmission flow diagram according to an embodiment of the present application;

fig. 6 shows an illustrative diagram where a second quantity is used to determine a starting physical resource block occupied by the first signal in the frequency domain in accordance with one embodiment of the present application;

fig. 7 shows a schematic diagram of a relationship between at least the former of both the first bit block and the second bit block, the first output bit sequence, the first number and the first signal according to an embodiment of the application;

FIG. 8 is a diagram illustrating a relationship between a number of bits included in a first block of bits, a first amount of computation, and a first number according to one embodiment of the application;

FIG. 9 shows a schematic diagram of a relationship between a first parameter value, a given parameter value, X1 candidate parameter values, and a block of bits carried by a first signal according to an embodiment of the application;

fig. 10 is a diagram illustrating a relationship between a priority index of control information bits included in a first bit block, the first index, a priority index of control information bits included in a second bit block, and the second index according to an embodiment of the present application;

FIG. 11 shows a schematic diagram of the relationship between the number of bits comprised by the second block of bits and the magnitude of the first threshold, and the manner in which the second block of bits is used to generate the first sequence of output bits, according to an embodiment of the present application;

figure 12 shows a schematic diagram of the relationship between the first node/first receiver and the first signaling according to an embodiment of the application;

FIG. 13 shows a block diagram of a processing arrangement in a first node device according to an embodiment of the present application;

fig. 14 shows a block diagram of a processing apparatus in a second node device according to an embodiment of the present application.

Detailed Description

The technical solutions of the present application will be further described in detail with reference to the accompanying drawings, and it should be noted that the embodiments and features of the embodiments of the present application can be arbitrarily combined with each other without conflict.

Example 1

Embodiment 1 illustrates a processing flow diagram of a first node according to an embodiment of the present application, as shown in fig. 1.

In embodiment 1, the first node in the present application receives a first information block in step 101; a first signal is transmitted in step 102.

In embodiment 1, the first information block is used to determine a first pool of empty resources; the first signal is used to carry a first block of bits, the first block of bits comprising at least one control information bit; the empty resource occupied by the first signal belongs to the first empty resource pool, the number of the physical resource blocks occupied by the first signal in the frequency domain is equal to a first number, and the first number is not greater than the number of the physical resource blocks included by the first empty resource pool in the frequency domain; the number of bits comprised by the first block of bits is used to determine the first number, the first number being a positive integer; the second bit block comprises at least one control information bit, and the category of the control information bit contained in the first bit block is different from that of the control information bit contained in the second bit block; a second number is related to the second block of bits, the second number being used to determine a starting physical resource block occupied by the first signal in the frequency domain, the second number being a non-negative integer.

As an embodiment, the first signal in this application comprises a wireless signal.

As an example, the first signal in this application includes a radio frequency signal.

As an embodiment, the first signal in this application includes a baseband signal.

As an embodiment, the meaning that the sentence the first signal is used to carry a first bit block comprises: the first signal includes an output of all or a part of bits in the first bit block (or a bit block generated by the first bit block) after CRC addition, segmentation, coding block level CRC addition, channel coding, rate matching, concatenation, scrambling (Scrambling), modulation (Modulation), layer Mapping (Layer Mapping), precoding (Precoding), mapping to Resource elements (Mapping to Resource elements), multi-carrier symbol Generation (Generation), and Modulation up-conversion (Modulation and up-conversion) in sequence.

As an embodiment, the meaning that the sentence the first signal is used to carry a first bit block comprises: the first signal is a signal carrying the first block of bits (or a block of bits generated by the first block of bits).

As an embodiment, in the present application, the meaning that the first signal carries the second bit block includes: the first signal comprises all or part of the bits in the second bit block (or a bit block generated by the second bit block) and is output after CRC addition, segmentation, coding block level CRC addition, channel coding, rate matching, concatenation, scrambling, modulation, layer mapping, precoding, mapping to resource elements, multi-carrier symbol generation and part or all of modulation up-conversion.

As an embodiment, in the present application, the meaning that the first signal carries the second bit block includes: the first signal is a signal carrying the second block of bits (or a block of bits generated by the second block of bits).

As an embodiment, in the present application, the meaning of the first signal carrying one bit block generated by the second bit block includes: the first signal comprises an output of all or part of bits in the one bit block generated by the second bit block after CRC addition, segmentation, coding block level CRC addition, channel coding, rate matching, concatenation, scrambling, modulation, layer mapping, precoding, mapping to resource elements, multi-carrier symbol generation, and modulation up-conversion in sequence.

As an embodiment, in the present application, the meaning of the first signal carrying one bit block generated by the second bit block includes: the first signal is a signal carrying the one bit block generated by the second bit block.

As an embodiment, one of the air interface Resource pools in the present application includes at least one RE (Resource Element) in a time-frequency domain.

As an embodiment, one RE occupies one multicarrier symbol in the time domain and one subcarrier in the frequency domain.

As an embodiment, the multi-carrier Symbol in this application is an OFDM (Orthogonal Frequency Division Multiplexing) Symbol (Symbol).

As an embodiment, the multi-Carrier symbol in this application is an SC-FDMA (Single Carrier-frequency division multiple Access) symbol.

As an embodiment, the multicarrier symbol in this application is a DFT-S-OFDM (Discrete Fourier Transform Spread OFDM) symbol.

As an embodiment, the multi-Carrier symbol in the present application is an FBMC (Filter bank multi Carrier) symbol.

As an embodiment, the multicarrier symbol in this application includes CP (Cyclic Prefix).

As an embodiment, one of the air interface resource pools in this application includes a positive integer number of subcarriers (subcarriers) in a frequency domain.

As an embodiment, one of the air interface Resource pools in this application includes a positive integer number of PRBs (Physical Resource blocks) in a frequency domain.

As an embodiment, one of the air interface resource pools in this application includes a positive integer number of RBs (resource blocks) in a frequency domain.

As an embodiment, one of the air interface resource pools in the present application includes a positive integer number of multicarrier symbols in a time domain.

As an embodiment, one of the air interface resource pools in the present application includes a positive integer number of slots (slots) in a time domain.

As an embodiment, one of the air interface resource pools in the present application includes a positive integer number of sub-slots (sub-slots) in a time domain.

As an embodiment, in a time domain, one of the air interface resource pools in this application includes a positive integer of milliseconds (ms).

As an embodiment, one of the air interface resource pools in the present application includes a positive integer number of consecutive multicarrier symbols in a time domain.

As an embodiment, in a time domain, one of the air interface resource pools in the present application includes a positive integer of discontinuous time slots.

As an embodiment, one of the air interface resource pools in the present application includes a positive integer of consecutive time slots in a time domain.

As an embodiment, one of the air interface resource pools in the present application includes a positive integer number of subframes (sub-frames) in a time domain.

As an embodiment, one of the air interface resource pools in the present application is indicated by physical layer signaling or configured by higher layer signaling.

As an embodiment, one of the air interface Resource pools in the present application is indicated by DCI, or configured by an RRC (Radio Resource Control) signaling, or configured by a MAC CE (media access Control layer Control Element) signaling.

As an embodiment, one of the air interface resource pools in this application is reserved for an uplink physical layer channel.

As an embodiment, one of the air interface resource pools in the present application includes an air interface resource occupied by an uplink physical layer channel.

As an embodiment, one of the Uplink Physical layer channels in this application is a PUCCH (Physical Uplink Control CHannel) or a PUSCH (Physical Uplink Shared CHannel).

As an embodiment, one of the air interface resource pools in the present application is a PUCCH resource (PUCCH resource).

As an embodiment, one of the air interface resource pools in the present application is at least a part of one PUCCH resource.

As an embodiment, the first pool of empty resources in this application is a PUCCH resource.

As an embodiment, the first pool of empty resources in this application is a part of one PUCCH resource.

As one embodiment, the first information block includes RRC signaling.

As an embodiment, the first information block includes one IE.

As an embodiment, the first information block is an IE.

As an embodiment, the first information block includes one or more fields in one IE.

As one embodiment, the first information block includes MAC CE signaling.

As an embodiment, the first information block comprises higher layer signaling.

As an embodiment, the first information block is PUCCH-config.

As one embodiment, the first information block is a PUCCH-configurable list.

As an embodiment, the first information block is BWP-decoded.

In one embodiment, the first information block is sps-PUCCH-AN.

As AN embodiment, the first information block is sps-PUCCH-AN-resource id.

As an embodiment, the name of the first information block comprises PUCCH.

As an embodiment, the name of the first information block includes PUCCH-config.

As an embodiment, the first information block indicates the first pool of empty resources.

As one embodiment, the first information block explicitly indicates the first pool of empty resources.

As one embodiment, the first information block implicitly indicates the first pool of empty resources.

As an embodiment, the first air interface resource pool is one air interface resource pool in a set of air interface resource pools indicated by the first information block.

As an embodiment, the first signal is a signal transmitted on one PUCCH.

As an embodiment, the first signal is a PUCCH.

In one embodiment, the first signal comprises signals in one or more of a plurality of hop-intervals for one PUCCH transmission.

As an embodiment, the first bit block includes at least one HARQ-ACK (Hybrid Automatic Repeat reQuest ACKnowledgement) information bit.

As an embodiment, the second bit block comprises at least one HARQ-ACK information bit.

As an embodiment, the first bit block comprises only HARQ-ACK information bits.

As an embodiment, the second bit block comprises only HARQ-ACK information bits.

As an embodiment, the first bit block further comprises control information bits other than HARQ-ACK bits.

As an embodiment, the second bit block further comprises control information bits other than HARQ-ACK bits.

As an embodiment, the first block of bits does not include CRC (Cyclic Redundancy Check) bits.

As an embodiment, the first bit block comprises at least one CRC bit.

As an embodiment, the second block of bits does not comprise CRC bits.

As an embodiment, the second bit block comprises at least one CRC bit.

As an embodiment, one of the control information bits is one UCI bit.

As an embodiment, one of the control information bits is one HARQ _ ACK information bit.

As an embodiment, one of the control information bits is one HARQ _ ACK information bit or SR bit.

As an embodiment, one of the control information bits is one HARQ _ ACK information bit or SR bit or an indication bit of CSI report.

As an embodiment, one of the control information bits is one bit carrying control information of higher layer signaling.

As an embodiment, one of the control information bits is one SCI bit.

In one embodiment, the first pool of empty resources includes one PUCCH resource.

As an embodiment, the first pool of empty resources is one PUCCH resource.

As an embodiment, the first air interface resource pool includes an air interface resource occupied by one of multiple frequency hopping intervals used for PUCCH transmission in one PUCCH resource.

As an embodiment, the meaning that the categories of the control information bits included in the first bit block and the control information bits included in the second bit block in the sentence are different includes: the control information bits included in the first bit block and the control information bits included in the second bit block are for different traffic types, respectively.

As an embodiment, the meaning that the categories of the control information bits included in the first bit block and the control information bits included in the second bit block are different in the sentence includes: the control information bits included in the first bit block and the control information bits included in the second bit block are control information bits for different transmission modes (e.g., broadcast, multicast, or unicast), respectively.

As an embodiment, the meaning that the categories of the control information bits included in the first bit block and the control information bits included in the second bit block are different in the sentence includes: the control information bits included in the first bit block and the control information bits included in the second bit block are used to indicate control information on different links, respectively.

As an embodiment, the meaning that the categories of the control information bits included in the first bit block and the control information bits included in the second bit block are different in the sentence includes: the control information bits included in the first bit block and the control information bits included in the second bit block are control information bits of different priorities, respectively.

As an embodiment, the meaning that the categories of the control information bits included in the first bit block and the control information bits included in the second bit block are different in the sentence includes: the control information bits included in the first bit block and the control information bits included in the second bit block correspond to a priority index 0 and a priority index 1, respectively.

As an embodiment, the meaning that the categories of the control information bits included in the first bit block and the control information bits included in the second bit block in the sentence are different includes: the control information bits included in the first bit block and the control information bits included in the second bit block correspond to a priority index 1 and a priority index 0, respectively.

As an embodiment, the number of physical resource blocks included in the frequency domain by the first air interface resource pool is the number of physical resource blocks included in the frequency domain by the first air interface resource pool in one multicarrier symbol.

As an embodiment, the number of physical resource blocks included in the frequency domain by the first air interface resource pool is the number of physical resource blocks included in the frequency domain by the first air interface resource pool in one frequency hopping interval.

As an embodiment, the first empty resource pool is a PUCCH resource using PUCCH format 2.

As an embodiment, the first pool of empty resources is a PUCCH resource using PUCCH format 3.

As an embodiment, the first pool of empty resources is a PUCCH resource using PUCCH format 4.

As an embodiment, the number of bits comprised by the first bit block and the number of bits comprised by the second bit block or a bit block generated by the second bit block are together used to determine the first number.

As an embodiment, the number of bits comprised by the first block of bits, together with the number of bits carried by the first signal relating to the second block of bits, is used to determine the first number.

As an embodiment, the number of the bits comprised by the first bit block, the first parameter value in this application and the first code rate in this application together indicate the first number.

As an embodiment, the number of bits comprised by the first bit block together with the sum of the first parameter value in this application and the first code rate in this application is used for determining the first number.

As an embodiment, the number of bits comprised by the first bit block together with the first parameter value in this application is used to determine a first amount of computation, and a third number is used to determine a second amount of computation; the third number is equal to the number of physical resource blocks included in the frequency domain of the first air interface resource pool, or the third number is determined by the first information block; when the first calculated amount is greater than the second calculated amount, the first number is equal to the third number; when the first calculated amount is not greater than the second calculated amount: the first number is related to the first calculated amount.

As an embodiment, the number of bits comprised by the first bit block together with the first parameter value in this application is used to determine a first calculation amount, and a third number is used to determine a second calculation amount; the third number is equal to the number of physical resource blocks included in the frequency domain of the first air interface resource pool, or the third number is determined by the first information block; when the first calculated amount is not greater than the second calculated amount, the first number is equal to the third number; when the first calculated amount is greater than the second calculated amount: the first number is related to the first calculated amount.

As an embodiment, the number of bits comprised by the first bit block together with the first parameter value in this application is used to determine a first amount of computation, and a third number is used to determine a second amount of computation; the third number is equal to the number of physical resource blocks included in the frequency domain of the first air interface resource pool, or the third number is determined by the first information block; when the first calculation amount is smaller than the second calculation amount, the first number is equal to the third number; when the first calculation amount is not less than the second calculation amount: the first number is related to the first calculated amount.

As an embodiment, the number of bits comprised by the first bit block together with the first parameter value in this application is used to determine a first calculation amount, and a third number is used to determine a second calculation amount; the third number is equal to the number of physical resource blocks included in the frequency domain of the first air interface resource pool, or the third number is determined by the first information block; when the first calculation amount is not less than the second calculation amount, the first number is equal to the third number; when the first calculated amount is less than the second calculated amount: the first number is related to the first calculated amount.

As an embodiment, the second block of bits is used to determine the second number.

As an embodiment, the second number is equal to a number of control information bits comprised by the second bit block.

As an embodiment, the first information block indicates whether multiplexing between UCI of different priorities is performed.

As an embodiment, one RRC signaling or one MAC CE signaling indicates whether multiplexing between UCI of different priorities is performed.

As an embodiment, the first information block indicates whether the first signal carries the second bit block.

As an embodiment, the first information block indicates whether the first signal carries the second bit block or a bit block generated by the second bit block.

As an embodiment, one DCI or one RRC signaling or one MAC CE signaling received by the first node indicates whether the first signal carries the second bit block.

As an embodiment, a DCI or an RRC signaling or a MAC CE signaling received by the first node indicates whether the first signal carries the second bit block or a bit block generated by the second bit block.

As an embodiment, the first node determines whether the first signal carries the second bit block according to a received indication.

As an embodiment, the first node determines, according to the received indication, whether the first signal carries the second bit block or a bit block generated by the second bit block.

As an embodiment, the first signal carries the second block of bits.

As an embodiment, the first signal carries the second bit block or a bit block generated by the second bit block.

As an embodiment, the second number is equal to a number of bits carried by the first signal relating to the second block of bits.

As a sub-embodiment of the above embodiment, when the first signal carries the second bit block or a bit block generated by the second bit block, the number of bits carried by the first signal related to the second bit block is: the second bit block or a number of bits included in one bit block generated by the second bit block when CRC addition is to be performed.

As a sub-embodiment of the above embodiment, when the first signal carries the second bit block or a bit block generated by the second bit block, the number of bits carried by the first signal related to the second bit block is: the second bit block or a number of bits comprised by a bit block generated by the second bit block when channel coding is to be performed.

As a sub-embodiment of the above embodiment, the number of the bits carried by the first signal relating to the second block of bits is equal to 0 or greater than 0.

As a sub-implementation of the above embodiment, when the first signal does not carry the second block of bits nor the block of bits generated by the second block of bits, the number of bits carried by the first signal relating to the second block of bits is equal to 0.

As a sub-embodiment of the above embodiment, when the first signal carries the second bit block or a bit block generated by the second bit block, the number of bits carried by the first signal related to the second bit block is greater than 0.

As a sub-embodiment of the foregoing embodiment, when the first signal carries the second bit block or one bit block generated by the second bit block, the number of bits carried by the first signal related to the second bit block is equal to the number of bits included in the second bit block or the number of bits included in the one bit block generated by the second bit block.

As an embodiment, the second number is equal to a number of bits comprised by the second block of bits.

As an embodiment, the second number is equal to a number of bits comprised by one bit block generated by the second bit block.

As an embodiment, the second number is a number of control information bits comprised by the second block of bits.

As an embodiment, the second number is a number of bits carried by the first signal relating to the second block of bits.

As an embodiment, the second number is a number of bits comprised by the second block of bits.

As an embodiment, the second number is a number of bits included in one bit block generated by the second bit block.

As an embodiment, the second number indicates a starting physical resource block occupied by the first signal in a frequency domain.

As an embodiment, the second number explicitly indicates a starting physical resource block occupied by the first signal in a frequency domain.

As an embodiment, the second number implicitly indicates a starting physical resource block occupied by the first signal in a frequency domain.

As an example, the expression "the second number is related to said second bit block" in the claims is achieved by claim 2 in this application.

As one embodiment, the first signal comprises a transmitted signal in a plurality of frequency Hop intervals (hops); the starting physical resource block occupied by the first signal in the frequency domain in the present application means: a starting physical resource block occupied by one of the multiple frequency hopping intervals.

As one embodiment, the first signal comprises a transmitted signal in a plurality of frequency hop intervals; the initial physical resource block occupied by the first signal in the frequency domain in the present application means: a starting physical resource block occupied by a first one of the multiple frequency hopping intervals.

As one embodiment, the first signal comprises a transmitted signal in a plurality of hop intervals; the initial physical resource block occupied by the first signal in the frequency domain in the present application means: a starting physical resource block occupied by a second one of the multiple frequency hopping intervals.

As an embodiment, the starting physical resource block occupied by the first signal in the frequency domain in this application refers to: and the physical resource block with the minimum index in all the physical resource blocks occupied by the first signal in the frequency domain.

As an embodiment, the starting physical resource block occupied by the first signal in the frequency domain in the present application refers to: and the physical resource block with the largest index in all the physical resource blocks occupied by the first signal in the frequency domain.

As an embodiment, the first number is equal to a positive integer.

As an embodiment, the first number is equal to a number of Physical Resource Blocks (PRBs) occupied by the first signal in a frequency domain in one frequency hopping interval (Hop).

As an embodiment, the first number is not greater than the number of physical resource blocks occupied by the first signal in a frequency domain in one frequency hopping interval (Hop).

As an embodiment, the first number is equal to the number of physical resource blocks occupied by the first signal in a frequency domain in one multicarrier symbol.

As an embodiment, the first number is not greater than the number of physical resource blocks occupied by the first signal in a frequency domain in one multicarrier symbol.

As an embodiment, one or more fields (fields) included in the first information block are used to indicate the number of physical resource blocks included in the frequency domain in the first pool of empty resources.

Example 2

Embodiment 2 illustrates a schematic diagram of a network architecture according to the present application, as shown in fig. 2.

FIG. 2 illustrates a diagram of a network architecture 200 for the 5G NR, LTE (Long-Term Evolution), and LTE-A (Long-Term Evolution Advanced) systems. The 5G NR or LTE network architecture 200 may be referred to as EPS (Evolved Packet System) 200 or some other suitable terminology. The EPS 200 may include one or more UEs (User Equipment) 201, ng-RANs (next generation radio access networks) 202, epcs (Evolved Packet Core)/5G-CNs (5G-Core Network,5G Core Network) 210, hss (Home Subscriber Server) 220, and internet services 230. The EPS may interconnect with other access networks, but these entities/interfaces are not shown for simplicity. As shown, the EPS provides packet switched services, however those skilled in the art will readily appreciate that the various concepts presented throughout this application may be extended to networks providing circuit switched services or other cellular networks. The NG-RAN includes NR node bs (gnbs) 203 and other gnbs 204. The gNB203 provides user and control plane protocol termination towards the UE 201. The gnbs 203 may be connected to other gnbs 204 via an Xn interface (e.g., backhaul). The gNB203 may also be referred to as a base station, a base transceiver station, a radio base station, a radio transceiver, a transceiver function, a Basic Service Set (BSS), an Extended Service Set (ESS), a TRP (transmitting receiving node), or some other suitable terminology. The gNB203 provides an access point for the UE201 to the EPC/5G-CN 210. Examples of UEs 201 include cellular phones, smart phones, session Initiation Protocol (SIP) phones, laptops, personal Digital Assistants (PDAs), satellite radios, non-terrestrial base station communications, satellite mobile communications, global positioning systems, multimedia devices, video devices, digital audio players (e.g., MP3 players), cameras, game consoles, drones, aircraft, narrowband internet of things equipment, machine-type communication equipment, land vehicles, automobiles, wearable equipment, or any other similar functioning device. Those skilled in the art may also refer to UE201 as a mobile station, a subscriber station, a mobile unit, a subscriber unit, a wireless unit, a remote unit, a mobile device, a wireless communication device, a remote device, a mobile subscriber station, an access terminal, a mobile terminal, a wireless terminal, a remote terminal, a handset, a user agent, a mobile client, a client, or some other suitable terminology. The gNB203 is connected to the EPC/5G-CN 210 via an S1/NG interface. The EPC/5G-CN 210 includes MME (Mobility Management Entity)/AMF (Authentication Management Domain)/UPF (User Plane Function) 211, other MMEs/AMF/UPF 214, S-GW (Service Gateway) 212, and P-GW (Packet data Network Gateway) 213.MME/AMF/UPF211 is a control node that handles signaling between UE201 and EPC/5G-CN 210. In general, the MME/AMF/UPF211 provides bearer and connection management. All user IP (Internet protocol) packets are transmitted through the S-GW212, and the S-GW212 itself is connected to the P-GW213. The P-GW213 provides UE IP address assignment as well as other functions. The P-GW213 is connected to the internet service 230. The internet service 230 includes an operator-corresponding internet protocol service, and may specifically include the internet, an intranet, an IMS (IP Multimedia Subsystem), and a packet-switched streaming service.

As an embodiment, the UE201 corresponds to the first node in this application.

As an embodiment, the UE241 corresponds to the second node in this application.

As an embodiment, the gNB203 corresponds to the first node in this application.

As an embodiment, the gNB203 corresponds to the second node in this application.

As an embodiment, the UE241 corresponds to the first node in this application.

As an embodiment, the UE201 corresponds to the second node in this application.

Example 3

Embodiment 3 shows a schematic diagram of an embodiment of a radio protocol architecture for the user plane and the control plane according to the present application, as shown in fig. 3. Fig. 3 is a schematic diagram illustrating an embodiment of radio protocol architecture for the user plane 350 and the control plane 300, fig. 3 showing the radio protocol architecture for the first communication node device (UE, RSU in gNB or V2X) and the second communication node device (gNB, RSU in UE or V2X), or the control plane 300 between two UEs, in three layers: layer 1, layer 2 and layer 3. Layer 1 (L1 layer) is the lowest layer and implements various PHY (physical layer) signal processing functions. The L1 layer will be referred to herein as PHY301. Layer 2 (L2 layer) 305 is above the PHY301 and is responsible for the link between the first and second communication node devices and the two UEs through the PHY301. The L2 layer 305 includes a MAC (media access Control) sublayer 302, an RLC (Radio Link Control) sublayer 303, and a PDCP (Packet Data Convergence Protocol) sublayer 304, which terminate at the second communication node device. The PDCP sublayer 304 provides multiplexing between different radio bearers and logical channels. The PDCP sublayer 304 also provides security by ciphering data packets and provides handover support for a first communication node device between second communication node devices. The RLC sublayer 303 provides segmentation and reassembly of upper layer packets, retransmission of lost packets, and reordering of packets to compensate for out-of-order reception due to HARQ. The MAC sublayer 302 provides multiplexing between logical and transport channels. The MAC sublayer 302 is also responsible for allocating various radio resources (e.g., resource blocks) in one cell between the first communication node devices. The MAC sublayer 302 is also responsible for HARQ operations. A RRC (Radio Resource Control) sublayer 306 in layer 3 (L3 layer) in the Control plane 300 is responsible for obtaining Radio resources (i.e., radio bearers) and configuring the lower layers using RRC signaling between the second communication node device and the first communication node device. The radio protocol architecture of the user plane 350 comprises layer 1 (L1 layer) and layer 2 (L2 layer), the radio protocol architecture in the user plane 350 for the first and second communication node devices is substantially the same for the physical layer 351, the PDCP sublayer 354 in the L2 layer 355, the RLC sublayer 353 in the L2 layer 355 and the MAC sublayer 352 in the L2 layer 355 as the corresponding layers and sublayers in the control plane 300, but the PDCP sublayer 354 also provides header compression for upper layer packets to reduce radio transmission overhead. The L2 layer 355 in the user plane 350 further includes a Service Data Adaptation Protocol (SDAP) sublayer 356, and the SDAP sublayer 356 is responsible for mapping between QoS streams and Data Radio Bearers (DRBs) to support diversity of services. Although not shown, the first communication node device may have several upper layers above the L2 layer 355, including a network layer (e.g., IP layer) that terminates at the P-GW on the network side and an application layer that terminates at the other end of the connection (e.g., far end UE, server, etc.).

As an example, the wireless protocol architecture in fig. 3 is applicable to the first node in this application.

As an example, the radio protocol architecture in fig. 3 is applicable to the second node in this application.

As an embodiment, the first information block in this application is generated in the RRC sublayer 306.

As an embodiment, the first information block in this application is generated in the MAC sublayer 302.

As an embodiment, the first information block in this application is generated in the MAC sublayer 352.

As an embodiment, the first signaling in this application is generated in the RRC sublayer 306.

As an embodiment, the first signaling in this application is generated in the MAC sublayer 302.

As an embodiment, the first signaling in this application is generated in the MAC sublayer 352.

As an embodiment, the first signaling in this application is generated in the PHY301.

As an embodiment, the first signaling in this application is generated in the PHY351.

As an embodiment, the first bit block in this application is generated in the MAC sublayer 302.

As an embodiment, the first bit block in this application is generated in the MAC sublayer 352.

As an embodiment, the first bit block in this application is generated in the PHY301.

As an embodiment, the first bit block in this application is generated in the PHY351.

As an embodiment, the second bit block in this application is generated in the MAC sublayer 302.

As an embodiment, the second bit block in this application is generated in the MAC sublayer 352.

As an embodiment, the second bit block in this application is generated in the PHY301.

As an embodiment, the second bit block in this application is generated in the PHY351.

As an embodiment, the first output bit sequence in this application is generated in the MAC sublayer 302.

As an embodiment, the first output bit sequence in this application is generated in the MAC sublayer 352.

As an example, the first output bit sequence in this application is generated in the PHY301.

As an embodiment, the first output bit sequence in this application is generated in the PHY351.

As an example, the first signal in this application is generated in the PHY301.

As an embodiment, the first signal in this application is generated in the PHY351.

Example 4

Embodiment 4 shows a schematic diagram of a first communication device and a second communication device according to the present application, as shown in fig. 4. Fig. 4 is a block diagram of a first communication device 410 and a second communication device 450 communicating with each other in an access network.

The first communications device 410 includes a controller/processor 475, a memory 476, a receive processor 470, a transmit processor 416, a multiple antenna receive processor 472, a multiple antenna transmit processor 471, a transmitter/receiver 418, and an antenna 420.

The second communications device 450 includes a controller/processor 459, a memory 460, a data source 467, a transmit processor 468, a receive processor 456, a multi-antenna transmit processor 457, a multi-antenna receive processor 458, a transmitter/receiver 454, and an antenna 452.

In the transmission from the first communication device 410 to the second communication device 450, at the first communication device 410, upper layer data packets from the core network are provided to the controller/processor 475. The controller/processor 475 implements the functionality of the L2 layer. In transmissions from the first communications device 410 to the first communications device 450, the controller/processor 475 provides header compression, encryption, packet segmentation and reordering, multiplexing between logical and transport channels, and radio resource allocation to the second communications device 450 based on various priority metrics. The controller/processor 475 is also responsible for retransmission of lost packets and signaling to the second communication device 450. The transmit processor 416 and the multi-antenna transmit processor 471 implement various signal processing functions for the L1 layer (i.e., the physical layer). The transmit processor 416 implements coding and interleaving to facilitate Forward Error Correction (FEC) at the second communication device 450 and mapping of signal constellation based on various modulation schemes (e.g., binary Phase Shift Keying (BPSK), quadrature Phase Shift Keying (QPSK), M-phase shift keying (M-PSK), M-quadrature amplitude modulation (M-QAM)). The multi-antenna transmit processor 471 performs digital spatial precoding, including codebook-based precoding and non-codebook based precoding, and beamforming on the coded and modulated symbols to generate one or more spatial streams. Transmit processor 416 then maps each spatial stream to subcarriers, multiplexes with reference signals (e.g., pilots) in the time and/or frequency domain, and then uses an Inverse Fast Fourier Transform (IFFT) to generate the physical channels carrying the time-domain multicarrier symbol streams. The multi-antenna transmit processor 471 then performs analog precoding/beamforming operations on the time domain multi-carrier symbol stream. Each transmitter 418 converts the baseband multi-carrier symbol stream provided by the multi-antenna transmit processor 471 into a radio frequency stream that is then provided to a different antenna 420.

In a transmission from the first communications device 410 to the second communications device 450, at the second communications device 450, each receiver 454 receives a signal through its respective antenna 452. Each receiver 454 recovers information modulated onto a radio frequency carrier and converts the radio frequency stream into a baseband multi-carrier symbol stream provided to a receive processor 456. Receive processor 456 and multi-antenna receive processor 458 implement the various signal processing functions of the L1 layer. A multi-antenna receive processor 458 performs receive analog precoding/beamforming operations on the baseband multi-carrier symbol stream from the receiver 454. Receive processor 456 converts the baseband multicarrier symbol stream after the receive analog precoding/beamforming operation from the time domain to the frequency domain using a Fast Fourier Transform (FFT). In the frequency domain, the physical layer data signals and the reference signals to be used for channel estimation are demultiplexed by the receive processor 456, and the data signals are subjected to multi-antenna detection in the multi-antenna receive processor 458 to recover any spatial streams destined for the second communication device 450. The symbols on each spatial stream are demodulated and recovered at a receive processor 456 and soft decisions are generated. The receive processor 456 then decodes and deinterleaves the soft decisions to recover the upper layer data and control signals transmitted by the first communications device 410 on the physical channel. The upper layer data and control signals are then provided to a controller/processor 459. The controller/processor 459 implements the functions of the L2 layer. The controller/processor 459 may be associated with a memory 460 that stores program codes and data. Memory 460 may be referred to as a computer-readable medium. In transmissions from the first communications device 410 to the second communications device 450, the controller/processor 459 provides demultiplexing between transport and logical channels, packet reassembly, deciphering, header decompression, control signal processing to recover upper layer packets from the core network. The upper layer packet is then provided to all protocol layers above the L2 layer. Various control signals may also be provided to L3 for L3 processing.

In a transmission from the second communications device 450 to the first communications device 410, a data source 467 is used at the second communications device 450 to provide upper layer data packets to a controller/processor 459. The data source 467 represents all protocol layers above the L2 layer. Similar to the send function at the first communications apparatus 410 described in the transmission from the first communications apparatus 410 to the second communications apparatus 450, the controller/processor 459 performs header compression, encryption, packet segmentation and reordering, and multiplexing between logical and transport channels based on radio resource allocation, performing L2 layer functions for the user plane and control plane. The controller/processor 459 is also responsible for retransmission of lost packets and signaling to said first communications device 410. The transmit processor 468 performs modulation mapping, channel coding, and digital multi-antenna spatial precoding, including codebook-based precoding and non-codebook-based precoding, and beamforming, by the multi-antenna transmit processor 457, and then the transmit processor 468 modulates the resulting spatial streams into multi-carrier/single-carrier symbol streams, which are provided to the different antennas 452 via the transmitter 454 after analog precoding/beamforming in the multi-antenna transmit processor 457. Each transmitter 454 first converts the baseband symbol stream provided by the multi-antenna transmit processor 457 into a radio frequency symbol stream and provides the radio frequency symbol stream to the antenna 452.

In a transmission from the second communication device 450 to the first communication device 410, the functionality at the first communication device 410 is similar to the receiving functionality at the second communication device 450 described in the transmission from the first communication device 410 to the second communication device 450. Each receiver 418 receives an rf signal through its respective antenna 420, converts the received rf signal to a baseband signal, and provides the baseband signal to a multi-antenna receive processor 472 and a receive processor 470. The receive processor 470 and the multiple antenna receive processor 472 collectively implement the functionality of the L1 layer. The controller/processor 475 implements the L2 layer functions. The controller/processor 475 may be associated with a memory 476 that stores program codes and data. Memory 476 may be referred to as a computer-readable medium. In transmissions from the second communications device 450 to the first communications device 410, the controller/processor 475 provides demultiplexing between transport and logical channels, packet reassembly, deciphering, header decompression, control signal processing to recover upper layer packets from the UE 450. Upper layer data packets from the controller/processor 475 may be provided to a core network.

As an embodiment, the first node in this application includes the second communication device 450, and the second node in this application includes the first communication device 410.

As a sub-embodiment of the foregoing embodiment, the first node is a user equipment, and the second node is a user equipment.

As a sub-embodiment of the foregoing embodiment, the first node is a user equipment, and the second node is a relay node.

As a sub-embodiment of the foregoing embodiment, the first node is a relay node, and the second node is a user equipment.

As a sub-embodiment of the foregoing embodiment, the first node is a user equipment, and the second node is a base station equipment.

As a sub-embodiment of the foregoing embodiment, the first node is a relay node, and the second node is a base station device.

As a sub-embodiment of the foregoing embodiment, the second node is a user equipment, and the first node is a base station equipment.

As a sub-embodiment of the foregoing embodiment, the second node is a relay node, and the first node is a base station device.

As a sub-embodiment of the above-described embodiment, the second communication device 450 includes: at least one controller/processor; the at least one controller/processor is responsible for HARQ operations.

As a sub-embodiment of the above-described embodiment, the first communication device 410 includes: at least one controller/processor; the at least one controller/processor is responsible for HARQ operations.

As a sub-embodiment of the above-mentioned embodiments, the first communication device 410 comprises: at least one controller/processor; the at least one controller/processor is responsible for error detection using a positive Acknowledgement (ACK) and/or Negative Acknowledgement (NACK) protocol to support HARQ operations.

As an embodiment, the second communication device 450 includes: at least one processor and at least one memory including computer program code; the at least one memory and the computer program code are configured for use with the at least one processor. The second communication device 450 apparatus at least: receiving the first information block in the present application, where the first information block is used to determine the first pool of empty resources in the present application; transmitting the first signal in the present application, the first signal being used to carry the first bit block in the present application, the first bit block including at least one control information bit; the air interface resources occupied by the first signal belong to the first air interface resource pool, the number of physical resource blocks occupied by the first signal in the frequency domain is equal to the first number in the application, and the first number is not greater than the number of physical resource blocks included by the first air interface resource pool in the frequency domain; the number of bits comprised by the first block of bits is used to determine the first number, the first number being a positive integer; the second bit block in this application includes at least one control information bit, and the category of the control information bit included in the first bit block is different from the category of the control information bit included in the second bit block; the second number in this application relates to the second bit block, the second number being used to determine a starting physical resource block occupied by the first signal in the frequency domain, the second number being a non-negative integer.

As a sub-embodiment of the foregoing embodiment, the second communication device 450 corresponds to the first node in this application.

As an embodiment, the second communication device 450 includes: a memory storing a program of computer readable instructions that when executed by at least one processor result in actions comprising: receiving the first information block in the present application, where the first information block is used to determine the first pool of empty resources in the present application; transmitting the first signal in the present application, the first signal being used to carry the first bit block in the present application, the first bit block including at least one control information bit; the air interface resources occupied by the first signal belong to the first air interface resource pool, the number of the physical resource blocks occupied by the first signal in the frequency domain is equal to the first number in the application, and the first number is not greater than the number of the physical resource blocks included by the first air interface resource pool in the frequency domain; the number of bits comprised by the first block of bits is used to determine the first number, the first number being a positive integer; the second bit block in this application includes at least one control information bit, and the category of the control information bit included in the first bit block is different from the category of the control information bit included in the second bit block; the second number in this application relates to the second bit block, the second number being used to determine a starting physical resource block occupied by the first signal in the frequency domain, the second number being a non-negative integer.

As a sub-embodiment of the above embodiment, the second communication device 450 corresponds to the first node in the present application.

As an embodiment, the first communication device 410 includes: at least one processor and at least one memory including computer program code; the at least one memory and the computer program code are configured for use with the at least one processor. The first communication device 410 means at least: sending the first information block in the present application, where the first information block is used to determine the first pool of empty resources in the present application; receiving the first signal in this application, the first signal being used to carry the first bit block in this application, the first bit block including at least one control information bit; the air interface resources occupied by the first signal belong to the first air interface resource pool, the number of the physical resource blocks occupied by the first signal in the frequency domain is equal to the first number in the application, and the first number is not greater than the number of the physical resource blocks included by the first air interface resource pool in the frequency domain; the number of bits comprised by the first block of bits is used to determine the first number, the first number being a positive integer; the second bit block in the present application includes at least one control information bit, and the categories of the control information bits included in the first bit block and the control information bits included in the second bit block are different; the second number in this application relates to the second bit block, the second number being used to determine a starting physical resource block occupied by the first signal in the frequency domain, the second number being a non-negative integer.

As a sub-embodiment of the above embodiment, the first communication device 410 corresponds to the second node in this application.

As an embodiment, the first communication device 410 includes: a memory storing a program of computer readable instructions that when executed by at least one processor result in actions comprising: sending the first information block in the present application, where the first information block is used to determine the first pool of empty resources in the present application; receiving the first signal in the present application, where the first signal is used to carry the first bit block in the present application, and the first bit block includes at least one control information bit; the air interface resources occupied by the first signal belong to the first air interface resource pool, the number of physical resource blocks occupied by the first signal in the frequency domain is equal to the first number in the application, and the first number is not greater than the number of physical resource blocks included by the first air interface resource pool in the frequency domain; the number of bits comprised by the first block of bits is used to determine the first number, the first number being a positive integer; the second bit block in this application includes at least one control information bit, and the category of the control information bit included in the first bit block is different from the category of the control information bit included in the second bit block; the second number in this application relates to the second bit block, the second number being used to determine a starting physical resource block occupied by the first signal in the frequency domain, the second number being a non-negative integer.

As one example, at least one of the antenna 452, the receiver 454, the multi-antenna receive processor 458, the receive processor 456, the controller/processor 459, the memory 460, and the data source 467 is configured to receive the first information block of the present application.

As an example, at least one of { the antenna 420, the transmitter 418, the multi-antenna transmit processor 471, the transmit processor 416, the controller/processor 475, the memory 476} is used to transmit the first information block in this application.

As one example, at least one of the antenna 452, the receiver 454, the multi-antenna receive processor 458, the receive processor 456, the controller/processor 459, the memory 460, and the data source 467 is configured to receive the first signaling of the present application.

As an example, at least one of { the antenna 420, the transmitter 418, the multi-antenna transmit processor 471, the transmit processor 416, the controller/processor 475, the memory 476} is used to transmit the first signaling in this application.

As one example, at least one of the antenna 452, the transmitter 454, the multi-antenna transmit processor 458, the transmit processor 468, the controller/processor 459, the memory 460, the data source 467 may be utilized to transmit the first signal in this application.

As an example, at least one of { the antenna 420, the receiver 418, the multi-antenna reception processor 472, the reception processor 470, the controller/processor 475, the memory 476} is used to receive the first signal in this application.

Example 5

Embodiment 5 illustrates a signal transmission flow chart according to an embodiment of the present application, as shown in fig. 5. In fig. 5, the first node U1 and the second node U2 communicate over an air interface. The step in the dashed box F1 is optional.

A first node U1 receiving the first information block in step S511; receiving a first signaling in step S5101; a first signal is transmitted in step S512.

The second node U2, which transmits the first information block in step S521, and transmits the first signaling in step S5201; the first signal is received in step S522.

In embodiment 5, the first information block is used to determine a first pool of empty resources; the first signal is used to carry a first block of bits, the first block of bits comprising at least one control information bit; the air interface resources occupied by the first signal belong to the first air interface resource pool, the number of physical resource blocks occupied by the first signal in the frequency domain is equal to a first number, and the first number is not greater than the number of physical resource blocks included by the first air interface resource pool in the frequency domain; the number of bits comprised by the first block of bits is used to determine the first number, the first number being a positive integer; the second bit block comprises at least one control information bit, and the category of the control information bit contained in the first bit block is different from that of the control information bit contained in the second bit block; a second number is related to the second bit block, the second number being used to determine a starting physical resource block occupied by the first signal in the frequency domain, the second number being a non-negative integer; the second number is equal to the number of bits carried by the first signal and related to the second bit block, or the second number is equal to the number of bits included in one bit block generated by the second bit block; the second number belongs to one of a plurality of numerical intervals, any one of the plurality of numerical intervals including at least one non-negative integer; the plurality of value intervals comprise a first value interval and a second value interval; any two value intervals in the plurality of value intervals are orthogonal to each other; when the second number belongs to the first numerical interval, the index of the initial physical resource block occupied by the first signal in the frequency domain is a first physical resource block index; when the second number belongs to the second numerical interval, the index of the initial physical resource block occupied by the first signal in the frequency domain is equal to the index of the first physical resource block plus a first offset; the plurality of value intervals are predefined or configurable, the first physical resource block index is predefined or configurable, the first offset is predefined or configurable; at least the former of both the first bit block and the second bit block is used to generate a first output bit sequence comprising a positive integer number of bits greater than 1; the number of bits comprised by the first output bit sequence and the first number are linearly related, the first output bit sequence being used for generating the first signal; the priority index of the control information bits included in the first bit block is equal to a first index, the priority index of the control information bits included in the second bit block is equal to a second index, the first index is a non-negative integer, and the second index is a non-negative integer; the first index and the second index are not equal; the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block is greater than 2.

As a sub-embodiment of embodiment 5, the number of bits included in the first bit block and a first parameter value are used together to determine the first number; the first parameter value is a predefined or configurable non-negative number or the first parameter value is related to the second block of bits.

As a sub-embodiment of embodiment 5, a size relationship between a number of bits comprised by the second block of bits and a first threshold is used to determine a manner in which the second block of bits is used to generate the first sequence of output bits, the first threshold being a non-negative integer; the first threshold value is predefined, or the first threshold value is configurable, or the first threshold value is related to a first parameter value.

As a sub-embodiment of embodiment 5, the first parameter value is equal to one of X1 candidate parameter values, where X1 is a positive integer greater than 1; a given parameter value equal to one of the X1 candidate parameter values, the first parameter value and the given parameter value being unequal is used to determine that the first signal carries the first block of bits and the second block of bits.

As a sub-embodiment of embodiment 5, a third pool of empty resources is reserved for the first bit block, and a second pool of empty resources is reserved for the second bit block; and the third air interface resource pool and the second air interface resource pool are overlapped in a time domain.

As a sub-embodiment of embodiment 5, the first air interface resource pool belongs to a first air interface resource pool set, where the first air interface resource pool set includes at least one air interface resource pool, and the first signaling is used to determine the first air interface resource pool from the first air interface resource pool set; the first air interface resource pool set is one of X2 alternative air interface resource pool sets, where X2 is a positive integer greater than 1, and the first information block is used to determine the X2 alternative air interface resource pool sets; at least one of the number of bits included in the first bit block or the number of bits included in the second bit block is used to determine the first air interface resource pool set from the X2 air interface candidate resource pool sets.

As an embodiment, the first node U1 is the first node in this application.

As an embodiment, the second node U2 is the second node in this application.

As an embodiment, the first node U1 is a UE.

As an embodiment, the first node U1 is a base station.

As an embodiment, the second node U2 is a base station.

As an embodiment, the second node U2 is a UE.

As an embodiment, the air interface between the second node U2 and the first node U1 is a Uu interface.

For one embodiment, the air interface between the second node U2 and the first node U1 comprises a cellular link.

As an embodiment, the air interface between the second node U2 and the first node U1 is a PC5 interface.

For one embodiment, the air interface between the second node U2 and the first node U1 includes a sidelink.

As an embodiment, the air interface between the second node U2 and the first node U1 comprises a radio interface between a base station device and a user equipment.

As an embodiment, the air interface between the second node U2 and the first node U1 comprises a radio interface between user equipment and user equipment.

As an embodiment, a sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block is greater than 2.

As an embodiment, when the first signal carries the second block of bits, the number of bits comprised by the first block of bits and the number of bits comprised by the second block of bits are jointly used for determining the first number.

As an embodiment, when the first signal carries one bit block generated by the second bit block, the number of bits comprised by the first bit block and the number of bits comprised by the one bit block generated by the second bit block are jointly used for determining the first number.

As an embodiment, when the first signal carries the second bit block or a bit block generated by the second bit block, the number of bits comprised by the first bit block and a first parameter value are jointly used for determining the first number; the first parameter value is a predefined or configurable non-negative number or the first parameter value is related to the second block of bits.

As an embodiment, when the first signal does not carry the second block of bits nor the block of bits generated by the second block of bits, the number of bits comprised by the first block of bits is used to determine the first number.

As an embodiment, a third pool of air resources is reserved for the first block of bits, and a second pool of air resources is reserved for the second block of bits; and the third air interface resource pool and the second air interface resource pool are overlapped in a time domain.

As an embodiment, the first signaling indicates the third pool of empty resources.

As an embodiment, the first signaling indicates the second pool of empty resources.

As an embodiment, the third pool of empty resources is one PUCCH resource.

As an embodiment, the second pool of empty resources is one PUCCH resource.

As an example, the step in the dashed box F1 exists.

As an example, the step in the dashed box F1 is not present.

Example 6

Embodiment 6 illustrates an explanatory diagram that the second quantity is used for determining the starting physical resource block occupied by the first signal in the frequency domain according to an embodiment of the present application, as shown in fig. 6.

In example 6, the second quantity belongs to one of a plurality of intervals of values, any one of the plurality of intervals of values comprising at least one non-negative integer; the plurality of numerical intervals comprise a first numerical interval and a second numerical interval; any two value intervals in the plurality of value intervals are orthogonal to each other; when the second number belongs to the first numerical interval, the index of the initial physical resource block occupied by the first signal in the frequency domain is the index of the first physical resource block; when the second number belongs to the second numerical interval, the index of the initial physical resource block occupied by the first signal in the frequency domain is equal to the index of the first physical resource block plus a first offset; the plurality of value intervals are predefined or configurable, the first physical resource block index is predefined or configurable, and the first offset is predefined or configurable.

As an example, the meaning of orthogonal in this application includes: there is no overlap.

As an embodiment, the plurality of value intervals are configured for higher layer signaling.

As an embodiment, the plurality of value intervals are configured by RRC signaling.

As an embodiment, the plurality of value intervals are configured for MAC CE signaling.

In one embodiment, the plurality of value intervals are configured by the first information block.

As an embodiment, any one of the numerical intervals is a continuous interval.

As an embodiment, one of the value intervals includes only 0.

As an embodiment, a numerical range of the plurality of numerical ranges includes only one non-negative integer.

As an embodiment, a numerical range of the plurality of numerical ranges includes one or more non-negative integers.

As an embodiment, the first value interval comprises 0.

As an embodiment, the first interval of values comprises only 0.

As an embodiment, the first interval of values comprises at least one positive integer.

As an embodiment, the second numerical interval comprises 0.

As an embodiment, the second numerical interval comprises only 0.

As an embodiment, the second value interval does not comprise 0.

As an embodiment, the second interval of values comprises at least one positive integer.

As an embodiment, the first physical resource block index is configured for higher layer signaling.

As an embodiment, the first physical resource block index is RRC signaling configured.

As an embodiment, the first physical resource block index is configured for MAC CE signaling.

As an embodiment, the first physical resource block index is configured by the first information block.

As an embodiment, the first physical Resource block index is configured in one PUCCH-Resource domain.

As an embodiment, the first physical resource block index is a positive integer.

As an embodiment, the first physical resource block index is equal to a physical resource block index configured by the first information block or an RRC signaling or a MAC CE signaling plus an offset; the one offset is predefined or configured by the first information block or configured by one RRC signaling or configured by one MAC CE signaling.

As an embodiment, the first offset is configured for the first information block.

As an embodiment, the first offset is configured for higher layer (higher layer) signaling.

As an embodiment, the first offset is RRC signaling configured.

As an embodiment, the first offset is configured for MAC CE signaling.

As an embodiment, the first offset is indicated by one DCI.

As an embodiment, the first offset is configured in one PUCCH-Resource domain.

As an embodiment, the first offset is a positive integer.

As an embodiment, the plurality of value intervals respectively correspond to a plurality of offset amounts; the difference value between the index of the initial physical resource block occupied by the first signal in the frequency domain and the index of the initial physical resource block occupied by the first air interface resource pool in the frequency domain is equal to one of the plurality of offsets corresponding to the numerical interval to which the second number belongs in the plurality of numerical intervals.

As an embodiment, the plurality of value intervals respectively correspond to a plurality of offset amounts; a difference between an index of a starting physical resource block occupied by the first signal in a frequency domain in one frequency hopping interval (Hop) and an index of a starting physical resource block occupied by the first pool of air interface resources in the frequency domain in the one frequency hopping interval is equal to one of the plurality of offsets corresponding to the value intervals to which the second number belongs in the plurality of value intervals.

As one embodiment, the plurality of offsets includes 0.

As one embodiment, the plurality of offsets includes 1.

For one embodiment, the plurality of offsets includes a non-negative integer no greater than 65536.

As an embodiment, the correspondence between the plurality of value intervals and the plurality of offsets is predefined.

As an embodiment, the correspondence between the plurality of value intervals and the plurality of offsets is configurable.

Example 7

Embodiment 7 illustrates a schematic diagram of a relationship between at least the former of the first bit block and the second bit block, the first output bit sequence, the first number and the first signal according to an embodiment of the present application, as shown in fig. 7.

In embodiment 7, at least the former of both the first bit block and the second bit block is used to generate a first output bit sequence comprising a positive integer number of bits greater than 1; the number of bits comprised by the first output bit sequence is linearly related to a first number, the first output bit sequence being used for generating the first signal.

As an embodiment, when the first signal carries the second bit block or a bit block generated by the second bit block, both the first bit block and the second bit block are used for generating a first output bit sequence.

As an embodiment, when the first signal does not carry the second block of bits nor the block of bits generated by the second block of bits, only the former of both the first block of bits and the second block of bits is used for generating a first sequence of output bits.

As an embodiment, the first signal carries only the former of both the first and second bit blocks when only the former of both the first and second bit blocks is used for generating the first output bit sequence.

As an embodiment, in the present application, the meaning that the first signal carries only the former of both the first bit block and the second bit block includes: the first signal carries neither the second block of bits nor the block of bits generated by the second block of bits.

As an embodiment, when only the former of the first bit block and the second bit block is used for generating the first output bit sequence: the first bit block or a bit block generated by the first bit block is used to generate the first output bit sequence.

As an embodiment, the first output bit sequence is an output of the first bit block or a bit block generated by the first bit block after CRC adding (CRC), segmenting (Segmentation), coding block level CRC adding, channel Coding (Channel Coding), rate Matching (Rate Matching), and Concatenation (Concatenation) in sequence.

As an embodiment, the first output bit sequence includes an output of the first bit block or a bit block generated by the first bit block after being sequentially subjected to part or all of CRC adding (crcottachment), segmenting (Segmentation), coding block level CRC adding (CRC adding), channel Coding (Channel Coding), rate Matching (Rate Matching), and Concatenation (Concatenation).

As an embodiment, when both the first bit block and the second bit block are used to generate the first output bit sequence: the first output bit sequence comprises a first output bit subsequence and a second output bit subsequence; the first bit block or a bit block generated by the first bit block is used to generate the first output bit sub-sequence and the second bit block or a bit block generated by the second bit block is used to generate the second output bit sub-sequence.

As an embodiment, the first output bit subsequence is an output of the first bit block or a bit block generated by the first bit block after performing CRC addition (crcatachment), segmentation (Segmentation), coding block level CRC addition, channel Coding (Channel Coding), rate Matching (Rate Matching), concatenation (Concatenation) on part or all of the first bit block or the bit block sequentially.

As an embodiment, the second output bit subsequence is an output after CRC adding, segmenting, coding block level CRC adding, channel coding, rate matching, a part or all of the concatenation of the second bit block or a bit block generated by the second bit block.

As an embodiment, the first output bit subsequence includes an output of the first bit block or a bit block generated by the first bit block after being sequentially subjected to part or all of CRC adding (crcatachment), segmenting (Segmentation), coding block level CRC adding (CRC adding), channel Coding (Channel Coding), rate Matching (Rate Matching), and Concatenation (Concatenation).

As an embodiment, the second output bit sub-sequence includes output of the second bit block or a bit block generated by the second bit block after partial or all of CRC addition, segmentation, coded block level CRC addition, channel coding, rate matching, concatenation in sequence.

As an embodiment, the first output bit sub-sequence is an output of the first bit block or a bit block generated by the first bit block after sequentially performing part or all of channel coding, rate matching, and concatenation.

As an embodiment, the second output bit subsequence is an output of the second bit block or a bit block generated by the second bit block after sequentially performing channel coding, rate matching, and concatenation on part or all of the second bit block or the bit block.

As an embodiment, the first output bit sub-sequence includes the first bit block or an output after a part or all of the first bit block or a bit block generated by the first bit block is sequentially subjected to channel coding, rate matching and concatenation.

As an embodiment, the second output bit sub-sequence includes an output of the second bit block or a bit block generated by the second bit block after being subjected to channel coding, rate matching, concatenation, or all of them in sequence.

As an embodiment, the first output bit sequence includes outputs after partial or all of the first bit block or one bit block generated by the first bit block and the second bit block or one bit block generated by the second bit block are concatenated and then sequentially undergo CRC addition (CRC Insertion), segmentation (Segmentation), coding block level CRC addition (CRC Insertion), channel Coding (Channel Coding), rate Matching (Rate Matching), and Concatenation (Concatenation).

In one embodiment, the first output bit sequence includes coded bits.

As an embodiment, the first signal carries at least one of the first block of bits and the second block of bits by carrying the first output sequence of bits.

As an embodiment, the one bit block generated by the first bit block is: and outputting at least one of logical AND, logical OR, exclusive OR, repetition, bit deletion and zero padding operation to at least part of bits in the first bit block.

As an embodiment, the one bit block generated by the second bit block is: and outputting at least one of logical AND, logical OR, exclusive OR, repetition, bit deletion and zero padding operation to at least part of bits in the second bit block.

As an embodiment, the one bit block generated by the first bit block comprises: and outputting at least one of logical AND, logical OR, exclusive OR, repetition, bit deletion and zero padding operation to at least part of bits in the first bit block.

As an embodiment, the one bit block generated by the second bit block includes: and outputting at least one of logical AND, logical OR, exclusive OR, repetition, bit deletion and zero padding operation to at least part of bits in the second bit block.

In one embodiment, the first output bit sequence includes a number of bits equal to a first multiplier value multiplied by the first number multiplied by a second number of UCI symbols divided by a first spreading factor.

In one embodiment, the first multiplier value is equal to a predetermined or configured value.

As one example, the first multiplier value is equal to 12.

As an example, the first multiplier value is equal to 16.

As an example, the first multiplier value is equal to 24.

As an embodiment, the second number of UCI symbols is equal to the first number of UCI symbols in the present application.

As an embodiment, the second number of UCI symbols is the number of symbols carrying UCI in PUCCH format 2 or PUCCH format 3.

As an embodiment, the second number of UCI symbols is the number of UCI-carrying symbols in PUCCH format 4.

As an embodiment, the first spreading factor is a spreading factor (spreading factor) of PUCCH format 2 or PUCCH format 3.

As an embodiment, the first spreading factor is a spreading factor of PUCCH format 4.

As an embodiment, the first spreading factor is a positive integer.

In one embodiment, the first spreading factor is equal to a predetermined or configurable value.

In one embodiment, the first spreading factor is equal to the length of an orthogonal cover code.

As an embodiment, the first spreading factor is equal to a length of one orthogonal cover code included in one PUCCH resource using PUCCH format 2 or PUCCH format 3.

As an embodiment, the first output bit sequence comprises a number of bits equal to a positive integer multiple of the first number.

As an embodiment, the meaning that the sentence the first output bit sequence is used to generate the first signal comprises: the first signal comprises the output of the first output bit sequence after scrambling, modulation, layer mapping, precoding, mapping to resource elements, multi-carrier symbol generation and modulation up-conversion in sequence.

Example 8

Embodiment 8 illustrates a schematic diagram of the relationship between the number of bits included in the first bit block, the first calculation amount, and the first number according to an embodiment of the present application, as shown in fig. 8.

In embodiment 8, the number of bits included in the first bit block is used to determine the first calculation amount; the first number is related to the first calculated amount.

As an embodiment, a first code rate is used for determining the first calculation amount.

As an embodiment, a first code rate is used to determine the first number.

As an embodiment, the first information block is used to determine a first code rate, the first code rate being a non-negative number.

As an embodiment, the first information block is used to indicate the first code rate.

As an embodiment, the first information block explicitly indicates the first code rate.

As an embodiment, the first information block implicitly indicates the first code rate.

As an embodiment, the first information block indicates that the first code rate is the corresponding one of the first pool of air interface resources.

As an embodiment, the first information block indicates that the first code rate is the corresponding one of the maximum code rates of the first pool of air interface resources.

As an embodiment, the first code rate is one code rate of a set of code rates indicated by the first information block.

As an embodiment, the first code rate is not greater than 1.

As an embodiment, the first code rate is equal to one of 0.08,0.15,0.25,0.35,0.45,0.60, 0.80.

As an embodiment, the first pool of empty resources includes one PUCCH resource, and the first code rate is a maximum code rate configured for a PUCCH format (format) of the one PUCCH resource.

As an embodiment, the first code rate is a maximum code rate configured in a PUCCH-format config field.

As an embodiment, the third number is used to determine a second calculated amount, the first calculated amount being not greater than the second calculated amount; the third number is not greater than the number of physical resource blocks included in the frequency domain of the first pool of air interface resources, or the third number is determined by the first information block.

As an embodiment, the first calculation amount is smaller than the second calculation amount.

As an embodiment, the first number is not greater than the third number.

As an embodiment, the third number is determined by the first information block.

As an embodiment, the third number is indicated by the first information block.

As an embodiment, the third number is derived from all or part of the information in the first information block.

As an example, said third number is equal to the value of an nrofPRBs parameter.

As an embodiment, the third number is equal to a positive integer.

As an embodiment, the third number is equal to the number of physical resource blocks included in the frequency domain by the first air interface resource pool.

As an embodiment, the third number is equal to the number of physical resource blocks occupied by the first signal in a frequency domain in one frequency hopping interval.

As an embodiment, the third number is equal to the number of physical resource blocks occupied by the first signal in a frequency domain in one multicarrier symbol.

As an embodiment, when the first signal carries the second bit block, the number of bits comprised by the first bit block and the number of bits comprised by the second bit block are jointly used for determining the first computation amount.

As a sub-embodiment of the above embodiment, the first amount of computation is equal to the number of the bits comprised by the first block of bits plus the number of the bits comprised by the second block of bits.

As a sub-implementation of the above embodiment, the first computation amount is equal to a sum of a plurality of values, the plurality of values including the number of the bits included in the first block of bits and the number of the bits included in the second block of bits; one of the plurality of values is predefined or configurable or is calculated; the plurality of values may or may not include the number of CRC bits.

As a sub-embodiment of the above embodiment, the first calculated amount is equal to the number of the bits included in the first block of bits divided by the first code rate plus the number of the bits included in the second block of bits.

As a sub-implementation of the above embodiment, the first calculation amount is equal to the number of bits included in the first bit block divided by the number of bits included in the second bit block, rounded by the first code rate, and added to the number of bits included in the first bit block.

As a sub-embodiment of the above embodiment, the first calculation amount is not less than the number of the bits included in the first bit block plus the number of the bits included in the second bit block.

As a sub-implementation of the above embodiment, the first calculation amount is not less than the number of the bits included in the first bit block divided by the first code rate plus the number of the bits included in the second bit block.

As a sub-implementation of the above embodiment, the first calculation amount is equal to a sum of the number of the bits included in the first bit block plus a number of corresponding CRC bits divided by the first code rate plus the number of the bits included in the second bit block plus a number of corresponding CRC bits.

As a sub-embodiment of the above embodiment, the first calculated amount is equal to a sum of the number of the bits included in the first bit block plus a number of corresponding CRC bits divided by a result of the first code rate rounded plus the number of the bits included in the second bit block plus a number of corresponding CRC bits.

As a sub-embodiment of the above embodiment, the first calculation amount is equal to a sum of the number of the bits included in the first bit block and a number of corresponding CRC bits plus a sum of the number of the bits included in the second bit block and a number of corresponding CRC bits.

As a sub-embodiment of the above embodiment, the first calculation amount is not less than a sum of the number of the bits included in the first bit block and a number of corresponding CRC bits plus a sum of the number of the bits included in the second bit block and a number of corresponding CRC bits.

As a sub-implementation of the foregoing embodiment, the first calculation amount is not less than a sum of the number of the bits included in the first bit block and a number of corresponding CRC bits divided by the first code rate plus a sum of the number of the bits included in the second bit block and a number of corresponding CRC bits.

As a sub-implementation of the foregoing embodiment, the first calculation amount is not less than a sum of the number of the bits included in the first bit block plus a number of the corresponding CRC bits divided by a result of rounding the first code rate plus a sum of the number of the bits included in the second bit block plus a number of the corresponding CRC bits.

As a sub-embodiment of the above embodiment, the first calculated amount is equal to a sum of the number of the bits included in the first block of bits plus a number of CRC bits for the first block of bits divided by the first code rate plus a sum of the number of the bits included in the second block of bits plus a number of CRC bits for the second block of bits.

As a sub-implementation of the above embodiment, the first calculation amount is equal to a sum of the number of the bits included in the first bit block plus a number of CRC bits for the first bit block divided by a result of the first code rate, rounded plus a sum of the number of the bits included in the second bit block plus a number of CRC bits for the second bit block.

As a sub-implementation of the above embodiment, the first calculation amount is equal to a sum of the number of the bits included in the first bit block and a number of CRC bits for the first bit block plus a sum of the number of the bits included in the second bit block and a number of CRC bits for the second bit block.

As a sub-embodiment of the above embodiment, the first calculation amount is not less than a sum of the number of the bits included in the first bit block and a number of CRC bits for the first bit block plus a sum of the number of the bits included in the second bit block and a number of CRC bits for the second bit block.

As a sub-embodiment of the above embodiment, the first calculation amount is not less than a sum of the number of the bits included in the first bit block and a number of CRC bits for the first bit block divided by the first code rate plus a sum of the number of the bits included in the second bit block and a number of CRC bits for the second bit block.

As a sub-implementation of the above embodiment, the first calculation amount is not less than a sum of the number of the bits included in the first bit block plus a number of CRC bits for the first bit block divided by a result of the first code rate being rounded plus a sum of the number of the bits included in the second bit block plus a number of CRC bits for the second bit block.

As an embodiment, the number of the corresponding CRC bits in this application is equal to 0 or a positive integer.

As an embodiment, in the present application, the number of CRC bits for the first bit block is equal to 0 or a positive integer.

As an embodiment, in the present application, the number of CRC bits for the second bit block is equal to 0 or a positive integer.

As an embodiment, when the first signal carries one bit block generated by the second bit block, the number of bits included in the first bit block and the number of bits included in the one bit block generated by the second bit block are jointly used for determining the first computation amount.

As a sub-implementation of the above embodiment, the first calculation amount is equal to the number of the bits included in the first bit block plus the number of the bits included in the one bit block generated by the second bit block.

As a sub-embodiment of the above embodiment, the first calculated amount is equal to a sum of a plurality of values, the plurality of values including the number of the bits included in the first bit block and the number of the bits included in the one bit block generated by the second bit block; one of the plurality of values is predefined or configurable or is calculated; the plurality of values may or may not include the number of CRC bits.

As a sub-implementation of the above embodiment, the first calculation amount is equal to the number of the bits included in the first bit block divided by the first code rate plus the number of the bits included in the one bit block generated by the second bit block.

As a sub-implementation of the above embodiment, the first calculation amount is equal to the number of bits included in the first bit block divided by the number of bits of the first code rate, rounded, and added to the number of bits included in the one bit block generated by the second bit block.

As a sub-implementation of the above-described embodiment, the first calculation amount is not less than the number of the bits included in the first bit block plus the number of the bits included in the one bit block generated by the second bit block.

As a sub-embodiment of the foregoing embodiment, the first calculation amount is not less than the number of the bits included in the first bit block divided by the first code rate plus the number of the bits included in the one bit block generated by the second bit block.

As a sub-implementation of the above embodiment, the first calculation amount is equal to a sum of the number of the bits included in the first bit block plus a number of corresponding CRC bits divided by the first code rate plus the number of the bits included in the one bit block generated by the second bit block plus a number of corresponding CRC bits.

As a sub-embodiment of the above embodiment, the first calculated amount is equal to a sum of the number of the bits included in the first bit block plus a number of corresponding CRC bits divided by a result of rounding the first code rate plus the number of the bits included in the one bit block generated by the second bit block plus a number of corresponding CRC bits.

As a sub-implementation of the above-described embodiment, the first calculation amount is equal to a sum of the number of the bits included in the first bit block and a number of corresponding CRC bits plus a sum of the number of the bits included in the one bit block generated by the second bit block and a number of corresponding CRC bits.

As a sub-embodiment of the above embodiment, the first calculation amount is not less than a sum of the number of the bits included in the first bit block and a number of corresponding CRC bits plus a sum of the number of the bits included in the one bit block generated by the second bit block and a number of corresponding CRC bits.

As a sub-embodiment of the foregoing embodiment, the first calculation amount is not less than the sum of the number of the bits included in the first bit block and the number of corresponding CRC bits divided by the first code rate plus the sum of the number of the bits included in the one bit block generated by the second bit block and the number of corresponding CRC bits.

As a sub-implementation of the foregoing embodiment, the first calculation amount is not less than a sum of the number of the bits included in the first bit block plus a number of the corresponding CRC bits divided by a result of rounding the first code rate plus a sum of the number of the bits included in the one bit block generated by the second bit block plus a number of the corresponding CRC bits.

As a sub-implementation of the above embodiment, the first calculation amount is equal to a sum of the number of the bits included in the first bit block plus a number of CRC bits for the first bit block divided by the first code rate plus the number of the bits included in the one bit block generated by the second bit block and a number of CRC bits for the one bit block generated by the second bit block.

As a sub-embodiment of the above-mentioned embodiments, the first calculated amount is equal to a result of rounding a sum of the number of the bits included in the first bit block plus a number of CRC bits for the first bit block divided by the first code rate plus the number of the bits included in the one bit block generated by the second bit block and a number of CRC bits for the one bit block generated by the second bit block.

As a sub-implementation of the above-described embodiment, the first calculation amount is equal to a sum of the number of the bits included in the first bit block and a number of CRC bits for the first bit block plus a sum of the number of the bits included in the one bit block generated by the second bit block and a number of CRC bits for the one bit block generated by the second bit block.

As a sub-embodiment of the above-mentioned embodiment, the first calculation amount is not less than a sum of the number of the bits included in the first bit block and a number of CRC bits for the first bit block plus a sum of the number of the bits included in the one bit block generated by the second bit block and a number of CRC bits for the one bit block generated by the second bit block.

As a sub-embodiment of the above embodiment, the first calculation amount is not less than the sum of the number of the bits included in the first bit block and the number of CRC bits for the first bit block divided by the first code rate plus the sum of the number of the bits included in the one bit block generated by the second bit block and the number of CRC bits for the one bit block generated by the second bit block.

As a sub-embodiment of the above embodiment, the first calculation amount is not less than a sum of the number of the bits included in the first bit block plus a number of CRC bits for the first bit block divided by a result of rounding the first code rate plus a sum of the number of the bits included in the one bit block generated by the second bit block and a number of CRC bits for the one bit block generated by the second bit block.

As an embodiment, in the present application, the number of CRC bits of one bit block generated for the second bit block is equal to 0 or a positive integer.

As an embodiment, when the first signal carries the second bit block or a bit block generated by the second bit block, the number of bits included in the first bit block and a first parameter value are jointly used for determining the first computation amount; the first parameter value is a predefined or configurable non-negative number or the first parameter value is related to the second block of bits.

As a sub-implementation of the above embodiment, the first calculation amount is equal to the number of the bits comprised by the first bit block plus the first parameter value.

As a sub-embodiment of the above embodiment, said first calculation amount is equal to the sum of said number of said bits comprised by said first bit block and the number of corresponding CRC bits plus said first parameter value.

As a sub-embodiment of the above embodiment, the first calculation amount is equal to the sum of the number of the bits comprised by the first bit block and the number of CRC bits for the first bit block plus the first parameter value.

As a sub-implementation of the above embodiment, the first calculation amount is equal to a sum of a plurality of values, the plurality of values including the number of the bits included in the first bit block and the first parameter value; one of the plurality of values is predefined or configurable or is calculated; the plurality of values may or may not include the number of CRC bits.

As a sub-embodiment of the above embodiment, the first calculated amount is equal to the number of bits included in the first bit block divided by the first code rate plus the first parameter value.

As a sub-implementation of the above-mentioned embodiment, the first calculation amount is equal to a rounding of the number of bits included in the first bit block divided by the first code rate plus the first parameter value.

As a sub-embodiment of the above embodiment, the first calculation amount is not less than the number of the bits included in the first bit block plus the first parameter value.

As a sub-implementation of the foregoing embodiment, the first calculation amount is not less than the number of bits included in the first bit block divided by the first code rate plus the first parameter value.

As a sub-implementation of the above embodiment, the first calculation amount is equal to a sum of the number of the bits included in the first bit block plus a number of corresponding CRC bits divided by the first code rate plus the first parameter value.

As a sub-embodiment of the above embodiment, the first calculation amount is equal to a sum of the number of the bits included in the first bit block plus a number of corresponding CRC bits divided by a result of rounding the first code rate plus the first parameter value.

As a sub-embodiment of the above embodiment, the first calculation amount is not less than the number of the bits included in the first bit block plus the number of corresponding CRC bits plus the first parameter value.

As a sub-implementation of the foregoing embodiment, the first calculation amount is not less than a sum of the number of the bits included in the first bit block plus a number of corresponding CRC bits divided by the first code rate plus the first parameter value.

As a sub-implementation of the foregoing embodiment, the first calculation amount is not less than a sum of the number of bits included in the first bit block plus a number of corresponding CRC bits divided by a result of rounding the first code rate plus the first parameter value.

As a sub-embodiment of the above embodiment, the first calculated amount is equal to a sum of the number of the bits comprised by the first bit block plus a number of CRC bits for the first bit block divided by the first code rate plus the first parameter value.

As a sub-implementation of the above embodiment, the first calculation amount is equal to a sum of the number of the bits included in the first bit block plus a number of CRC bits for the first bit block divided by a result of the first code rate, rounded, plus the first parameter value.

As a sub-embodiment of the above embodiment, the first calculation amount is not less than the number of the bits included in the first bit block plus the number of CRC bits for the first bit block plus the first parameter value.

As a sub-embodiment of the above embodiment, the first calculation amount is not less than a sum of the number of the bits included in the first bit block plus a number of CRC bits for the first bit block divided by the first code rate plus the first parameter value.

As a sub-embodiment of the above embodiment, the first calculation amount is not less than a sum of the number of bits included in the first bit block plus a number of CRC bits for the first bit block divided by the first code rate, rounded, plus the first parameter value.

As an embodiment, the expression "the first parameter value is a predefined or configurable non-negative number" includes the following meanings: the first parameter value is related to the first code rate, and the first information block is used to configure the first code rate.

As an embodiment, the expression "the first parameter value is a predefined or configurable non-negative number" includes the following meanings: the first information block is used to configure the first code rate, which is used to determine the first parameter value.

As an embodiment, the expression "the first parameter value is a predefined or configurable non-negative number" includes the following meanings: the first information block is used to configure the first code rate, the first parameter value being calculated or inferred from the first code rate.

As an embodiment, the expression "the first parameter value is a predefined or configurable non-negative number" includes the following meanings: the first information block is used to configure the first code rate, the first parameter value being calculated or inferred from the first code rate and the number of bits comprised by the first bit block.

As an embodiment, the expression "the first parameter value is a predefined or configurable non-negative number" includes the following meanings: the first parameter value is configured for the first information block or other information blocks.

As an embodiment, the first parameter value is equal to one of X1 candidate parameter values, where X1 is a positive integer greater than 1.

As an embodiment, the first parameter value is a largest parameter value of the X1 candidate parameter values that is not larger than the number of bits comprised by the second block of bits.

As an embodiment, the first parameter value is a smallest parameter value of the X1 candidate parameter values that is not smaller than the number of bits comprised by the second bit block.

As an embodiment, when the first signal does not carry the second block of bits nor the block of bits generated by the second block of bits, the number of bits comprised by the first block of bits is used to determine the first computation amount.

As a sub-embodiment of the above embodiment, said first amount of computation is equal to said number of said bits comprised by said first block of bits.

As a sub-embodiment of the above embodiment, said first calculation amount is equal to a sum of said number of said bits comprised by said first bit block and a number of corresponding CRC bits.

As a sub-embodiment of the above embodiment, the first calculation amount is equal to a sum of the number of the bits comprised by the first bit block and a number of CRC bits for the first bit block.

As a sub-embodiment of the above embodiment, the first calculated amount is equal to a sum of a plurality of values, the plurality of values including the number of the bits included in the first block of bits; one of the plurality of values is predefined or configurable or is calculated; the plurality of values may or may not include the number of CRC bits.

As an example, the rounding in this application refers to rounding up.

As an example, the rounding in this application refers to downward rounding.

As an embodiment, the second calculated amount is calculated or inferred from the third amount.

As an embodiment, the second calculated amount is linearly related to the third amount.

As an embodiment, the second calculation amount is equal to a product of the third number, the first number of subcarriers, the first number of UCI symbols, the first modulation order, and the first code rate.

As an embodiment, the second calculation amount is equal to a product of the third number, the first number of subcarriers, the first number of UCI symbols, and the first modulation order and the first code rate.

As an example, the meaning that the first number of the sentence is related to the first calculation amount includes: the first number is equal to one of a first set of numbers that satisfies a first condition relating to both the first code rate and the first computational quantity, the maximum number of the first set of numbers being no greater than the third number.

As a sub-embodiment of the above embodiment, if a product of one of the first number set, the first number of subcarriers, the first number of UCI symbols, the first modulation order, and the first code rate is not less than the first calculation amount, and any of the first number set is less than the number of the one of the first number set, the first number of subcarriers, the first number of UCI symbols, the product of the first modulation order, and the first code rate is less than the first calculation amount, then the one of the first number set is one of the first number set that satisfies the first condition.

As an embodiment, the first set of numbers includes at least one number.

As an embodiment, there is only one number of the first set of numbers that satisfies the first condition.

As an embodiment, the maximum number in the first set of numbers is not greater than the third number.

As an embodiment, any number in the first set of numbers is one of an integer power of 2, an integer power of 3, and an integer power of 5.

As an embodiment, the first set of numbers only includes all integer powers of 2, 3 and 5 that are not larger than the third number.

As an embodiment, the first set of numbers includes 1, 2., N, which is a positive integer no greater than the third number.

As an embodiment, the first set of quantities includes 1, 2.

As an embodiment, the first set of numbers includes 1, 2., N, which is equal to a total number of physical resource blocks included in a frequency domain by the first pool of air interface resources.

As an example, the meaning that the first number of the sentence is related to the first calculation amount includes: the first number is equal to a product of a first number of subcarriers, a first number of UCI symbols, a first modulation order and the first code rate in a first number set, and is not less than a minimum number of the first calculation amount, and a maximum number in the first number set is not more than the third number.

As an embodiment, the meaning that the first number of the sentences is related to the first calculation amount includes: the first number is equal to or greater than the third number and a product of a first number of subcarriers, a first number of UCI symbols, a first modulation order, and the first code rate is not less than a minimum number of the first calculation amount.

As an embodiment, the meaning that the first number of the sentences is related to the first calculation amount includes: the first number is equal to a product of a first number of subcarriers in a first number set, a first number of UCI symbols and a first modulation order, and is not less than a minimum number of the first calculation amount, and a maximum number in the first number set is not more than the third number.

As an example, the meaning that the first number of the sentence is related to the first calculation amount includes: the first number is equal to or greater than the third number and a product of a first number of subcarriers, a first number of UCI symbols, and a first modulation order is no less than a minimum number of the first calculation amount.

As an example, the meaning that the first number of the sentence is related to the first calculation amount includes: the first number is equal to a minimum number of values in a first number set that is not less than a value obtained by dividing the first calculation amount by a first intermediate amount, the first intermediate amount is related to at least one of the first code rate, the first modulation order, the first number of subcarriers, and the first number of UCI symbols, and the maximum number in the first number set is not greater than the third number.

As an example, the meaning that the first number of the sentence is related to the first calculation amount includes: the first number is equal to or less than a minimum number of values obtained by dividing the first calculation amount by a first intermediate amount, where the first intermediate amount is related to at least one of the first code rate, the first modulation order, the first number of subcarriers, and the first number of UCI symbols. .

As an example, one of the numbers in this application is a non-negative integer.

As an example, the first number of subcarriers is used

And (4) showing.

As an embodiment, the number of the first subcarriers is equal to the number of subcarriers included in each resource block minus 4, or is equal to the difference between the number of subcarriers included in each resource block minus 4 divided by the length of one orthogonal cover code.

As a sub-embodiment of the above embodiment, the above-mentioned determination method of the number of first subcarriers is for PUCCH format 2.

As an embodiment, the number of the first subcarriers is equal to the number of subcarriers included in each resource block, or is equal to the number of subcarriers included in each resource block divided by the length of one orthogonal cover code.

As a sub-embodiment of the foregoing embodiment, the manner of determining the number of the first subcarriers is for PUCCH format 3.

As an embodiment, the number of the first subcarriers is equal to the number of subcarriers included in each resource block divided by the length of one orthogonal cover code.

As a sub-embodiment of the above embodiment, the above-mentioned determination method of the number of first subcarriers is for PUCCH format 4.

As an example, the first UCI symbol number is used

And (4) showing.

As an example, the first UCI symbol number is indicated by one nrofSymbols field.

As an embodiment, the first number of UCI symbols is the number of UCI-carrying symbols in PUCCH format 2.

As an embodiment, the first number of UCI symbols is the number of UCI-carrying symbols in PUCCH format 3.

As one embodiment, the first UCI symbol number is the number of symbols except for the symbol used for DM-RS transmission in PUCCH format 3.

As an embodiment, the first number of UCI symbols is the number of UCI-carrying symbols in PUCCH format 4.

As one embodiment, the first UCI symbol number is the number of symbols except for symbols used for DM-RS transmission in PUCCH format 4.

As an embodiment, the first modulation order is Q_mAnd (4) showing.

As an embodiment, for PUCCH format 3 and PUCCH format 4: said first modulation order is equal to 1 if a pi/2-BPSK modulation strategy is used; the first modulation order is equal to 2 if a QPSK modulation strategy is used.

As an embodiment, for PUCCH format 2, the first modulation order is equal to 2.

As an embodiment, the first intermediate quantity is linearly related to at least one of the first code rate, the first modulation order, the first number of subcarriers, and the first number of UCI symbols.

As an embodiment, the first intermediate quantity is equal to a product of the first code rate, the first modulation order, the first number of subcarriers, and the first number of UCI symbols.

As an embodiment, the first intermediate amount is equal to a product of the first modulation order, the first number of subcarriers, and the first number of UCI symbols.

As an embodiment, the first intermediate amount is equal to a product of the first modulation order and the first number of subcarriers.

As an embodiment, the first intermediate amount is equal to a product of the first modulation order and the first number of UCI symbols.

As an embodiment, the first intermediate amount is equal to a product of the first code rate and the first number of UCI symbols.

As an embodiment, the first intermediate amount is equal to a positive integer multiple of the first code rate.

Example 9

Embodiment 9 illustrates a schematic diagram of the relationship between the first parameter value, the given parameter value, the X1 candidate parameter values, and the bit block carried by the first signal according to an embodiment of the present application, as shown in fig. 9.

In example 9, the first parameter value is equal to one of X1 candidate parameter values, said X1 being a positive integer greater than 1; a given parameter value is equal to one of the X1 candidate parameter values, the first parameter value and the given parameter value not being equal being used to determine that the first signal carries the first block of bits and the second block of bits.

As an embodiment, any one of the X1 candidate parameter values is a non-negative integer.

As an embodiment, any one of the X1 candidate parameter values is not less than 0.

As an embodiment, one candidate parameter value of the X1 candidate parameter values is equal to 0.

As an embodiment, the given parameter value is equal to a predefined one of the X1 candidate parameter values.

For one embodiment, the given parameter value is equal to a configurable one of the X1 candidate parameter values.

As an embodiment, the first parameter value is configurable, the first information block being used to indicate the first parameter value from the X1 candidate parameter values.

As an embodiment, the first parameter value is configurable, information blocks other than the first information block being used to indicate the first parameter value from the X1 candidate parameter values.

As an embodiment, the first parameter value is configurable, one DCI being used to indicate the first parameter value from the X1 candidate parameter values.

As an embodiment, the first parameter value and the given parameter value being unequal indicates that the first signal carries the first block of bits and the second block of bits.

As one embodiment, the first parameter value and the given parameter value are not equal to explicitly indicate that the first signal carries the first block of bits and the second block of bits.

As an embodiment, the first parameter value and the given parameter value being unequal implicitly indicate that the first signal carries the first block of bits and the second block of bits.

As an embodiment, the first parameter value and the given parameter value being equal are used to determine that the first signal does not carry the second block of bits.

As an embodiment, the first parameter value and the given parameter value being equal indicates that the first signal does not carry the second block of bits.

As an embodiment, the first parameter value and the given parameter value being equal explicitly indicates that the first signal does not carry the second block of bits.

As an embodiment, equality of the first parameter value and the given parameter value implicitly indicates that the first signal does not carry the second block of bits.

As an embodiment, the first parameter value and the given parameter value being equal are used to determine that the first signal carries only the first bit block of both the first bit block and the second bit block.

As an embodiment, the first parameter value and the given parameter value being equal indicate that the first signal carries only the first block of bits of both the first block of bits and the second block of bits.

As one embodiment, the first parameter value and the given parameter value being equal explicitly indicate that the first signal carries only the first block of bits of both the first block of bits and the second block of bits.

As an embodiment, the first parameter value and the given parameter value being equal implicitly indicate that the first signal carries only the first bit block of both the first bit block and the second bit block.

Example 10

Embodiment 10 illustrates a schematic diagram of a relationship among a priority index of control information bits included in a first bit block, the first index, a priority index of control information bits included in a second bit block, and the second index according to an embodiment of the present application, as shown in fig. 10.

In embodiment 10, the priority index of a control information bit included in a first bit block is equal to a first index, the priority index of a control information bit included in a second bit block is equal to a second index, the first index is a non-negative integer, and the second index is a non-negative integer; the first index and the second index are not equal.

As an embodiment, a priority index of a control information bit included in the first bit block is indicated by one DCI.

As an embodiment, the priority index of the control information bits comprised by the first bit block is configured by higher layer signaling.

As an embodiment, a priority index of the control information bits included in the second bit block is indicated by one DCI.

As an embodiment, the priority index of the control information bits comprised by the second bit block is configured by higher layer signaling.

As an embodiment, the first index is equal to 0 and the second index is equal to 1.

As an embodiment, the first index is equal to 1 and the second index is equal to 0.

As an embodiment, the first Index is a Priority Index (Priority Index) 0, and the second Index is a Priority Index 1.

As an embodiment, the first index is a priority index 1 and the second index is a priority index 0.

For one embodiment, the first index indicates a high priority and the second index indicates a low priority.

For one embodiment, the second index indicates a high priority and the first index indicates a low priority.

For one embodiment, the second index indicates a higher priority than the first index.

For one embodiment, the second index indicates a lower priority than the first index.

As an embodiment, the priority index of the control information bits comprised by the first bit block and the priority index of the control information bits comprised by the second bit block are both physical layer priority indexes.

As an embodiment, the priority index of the control information bits comprised by the first bit block and the priority index of the control information bits comprised by the second bit block are both higher layer priority indexes.

As an embodiment, the first bit block includes a number of control information bits equal to 1, and the second bit block includes a number of control information bits greater than 1.

As an embodiment, the number of control information bits included in the first bit block is greater than 1, and the number of control information bits included in the second bit block is equal to 1.

As an embodiment, the number of control information bits included in the first bit block is greater than 1, and the number of control information bits included in the second bit block is greater than 1.

Example 11

Embodiment 11 illustrates a size relationship between the number of bits included in the second bit block and the first threshold, and a relationship between the manner in which the second bit block is used to generate the first output bit sequence, according to an embodiment of the present application, as shown in fig. 11.

In embodiment 11, the magnitude relation between the number of bits comprised by the second block of bits and the first threshold is used to determine the way in which said second block of bits is used to generate the first output sequence of bits; the first threshold is a non-negative integer, the first threshold is predefined, or the first threshold is configurable, or the first threshold is related to the first parameter value in the present application.

As an embodiment, when the first signal carries the second bit block or a bit block generated by the second bit block, a size relationship between the number of bits comprised by the second bit block and the first threshold is used to determine the way in which the second bit block is used to generate the first output bit sequence.

As an embodiment, when the number of bits included in the second bit block is greater than the first threshold, the second bit block is used to generate a third bit block, the third bit block includes no more bits than the first threshold, the third bit block is used to generate the first output bit sequence through channel coding; when the number of bits comprised by the second block of bits is not greater than the first threshold, the second block of bits is used to generate the first sequence of output bits via channel coding.

As an embodiment, when the number of bits included in the second bit block is smaller than the first threshold, the second bit block is used to generate a third bit block, the number of bits included in the third bit block is not smaller than the first threshold, and the third bit block is used to generate the first output bit sequence through channel coding; when the number of bits included in the second bit block is not less than the first threshold, the second bit block is used to generate the first output bit sequence through channel coding.

As an embodiment, when the number of bits included in the second bit block is not less than the first threshold, the second bit block is used to generate a third bit block, the third bit block includes a number of bits not greater than the first threshold, the third bit block is used to generate the first output bit sequence through channel coding; when the number of bits comprised by the second block of bits is smaller than the first threshold, the second block of bits is used to generate the first output sequence of bits via channel coding.

As an embodiment, when the number of bits included in the second bit block is not greater than the first threshold, the second bit block is used to generate a third bit block, the number of bits included in the third bit block is not less than the first threshold, and the third bit block is used to generate the first output bit sequence through channel coding; when the number of bits comprised by the second block of bits is greater than the first threshold, the second block of bits is used to generate the first sequence of output bits via channel coding.

As an embodiment, the first parameter value is used for determining the first threshold value.

As an embodiment, the first threshold value is the first parameter value.

As an embodiment, the first threshold value is equal to the first parameter value.

As an embodiment, the first threshold value is not the first parameter value.

As an embodiment, the first threshold value is not less than the first parameter value.

As an embodiment, the first threshold value is not greater than the first parameter value.

As an embodiment, the first threshold is equal to 2.

As an embodiment, the first threshold is greater than 2.

As an embodiment, the first threshold is equal to 3.

As one embodiment, the first threshold is greater than 3.

As an embodiment, the first threshold is equal to 4.

As an embodiment, the first threshold is greater than 4.

As one embodiment, the first threshold is a positive integer no greater than 65536.

As an embodiment, the total number of bits comprised by the third block of bits is smaller than the total number of bits comprised by the second block of bits.

As an embodiment, the meaning that the sentence the second bit block is used to generate the third bit block comprises: the third bit block is a sub-block of bits of the second bit block.

As an embodiment, the meaning that the sentence the second bit block is used to generate the third bit block comprises: the third bit block is a bit block obtained by compressing at least bits of the second bit block.

As an embodiment, the meaning that the second bit block is used to generate a third bit block in the sentence includes: the third bit block is: and outputting at least part of bits in the second bit block after at least one of logical AND, logical OR, exclusive OR, repetition and bit deletion operation.

As an embodiment, the meaning that the sentence the second bit block is used to generate the third bit block comprises: the third bit block is: and outputting the second bit block after at least one of repeated operation or zero filling operation of at least partial bits.

As an embodiment, said channel coding of said third bit block of said sentence to generate said first output bit sequence means comprises: one bit subsequence of the first output bit sequence comprises output of the third bit block after partial or all of CRC addition, segmentation, coding block level CRC addition, channel coding, rate matching and concatenation.

As an embodiment, said channel coding of said third bit block of said sentence to generate said first output bit sequence means comprises: and one bit subsequence of the first output bit sequence comprises the output of the third bit block after being subjected to part or all of channel coding, rate matching and concatenation in sequence.

As an embodiment, said channel coding of said third bit block of said sentence to generate said first output bit sequence means comprises: the channel coded output of the third block of bits is used to generate a sub-sequence of bits of the first output bit sequence.

As an embodiment, the channel coding of the second bit block of the sentence used for generating the first output bit sequence may comprise: one bit subsequence of the first output bit sequence comprises output of the second bit block after partial or all of CRC addition, segmentation, coding block level CRC addition, channel coding, rate matching and concatenation.

As an embodiment, the channel coding of the second bit block of the sentence used for generating the first output bit sequence may comprise: and one bit subsequence of the first output bit sequence comprises the output of the second bit block after partial or all of channel coding, rate matching and concatenation.

As an embodiment, the channel coding of the second bit block of the sentence used for generating the first output bit sequence may comprise: the channel coded output of the second block of bits is used to generate a sub-sequence of bits of the first output bit sequence.

Example 12

Embodiment 12 illustrates a schematic diagram of the relationship between the first node/first receiver and the first signaling according to an embodiment of the present application, as shown in fig. 12.

In embodiment 12, the first node/the first receiver in the present application further receives first signaling; the first air interface resource pool in the present application belongs to a first air interface resource pool set, where the first air interface resource pool set includes at least one air interface resource pool, and the first signaling is used to determine the first air interface resource pool from the first air interface resource pool set; the first air interface resource pool set is one of X2 alternative air interface resource pool sets, where X2 is a positive integer greater than 1, and the first information block in this application is used to determine the X2 alternative air interface resource pool sets; at least one of the number of bits included in the first bit block or the number of bits included in the second bit block in this application is used to determine the first air interface resource pool set from the X2 air interface candidate resource pool sets.

As an embodiment, when the first signal carries the first bit block and the second bit block, the number of bits included in the first bit block and the number of bits included in the second bit block (or a bit block generated by the second bit block) are used together to determine the first air interface resource pool set from the X2 candidate air interface resource pool sets; when the first signal carries only the former of the first bit block and the second bit block, the number of bits included in the first bit block is used to determine the first air interface resource pool set from the X2 candidate air interface resource pool sets.

As an embodiment, when the first signal carries the first bit block and the second bit block, the number of bits included in the first bit block and the first parameter value (or the first threshold value in this application) are used together to determine the first air interface resource pool set from the X2 air interface candidate resource pool sets; when the first signal carries only the former of the first bit block and the second bit block, the number of bits included in the first bit block is used to determine the first air interface resource pool set from the X2 candidate air interface resource pool sets.

As an embodiment, the first signaling indicates whether multiplexing between UCI of different priorities is performed.

As an embodiment, the first signaling indicates whether the first signal carries the second bit block.

As an embodiment, the first signaling indicates whether the first signal carries the second bit block or one bit block generated by the second bit block.

As an embodiment, the first signaling is dynamically configured.

As an embodiment, the first signaling comprises layer 1 (L1) signaling.

As an embodiment, the first signaling comprises layer 1 (L1) control signaling.

As one embodiment, the first signaling comprises Physical Layer (Physical Layer) signaling.

As an embodiment, the first signaling comprises one or more fields (fields) in a physical layer signaling.

As an embodiment, the first signaling comprises higher layer (HigherLayer) signaling.

As an embodiment, the first signaling comprises one or more fields in a higher layer signaling.

As an embodiment, the first signaling includes RRC (Radio Resource Control) signaling.

As an embodiment, the first signaling includes MAC CE (media access Control layer Control Element) signaling.

As an embodiment, the first signaling comprises one or more fields in one RRC signaling.

As an embodiment, the first signaling comprises one or more fields in one MAC CE signaling.

As one embodiment, the first signaling includes DCI (Downlink Control Information).

As one embodiment, the first signaling includes one or more fields in one DCI.

As an embodiment, the first signaling is a DCI.

As an embodiment, the first signaling includes SCI (sidelink control Information).

As an embodiment, the first signaling comprises one or more fields in one SCI.

As an embodiment, the first signaling comprises one or more fields in an IE (Information Element).

As an embodiment, the first signaling is a DownLink scheduling signaling (DownLink Grant signaling).

As an embodiment, the first signaling is an UpLink scheduling signaling (UpLink Grant signaling).

As an embodiment, the first signaling is transmitted on a downlink physical layer control channel (i.e. a downlink channel that can only be used to carry physical layer signaling).

As an embodiment, the Downlink Physical layer Control CHannel in the present application is a PDCCH (Physical Downlink Control CHannel).

As an embodiment, the downlink physical layer control channel in the present application is an sPDCCH (short PDCCH).

As an embodiment, the downlink physical layer control channel in this application is NB-PDCCH (Narrow Band PDCCH).

As an embodiment, the first signaling is DCI format 1 \u0, and the specific definition of the DCI format 1 \u0 is described in section 7.3.1.2 of 3gpp ts38.212.

As an embodiment, the first signaling is DCI format 1 \u1, and the specific definition of the DCI format 1 \u1 is described in section 7.3.1.2 of 3gpp ts38.212.

As an embodiment, the first signaling is DCI format 1 \u2, and the specific definition of the DCI format 1 \u2 is described in section 7.3.1.2 of 3gpp ts38.212.

As an example, the first signaling is DCI format 0 \u0, and the specific definition of DCI format 0 \u0 is referred to in section 7.3.1.1 of 3gpp ts 38.212.

As an embodiment, the first signaling is DCI format 0 \u1, and the specific definition of the DCI format 0 \u1 is described in section 7.3.1.1 in 3gpp ts38.212.

As an example, the first signaling is DCI format 0 \u2, and the specific definition of DCI format 0 \u2 is referred to in section 7.3.1.1 of 3gpp ts 38.212.

As an embodiment, the first signaling indicates transmission of one PDSCH, and the first bit block includes HARQ-ACK information bits corresponding to the one PDSCH.

As an embodiment, the first signaling indicates transmission of one PDSCH, and the second bit block includes HARQ-ACK information bits corresponding to the one PDSCH.

As an embodiment, the first information block in this application indicates the X2 candidate air interface resource pool sets.

As an embodiment, a domain included in the first information block in the present application configures the X2 spare air interface resource pool sets.

As an example, the expression in the claims that at least one of the number of bits included in the first bit block in the present application or the number of bits included in the second bit block in the present application is used to determine the first air interface resource pool set from the X2 air interface candidate resource pool sets includes the following meanings: the number of bits included in the first bit block and the first parameter value in this application are used together to determine the first air interface resource pool set from the X2 candidate air interface resource pool sets.

As a sub-embodiment of the foregoing embodiment, an X2 number range corresponds to the X2 candidate empty resource pool sets, respectively, a sum of a number of bits included in the first bit block and the first parameter value in this application belongs to a first number range in the X2 number range, and the first empty resource pool set is an empty resource pool in the X2 candidate empty resource pool sets, which corresponds to the first number range.

As a sub-embodiment of the foregoing embodiment, an X2 number range corresponds to the X2 candidate empty resource pool sets, respectively, a sum of a number of bits included in the first bit block, a number of corresponding CRC bits, and the first parameter value in this application belongs to a first number range in the X2 number range, and the first empty resource pool set is an empty resource pool in the X2 candidate empty resource pool sets, which corresponds to the first number range.

As an embodiment, the statement in the claims that at least one of the number of bits included in the first bit block in the present application or the number of bits included in the second bit block in the present application is used to determine the first air interface resource pool set from the X2 alternative air interface resource pool sets includes the following meanings: the number of bits included in the first bit block is used to determine the first air interface resource pool set from the X2 candidate air interface resource pool sets.

As a sub-embodiment of the foregoing embodiment, an X2 number range corresponds to the X2 candidate air interface resource pool sets, respectively, the number of bits included in the first bit block belongs to a first number range in the X2 number range, and the first air interface resource pool set is an air interface resource pool in the X2 candidate air interface resource pool sets, which corresponds to the first number range.

As a sub-embodiment of the foregoing embodiment, an X2 number range corresponds to the X2 candidate empty resource pool sets, respectively, the number of bits included in the first bit block and the number of corresponding CRC bits belong to a first number range in the X2 number range, and the first empty resource pool set is an empty resource pool in the X2 candidate empty resource pool sets, which corresponds to the first number range.

As an example, the expression in the claims that at least one of the number of bits included in the first bit block in the present application or the number of bits included in the second bit block in the present application is used to determine the first air interface resource pool set from the X2 air interface candidate resource pool sets includes the following meanings: the number of bits included in the first bit block and the number of bits included in the second bit block (or one bit block generated by the second bit block) are used together to determine the first air interface resource pool set from the X2 air interface candidate resource pool sets.

As a sub-embodiment of the foregoing embodiment, X2 number ranges respectively correspond to the X2 candidate empty resource pool sets, a sum of a number of bits included in the first bit block and a number of bits included in the second bit block (or a bit block generated by the second bit block) belongs to a first number range in the X2 number ranges, and the first empty resource pool set is an empty resource pool in the X2 candidate empty resource pool sets, which corresponds to the first number range.

As a sub-embodiment of the foregoing embodiment, the X2 number ranges respectively correspond to the X2 candidate pool sets, a sum of a number of bits included in the first bit block and a number of corresponding CRC bits, and a number of bits included in the second bit block (or a bit block generated by the second bit block) and a number of corresponding CRC bits belongs to a first number range in the X2 number ranges, and the first pool set is a pool corresponding to the first number range in the X2 candidate pool sets.

As an example, the expression in the claims that at least one of the number of bits included in the first bit block in the present application or the number of bits included in the second bit block in the present application is used to determine the first air interface resource pool set from the X2 air interface candidate resource pool sets includes the following meanings: the number of bits included in the first bit block, the first parameter value in the present application, and the first code rate in the present application are used together to determine the first air interface resource pool set from the X2 candidate air interface resource pool sets.

As an example, the expression in the claims that at least one of the number of bits included in the first bit block in the present application or the number of bits included in the second bit block in the present application is used to determine the first air interface resource pool set from the X2 air interface candidate resource pool sets includes the following meanings: the number of bits included in the first bit block and the first threshold in this application are used together to determine the first air interface resource pool set from the X2 candidate air interface resource pool sets.

As an embodiment, the first information block in this application is used to determine X3 spare air interface resource pools, where X3 is a positive integer greater than 1; at least one of the number of bits included in the first bit block or the number of bits included in the second bit block in this application is used to determine the first air interface resource pool from the X3 air interface candidate resource pools.

As an example, the expression in the claims that at least one of the number of bits included in the first bit block in the present application or the number of bits included in the second bit block in the present application is used to determine the first air interface resource pool from the X3 air interface candidate resource pools includes the following meanings: the sum of the number of bits included in the first bit block and the first parameter value in this application is used to indicate the first air interface resource pool from the X3 candidate air interface resource pools.

As an example, the expression in the claims that at least one of the number of bits included in the first bit block in the present application or the number of bits included in the second bit block in the present application is used to determine the first air interface resource pool from the X3 air interface candidate resource pools includes the following meanings: the number of bits included in the first bit block, the first parameter value in the present application, and the first code rate in the present application are used together to indicate the first air interface resource pool from the X3 alternative air interface resource pools.

As an embodiment, the statement in the claims that at least one of the number of bits included in the first bit block in the present application or the number of bits included in the second bit block in the present application is used to determine the first air interface resource pool from the X3 air interface resource pools includes the following meanings: the sum of the number of bits included in the first bit block and the number of bits included in the second bit block (or one bit block generated by the second bit block) is used to indicate the first air interface resource pool from the X3 air interface candidate resource pools.

Example 13

Embodiment 13 is a block diagram illustrating a processing apparatus in a first node device, as shown in fig. 13. In fig. 13, a first node device processing apparatus 1300 includes a first receiver 1301 and a first transmitter 1302.

For one embodiment, the first node apparatus 1300 is a user equipment.

As an embodiment, the first node apparatus 1300 is a relay node.

As an embodiment, the first node apparatus 1300 is an in-vehicle communication apparatus.

For one embodiment, the first node apparatus 1300 is a user equipment supporting V2X communication.

As an embodiment, the first node apparatus 1300 is a relay node supporting V2X communication.

For one embodiment, the first receiver 1301 includes at least one of the antenna 452, the receiver 454, the multi-antenna receive processor 458, the receive processor 456, the controller/processor 459, the memory 460, and the data source 467 of fig. 4.

For one embodiment, the first receiver 1301 includes at least the first five of the antenna 452, the receiver 454, the multi-antenna receive processor 458, the receive processor 456, the controller/processor 459, the memory 460, and the data source 467 of fig. 4.

For one embodiment, the first receiver 1301 includes at least the first four of the antenna 452, the receiver 454, the multi-antenna receive processor 458, the receive processor 456, the controller/processor 459, the memory 460, and the data source 467 of fig. 4.

For one embodiment, the first receiver 1301 includes at least the first three of the antenna 452, the receiver 454, the multi-antenna receive processor 458, the receive processor 456, the controller/processor 459, the memory 460, and the data source 467 of fig. 4.

For one embodiment, the first receiver 1301 includes at least two of the antenna 452, the receiver 454, the multi-antenna receive processor 458, the receive processor 456, the controller/processor 459, the memory 460, and the data source 467 of fig. 4.

For one embodiment, the first transmitter 1302 includes at least one of the antenna 452, the transmitter 454, the multi-antenna transmitter processor 457, the transmit processor 468, the controller/processor 459, the memory 460, and the data source 467 of fig. 4 of the present application.

For one embodiment, the first transmitter 1302 includes at least the first five of the antenna 452, the transmitter 454, the multi-antenna transmitter processor 457, the transmit processor 468, the controller/processor 459, the memory 460, and the data source 467 of fig. 4 of the present application.

For one embodiment, the first transmitter 1302 includes at least the first four of the antenna 452, the transmitter 454, the multi-antenna transmitter processor 457, the transmit processor 468, the controller/processor 459, the memory 460, and the data source 467 of fig. 4 of the present application.

For one embodiment, the first transmitter 1302 includes at least three of the antenna 452, the transmitter 454, the multi-antenna transmitter processor 457, the transmit processor 468, the controller/processor 459, the memory 460, and the data source 467 of fig. 4.

For one embodiment, the first transmitter 1302 includes at least two of the antenna 452, the transmitter 454, the multi-antenna transmitter processor 457, the transmit processor 468, the controller/processor 459, the memory 460, and the data source 467 of fig. 4 of the present application.

In embodiment 13, the first receiver 1301 receives a first information block, the first information block being used to determine a first pool of empty resources; the first transmitter 1302, configured to transmit a first signal, the first signal being used to carry a first bit block, the first bit block comprising at least one control information bit; the air interface resources occupied by the first signal belong to the first air interface resource pool, the number of the physical resource blocks occupied by the first signal in the frequency domain is equal to a first number, and the first number is not greater than the number of the physical resource blocks included by the first air interface resource pool in the frequency domain; the number of bits comprised by the first block of bits is used to determine the first number, the first number being a positive integer; the second bit block comprises at least one control information bit, and the category of the control information bit contained in the first bit block is different from that of the control information bit contained in the second bit block; a second number is related to the second block of bits, the second number being used to determine a starting physical resource block occupied by the first signal in the frequency domain, the second number being a non-negative integer.

As an embodiment, the second number is equal to the number of bits carried by the first signal and related to the second bit block, or the second number is equal to the number of bits included in one bit block generated by the second bit block.

As an embodiment, the second quantity belongs to one of a plurality of value intervals, any one of which includes at least one non-negative integer; the plurality of value intervals comprise a first value interval and a second value interval; any two value intervals in the plurality of value intervals are orthogonal to each other; when the second number belongs to the first numerical interval, the index of the initial physical resource block occupied by the first signal in the frequency domain is a first physical resource block index; when the second number belongs to the second numerical interval, the index of the initial physical resource block occupied by the first signal in the frequency domain is equal to the index of the first physical resource block plus a first offset; the plurality of value intervals are predefined or configurable, the first physical resource block index is predefined or configurable, and the first offset is predefined or configurable.

As an embodiment, at least the former of both the first bit block and the second bit block is used to generate a first output bit sequence comprising a positive integer number of bits greater than 1; the first output bit sequence comprises a number of bits that is linearly related to the first number, the first output bit sequence being used for generating the first signal.

As an embodiment, the number of bits comprised by the first bit block and a first parameter value are together used for determining the first number; the first parameter value is a predefined or configurable non-negative number or the first parameter value is related to the second block of bits.

As an embodiment, the priority index of the control information bits included in the first bit block is equal to a first index, the priority index of the control information bits included in the second bit block is equal to a second index, the first index is a non-negative integer, and the second index is a non-negative integer; the first index and the second index are not equal; the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block is greater than 2.

As an embodiment, a size relationship between a number of bits comprised by the second block of bits and a first threshold is used to determine a manner in which the second block of bits is used to generate the first sequence of output bits, the first threshold being a non-negative integer; the first threshold value is predefined, or the first threshold value is configurable, or the first threshold value is related to a first parameter value.

Example 14

Embodiment 14 is a block diagram illustrating a processing apparatus in a second node device, as shown in fig. 14. In fig. 14, a second node device processing apparatus 1400 comprises a second transmitter 1401 and a second receiver 1402.

For one embodiment, the second node device 1400 is a user device.

As an embodiment, the second node apparatus 1400 is a base station.

As an embodiment, the second node device 1400 is a relay node.

As an embodiment, the second node device 1400 is a vehicle communication device.

For one embodiment, the second node device 1400 is a user equipment supporting V2X communication.

For one embodiment, the second transmitter 1401 includes at least one of the antenna 420, the transmitter 418, the multi-antenna transmit processor 471, the transmit processor 416, the controller/processor 475, and the memory 476 of fig. 4 of the present application.

For one embodiment, the second transmitter 1401 includes at least the first five of the antenna 420, the transmitter 418, the multi-antenna transmit processor 471, the transmit processor 416, the controller/processor 475, and the memory 476 of fig. 4 of the present application.

For one embodiment, the second transmitter 1401 includes at least the first four of the antenna 420, the transmitter 418, the multi-antenna transmit processor 471, the transmit processor 416, the controller/processor 475, and the memory 476 of fig. 4 of the present application.

As an example, the second transmitter 1401 includes at least the first three of the antenna 420, the transmitter 418, the multi-antenna transmit processor 471, the transmit processor 416, the controller/processor 475, and the memory 476 of fig. 4 of the present application.

As an example, the second transmitter 1401 includes at least two of the antenna 420, the transmitter 418, the multi-antenna transmit processor 471, the transmit processor 416, the controller/processor 475, and the memory 476 of fig. 4 of the present application.

For one embodiment, the second receiver 1402 includes at least one of the antenna 420, the receiver 418, the multiple antenna receive processor 472, the receive processor 470, the controller/processor 475, and the memory 476 of fig. 4 of the present application.

For one embodiment, the second receiver 1402 includes at least the first five of the antenna 420, the receiver 418, the multiple antenna receive processor 472, the receive processor 470, the controller/processor 475, and the memory 476 of fig. 4 of the present application.

For one embodiment, the second receiver 1402 includes at least the first four of the antenna 420, the receiver 418, the multiple antenna receive processor 472, the receive processor 470, the controller/processor 475, and the memory 476 of fig. 4 of the present application.

For one embodiment, the second receiver 1402 includes at least the first three of the antenna 420, the receiver 418, the multi-antenna receive processor 472, the receive processor 470, the controller/processor 475, and the memory 476 of fig. 4.

For one embodiment, the second receiver 1402 includes at least two of the antenna 420, the receiver 418, the multiple antenna receive processor 472, the receive processor 470, the controller/processor 475, and the memory 476 of fig. 4 of the present application.

In embodiment 14, the second transmitter 1401, transmits a first information block, the first information block being used to determine a first pool of empty resources; the second receiver 1402, receiving a first signal, the first signal being used to carry a first bit block, the first bit block comprising at least one control information bit; the air interface resources occupied by the first signal belong to the first air interface resource pool, the number of the physical resource blocks occupied by the first signal in the frequency domain is equal to a first number, and the first number is not greater than the number of the physical resource blocks included by the first air interface resource pool in the frequency domain; the number of bits comprised by the first block of bits is used to determine the first number, the first number being a positive integer; the second bit block comprises at least one control information bit, and the category of the control information bit contained in the first bit block is different from that of the control information bit contained in the second bit block; a second number is related to the second block of bits, the second number being used to determine a starting physical resource block occupied by the first signal in the frequency domain, the second number being a non-negative integer.

As an embodiment, the second number belongs to one of a plurality of value intervals, any one of the plurality of value intervals comprising at least one non-negative integer; the plurality of numerical intervals comprise a first numerical interval and a second numerical interval; any two value intervals in the plurality of value intervals are orthogonal to each other; when the second number belongs to the first value interval, the index of the initial physical resource block occupied by the first signal in the frequency domain is a first physical resource block index; when the second number belongs to the second numerical interval, the index of the initial physical resource block occupied by the first signal in the frequency domain is equal to the index of the first physical resource block plus a first offset; the plurality of value intervals are predefined or configurable, the first physical resource block index is predefined or configurable, and the first offset is predefined or configurable.

As an embodiment, at least the former of both the first bit block and the second bit block is used to generate a first output bit sequence comprising a positive integer number of bits greater than 1; the number of bits comprised by the first output bit sequence and the first number are linearly related, the first output bit sequence being used for generating the first signal.

As an embodiment, the priority index of the control information bits comprised by the first bit block is equal to a first index, the priority index of the control information bits comprised by the second bit block is equal to a second index, the first index is a non-negative integer, the second index is a non-negative integer; the first index and the second index are not equal; the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block is greater than 2.

It will be understood by those skilled in the art that all or part of the steps of the above methods may be implemented by instructing relevant hardware through a program, and the program may be stored in a computer readable storage medium, such as a read-only memory, a hard disk or an optical disk. Alternatively, all or part of the steps of the above embodiments may be implemented by using one or more integrated circuits. Accordingly, the module units in the above embodiments may be implemented in a hardware form, or may be implemented in a form of software functional modules, and the present application is not limited to any specific form of combination of software and hardware. First node equipment in this application includes but not limited to cell-phone, panel computer, notebook, network card, low-power consumption equipment, eMTC equipment, NB-IoT equipment, vehicle communication equipment, aircraft, unmanned aerial vehicle, wireless communication equipment such as telecontrolled aircraft. The second node device in the application includes but is not limited to wireless communication devices such as cell-phones, tablet computers, notebooks, network access cards, low power consumption devices, eMTC devices, NB-IoT devices, vehicle-mounted communication devices, aircrafts, airplanes, unmanned aerial vehicles, and remote control airplanes. User equipment or UE or terminal in this application include but not limited to cell-phone, panel computer, notebook, network card, low-power consumption equipment, eMTC equipment, NB-IoT equipment, vehicle communication equipment, aircraft, unmanned aerial vehicle, wireless communication equipment such as remote control aircraft. The base station device, the base station or the network side device in the present application includes, but is not limited to, a macro cell base station, a micro cell base station, a home base station, a relay base station, an eNB, a gNB, a transmission and reception node TRP, a GNSS, a relay satellite, a satellite base station, an air base station, a testing apparatus, a testing device, a testing instrument, and other devices.

The above description is only a preferred embodiment of the present application, and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A first node device for wireless communication, comprising:

a first transmitter to transmit a first signal, the first signal being used to carry a first bit block, the first bit block comprising at least one control information bit;

2. The first node device of claim 1, wherein the second number is equal to a number of bits carried by the first signal related to the second bit block, or wherein the second number is equal to a number of bits included in one bit block generated by the second bit block.

3. The first node apparatus of claim 1 or 2, wherein the second quantity belongs to one of a plurality of value intervals, any one of the plurality of value intervals comprising at least one non-negative integer; the plurality of numerical intervals comprise a first numerical interval and a second numerical interval; any two value intervals in the plurality of value intervals are orthogonal to each other; when the second number belongs to the first value interval, the index of the initial physical resource block occupied by the first signal in the frequency domain is a first physical resource block index; when the second number belongs to the second numerical interval, the index of the initial physical resource block occupied by the first signal in the frequency domain is equal to the index of the first physical resource block plus a first offset; the plurality of value intervals are predefined or configurable, the first physical resource block index is predefined or configurable, and the first offset is predefined or configurable.

4. The first node device of any of claims 1-3, wherein at least the former of the first bit block and the second bit block are used to generate a first output bit sequence comprising a positive integer number of bits greater than 1; the number of bits comprised by the first output bit sequence and the first number are linearly related, the first output bit sequence being used for generating the first signal.

5. The first node device of any of claims 1 to 4, wherein the number of bits comprised by the first block of bits and a first parameter value are used together to determine the first number; the first parameter value is a predefined or configurable non-negative number or the first parameter value is related to the second block of bits.

6. The first node device of any of claims 1-5, wherein the priority index of the control information bits comprised by the first block of bits is equal to a first index, wherein the priority index of the control information bits comprised by the second block of bits is equal to a second index, wherein the first index is a non-negative integer and wherein the second index is a non-negative integer; the first index and the second index are not equal; the sum of the number of control information bits included in the first bit block and the number of control information bits included in the second bit block is greater than 2.

7. The first node device of any of claims 1-6, wherein a size relationship between a number of bits comprised by the second block of bits and a first threshold is used to determine a manner in which the second block of bits is used to generate the first sequence of output bits, the first threshold being a non-negative integer; the first threshold is predefined, or the first threshold is configurable, or the first threshold is related to a first parameter value.

8. A second node device configured for wireless communication, comprising:

9. A method in a first node used for wireless communication, comprising:

transmitting a first signal, the first signal being used to carry a first bit block, the first bit block comprising at least one control information bit;

10. A method in a second node used for wireless communication, comprising: