CN115276660A

CN115276660A - Digital-to-analog converter sampling rate switching device and control system, method and chip thereof

Info

Publication number: CN115276660A
Application number: CN202210951048.5A
Authority: CN
Inventors: 王硕; 黄斌
Original assignee: Chinainstru and Quantumtech Hefei Co Ltd
Current assignee: Chinainstru and Quantumtech Hefei Co Ltd
Priority date: 2022-08-09
Filing date: 2022-08-09
Publication date: 2022-11-01

Abstract

The application discloses a digital-to-analog converter sampling rate switching device, a control system, a method and a chip, wherein the device comprises: the device comprises a clock generation module, a configuration module and a protocol establishment module; the device comprises a clock generation module, a protocol establishment module and a digital-to-analog converter, wherein the clock generation module is used for generating a first clock signal, a second clock signal and a synchronous pulse signal, supplying the first clock signal to the digital-to-analog converter, supplying the second clock signal to the configuration module and respectively supplying the synchronous pulse signal to the protocol establishment module and the digital-to-analog converter, and the first clock signal and the second clock signal are determined according to the target sampling rate of the digital-to-analog converter; the configuration module is used for outputting a target line rate corresponding to the target sampling rate according to the second clock signal; and the protocol establishing module is used for establishing a JESD204B protocol according to the target line rate and the synchronous pulse signal, and realizing that the digital-to-analog converter switches from the current sampling rate to the target sampling rate for data transmission. The device can realize flexible conversion of the sampling rate of the digital-to-analog converter by adjusting the configuration of related parameters and does not occupy storage space.

Description

Digital-to-analog converter sampling rate switching device and control system, method and chip thereof

Technical Field

The present application relates to the field of electronic devices, and in particular, to a sample rate switching device, a control system, a method, and a chip for a digital-to-analog converter based on JESD 204B.

Background

Digital-to-analog converters (DACs) are one of the important interface circuits in modern digital circuits, and are widely used in the fields of communication, audio, video, and other applications. The sampling rate, which is an important technical index of DAC operation, indicates the number of samples that can be sampled in a given time interval, and determines the maximum frequency component of the DAC output signal. Only a small part of products in the market can provide sampling rate switching at present, and most of technical schemes are adjusted through interpolation, on one hand, the variable sampling rate which can be provided by the scheme is in an even-number multiple relation, on the other hand, due to the interpolation, the storage space which is actually used while the sampling rate is reduced is not reduced, and therefore the maximum storage and playing time is reduced in a phase-changing manner.

Disclosure of Invention

The present application is directed to solving, at least in part, one of the technical problems in the related art.

To this end, the first objective of the present application is to provide a sampling rate switching apparatus of digital-to-analog converter based on JESD 204B. The device can realize the flexible switching of the sampling rate of the digital-to-analog converter by adjusting the related clock frequency and the related parameter configuration of the JESD204B protocol, and has larger storage and playing time under the condition of fixed storage space.

A second objective of the present application is to provide a field programmable gate array chip.

A third objective of the present application is to provide a control system of a sample rate switching device of a digital-to-analog converter based on JESD 204B.

A fourth objective of the present application is to provide a method for controlling a sample rate switching device of a digital-to-analog converter based on JESD 204B.

In order to achieve the above object, a JESD 204B-based sampling rate switching apparatus according to an embodiment of the first aspect of the present application includes: the system comprises a clock generation module, a configuration module and a protocol establishment module, wherein the clock generation module is respectively connected with the configuration module and the protocol establishment module, and the configuration module is connected with the protocol establishment module; the clock generation module is configured to generate a first clock signal, a second clock signal, and a synchronization pulse signal, provide the first clock signal to a digital-to-analog converter, provide the second clock signal to the configuration module, and provide the synchronization pulse signal to the protocol establishment module and the digital-to-analog converter, respectively, where the first clock signal and the second clock signal are determined according to a target sampling rate of the digital-to-analog converter; the configuration module is used for outputting a target line rate corresponding to the target sampling rate according to the second clock signal; the protocol establishing module is used for establishing a JESD204B protocol according to the target line rate and the synchronous pulse signal, and realizing that the digital-to-analog converter is switched from the current sampling rate to the target sampling rate for data transmission.

According to the sampling rate switching device of the digital-to-analog converter based on the JESD204B, clock signals required by all modules can be generated through the clock generation module, the target line rate corresponding to the target sampling rate is generated according to the configuration module, and the JESD204B protocol is reestablished through the protocol establishment module, so that flexible switching of digital-to-analog converter variable sampling is achieved, and meanwhile, the storage and playing time is longer under the condition that the storage space is fixed.

In order to achieve the above object, a field programmable gate array chip provided in an embodiment of the second aspect of the present application includes a JESD 204B-based digital-to-analog converter sampling rate switching apparatus described in the above embodiment of the present application.

In order to achieve the above object, a control system for a sampling rate switching device of a digital-to-analog converter based on JESD204B according to an embodiment of the third aspect of the present application includes: the digital-to-analog converter and the field programmable gate array chip described in the above embodiments adopt the JESD204B protocol for data transmission.

In order to achieve the above object, a method for controlling a sample rate switching device of a digital-to-analog converter based on JESD204B according to an embodiment of the present application is characterized in that the sample rate switching device of the digital-to-analog converter based on FPGA includes a clock generation module, a configuration module, and a protocol establishment module, and the method includes: determining a target sampling rate; generating a first clock signal and a second clock signal according to the target sampling rate through the clock generation module, providing the first clock signal to a digital-to-analog converter, and providing the second clock signal to the configuration module; outputting a target line rate corresponding to the target sampling rate through the configuration module according to the second clock signal, and providing the target line rate to the protocol establishing module; generating a synchronous pulse signal through the clock generation module, and respectively providing the synchronous pulse signal to the digital-to-analog converter and the protocol establishment module; and establishing a JESD204B protocol by the protocol establishing module according to the target line rate and the synchronous pulse signal, and realizing that the digital-to-analog converter is switched from the current sampling rate to the target sampling rate for data transmission.

According to the control method of the sampling rate switching device of the digital-to-analog converter based on the JESD204B, the first clock signal for configuring the digital-to-analog converter and the second clock signal for configuring the field programmable gate array chip are obtained by determining the target sampling rate, the related configuration parameters can be obtained according to the second clock signal and the target sampling rate, and finally, the JESD204B protocol is reestablished, so that the digital-to-analog converter is switched from the current sampling rate to the target sampling rate for data transmission, the flexible switching of variable sampling of the digital-to-analog converter is completed, and meanwhile, the storage and playing time is longer under the condition that the storage space is fixed.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

FIG. 1 is a block diagram of a JESD204B based sampling rate switching apparatus of a digital-to-analog converter according to one embodiment of the present application;

FIG. 2 is a block diagram of a JESD204B based sampling rate switching apparatus of a digital to analog converter according to an embodiment of the present application;

FIG. 3 is a block diagram of a configuration module according to one embodiment of the present application;

FIG. 4 is a block diagram of a configuration module according to a first embodiment of the present application;

FIG. 5 is a block diagram of a configuration module according to a second embodiment of the present application;

FIG. 6 is a block diagram of a configuration module according to a third embodiment of the present application;

FIG. 7 is a block diagram of a control system of a JESD204B based sampling rate switching device of a digital-to-analog converter according to an embodiment of the present application;

fig. 8 is a flowchart of a control method of a sampling rate switching device of a digital-to-analog converter based on JESD204B according to an embodiment of the present application.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.

The following describes a sampling rate switching device of a digital-to-analog converter, and a control system, a method and a chip thereof according to an embodiment of the present application with reference to fig. 1 to 8.

Fig. 1 is a block diagram of a JESD 204B-based sampling rate switching apparatus of a digital-to-analog converter according to an embodiment of the present application.

As shown in fig. 1, the JESD 204B-based digital-to-analog converter sampling rate switching apparatus 1000 may include: clock generation module 100, configuration module 200, protocol establishment module 300. The clock generation module 100 is connected to the configuration module 200 and the protocol establishment module 300 respectively, and the configuration module 200 is connected to the protocol establishment module 300.

Referring to fig. 2, the clock generation module 100 is configured to generate a first clock signal DAC _ DCLK, a second clock signal FPGA _ DCLK, and a synchronization pulse signal SYSREF, provide the first clock signal to a digital-to-analog converter (DAC), provide the second clock signal FPGA _ DCLK to the configuration module 200, and provide the synchronization pulse signal SYSREF to the protocol establishment module 300 and the digital-to-analog converter (providing the signal labeled as FPGA _ SYSREF of the protocol establishment module 300 and the signal labeled as DAC _ SYSREF of the DAC), respectively, where the first clock signal DAC _ DCLK and the second clock signal FPGA _ DCLK are determined according to a target sampling rate of the digital-to-analog converter; the configuration module 200 is configured to output a target line rate corresponding to the target sampling rate according to the second clock signal FPGA _ DCLK; the protocol establishing module 300 is configured to establish a JESD204B protocol according to the target line rate and the synchronization pulse signal FPGA _ SYSREF, and implement data transmission by switching the digital-to-analog converter from the current sampling rate to the target sampling rate.

It can be understood that the JESD204B protocol is a high-speed serial interface for connecting a digital-to-analog converter (DAC) and a field programmable gate array chip (FPGA), supports a serial data rate of up to 12.5Gbps, and is a preferred interface protocol for data transmission between a data converter and the FPGA. The JESD204B protocol uses the edge of a clock signal to identify the start of synchronization, and uses a certain handshake signal to enable both the transmitter and the receiver to correctly identify the length and the boundary of a frame, so the clock signal and its timing relationship are very important for the JESD 204B.

In this embodiment, the clock generating module 100 generates the clock signals required by the respective modules, and specifically, the first clock signal DAC _ DCLK generated by the clock generating module 100 is used for providing to the digital-to-analog converter DAC, and the second clock signal FPGA _ DCLK is provided to the configuration module 200, where the configuration module 200 is located in the field programmable gate array chip FPGA, i.e., the clock generating module 100 is used for providing to the digital-to-analog converter DAC and the field programmable gate array chip FPGA sampling clock. Secondly, the JESD204B protocol recognizes the start of synchronization by the edge of the clock signal, and after all internal clocks in the FPGA chip and the digital-to-analog converter are ready, the clock generation module 100 generates two synchronized pulse signals (FPGA _ SYSREF and DAC _ SYSREF) to be respectively provided to the protocol establishing module 300 and the digital-to-analog converter, so as to establish a Frame clock and an LFMC (local multi-Frame clock) during the JESD204B protocol. The establishment of the JESD204B protocol is realized after the Frame clock and the LFMC are aligned.

Exemplarily, in this embodiment, a corresponding relationship between the sampling rate and the first clock signal DAC _ DCLK and the second clock signal FPGA _ DCLK may be pre-established and stored, and then the first clock signal DAC _ DCLK required by the digital-to-analog converter and the second clock signal FPGA _ DCLK required by the configuration module 200 in the programmable gate array chip may be obtained according to the target sampling rate required to be switched according to the corresponding relationship. Wherein the corresponding relationship may be stored in a table form.

Further, the configuration module 200 outputs the target line rate according to the second clock signal FPGA _ DCLK after receiving the second clock signal FPGA _ DCLK, so as to provide the target line rate in the JESD204B protocol.

After the target sampling rate is output and the sampling clock of the digital-to-analog converter and the sampling clock of the programmable gate array chip are prepared, when the protocol establishing module 300 receives the synchronous pulse signal FPGA _ SYSREF provided by the clock generating module 100 and the digital-to-analog converter receives the synchronous pulse signal DAC _ SYSREF provided by the clock generating module 100, the JESD204B protocol is established, so that the digital-to-analog converter is switched from the current sampling rate to the target sampling rate for data transmission.

FIG. 3 is a block diagram of a configuration module according to one embodiment of the present application.

As shown in fig. 3, the configuration module 200 includes a phase detector 201, a voltage controlled oscillator 202, and a first frequency divider 203. A first input end of the phase detector 201 is connected to the clock generation module 100, a second input end of the phase detector 201 is connected to an output end of the first frequency divider203, an output end of the phase detector 201 is connected to an input end of the voltage controlled oscillator 202, and an output end of the voltage controlled oscillator 202 is connected to an input end of the first frequency divider203 and the protocol establishment module 300.

The phase detector 201 is configured to phase-detect the second clock signal FPGA _ DCLK and the first frequency-divided signal output by the first frequency divider 203; the voltage-controlled oscillator 202 is used for generating a third clock signal with corresponding frequency according to the phase discrimination result; the first frequency divider203 is configured to perform frequency division processing on the third clock signal by using the first frequency division parameter to obtain a first frequency division signal.

Further, the protocol establishing module 300 is configured to establish the JESD204B protocol when the voltage-controlled oscillator 203 outputs the stable third clock signal.

It will be appreciated that the first frequency divider203 is located between the input of the phase detector 201 and the output of the voltage controlled oscillator 202 to form a feedback loop with the phase detector 201 and the voltage controlled oscillator 202.

Specifically, a first input end of the phase detector 201 receives a second clock signal FPGA _ DCLK generated by the clock generation module 100, a second input end of the phase detector 201 receives a signal subjected to frequency division processing by the first frequency divider203, the phase detector 201 compares frequencies of signals of a feedback loop formed by the input second clock signal FPGA _ DCLK and the first frequency divider203, outputs a signal representing a phase difference between the two signals, and uses the signal as an input signal of the voltage controlled oscillator 202, and the phase detector 201 performs phase discrimination on the signal of the phase difference between the two signals to control the frequency of an output signal of the voltage controlled oscillator. The input end of the voltage-controlled oscillator 202 is connected with the output end of the phase detector 201, and a periodic signal with corresponding frequency is output according to the signal output by the phase detector 201. The input of the first frequency divider203 is connected to the output of the voltage controlled oscillator 202, which is reduced to the same level as the second time signal and then input to the phase detector 201 for comparison of the two signals.

It can be understood that the output signal of the voltage controlled oscillator 202 is divided by the first frequency divider203 and then input to the phase detector 201 together with the second clock signal FPGA _ DCLK, the phase detector 201 outputs a signal representing the two differences by comparing the frequency difference between the two signals, and the frequency of the signal is changed by the voltage controlled oscillator 202, so as to achieve the stability of the output of the voltage controlled oscillator 202. The second clock signal FPGA _ DCLK is generated by the clock generation module 100, and is used as a crystal oscillator with stable frequency, and is compared with a signal generated by an oscillation circuit inside the configuration module 200 after frequency division, so that the frequency of the signal output by the configuration module 200 is stable.

Fig. 4 is a block diagram of a configuration module according to a first embodiment of the present application.

As shown in fig. 4, the configuration module 200 may further include: the second frequency divider204 is connected between the clock generating module 100 and the first input end of the phase detector 201, and configured to perform frequency division processing on the second clock signal FPGA _ DCLK by using a second frequency dividing parameter.

Specifically, the second frequency divider204 is configured to perform frequency division processing on the second clock signal FPGA _ DCLK generated by the clock generation module 100, and perform phase detection on the signal subjected to frequency division processing by the first frequency divider203 through the phase detector 201 together with the signal subjected to frequency division processing by the first frequency divider 203.

Fig. 5 is a block diagram of a configuration module according to a second embodiment of the present application.

As shown in fig. 5, the configuration module 200 further includes: and the third frequency divider205 is connected between the output end of the voltage controlled oscillator 203 and the protocol establishment module 300, and is configured to perform frequency division processing on the third clock signal by using a third frequency division parameter.

Specifically, the third frequency divider205 is configured to perform frequency division processing on the signal passing through the voltage controlled oscillator 202, and the signal after being processed by the third frequency divider205 is the target line rate.

Illustratively, as shown in fig. 6, a low-pass filter206 may be further connected between the phase detector 201 and the voltage controlled oscillator 202, and high-frequency components in the configuration module 200 are filtered by the low-pass filter206, so that the signal is converted into a dc pulse voltage and input to the voltage controlled oscillator 202. Wherein, f _PLLClkin The second clock signal FPGA _ DCLK, f generated by the clock generation module 100 _PLLClkin After frequency division is carried out by a second frequency Divider M Divider204, a signal fed back by a first frequency Divider N Divider203 is subjected to phase detection by a phase detector PFD201, a high-frequency component in the signal generated by the phase detector PFD201 is filtered by a low-pass Filter Loop Filter206, a direct-current part is reserved, a voltage controlled oscillator VCO202 outputs a periodic signal with corresponding frequency according to input voltage, and then the signal generates a target line rate f by a third frequency Divider N Divider205 _LineRate 。

As a possible implementation manner, the first frequency-division parameter, the second frequency-division parameter, and the third frequency-division parameter may be obtained according to a target sampling rate.

For example, the first clock signal DAC _ DCLK and the second clock signal FPGA _ DCLK may be obtained according to a target sampling rate, and then the first frequency-dividing parameter, the second frequency-dividing parameter, and the third frequency-dividing parameter may be obtained according to the target sampling rate and the second clock signal FPGA _ DCLK.

Optionally, a correspondence table is provided between the first clock signal DAC _ DCLK, the second clock signal FPGA _ DCLK, the first frequency division parameter, the second frequency division parameter, the third frequency division parameter, and the target sampling rate, when the digital-to-analog converter sampling rate switching apparatus based on the JESD204B switches the target sampling rate, the values of the first clock signal DAC _ DCLK (i.e., the target sampling rate), the second clock signal FPGA _ DCLK, the first frequency division parameter, the second frequency division parameter, and the third frequency division parameter can be obtained directly according to the value of the target sampling rate to be switched, and the correspondence table is shown in the following table:

for example, the first clock signal DAC _ DCLK and the second clock signal FPGA _ DCLK initially generated by the clock generating module 100 are 1200MHz and 300MHz, respectively, the values of the first frequency-dividing parameter, the second frequency-dividing parameter and the third frequency-dividing parameter are 40, 1 and 1, respectively, the jesd204b protocol is stably established, and at this time, the target sampling rate of the digital-to-analog converter is 1200MHz; when the target sampling rate needs to be switched to 600MHz, according to the corresponding relationship table, the clock generation module 100 generates new first clock signal DAC _ DCLK and second clock signal FPGA _ DCLK which are 600MHz and 150MHz respectively, then the values of the first frequency division parameter, the second frequency division parameter and the third frequency division parameter are adjusted to be 80, 1 and 2 respectively, the corresponding target linear rate is 6000mbps, and the jesd204b protocol is stably established, so that the target sampling rate is switched from 1200MHz to 600 MHz.

As a possible implementation manner, the following relations exist among the target line rate, the second clock signal, the first frequency dividing parameter, the second frequency dividing parameter, and the third frequency dividing parameter:

wherein f is _LineRate Representing target line velocity, f _PLLClkin Representing the second clock signal, N representing the first frequency-dividing parameter, M representing the second frequency-dividing parameter, D representing the third frequency-dividing parameter.

Specifically, the second clock signal FPGA _ DCLK is subjected to frequency division processing by three frequency dividers with different frequency division parameters in the configuration module 200 to generate a target line rate, and the conversion of the second clock signal to the target sampling rate can be realized by adjusting the frequency division parameters of the frequency dividers in the configuration module 200, where the frequency division parameters of the frequency dividers indicate that the frequency dividers divide the signal by several frequencies, for example, when the first frequency division parameter is 40, the first frequency divider203 divides the third clock signal by 40 frequencies.

It should be noted that the first clock signal DAC _ DCLK, the second clock signal FPGA _ DCLK, the first frequency division parameter, the second frequency division parameter, and the third frequency division parameter may be valued in a reasonable range according to actual needs, which is not limited in the present application.

Further, the clock generating module 100 is specifically configured to: after the first and second clock signals DAC _ DCLK and FPGA _ DCLK are generated, the synchronization pulse signal SYSREF is generated.

Specifically, after the first clock signal DAC _ DCLK and the second clock signal FPGA _ DCLK are generated, the second clock signal FPGA _ DCLK generates a target line rate through the configuration module 200, the clock generation module 100 synchronously generates a synchronization pulse signal SYSREF, and the synchronization pulse signal SYSREF is respectively provided to the protocol establishment module 300 and the DAC, the SYNC signal is pulled down, and the JESD204B protocol is reestablished.

In order to implement the foregoing embodiments, the present application further provides a field programmable gate array chip, including the sampling rate switching device of the digital-to-analog converter based on JESD204B as described in any one of the foregoing embodiments of the present application.

Illustratively, the FPGA chip may be an FPGA of XCKU040-FFVA1156 model.

In order to implement the foregoing embodiment, the present application further provides a control system of a sampling rate switching device of a digital-to-analog converter based on JESD204B, and fig. 7 is a structural diagram of the control system of the sampling rate switching device of the digital-to-analog converter based on JESD204B according to an embodiment of the present application.

As shown in fig. 7, the control system 2000 of the sampling rate switching device of the digital-to-analog converter based on JESD204B includes: the digital-to-analog converter 2001 and the field programmable gate array chip 2002 are used, and the JESD204B protocol is used for data transmission between the digital-to-analog converter 2001 and the field programmable gate array chip 2002.

Illustratively, the model of the digital-to-analog converter may be DAC37J84, which is a DAC chip capable of supporting a maximum input data rate of 1.23GSPS, and has an ESD204B interface of 12.5Gbps, which is available for multiple sample rate switching.

In order to implement the foregoing embodiment, the present application further provides a control method for a sampling rate switching device of a digital-to-analog converter based on JESD 204B.

Fig. 8 is a flowchart of a control method of a JESD 204B-based digital-to-analog converter sampling rate switching apparatus according to an embodiment of the present application, where the FPGA-based digital-to-analog converter sampling rate switching apparatus includes a clock generation module, a configuration module, and a protocol establishment module, and the method may include the following steps:

and S101, determining a target sampling rate.

S102, generating a first clock signal and a second clock signal according to a target sampling rate through a clock generating module, providing the first clock signal to a digital-to-analog converter, and providing the second clock signal to a configuration module.

And S103, outputting a target line rate corresponding to the target sampling rate through the configuration module according to the second clock signal, and providing the target line rate to the protocol establishment module.

And S104, generating a synchronous pulse signal through the clock generation module, and respectively providing the synchronous pulse signal to the digital-to-analog converter and the protocol establishment module.

And S105, establishing a JESD204B protocol according to the target line rate and the synchronous pulse signal through the protocol establishing module, and realizing that the digital-to-analog converter is switched from the current sampling rate to the target sampling rate for data transmission.

It should be noted that, for other specific implementations of the control method of the sampling rate switching device of the digital-to-analog converter based on the JESD204B in the embodiment of the present application, reference may be made to specific implementations of the sampling rate switching device of the digital-to-analog converter based on the JESD204B in the above-mentioned embodiment of the present application.

In addition, other configurations and functions of the digital-to-analog converter and the field programmable gate array chip according to the embodiment of the present application are known to those skilled in the art, and are not described herein for reducing redundancy.

It should be noted that the logic and/or steps shown in the flowcharts or otherwise described herein, such as an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.

It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

In the description of the present specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present application, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the present application.

Furthermore, the terms "first", "second", and the like, used in the embodiments of the present application, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated in the embodiments. Thus, a feature defined in terms of "first," "second," etc. in an embodiment of the present application may explicitly or implicitly indicate that at least one such feature is included in the embodiment. In the description of the present application, the word "plurality" means at least two or two and more, for example two, three, four, etc., unless the embodiment is specifically defined otherwise.

In this application, unless otherwise specifically stated or limited by the context of an embodiment, the terms "mounted," "connected," and "fixed" in the context of an embodiment are to be construed broadly, e.g., a connection may be a fixed connection, a detachable connection, or an integral connection, a mechanical connection, an electrical connection, etc.; of course, they may be directly connected or indirectly connected through intervening media, or they may be interconnected within one another or in an interactive relationship. The specific meaning of the above terms in this application can be understood by one of ordinary skill in the art based on the specific implementation.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through intervening media. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are exemplary and should not be construed as limiting the present application and that changes, modifications, substitutions and alterations in the above embodiments may be made by those of ordinary skill in the art within the scope of the present application.

Claims

1. A sample rate switching device of digital-to-analog converter based on JESD204B, comprising: the system comprises a clock generation module, a configuration module and a protocol establishment module, wherein the clock generation module is respectively connected with the configuration module and the protocol establishment module, and the configuration module is connected with the protocol establishment module;

the clock generation module is configured to generate a first clock signal, a second clock signal, and a synchronization pulse signal, provide the first clock signal to a digital-to-analog converter, provide the second clock signal to the configuration module, and provide the synchronization pulse signal to the protocol establishment module and the digital-to-analog converter, respectively, where the first clock signal and the second clock signal are determined according to a target sampling rate of the digital-to-analog converter;

the configuration module is used for outputting a target line rate corresponding to the target sampling rate according to the second clock signal;

the protocol establishing module is used for establishing a JESD204B protocol according to the target line rate and the synchronous pulse signal, and realizing that the digital-to-analog converter is switched from the current sampling rate to the target sampling rate for data transmission.

2. The JESD 204B-based digital-to-analog converter sampling rate switching apparatus according to claim 1, wherein the configuration module comprises: the clock generation module is connected with the clock generation module, the second input end of the phase discriminator is connected with the output end of the first frequency divider, the output end of the phase discriminator is connected with the input end of the voltage-controlled oscillator, and the output end of the voltage-controlled oscillator is connected with the input end of the first frequency divider and the protocol establishment module; wherein the content of the first and second substances,

the phase discriminator is used for discriminating the phase of the second clock signal and the first frequency division signal output by the first frequency divider;

the voltage-controlled oscillator is used for generating a third clock signal with corresponding frequency according to the phase discrimination result;

the first frequency divider is configured to perform frequency division processing on the third clock signal by using a first frequency division parameter to obtain a first frequency division signal;

the protocol establishing module is used for establishing the JESD204B protocol when the voltage-controlled oscillator outputs a stable third clock signal.

3. A JESD 204B-based digital-to-analog converter sampling rate switching apparatus according to claim 2, wherein the configuration module further comprises:

and the second frequency divider is connected between the clock generation module and the first input end of the phase discriminator and is used for carrying out frequency division processing on the second clock signal by adopting a second frequency division parameter.

4. A JESD 204B-based digital-to-analog converter sampling rate switching system according to claim 3, wherein the configuration module further comprises:

and the third frequency divider is connected between the output end of the voltage-controlled oscillator and the protocol establishing module and is used for carrying out frequency division processing on the third clock signal by adopting a third frequency division parameter.

5. The JESD204B based sampling rate switching device of claim 4, wherein the first frequency dividing parameter, the second frequency dividing parameter and the third frequency dividing parameter are obtained according to the target sampling rate.

6. The JESD 204B-based sampling rate switching device for digital-to-analog converters of claim 5, wherein the target line rate, the second clock signal, the first frequency dividing parameter, the second frequency dividing parameter and the third frequency dividing parameter have the following relations:

wherein, f _LineRate Representing the target line rate, f _PLLClkin Represents the second clock signal, N represents the first division parameter, M represents the second division parameter, and D represents the third division parameter.

7. The JESD 204B-based digital to analog converter sample rate switching apparatus according to any one of claims 1 to 6, the clock generation module is specifically configured to: after the first clock signal and the second clock signal are generated, the synchronization pulse signal is generated.

8. A field programmable gate array chip comprising JESD204B based digital to analog converter sample rate switching means as claimed in any one of claims 1 to 7.

9. A control system of a sampling rate switching device of a digital-to-analog converter based on JESD204B is characterized by comprising: a digital-to-analog converter and the field programmable gate array chip of claim 8, the data transmission between the digital-to-analog converter and the field programmable gate array chip is performed by adopting JESD204B protocol.

10. A control method of a sampling rate switching device of a digital-to-analog converter based on JESD204B is characterized in that the sampling rate switching device of the digital-to-analog converter based on FPGA comprises a clock generation module, a configuration module and a protocol establishment module, and the method comprises the following steps:

determining a target sampling rate;

generating a first clock signal and a second clock signal according to the target sampling rate through the clock generation module, providing the first clock signal to a digital-to-analog converter, and providing the second clock signal to the configuration module;

outputting a target line rate corresponding to the target sampling rate through the configuration module according to the second clock signal, and providing the target line rate to the protocol establishing module;

generating a synchronous pulse signal through the clock generation module, and respectively providing the synchronous pulse signal to the digital-to-analog converter and the protocol establishment module;

and establishing a JESD204B protocol by the protocol establishing module according to the target line rate and the synchronous pulse signal, and realizing that the digital-to-analog converter is switched from the current sampling rate to the target sampling rate for data transmission.