CN115274881A - Solar cell, grid line manufacturing method thereof, cell module and photovoltaic system - Google Patents
Solar cell, grid line manufacturing method thereof, cell module and photovoltaic system Download PDFInfo
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- CN115274881A CN115274881A CN202210867802.7A CN202210867802A CN115274881A CN 115274881 A CN115274881 A CN 115274881A CN 202210867802 A CN202210867802 A CN 202210867802A CN 115274881 A CN115274881 A CN 115274881A
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- 238000005530 etching Methods 0.000 claims abstract description 22
- 238000009713 electroplating Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 29
- 239000002253 acid Substances 0.000 claims description 18
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- 238000004544 sputter deposition Methods 0.000 claims description 2
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Abstract
The application is suitable for the technical field of solar cells, and provides a solar cell, a grid line manufacturing method thereof, a cell module and a photovoltaic system. The manufacturing method of the grid line of the solar cell comprises the following steps: manufacturing a seed layer on a battery precursor on which a grid line is to be manufactured; manufacturing a first insulating coating on the seed layer; manufacturing a second insulating coating on the first insulating coating; carrying out graphical etching on the second insulating coating, and exposing the first insulating coating in the etched area; removing the first insulating coating exposed from the etched area, wherein the seed layer is exposed from the etched area; electroplating is carried out on the exposed seed layer to form the grid line. Therefore, the seed layer or the cell precursor can be prevented from being damaged by laser over-etching. Also, the accuracy of patterning can be increased. Moreover, the growth direction of the grid lines can be limited, so that the growth direction of the grid lines is more accurate.
Description
Technical Field
The application belongs to the technical field of solar cells, and particularly relates to a solar cell, a grid line manufacturing method of the solar cell, a cell module and a photovoltaic system.
Background
Solar cell power generation is a sustainable clean energy source that can convert sunlight into electrical energy using the photovoltaic effect of semiconductor p-n junctions.
In the preparation process of the mask for the grid line of the solar cell, the related art generally adopts the screen printing or 3D printing technology to make the insulating material coating. However, the insulating coating material is viscous and is easily stuck below the screen plate in the printing process, which leads to the alarm of a machine table or the damage of the screen plate. Furthermore, the tiny units of insulating coating material are polymers, which currently can only achieve a minimum printing accuracy of 25 um. This results in a poor accuracy of the fabricated gate line.
Therefore, how to improve the manufacturing precision of the grid line becomes a problem to be solved urgently.
Disclosure of Invention
The application provides a solar cell, a grid line manufacturing method thereof, a cell module and a photovoltaic system, and aims to solve the problem of how to improve the grid line manufacturing precision.
In a first aspect, the present application provides a method for manufacturing a gate line of a solar cell, including:
manufacturing a seed layer on a battery precursor of a grid line to be manufactured;
manufacturing a first insulating coating on the seed layer;
manufacturing a second insulating coating on the first insulating coating;
carrying out graphical etching on the second insulating coating, wherein the first insulating coating is exposed out of an etched area;
removing the first insulating coating exposed from the etched region, wherein the seed layer is exposed from the etched region;
and electroplating on the exposed seed layer to form a grid line.
Optionally, the step of manufacturing a seed layer on a cell precursor on which the gate line is to be manufactured includes:
and sputtering a seed layer on the battery precursor.
Optionally, the seed layer has a thickness of 20nm to 80nm.
Optionally, in the step of fabricating the first insulating layer on the seed layer, the thickness of the first insulating layer is 10 μm to 20 μm.
Optionally, in the step of forming a second insulating layer on the first insulating layer, the thickness of the second insulating layer is 3 μm to 8 μm.
Optionally, in the step of performing patterned etching on the second insulating coating, a diameter of a laser spot is 15 μm to 50 μm.
Optionally, the dissolving of the first insulating layer in an alkaline solution and the dissolving of the second insulating layer in an acidic solution remove the first insulating layer exposed from the etched region, including:
removing the first insulating coating exposed from the etched area by using alkali liquor;
or, the first insulating coating is dissolved in acid solution, the second insulating coating is dissolved in alkali solution, and the first insulating coating exposed from the etched area is removed, including:
and removing the first insulating coating exposed from the etched region by using an acid solution.
In a second aspect, the solar cell provided by the present application has a grid line manufactured by any one of the above methods for manufacturing a grid line of a solar cell.
In a third aspect, the present application provides a battery module including the solar cell described above.
In a fourth aspect, the present application provides a photovoltaic system including the above-mentioned cell assembly.
According to the solar cell and the grid line manufacturing method thereof, the cell module and the photovoltaic system, the second insulating coating is etched in a patterning mode, and the exposed first insulating coating is removed, so that the grid line is formed on the exposed seed layer, and the seed layer or a cell precursor can be prevented from being damaged by laser over-etching. And, the two coatings can be used together to increase the precision of the patterning. In addition, in the electroplating process, the coating can limit the growth direction of the grid line, so that the growth direction of the grid line is more accurate.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a gate line of a solar cell according to an embodiment of the present disclosure;
fig. 2 is a schematic view illustrating a scene of a method for manufacturing a gate line of a solar cell according to an embodiment of the present disclosure;
fig. 3 is a schematic view illustrating a scene of a method for manufacturing a gate line of a solar cell according to an embodiment of the present disclosure;
fig. 4 is a schematic flow chart illustrating a method for manufacturing a gate line of a solar cell according to an embodiment of the present disclosure;
fig. 5 is a schematic flow chart illustrating a method for manufacturing a gate line of a solar cell according to an embodiment of the present application;
description of the main element symbols:
the solar cell comprises a cell precursor 101, a seed layer 102, a first insulating coating 11, a second insulating coating 12 and a grid line 103.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The accuracy of grid line preparation is relatively poor among the correlation technique. According to the method, when the grid line of the solar cell is manufactured, the second insulating coating is etched in a graphical mode, and the exposed first insulating coating is removed, so that the grid line is formed on the exposed seed layer, and the seed layer or a cell precursor can be prevented from being damaged by laser over-etching. And, the two coatings can be used together to increase the precision of the patterning. In addition, in the electroplating process, the coating can limit the growth direction of the grid line, so that the growth direction of the grid line is more accurate.
Example one
Referring to fig. 1, fig. 2 and fig. 3, a method for manufacturing a gate line of a solar cell according to an embodiment of the present disclosure includes:
step S11: manufacturing a seed layer 102 on a cell precursor 101 of a grid line to be manufactured;
step S12: manufacturing a first insulating coating 11 on the seed layer 102;
step S13: manufacturing a second insulating coating 12 on the first insulating coating 11;
step S14: carrying out patterned etching on the second insulating coating 12, wherein the etched area exposes the first insulating coating 11;
step S15: removing the first insulating coating 11 exposed from the etched region, the seed layer 102 being exposed from the etched region;
step S16: electroplating is performed on the exposed seed layer 102 to form a gate line 103.
According to the method for manufacturing the grid line of the solar cell, the second insulating coating 12 is etched in a patterning mode, and then the exposed first insulating coating 11 is removed, so that the grid line 103 is formed on the exposed seed layer 102, and the seed layer 102 or the cell precursor 101 can be prevented from being damaged by laser over-etching. And, the two coatings can be used together to increase the precision of the patterning. In addition, in the electroplating process, the coating can limit the growth direction of the gate line 103, so that the growth direction of the gate line 103 is more accurate.
In this embodiment, the coating may limit growth of the gate line 103 in the thickness direction of the cell precursor 101.
In this example, the cell precursor 101 is based on a 210mm silicon wafer. It is understood that in other embodiments, the cell precursor 101 may be based on other sizes of silicon wafers.
In step S11, the battery precursor 101 may be an IBC battery precursor. It is understood that in other embodiments, the cell precursor 101 may also be an HJT cell precursor, a POLO-IBC cell precursor, or an HBC cell precursor. The specific form of the cell precursor 101 is not limited herein.
In step S11, the seed layer 102 may be a copper layer, an aluminum layer or other metal layer. The seed layer 102 may continuously cover the upper surface of the cell precursor 101. In other words, the projection of the seed layer 102 on the cell precursor 101 completely overlaps with the cell precursor 101. It is understood that in other embodiments, seed layer 102 may cover only a partial region of the upper surface of cell precursor 101.
In this embodiment, the first insulating layer 11 is dissolved in an alkaline solution, and the second insulating layer 12 is dissolved in an acid solution. Specifically, the first insulating layer 11 is acid-resistant insulating ink, and the second insulating layer 12 is alkali-resistant insulating ink. It is understood that in other embodiments, the first insulating layer 11 may be dissolved in an acid solution, and the second insulating layer 12 may be dissolved in an alkali solution. In this way, the first insulating coating 11 or the second insulating coating 12 can be selectively removed using an acid solution or an alkali solution by selective dissolution of the acid solution and the alkali solution by the first insulating coating 11 and the second insulating coating 12.
Specifically, the first insulating coating 11 and the second insulating coating 12 are both high molecular polymers, and have good plasticity and are insoluble in water. The first insulating coating 11 and the second insulating coating 12 are in a liquid state at a temperature of less than 50 ℃; the liquid coating can be solidified and shaped at the temperature of 70-150 ℃; at a temperature greater than 200 deg.c, the first insulating layer 11 and the second insulating layer 12 may melt.
In step S12, the first insulating layer 11 continuously covers the upper surface of the seed layer 102. The first insulating layer 11 is projected on the cell precursor 101 to completely overlap the cell precursor 101. It is understood that in other embodiments, the first insulating layer 11 may cover only a partial region of the upper surface of the seed layer 102.
Specifically, the thickness of the first insulating layer 11 is equal everywhere. Thus, the thickness of the first insulating layer 11 is uniform.
Specifically, the first insulating layer 11 in a liquid state may be coated on the seed layer 102, and the first insulating layer 11 in a liquid state may be cured into a solid state at a first preset temperature. Thus, the first insulating layer 11 is formed on the seed layer 102, and the efficiency is high. Further, the first insulating layer 11 may be applied on the seed layer 102 in a liquid state by printing, immersion, 3D printing, or the like. In this way, the first insulating layer 11 in liquid form can be efficiently applied to the seed layer 102. Further, the first preset temperature is 70-150 ℃. For example, 70 ℃, 75 ℃, 80 ℃, 100 ℃, 120 ℃, 150 ℃.
In step S13, the second insulating coating 12 continuously covers the upper surface of the first insulating coating 11. The second insulating coating 12 is projected on the cell precursor 101 so as to completely overlap the cell precursor 101. Specifically, the thickness of the second insulating coating 12 is equal everywhere. In this way, the thickness of the second insulating coating 12 is made uniform.
Specifically, the second insulating coating 12 in a liquid state may be coated on the first insulating coating 11, and the second insulating coating 12 in a liquid state may be cured into a solid state at a second preset temperature. Thus, the second insulating coating 12 is manufactured on the first insulating coating 11, and the efficiency is high. Further, the second insulating layer 12 may be applied in a liquid state on the first insulating layer 11 by printing, immersion, 3D printing, or the like. In this way, the second insulating coating 12 in a liquid form can be efficiently applied to the first insulating coating 11. Further, the second preset temperature is 70-150 ℃. For example, 70 ℃, 75 ℃, 80 ℃, 100 ℃, 120 ℃, 150 ℃.
In step S14, the second insulating coating 12 may be patterned by using a laser. Therefore, the efficiency and the precision of the patterning etching are higher. Specifically, the patterned etching means that the second insulating layer 12 is etched according to a predetermined pattern.
After step S16, the remaining second insulating coating 12 and first insulating coating 11 may also be removed. In this way, by removing the first insulating coating 11 and the second insulating coating 12, it is convenient to continue to fabricate other film layers such as a passivation layer, an antireflection layer, and the like on the seed layer 102. Specifically, the remaining second insulating coating 12 may be removed using an acid solution; and removing the residual first insulating layer by using alkali liquor.
For further explanation and explanation of this embodiment, reference may be made to other parts of the present document, and further explanation is omitted here to avoid redundancy.
Example two
Referring to fig. 4, in some alternative embodiments, step S11 includes:
step S111: a seed layer 102 is sputtered over the precursor.
Thus, the seed layer 102 is formed on the cell precursor 101, and the efficiency is high. Moreover, the seed layer 102 is relatively uniform and dense, and has relatively good quality.
It is understood that in other embodiments, seed layer 102 may be formed on the precursor by PVD, screen printing, evaporation, or the like.
For further explanation and explanation of this embodiment, reference may be made to other parts of the present document, and further explanation is omitted here to avoid redundancy.
EXAMPLE III
In some alternative embodiments, seed layer 102 has a thickness of 20nm to 80nm. For example, 20nm, 22nm, 30nm, 50nm, 70nm, 75nm, 80nm.
Thus, the thickness of the seed layer 102 is in a suitable range, which can avoid poor electroplating of the subsequent gate line 103 caused by too small thickness of the seed layer 102, and can also avoid material waste caused by too large thickness of the seed layer 102, and the cost is high.
For further explanation and explanation of this embodiment, reference may be made to other parts of the present document, and further explanation is omitted here to avoid redundancy.
Example four
In some alternative embodiments, the thickness of the first insulating layer 11 is 10 μm to 20 μm in step S12. For example, 10 μm, 12 μm, 15 μm, 18 μm, and 20 μm.
So for the thickness of first insulating coating 11 is in suitable scope, can avoid the protective effect to laser over-etching that the thickness undersize of first insulating coating 11 leads to relatively poor, also can avoid the extravagant material that the thickness of first insulating coating 11 too big leads to, and the cost is higher.
Preferably, the thickness of the first insulating layer 11 is 15 μm. Therefore, the laser etching protection device has the advantages of protecting laser etching and saving materials, and the whole effect is good.
For further explanation and explanation of this embodiment, reference may be made to other parts of the present document, and further explanation is omitted here to avoid redundancy.
EXAMPLE five
In some alternative embodiments, in step S13, the thickness of the second insulating coating 12 is 3 μm to 8 μm. For example, 3 μm, 4 μm, 5 μm, 7 μm, and 8 μm.
Thus, the thickness of the second insulating coating 12 is in a proper range, easy over-etching caused by too small thickness of the second insulating coating 12 can be avoided, and difficulty in exposing the first insulating coating 11 after patterning caused by too large thickness of the second insulating coating 12 can be avoided.
Preferably, the thickness of the second insulating coating 12 is 5 μm. Therefore, the method reduces the over-etching risk and facilitates the imaging, and the whole effect is best.
Note that, in step S14, the etching depth of the laser is the same as the thickness of the second insulating coating 12, which is also in the range of 3 μm to 8 μm. For example, 3 μm, 4 μm, 5 μm, 7 μm, and 8 μm. In this way, the etching depth of the laser is adapted to the thickness of the second insulating coating 12, reducing the risk of over-etching or insufficient etching.
For further explanation and explanation of this embodiment, reference may be made to other parts of the present document, and further explanation is omitted here to avoid redundancy.
Example six
In some alternative embodiments, the diameter of the laser spot is 15 μm to 50 μm in step S14. For example, 15 μm, 18 μm, 20 μm, 30 μm, and 50 μm.
Therefore, the diameter of the laser spot is within a proper range, the imaging efficiency caused by the over-small diameter of the laser spot is prevented from being too low, and the minimum width of the subsequently grown grid line 103 caused by the over-large diameter of the laser spot is also prevented from being too large.
For further explanation and explanation of this embodiment, reference may be made to other parts of the present document, and further explanation is omitted here to avoid redundancy.
EXAMPLE seven
Referring to fig. 5, in some alternative embodiments, the first insulating layer 11 is dissolved in an alkaline solution, and the second insulating layer 12 is dissolved in an acid solution, and the step S15 includes:
step S151: the first insulating layer 11 exposed from the etched region is removed by using an alkali solution.
In this way, the first insulating coating 11 exposed from the etched region is removed efficiently without affecting the second insulating layer.
Specifically, the lye includes, but is not limited to, naOH solution, KOH solution or a mixed lye of NaOH and KOH.
Specifically, the concentration of the alkali liquor is 3% -15%. For example, 3%, 4%, 5%, 7%, 10%, 12%, 15%.
Specifically, the patterned battery precursor 101 may be immersed in an alkali solution, thereby removing the first insulating coating 11 exposed from the etched region with the alkali solution. Thus, the efficiency is high.
It is understood that in other embodiments, the alkali solution may be applied to the first insulating layer 11 exposed from the etched area by painting, printing, etc. to remove the first insulating layer 11 exposed from the etched area.
In some alternative embodiments, the first insulating layer 11 is dissolved in an acid solution, the second insulating layer 12 is dissolved in an alkali solution, and the step S15 includes:
the first insulating layer 11 exposed from the etched region is removed using an acid solution.
In this way, the first insulating coating 11 exposed from the etched region is removed efficiently without affecting the second insulating layer.
Specifically, the acid solution includes but is not limited to HCL solution, H2SO4Solutions or HCL, H2SO4And HF.
Specifically, the concentration of the acid solution is 1.5% -15%. For example, 1.5%, 2%, 5%, 7%, 10%, 12%, 15%.
Specifically, the patterned battery precursor 101 may be immersed in an acid solution, so that the first insulating coating 11 exposed from the etched region is removed by the acid solution. Thus, the efficiency is high.
It is understood that, in other embodiments, the acid solution may be applied to the first insulating layer 11 exposed from the etched area by painting, printing, or the like, so as to remove the first insulating layer 11 exposed from the etched area.
For further explanation and explanation of this embodiment, reference may be made to other parts of the present document, and further explanation is omitted here to avoid redundancy.
Example eight
In the solar cell of the embodiment of the present application, the gate line 103 is manufactured by using the method for manufacturing a gate line of a solar cell of any one of the first to seventh embodiments.
According to the solar cell of the embodiment of the application, when the grid line 103 of the solar cell is manufactured, the second insulating coating 12 is etched in a patterning mode, and then the exposed first insulating coating 11 is removed, so that the grid line 103 is formed on the exposed seed layer 102, and the seed layer 102 or the cell precursor 101 can be prevented from being damaged by laser over-etching. And, the two coatings can be used together to increase the precision of the patterning. In addition, in the electroplating process, the coating can limit the growth direction of the gate line 103, so that the growth direction of the gate line 103 is more accurate.
For further explanation and explanation of this embodiment, reference may be made to other parts of the present document, and further explanation is omitted here to avoid redundancy.
Example nine
The battery module of the embodiment of the present application includes the solar cell of the eighth embodiment.
In the cell module of the embodiment of the application, when the gate line 103 of the solar cell is manufactured, the second insulating coating 12 is etched in a patterned manner, and then the exposed first insulating coating 11 is removed, so that the gate line 103 is formed on the exposed seed layer 102, and the seed layer 102 or the cell precursor 101 can be prevented from being damaged by laser over-etching. And, the two coatings can be used together to increase the precision of the patterning. In addition, in the electroplating process, the coating can limit the growth direction of the gate line 103, so that the growth direction of the gate line 103 is more accurate.
For further explanation and explanation of this embodiment, reference may be made to other parts of the present document, and further explanation is omitted here to avoid redundancy.
EXAMPLE ten
The photovoltaic system of this application embodiment includes the battery module of example nine.
In the photovoltaic system of the embodiment of the application, when the gate line 103 of the solar cell is manufactured, the second insulating coating 12 is etched in a patterned manner, and then the exposed first insulating coating 11 is removed, so that the gate line 103 is formed on the exposed seed layer 102, and the seed layer 102 or the cell precursor 101 can be prevented from being damaged by laser over-etching. And, the two coatings can be used together to increase the precision of the patterning. In addition, in the electroplating process, the coating can limit the growth direction of the gate line 103, so that the growth direction of the gate line 103 is more accurate.
In this embodiment, the photovoltaic system can be applied to photovoltaic power stations, such as ground power stations, roof power stations, water surface power stations, etc., and can also be applied to devices or apparatuses that generate electricity by using solar energy, such as user solar power sources, solar street lamps, solar cars, solar buildings, etc. Of course, it is understood that the application scenario of the photovoltaic system is not limited thereto, that is, the photovoltaic system can be applied in all fields requiring solar energy for power generation. Taking a photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a combiner box and an inverter, the photovoltaic array may be an array combination of a plurality of battery modules, for example, the plurality of battery modules may constitute a plurality of photovoltaic arrays, the photovoltaic array is connected to the combiner box, the combiner box may combine currents generated by the photovoltaic array, and the combined currents are converted into alternating currents required by a utility grid through the inverter and then are connected to the utility grid to realize solar power supply.
For further explanation and explanation of this embodiment, reference may be made to other parts of the present document, and further explanation is omitted here to avoid redundancy.
By integrating the manufacturing method, the error of the mask of the grid line can be controlled within 10 micrometers, so that the grid line can be manufactured more accurately, the high-precision grid line manufacturing method of the interdigitated back junction solar cell can be used for manufacturing the high-precision grid line, and the high-efficiency and rapid production of the cell can be realized. In particular, compared with a mask for screen printing of a grid line, by adopting the method, the average production time per sheet can be shortened to 2-6 s.
The present application is intended to cover various modifications, equivalent arrangements, and adaptations of the present application without departing from the spirit and scope of the present application. Furthermore, the particular features, structures, materials, or characteristics described in connection with the embodiments or examples disclosed herein may be combined in any suitable manner in any one or more of the embodiments or examples.
Claims (10)
1. A method for manufacturing a grid line of a solar cell is characterized by comprising the following steps:
manufacturing a seed layer on a battery precursor of a grid line to be manufactured;
manufacturing a first insulating coating on the seed layer;
manufacturing a second insulating coating on the first insulating coating;
carrying out graphical etching on the second insulating coating, wherein the first insulating coating is exposed out of an etched area;
removing the first insulating coating exposed from the etched region, wherein the seed layer is exposed from the etched region;
and electroplating on the exposed seed layer to form a grid line.
2. The method for manufacturing a gate line of a solar cell according to claim 1, wherein the step of manufacturing a seed layer on a cell precursor on which the gate line is to be manufactured comprises:
and sputtering a seed layer on the battery precursor.
3. The method for manufacturing a gate line of a solar cell according to claim 1, wherein the seed layer has a thickness of 20nm to 80nm.
4. The method as claimed in claim 1, wherein in the step of forming the first insulating layer on the seed layer, the thickness of the first insulating layer is 10 μm to 20 μm.
5. The method for manufacturing a grid line of a solar cell according to claim 1, wherein in the step of manufacturing the second insulating coating on the first insulating coating, the thickness of the second insulating coating is 3 μm to 8 μm.
6. The method for manufacturing a grid line of a solar cell according to claim 1, wherein in the step of performing the patterned etching on the second insulating coating, the diameter of a laser spot is 15 μm to 50 μm.
7. The method as claimed in claim 1, wherein the step of removing the first insulating layer exposed from the etched region comprises:
removing the first insulating coating exposed from the etched area by using alkali liquor;
or, the first insulating coating dissolves in acid solution, the second insulating coating dissolves in alkali solution, and the first insulating coating exposed from the etched area is removed, including:
and removing the first insulating coating exposed from the etched region by using an acid solution.
8. A solar cell, wherein the grid line of the solar cell is manufactured by the method for manufacturing the grid line of the solar cell according to any one of claims 1 to 7.
9. A battery module comprising the solar cell of claim 8.
10. A photovoltaic system comprising the cell assembly of claim 9.
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| CN202210867802.7A CN115274881A (en) | 2022-07-21 | 2022-07-21 | Solar cell, grid line manufacturing method thereof, cell module and photovoltaic system |
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| CN202210867802.7A CN115274881A (en) | 2022-07-21 | 2022-07-21 | Solar cell, grid line manufacturing method thereof, cell module and photovoltaic system |
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