CN115274857A - LDMOS device, manufacturing method of LDMOS device and chip - Google Patents
LDMOS device, manufacturing method of LDMOS device and chip Download PDFInfo
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- CN115274857A CN115274857A CN202211205447.3A CN202211205447A CN115274857A CN 115274857 A CN115274857 A CN 115274857A CN 202211205447 A CN202211205447 A CN 202211205447A CN 115274857 A CN115274857 A CN 115274857A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0882—Disposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
Abstract
The invention provides an LDMOS device, a manufacturing method of the LDMOS device and a chip, and belongs to the field of chips. The LDMOS device comprises: the semiconductor device comprises a semiconductor substrate, and a source electrode structure, a grid electrode structure and a drain electrode structure which are formed on the semiconductor substrate; a drift region and a body region are formed in the semiconductor substrate, the source electrode structure is connected with the body region, the drain electrode structure is connected with the drift region, and the grid electrode structure is formed between the source electrode structure and the drain electrode structure; the drain structure comprises a drain doped region and drain metal, the drain doped region is formed in the drift region and is away from the upper surface of the semiconductor substrate by a first preset distance, and the drain metal is connected with the drain doped region; and an air cavity is formed above the drain electrode doped region and surrounds the drain electrode metal. Air media are filled in the air cavity and surround the drain metal, so that the electric field of a drain end is reduced, and the breakdown voltage is improved.
Description
Technical Field
The invention relates to the field of chips, belongs to the field of power semiconductor chips, and particularly relates to an LDMOS device, a manufacturing method of the LDMOS device and a chip.
Background
With the development of the times, the application fields of semiconductors have also been expanded from traditional industrial control, communication, computers, consumer electronics to new fields such as new energy, smart grid, rail transit, automotive electronics, and the like. The power semiconductor device pursues the handling of electric energy, and is required to have high withstand voltage and large current characteristics itself. As a Lateral power device, an LDMOS (Lateral Double-Diffused MOSFET) has the advantages of high withstand voltage, large gain, good linearity, high efficiency, good broadband matching performance, and the like, and is widely applied to power integrated circuits, especially low-power and high-frequency circuits.
Typically, the LDMOSFET has a large operating voltage and current. When the LDMOSFET is conducted, an electric field of a drain end in a channel direction is strong, so that the breakdown voltage BVon during conduction is influenced, and meanwhile, because a large amount of electrons flow through a high electric field area, a hot electron effect is easily caused, so that the reliability of the LDMOSFET is influenced.
Disclosure of Invention
The LDMOS device is provided with a drain electrode doping area which is a first preset distance away from the upper surface of a semiconductor substrate, electrons on the surface are diffused when reaching the drain electrode doping area, and the phenomenon that the current is concentrated to cause impact ionization to generate a hot electron effect is reduced; air media are filled in the air cavity, the air media surround the drain metal, and the drain metal is equivalently used as a side field plate, so that the electric field of a drain end is reduced, and the breakdown voltage is improved.
In order to achieve the above object, a first aspect of the present invention provides an LDMOS device comprising: the semiconductor device comprises a semiconductor substrate, and a source electrode structure, a grid electrode structure and a drain electrode structure which are formed on the semiconductor substrate; a drift region and a body region are formed in the semiconductor substrate, the source electrode structure is connected with the body region, the drain electrode structure is connected with the drift region, and the gate electrode structure is formed between the source electrode structure and the drain electrode structure; the drain electrode structure comprises a drain electrode doped region and drain electrode metal, the drain electrode doped region is formed in the drift region and is away from the upper surface of the semiconductor substrate by a first preset distance, and the drain electrode metal is connected with the drain electrode doped region;
and an air cavity is formed above the drain electrode doped region and surrounds the drain electrode metal.
Optionally, the LDMOS device further includes a silicon nitride structure, and the silicon nitride structure is formed in the drift region and located between the drain structure and the source structure. The silicon nitride structure is equivalent to a gate field plate and can play a role in adjusting an electric field.
Optionally, the gate structure includes a gate oxide layer and a polysilicon gate; the gate oxide layer is formed between the drain electrode structure and the source electrode structure, the first end of the gate oxide layer is positioned above the drift region, and the second end of the gate oxide layer is positioned above the body region; the polysilicon gate is formed above the gate oxide layer; the first end of the gate oxide layer is also positioned above the silicon nitride structure.
Optionally, the source structure includes a source doped region and a source metal, the source doped region is formed in the body region, and the source metal is connected to the source doped region.
Optionally, the LDMOS device further includes a guard ring structure; the guard ring structure comprises a guard ring doping area and guard ring metal, the guard ring doping area is formed in the semiconductor substrate, and the guard ring metal is connected with the guard ring doping area.
Optionally, the LDMOS device further includes a silicon dioxide layer formed on the semiconductor substrate, and the drain metal, the source metal, and the guard ring metal penetrate through the silicon dioxide layer to be connected to the corresponding drain doped region, the source doped region, and the guard ring doped region.
Optionally, the LDMOS device further includes a shallow trench isolation structure formed in the semiconductor substrate; the shallow trench isolation structure comprises a first shallow trench isolation structure and a second shallow trench isolation structure, the first shallow trench isolation structure and the second shallow trench isolation structure are respectively arranged on two sides of the protection ring doping area, one end of the first shallow trench isolation structure is located in the drift area and adjacent to the drain electrode structure, and the other end of the first shallow trench isolation structure is located outside the drift area.
Optionally, the LDMOS device further includes a high voltage P-well and a high voltage N-well formed in the semiconductor substrate, and the drift region and the body region are formed in the high voltage N-well; one end of the second shallow trench isolation structure is formed in the high-voltage N well, and the other end of the second shallow trench isolation structure is adjacent to the high-voltage P well; and a preset distance is arranged between the high-voltage P trap and the high-voltage N trap.
In a second aspect, the present invention provides a method for manufacturing an LDMOS device, the method comprising:
forming a drift region and a body region in the semiconductor substrate by adopting an ion implantation process;
depositing a silicon nitride material on the surface of the semiconductor substrate, photoetching and etching the silicon nitride material and the semiconductor substrate at the corresponding position of the defined LOCOS region, and thermally oxidizing the semiconductor substrate to form a LOCOS structure;
etching to remove the LOCOS structure, depositing a silicon nitride material, and grinding the silicon nitride material to form a silicon nitride layer at a position corresponding to the LOCOS structure;
preparing a gate structure over a semiconductor substrate;
depositing a silicon dioxide material, photoetching and etching the silicon dioxide material at the corresponding positions of the defined source electrode doped region and the defined drain electrode doped region to form a silicon dioxide layer, and etching to remove the silicon nitride layer at the corresponding position of the drain electrode doped region;
forming a source electrode doped region and a drain electrode doped region in the semiconductor substrate at the corresponding positions of the defined source electrode doped region and the defined drain electrode doped region by adopting an ion implantation process;
and depositing a metal material, and photoetching and etching the metal material to form a source metal and a drain metal.
Optionally, before forming the drift region and the body region, the method further includes: and forming a high-voltage P well and a high-voltage N well in the semiconductor substrate by adopting an ion implantation process.
Optionally, the method further includes: before depositing silicon nitride material on the surface of the semiconductor substrate, a shallow trench isolation structure is manufactured on the semiconductor substrate.
Optionally, the method further includes: adopting the same manufacturing steps to form a source electrode doped region and a drain electrode doped region and simultaneously form a protection ring doped region;
the same metal material and manufacturing steps are adopted, and the guard ring metal is formed at the same time of forming the source electrode metal and the drain electrode metal.
The third aspect of the invention provides a chip, which is made by applying the LDMOS device.
The LDMOS device is provided with the drain electrode doping area which is a first preset distance away from the upper surface of the semiconductor substrate, electrons on the surface are diffused when reaching the drain electrode doping area, and the phenomenon that the current is concentrated to cause collision ionization to generate a hot electron effect is reduced; air media are filled in the air cavity, the air media surround the drain metal, and the drain metal is equivalently used as a side field plate, so that the electric field of a drain end is reduced, and the breakdown voltage is improved.
Additional features and advantages of embodiments of the present invention will be described in detail in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIG. 1 is a schematic structural diagram of an LDMOS device according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for manufacturing an LDMOS device according to an embodiment of the invention;
fig. 3A is a schematic structural diagram of an LDMOS device manufacturing method according to an embodiment of the invention after forming a high-voltage P-well, a high-voltage N-well, a drift region and a body region;
FIG. 3B is a schematic structural diagram of a shallow trench isolation structure fabricated by the LDMOS device fabrication method according to the embodiment of the present invention;
fig. 3C is a schematic structural diagram of an LDMOS device manufacturing method according to an embodiment of the present invention after forming a LOCOS structure;
FIG. 3D is a schematic structural diagram of an LDMOS device according to an embodiment of the present invention after a silicon nitride layer is formed;
fig. 3E is a schematic structural diagram of an LDMOS device according to an embodiment of the invention after a gate structure is fabricated;
fig. 3F is a schematic structural diagram of the LDMOS device manufacturing method according to the embodiment of the invention after a silicon dioxide layer is formed and a silicon nitride layer at a position corresponding to the drain doped region is removed by etching;
fig. 3G is a schematic structural diagram of the LDMOS device manufacturing method provided by the embodiment of the invention after forming the source doped region and the drain doped region.
Description of the reference numerals
The structure comprises a semiconductor substrate 1, a high-voltage N well 2, a body region 3, a drift region 4, a silicon nitride structure 5, a source metal 6, a source doped region 7, a drain metal 8, a drain doped region 9, a guard ring metal 10, a guard ring doped region 11, a shallow trench isolation structure 12, a high-voltage P well 13, an air cavity 14, a silicon dioxide layer 15, a polysilicon gate 16, a silicon nitride material 17 and a LOCOS structure 18.
Detailed Description
The following describes in detail embodiments of the present invention with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
Example one
Fig. 1 is a schematic structural diagram of an LDMOS device according to an embodiment of the present invention. As shown in fig. 1, the LDMOS device includes: a semiconductor substrate 1 and a source electrode structure, a gate electrode structure and a drain electrode structure formed on the semiconductor substrate 1; a drift region 4 and a body region 3 are formed in the semiconductor substrate 1, the source structure is connected with the body region 3, the drain structure is connected with the drift region 4, and the gate structure is formed between the source structure and the drain structure; the drain structure comprises a drain doped region 9 and drain metal 8, the drain doped region 9 is formed in the drift region 4 and is away from the upper surface of the semiconductor substrate 1 by a first preset distance, and the drain metal 8 is connected with the drain doped region 9;
an air cavity 14 is further formed above the drain doped region 9, and the air cavity 14 surrounds the drain metal 8.
In the embodiment of the present application, the LDMOS device further includes a silicon nitride structure 5, and the silicon nitride structure 5 is formed in the drift region 4 and located between the drain structure and the source structure. The silicon nitride structure 5 corresponds to a gate field plate and can function to adjust an electric field.
In the embodiment of the present application, the gate structure includes a gate oxide layer (not shown in the drawings of the present application) and a polysilicon gate 16; the gate oxide layer is formed between the drain electrode structure and the source electrode structure, the first end of the gate oxide layer is positioned above the drift region 4, and the second end of the gate oxide layer is positioned above the body region 3; the polysilicon gate 16 is formed over the gate oxide layer; the first end of the gate oxide layer is also positioned above the silicon nitride structure 5.
In the embodiment of the present application, the source structure includes a source doped region 7 and a source metal 6, the source doped region 7 is formed in the body region 3, and the source metal 6 is connected to the source doped region 7.
In the embodiment of the application, the LDMOS device further comprises a guard ring structure; the guard ring structure comprises a guard ring doping region 11 and a guard ring metal 10, wherein the guard ring doping region 11 is formed in the semiconductor substrate 1, and the guard ring metal 10 is connected with the guard ring doping region 11.
In the embodiment of the present application, the LDMOS device further includes a silicon dioxide layer 15, the silicon dioxide layer 15 is formed on the semiconductor substrate 1, and the drain metal 8, the source metal 6, and the guard ring metal 10 pass through the silicon dioxide layer 15 to be connected to the corresponding drain doped region 9, the source doped region 7, and the guard ring doped region 11.
In the embodiment of the present application, the LDMOS device further includes a shallow trench isolation structure 12, where the shallow trench isolation structure 12 is formed in the semiconductor substrate 1; the shallow trench isolation structure 12 includes a first shallow trench isolation structure and a second shallow trench isolation structure, the first shallow trench isolation structure and the second shallow trench isolation structure are respectively disposed on two sides of the protection ring doping area 11, one end of the first shallow trench isolation structure is located in the drift area 4 and adjacent to the drain structure, and the other end of the first shallow trench isolation structure is located outside the drift area 4.
In the embodiment of the application, the LDMOS device further comprises a high-voltage P-well 13 and a high-voltage N-well 2 which are formed in the semiconductor substrate 1, and the drift region 4 and the body region 3 are formed in the high-voltage N-well 2; one end of the second shallow trench isolation structure is formed in the high-voltage N well 2, and the other end of the second shallow trench isolation structure is adjacent to the high-voltage P well 13; the high-voltage P trap 13 and the high-voltage N trap 2 are separated by a preset distance.
In a second aspect, the present invention provides a method for manufacturing an LDMOS device, which is used to manufacture the LDMOS device, as shown in fig. 2, and comprises:
s1: a high-voltage P well 13, a high-voltage N well 2, a drift region 4 and a body region 3 are formed in the semiconductor substrate 1 by adopting an ion implantation process.
In some embodiments, in order to form the high voltage P-well 13, the high voltage N-well 2, the drift region 4 and the body region 3, a thin silicon dioxide layer is first oxidized over the semiconductor substrate 1, then a photoresist is coated, developed by light, the photoresist in the corresponding regions of the high voltage P-well 13 and the high voltage N-well 2 is removed, the remaining photoresist is used as a mask in the ion implantation process, then P-type or N-type ion implantation is selected according to the type of the LDMOS device, the photoresist is removed, the drift region 4 and the body region 3 are manufactured by the same process, and the manufactured structure is as shown in fig. 3A. In one embodiment, P-type ions are implanted to form P-type body regions 3 and N-type ions are implanted to form N-type drift regions 4.
S2: and manufacturing a shallow trench isolation structure 12 on the semiconductor substrate 11.
In some embodiments, a thin layer of silicon dioxide SiO is first thermally oxidized 2 Then CVD SiN, photoetching to expose the region corresponding to STI of the shallow trench isolation structure 12, and dry etching SiN and SiO 2 And a semiconductor substrate 11, photoresist-removed, thermally oxidized silicon-induced damage by a dry etch, HDP CVD SiO 2 Excess SiO on the CMP surface 2 Wet removal of SiN and its underlying thin SiO 2 And (5) annealing at high temperature to finish the manufacture of the shallow trench isolation structure 12, wherein the manufactured structure is shown as figure 3B.
S3: depositing a silicon nitride material 17 on the surface of the semiconductor substrate 1, photoetching and etching the silicon nitride material 17 and the semiconductor substrate 1 at the corresponding position of the defined LOCOS region, and thermally oxidizing the semiconductor substrate 1 to form a LOCOS structure 18.
In some embodiments, a thin silicon dioxide layer is first thermally oxidized, then LPCVD SiN is performed, the silicon nitride material 17 and the semiconductor substrate 1 corresponding to the defined LOCOS region are etched and etched, the photoresist is removed, then the semiconductor substrate 1 is thermally oxidized to form a LOCOS structure 18, and the completed structure is shown in fig. 3C.
S4: and etching to remove the LOCOS structure 18, depositing a silicon nitride material, grinding the silicon nitride material, and forming a silicon nitride layer at a position corresponding to the LOCOS structure 18.
In the present embodiment, a wet etch is used to remove the LOCOS structure 18, followed by thermal oxidation of a thin SiO layer 2 Depositing a silicon nitride material by LPCVD SiN, polishing the excess SiN on the surface by CMP, and forming a silicon nitride layer at the corresponding position of the LOCOS structure 18, wherein the structure after the fabrication is shown in FIG. 3D.
S5: a gate structure is prepared over a semiconductor substrate 1.
In some embodiments, first, on the structure in step S4, wet etching is used to remove the thin SiO2 obtained by thermal oxidation in step S4, then a gate oxide layer is formed by gate oxidation (not shown in fig. 3E), then LPCVD Polysilicon (Polysilicon) is formed, ion implantation is performed to heavily dope the Polysilicon, the Polysilicon is photo-etched, the Polysilicon is dry etched, and photoresist is removed to form a gate structure, and the structure after fabrication is shown in fig. 3E.
S6: depositing silicon dioxide material, photoetching and etching the silicon dioxide material at the positions corresponding to the defined source electrode doped region 7 and the drain electrode doped region 9 to form a silicon dioxide layer 15, and etching and removing the silicon nitride layer at the position corresponding to the drain electrode doped region 9. In the embodiment of the present application, a silicon dioxide material is etched by a dry method, a silicon nitride layer is etched by a wet method, and the structure after the fabrication is shown in fig. 3F.
S7: and forming a source doped region 7 and a drain doped region 9 in the semiconductor substrate 1 at the positions corresponding to the defined source doped region 7 and drain doped region 9 by adopting an ion implantation process.
In the embodiment of the present application, the silicon dioxide layer 15 in step S6 plays a role of a mask in the ion implantation process of S7, so as to save materials, annealing is performed after the ion implantation, and the structures of the drain doped region 9 and the source doped region 75 after the fabrication are the same as those of the drain doped region 9 and the source doped region 7 shown in fig. 3G. The fabrication of the guard ring is also included in fig. 3G.
S8: a metal material is deposited, and the metal material is lithographically and etched to form a source metal 6 and a drain metal 8.
In some embodiments, the metallic material is deposited using PVD and the metallic material is dry etched.
In an embodiment of the present application, the method further includes: adopting the same manufacturing steps, forming a guard ring doped region 11 while forming a source doped region 7 and a drain doped region 9;
the same metal material and manufacturing steps are used to form the guard ring metal 10 at the same time as the source metal 6 and the drain metal 8.
The third aspect of the invention provides a chip, which is made by applying the LDMOS device.
According to the LDMOS device, the drain electrode doping region 9 is arranged at a first preset distance away from the upper surface of the semiconductor substrate 1, electrons on the surface are diffused when reaching the drain electrode doping region 9, and the hot electron effect generated by impact ionization caused by current concentration is reduced; the air cavity 14 is filled with an air medium, the air medium surrounds the drain metal 8, and the drain metal 8 is equivalently used as a side field plate, so that the electric field of a drain end is reduced, and the breakdown voltage is improved.
The manufacturing method provided by the invention has the advantages of simple process, compatibility with the existing process and strong practicability.
While the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solution of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications are within the scope of the embodiments of the present invention. It should be noted that the various features described in the foregoing embodiments may be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the embodiments of the present invention will not be described separately for the various possible combinations.
In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as disclosed in the embodiments of the present invention as long as it does not depart from the spirit of the embodiments of the present invention.
Claims (13)
1. An LDMOS device comprising: the semiconductor device comprises a semiconductor substrate, and a source electrode structure, a grid electrode structure and a drain electrode structure which are formed on the semiconductor substrate; a drift region and a body region are formed in the semiconductor substrate, the source electrode structure is connected with the body region, the drain electrode structure is connected with the drift region, and the grid electrode structure is formed between the source electrode structure and the drain electrode structure; the semiconductor device is characterized in that the drain structure comprises a drain doped region and drain metal, the drain doped region is formed in the drift region and is away from the upper surface of the semiconductor substrate by a first preset distance, and the drain metal is connected with the drain doped region;
and an air cavity is formed above the drain electrode doped region and surrounds the drain electrode metal.
2. The LDMOS device of claim 1, further comprising a silicon nitride structure formed within the drift region and located between the drain structure and the source structure.
3. The LDMOS device of claim 2, wherein the gate structure comprises a gate oxide layer and a polysilicon gate; the gate oxide layer is formed between the drain electrode structure and the source electrode structure, the first end of the gate oxide layer is positioned above the drift region, and the second end of the gate oxide layer is positioned above the body region; the polysilicon gate is formed above the gate oxide layer; the first end of the gate oxide layer is also positioned above the silicon nitride structure.
4. The LDMOS device set forth in claim 1 wherein said source structure comprises a doped source region formed within said body region and a source metal connected to said doped source region.
5. The LDMOS device of claim 1, further comprising a guard ring structure; the guard ring structure comprises a guard ring doping area and guard ring metal, the guard ring doping area is formed in the semiconductor substrate, and the guard ring metal is connected with the guard ring doping area.
6. The LDMOS device of claim 5, further comprising a silicon dioxide layer formed on the semiconductor substrate, the drain metal, the source metal, and the guard ring metal being connected to the corresponding drain doped region, the source doped region, and the guard ring doped region through the silicon dioxide layer.
7. The LDMOS device of claim 6, further comprising a shallow trench isolation structure formed within the semiconductor substrate; the shallow trench isolation structure comprises a first shallow trench isolation structure and a second shallow trench isolation structure, the first shallow trench isolation structure and the second shallow trench isolation structure are respectively arranged on two sides of the protection ring doping area, one end of the first shallow trench isolation structure is located in the drift area and adjacent to the drain electrode structure, and the other end of the first shallow trench isolation structure is located outside the drift area.
8. The LDMOS device of claim 7, further comprising a high voltage P-well and a high voltage N-well formed within the semiconductor substrate, the drift region and the body region being formed within the high voltage N-well; one end of the second shallow trench isolation structure is formed in the high-voltage N well, and the other end of the second shallow trench isolation structure is adjacent to the high-voltage P well; and a preset distance is reserved between the high-voltage P trap and the high-voltage N trap.
9. A method of fabricating an LDMOS device, the method being for fabricating the LDMOS device of any one of claims 2 to 8, the method comprising:
forming a drift region and a body region in the semiconductor substrate by adopting an ion implantation process;
depositing a silicon nitride material on the surface of the semiconductor substrate, photoetching and etching the silicon nitride material and the semiconductor substrate at the corresponding position of the defined LOCOS region, and thermally oxidizing the semiconductor substrate to form a LOCOS structure;
etching to remove the LOCOS structure, depositing a silicon nitride material, and grinding the silicon nitride material to form a silicon nitride layer at a position corresponding to the LOCOS structure;
preparing a gate structure over a semiconductor substrate;
depositing a silicon dioxide material, photoetching and etching the silicon dioxide material at the corresponding positions of the defined source electrode doped region and the defined drain electrode doped region to form a silicon dioxide layer, and etching to remove the silicon nitride layer at the corresponding position of the drain electrode doped region;
forming a source electrode doped region and a drain electrode doped region in the semiconductor substrate at the corresponding positions of the defined source electrode doped region and the defined drain electrode doped region by adopting an ion implantation process;
and depositing a metal material, and photoetching and etching the metal material to form a source metal and a drain metal.
10. The method of fabricating an LDMOS device set forth in claim 9 wherein prior to forming the drift region and the body region, the method further comprises: and forming a high-voltage P well and a high-voltage N well in the semiconductor substrate by adopting an ion implantation process.
11. The method of fabricating the LDMOS device set forth in claim 9, further comprising: before depositing silicon nitride material on the surface of the semiconductor substrate, a shallow trench isolation structure is manufactured on the semiconductor substrate.
12. The method of fabricating an LDMOS device set forth in claim 9 further comprising: adopting the same manufacturing steps to form a protection ring doping area while forming a source doping area and a drain doping area;
the same metal material and manufacturing steps are adopted, and the guard ring metal is formed at the same time of forming the source electrode metal and the drain electrode metal.
13. A chip made using the LDMOS device of any one of claims 1 to 8.
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| CN115863416A (en) * | 2023-01-19 | 2023-03-28 | 北京智芯微电子科技有限公司 | LDMOSFET device isolated by air dielectric field plate and manufacturing method |
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| US20140027850A1 (en) * | 2012-07-27 | 2014-01-30 | Shanghai Hua Hong Nec Electronics Co., Ltd | Ldmos device with step-like drift region and fabrication method thereof |
| US20150145034A1 (en) * | 2013-11-24 | 2015-05-28 | United Microelectronics Corporation | Ldmos structure and manufacturing method thereof |
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| US20150145034A1 (en) * | 2013-11-24 | 2015-05-28 | United Microelectronics Corporation | Ldmos structure and manufacturing method thereof |
| US20200111906A1 (en) * | 2018-10-09 | 2020-04-09 | Richtek Technology Corporation | High voltage device and manufacturing method thereof |
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