CN115274660A - CMOS transistor based on AlPN/GaPN heterojunction and preparation method thereof - Google Patents

CMOS transistor based on AlPN/GaPN heterojunction and preparation method thereof Download PDF

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CN115274660A
CN115274660A CN202210762293.1A CN202210762293A CN115274660A CN 115274660 A CN115274660 A CN 115274660A CN 202210762293 A CN202210762293 A CN 202210762293A CN 115274660 A CN115274660 A CN 115274660A
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alpn
gapn
active region
hemt
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陈楷
张雅超
姚一昕
张进成
马佩军
郝跃
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Xidian University
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Xidian University
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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    • H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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Abstract

The invention discloses a CMOS transistor based on an AlPN/GaPN heterojunction and a preparation method thereof, wherein the transistor comprises a substrate, a first AlN layer, a second AlN layer, a GaN buffer layer and an SiN isolation layer which are sequentially arranged from bottom to top, wherein the SiN isolation layer is provided with a P-HEMT active region groove and an N-HEMT active region groove; a first AlPN barrier layer, a first GaPN channel layer and a first GaN cap layer are sequentially arranged in the groove of the active region of the P-HEMT from bottom to top; a second GaPN channel layer, a second AlPN barrier layer and a second GaN cap layer are sequentially arranged in the N-HEMT active region groove from bottom to top; the upper surface of the first GaN cap layer is provided with a first source electrode, a first drain electrode and a first grid electrode which are mutually spaced; and a second source electrode, a second drain electrode and a second grid electrode which are mutually spaced are arranged on the upper surface of the second GaN cap layer. The AlPN/GaPN heterojunction can realize lattice matching, the in-plane stress of the heterojunction can be effectively relieved, and the electrical property of the two-dimensional electron gas can be effectively improved.

Description

CMOS transistor based on AlPN/GaPN heterojunction and preparation method thereof
Technical Field
The invention belongs to the technical field of microelectronic integrated circuits, and particularly relates to a CMOS transistor based on an AlPN/GaPN heterojunction and a preparation method thereof.
Background
The third generation semiconductor represented by gallium nitride (GaN) has excellent physicochemical properties such as wide band gap, high breakdown field strength, high thermal conductivity, low dielectric constant, high electron saturation drift velocity, strong radiation resistance, good chemical stability and the like, becomes a key material for preparing a new generation of microelectronic devices and circuits after the first generation semiconductor silicon and the second generation semiconductor gallium arsenide, and is particularly suitable for developing high-frequency, high-power, high-temperature and radiation-resistant electronic devices and circuits. The GaN-based semiconductor material is the most important semiconductor material in the third generation semiconductor, has a wider forbidden band width, can effectively inhibit the band-to-band tunneling and the grid-induced drain leakage, and is widely applied commercially.
At present, a ternary alloy heterojunction structure such as an AlGaN/GaN heterojunction is used, stress exists between a barrier layer and a channel layer, between the barrier layer and the channel layer and between the channel layer and a lower buffer layer, which can cause poor crystallization quality of a film, and carriers in a lower channel have high alloy disordered scattering and inter-carrier scattering, so that the electrical properties such as mobility, surface density and sheet resistance of two-dimensional electron gas are poor, the performance of a device is reduced, and the development of many applications is limited.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a CMOS transistor based on an AlPN/GaPN heterojunction and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
one aspect of the invention provides a CMOS transistor based on an AlPN/GaPN heterojunction, which comprises a substrate, a first AlN layer, a second AlN layer, a GaN buffer layer and a SiN isolation layer which are arranged from bottom to top in sequence, wherein,
the SiN isolation layer is provided with a P-HEMT active region groove and an N-HEMT active region groove, and the P-HEMT active region groove and the N-HEMT active region groove extend from the upper surface of the SiN isolation layer to the upper surface of the GaN buffer layer;
a first AlPN barrier layer, a first GaPN channel layer and a first GaN cap layer are sequentially arranged in the P-HEMT active region groove from bottom to top; a second GaPN channel layer, a second AlPN barrier layer and a second GaN cap layer are sequentially arranged in the N-HEMT active region groove from bottom to top;
the upper surface of the first GaN cap layer is provided with a first source electrode, a first drain electrode and a first grid electrode which are mutually spaced; a second source electrode, a second drain electrode and a second grid electrode which are mutually spaced are arranged on the upper surface of the second GaN cap layer;
the growth temperature of the first AlN layer is lower than the growth temperature of the second AlN layer.
In an embodiment of the invention, the P-HEMT active region groove and the N-HEMT active region groove are symmetrically formed inside the SiN isolation layer and both extend from one side surface of the SiN isolation layer to the opposite other side surface.
In one embodiment of the present invention, the first source, the first drain and the first gate are isolated from each other by a SiN material, and the first gate is located between the first source and the first drain; the second source electrode, the second drain electrode and the second grid electrode are mutually isolated through SiN materials, and the second grid electrode is located between the second source electrode and the second drain electrode.
In one embodiment of the present invention, a pre-laid aluminum layer is further included between the substrate and the first AlN layer.
In one embodiment of the invention, the surface areas of the first AlPN barrier layer and the first GaPN channel layer are equal and equal to the inner surface area of the groove of the P-HEMT active region; the surface areas of the second GaPN channel layer and the second AlPN barrier layer are equal and equal to the inner surface area of the groove of the N-HEMT active area.
In one embodiment of the invention, the first AlPN barrier layer and the first GaPN channel layer form a heterojunction structure AlPN/GaPN, and the second GaPN channel layer and the second AlPN barrier layer form a heterojunction structure GaPN/AlPN.
In one embodiment of the invention, the first AlPN barrier layer has a thickness of 20-40nm, and the first GaPN channel layer has a thickness of 10-30nm; the thickness of the second GaPN channel layer is 10-30nm, and the thickness of the second AlPN barrier layer is 20-40nm.
Another aspect of the present invention provides a method for fabricating a CMOS transistor based on an AlPN/gap pn heterojunction, the method being used to fabricate the CMOS transistor in any one of the above embodiments, and the method comprising:
selecting a substrate and carrying out pre-baking treatment on the substrate;
sequentially growing a first AlN layer, a second AlN layer and a GaN buffer layer on the substrate;
depositing and forming a SiN isolation layer on the GaN buffer layer, and etching a groove of an active region of the P-HEMT on the SiN isolation layer;
forming a first AlPN barrier layer and a first GaPN channel layer in the groove of the active region of the P-HEMT from bottom to top respectively;
etching an N-HEMT active region groove on the SiN isolation layer, and respectively forming a second GaPN channel layer and a second AlPN barrier layer in the N-HEMT active region groove from bottom to top;
growing a first GaN cap layer on the first GaPN channel layer, and growing a second GaN cap layer on the second AlPN barrier layer;
and forming a first source electrode, a first drain electrode and a first grid electrode on the first GaN cap layer, and forming a second source electrode, a second drain electrode and a second grid electrode on the second GaN cap layer.
In one embodiment of the present invention, sequentially growing a first AlN layer, a second AlN layer, and a GaN buffer layer on the substrate includes:
introducing trimethyl aluminum into a reaction chamber of MOCVD equipment at the temperature of 1050-1150 ℃ to grow a pre-laid aluminum layer with the thickness of 30-100nm on the substrate;
introducing trimethylaluminum and ammonia gas to grow a first AlN layer with the thickness of 20-40nm on the pre-laid aluminum layer;
adjusting the temperature of the reaction chamber to 1150-1250 ℃, and introducing trimethylaluminum and ammonia gas to grow a second AlN layer with the thickness of 150-200nm on the first AlN layer;
adjusting the temperature of the reaction chamber to 1100-1200 ℃, and introducing trimethyl gallium and ammonia gas to grow a GaN buffer layer with the thickness of 800-1000nm on the second AlN layer.
In one embodiment of the invention, a first AlPN barrier layer and a first GaPN channel layer are respectively formed in the groove of the active area of the P-HEMT from bottom to top, comprising the following steps:
adjusting the temperature of a reaction chamber of MOCVD equipment to 1150-1160 ℃, introducing trimethylaluminum, tert-butylphosphine and ammonia gas to react to generate a first AlPN barrier layer with the thickness of 20-40nm, wherein the lower surface of the first AlPN barrier layer is in contact with the upper surface of the GaN buffer layer, the flow rate of the trimethylaluminum is 100sccm, the flow rate of the tert-butylphosphine is 30sccm, and the flow rate of the ammonia gas is 4000sccm;
adjusting the temperature of a reaction chamber of the MOCVD equipment to 1070-1085 ℃, introducing trimethyl gallium, tert-butylphosphine and ammonia gas to react on the first AlPN barrier layer to generate a first GaPN channel layer with the thickness of 10-30nm, wherein the flow rate of trimethyl gallium is 500sccm, the flow rate of tert-butylphosphine is 800sccm, and the flow rate of ammonia gas is 50000sccm.
Compared with the prior art, the invention has the beneficial effects that:
1. the CMOS transistor is based on the AlPN/GaPN heterojunction, can realize lattice matching, effectively relieves the in-plane stress of the heterojunction, and effectively improves the electrical property of two-dimensional electron gas; and the mobility of two-dimensional hole gas in GaPN/AlPN is larger, thereby realizing the application of high-efficiency CMOS transistor and circuit.
2. In the embodiment, two-dimensional hole gas generated by polarization induction in the GaPN/AlPN heterojunction is used as a source of a P-type HEMT carrier, monolithic integration is realized with an N-type HEMT material, the vacancy of a high-performance PMOS transistor can be filled, and the requirement of high-performance CMOS is further met.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of a CMOS transistor based on an AlPN/gap pn heterojunction according to an embodiment of the present invention;
fig. 2 is a top view of a CMOS transistor based on an AlPN/gap pn heterojunction according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for fabricating a CMOS transistor based on an AlPN/gap n heterojunction according to an embodiment of the present invention;
fig. 4a to fig. 4g are schematic diagrams of a process for fabricating a CMOS transistor based on an AlPN/gap pn heterojunction according to an embodiment of the present invention.
Description of the reference numerals:
1-a substrate; 2-a first AlN layer; 3-a second AlN layer; 4-a GaN buffer layer; 5-SiN isolation layer; 6-P-HEMT active region groove; 7-a first AlPN barrier layer; 8-a first GaPN channel layer; a 9-N-HEMT active region groove; 10-a second GaPN channel layer; 11-a second AlPN barrier layer; 12-a first GaN cap layer; 13-a second GaN cap layer; 14-a first source; 15-a first drain electrode; 16-a first gate; 17-a second source; 18-a second drain electrode; 19-second gate.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, a CMOS transistor based on AlPN/gap n heterojunction and a method for fabricating the same according to the present invention will be described in detail with reference to the accompanying drawings and embodiments.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of additional like elements in an article or apparatus that comprises the element.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a CMOS transistor based on AlPN/GaPN and GaPN/AlPN heterojunctions according to an embodiment of the present invention. The CMOS transistor comprises a substrate 1, a first AlN layer 2, a second AlN layer 3, a GaN buffer layer 4 and an SiN isolation layer 5 which are sequentially arranged from bottom to top, wherein a P-HEMT active region groove 6, an N-HEMT active region groove 9,P, the thickness of the SiN isolation layer 5 is equal to the depth of the N-HEMT active region groove 6 and the depth of the N-HEMT active region groove 9, namely the P-HEMT active region groove 6 and the N-HEMT active region groove 9 extend to the upper surface of the GaN buffer layer 4 from the upper surface of the SiN isolation layer 5. A first AlPN barrier layer 7, a first GaPN channel layer 8 and a first GaN cap layer 12 are sequentially arranged in the P-HEMT active region groove 6 from bottom to top; a second GaPN channel layer 10, a second AlPN barrier layer 11 and a second GaN cap layer 13 are sequentially arranged in the N-HEMT active region groove 9 from bottom to top; the upper surface of the first GaN cap layer 12 is provided with a first source electrode 14, a first drain electrode 15 and a first grid electrode 16 which are spaced from each other; a second source electrode 17, a second drain electrode 18 and a second gate electrode 19 are provided on the upper surface of the second GaN cap layer 13 at a distance from each other.
In this embodiment, the substrate 1 is a sapphire substrate, the first AlN layer 2 is a low-temperature AlN layer, the second AlN layer 3 is a high-temperature AlN layer, and the growth temperature of the first AlN layer 2 is lower than that of the second AlN layer 3. Preferably, the thickness of the first AlN layer 2 is 20 to 40nm, and the thickness of the second AlN layer 3 is 150 to 200nm. The first AlN layer 2 is formed by reacting at a temperature of 1050 ℃ to 1150 ℃, the second AlN layer 3 is formed by reacting at a temperature of 1150 ℃ to 1250 ℃, and AlN grows in a three-dimensional growth mode at a relatively low temperature and in a two-dimensional growth mode at a relatively high temperature. The thickness of the GaN buffer layer 4 is 800 to 1000nm.
Further, a pre-paved aluminum layer (not shown in the drawing) is further included between the substrate 1 and the first AlN layer 2, the thickness is about 20-40nm, and due to poor migration of Al atoms on the surface of the substrate, the mobility of aluminum can be effectively improved by the pre-paved aluminum layer, and the quality of a subsequent epitaxial layer is improved, so that the electrical performance of the transistor is improved.
Referring to fig. 1 and 2, fig. 2 is a top view of a CMOS transistor based on AlPN/gap heterojunction according to an embodiment of the present invention, in which a P-HEMT active region recess 6 and an N-HEMT active region recess 9 are symmetrically formed in an SiN isolation layer 5 and extend from one side of the SiN isolation layer 5 to the opposite side thereof, in other words, the P-HEMT active region recess 6 and the N-HEMT active region recess 9 are both open-ended slots having a width equal to the width of the SiN isolation layer 5.
Further, the P-HEMT active region groove 6 and the N-HEMT active region groove 9 have the same depth. The lower surfaces of the P-HEMT active region groove 6 and the N-HEMT active region groove 9 are both in contact with the upper surface of the GaN buffer layer 4. The surface areas of the first AlPN barrier layer 7 and the first GaPN channel layer 8 are equal and equal to the inner surface area of the groove 6 of the active area of the P-HEMT, and the first AlPN barrier layer 7 and the first GaPN channel layer 8 form a heterojunction structure AlPN/GaPN; the surface areas of the second GaPN channel layer 10 and the second AlPN barrier layer 11 are equal and equal to the inner surface area of the N-HEMT active area groove 9, and the second GaPN channel layer 10 and the second AlPN barrier layer 11 form a heterojunction structure GaPN/AlPN.
Further, the thickness of the first AlPN barrier layer 7 is 20-40nm, and the thickness of the first GaPN channel layer 8 is 10-30nm; the thickness of the second GaPN channel layer 10 is 10-30nm, and the thickness of the second AlPN barrier layer 11 is 20-40nm.
As shown in fig. 2, the first source 14, the first drain 15 and the first gate 16 are isolated from each other by SiN material, and the first gate 16 is located between the first source 14 and the first drain 15. The lower surfaces of the first source electrode 14, the first drain electrode 15 and the first gate electrode 16 are all in contact with the upper surface of the first GaN cap layer 12, and form ohmic contacts, respectively.
The second source electrode 17, the second drain electrode 18 and the second gate electrode 19 are isolated from each other by SiN material, the second gate electrode 19 is located between the second source electrode 17 and the second drain electrode 18, and the lower surfaces of the second source electrode 17, the second drain electrode 18 and the second gate electrode 19 are all in contact with the upper surface of the second GaN cap layer 13 and respectively form ohmic contact.
Preferably, the first source electrode 14, the first drain electrode 15, the second source electrode 17 and the second drain electrode 18 all include four layers of metal of Ti/Al/Ni/Au from bottom to top, and the first gate electrode 16 and the second gate electrode 19 include two layers of metal of Ni/Au from bottom to top.
This embodiment provides a CMOS transistor based on an AlPN/gap n heterojunction, in which the lattice matching between the AlPN and gap n materials is very small compared to the conventional AlGaN/GaN heterojunction transistor. In the embodiment, the AlPN is used as the barrier layer, so that high lattice vibration scattering caused by the quality reduction of the film material can be effectively inhibited, and the band limitation of the two-dimensional electron gas is improved by utilizing the energy band modulation, so that the electrical characteristics such as the surface density, the mobility and the like of the two-dimensional electron gas are improved. The AlPN and the GaPN can better realize lattice matching than the traditional AlGaN and GaN, and avoid the bad influence of the warping and heat dissipation problems caused by in-plane stress on the performance of subsequent devices. In addition, in the embodiment, two-dimensional hole gas generated by polarization induction in the GaPN/AlPN heterojunction is used as a source of a P-type HEMT carrier, monolithic integration is realized with an N-type HEMT material, the vacancy of a high-performance PMOS transistor can be filled, and the requirement of high-performance CMOS is further met.
Example two
On the basis of the above embodiments, this embodiment provides a method for manufacturing a CMOS transistor based on an AlPN/gap pn heterojunction, the manufacturing process is performed under the condition of Metal Organic Chemical Vapor Deposition (MOCVD) equipment, the MOCVD growth process is performed under a certain pressure and temperature, the metal organic source in the manufacturing process is ammonia gas, TMAl (trimethylaluminum), TMGa (trimethylgallium), tBp (tertiarybutylphosphine), and the carrier gas is N2. Specifically, the method for manufacturing the CMOS transistor of the present embodiment includes the following steps:
s1: selecting a substrate 1 and carrying out prebaking treatment on the substrate.
Specifically, sapphire is selected as the substrate 1, and a pre-baking process is performed in the MOCVD equipment.
S2: a first AlN layer 2, a second AlN layer 3, and a GaN buffer layer 4 are sequentially grown on a substrate 1, as shown in fig. 4 a.
S2 of the present embodiment includes:
s21: introducing trimethyl aluminum into a reaction chamber of the MOCVD equipment at the temperature of 1050-1150 ℃ to grow a pre-laid aluminum layer on the substrate 1.
Specifically, under the condition that the temperature of an MOCVD equipment reaction chamber is 1100 ℃, trimethylaluminum is introduced for 3min, and a pre-laid aluminum layer is grown on a substrate 1 to obtain a pre-laid aluminum layer (not shown in the attached drawing) with the thickness of 30-100 nm.
S22: trimethylaluminum and ammonia gas are fed at a temperature of 1050 ℃ to 1150 ℃ to grow a first AlN layer 2 on the pre-laid aluminum layer.
Specifically, under the condition that the temperature of the MOCVD equipment reaction chamber is 1100 ℃, trimethyl aluminum and ammonia gas are introduced to grow a first AlN layer 2 with the thickness of 20-40nm on the pre-laid aluminum layer, and AlN grows in a three-dimensional growth mode at a relatively low temperature.
S23: the temperature of the reaction chamber was adjusted to 1150 ℃ to 1250 ℃, and trimethylaluminum and ammonia gas were introduced to grow the second AlN layer 3 on the first AlN layer 2.
Specifically, under the temperature condition of 1210 ℃ in a reaction chamber of the MOCVD equipment, trimethyl aluminum and ammonia gas are introduced to grow a second AlN layer 3 with the thickness of 150-200nm on the first AlN layer 2, and AlN grows in a two-dimensional growth mode at a relatively high temperature. In this embodiment, the variable temperature growth mode of the second AlN layer 3 and the first AlN layer 2 is applied, so that the roughness of the subsequent epitaxial layer is lower and the crystal quality is better.
S24: the temperature of the reaction chamber was adjusted to 1100 ℃ to 1200 ℃, and trimethylgallium and ammonia gas were introduced to grow the GaN buffer layer 4 on the second AlN layer 3.
Specifically, trimethyl gallium and ammonia gas were introduced for 40min at a temperature of 1150 ℃ in the MOCVD apparatus reaction chamber to grow a 800-1000nm thick GaN buffer layer 4 on the basis of the second AlN layer 3.
S3: a SiN isolation layer 5 is deposited on the GaN buffer layer 4, and a P-HEMT active region groove 6 is etched on the SiN isolation layer 5, as shown in fig. 4b1 and 4b2, wherein fig. 4b2 is a top view corresponding to fig. 4b 1.
Specifically, a SiN isolation layer 5 is deposited on the GaN buffer layer 4, then a P-HEMT active region pattern is formed on the SiN isolation layer 5 by photolithography, the P-HEMT active region pattern is etched to form a P-HEMT active region groove 6, the depth of the P-HEMT active region groove 6 is equal to the thickness of the SiN isolation layer 5 so that the lower surface of the P-HEMT active region groove 6 extends to the upper surface of the GaN buffer layer 4, and the P-HEMT active region groove 6 extends from one side surface of the SiN isolation layer 5 to the opposite other side surface, in other words, the P-HEMT active region groove 6 is a groove open at both ends and has a width equal to the width of the SiN isolation layer 5.
S4: a first AlPN barrier layer 7 and a first GaPN channel layer 8 are respectively formed in the groove 6 of the active area of the P-HEMT from bottom to top.
Specifically, the temperature of the reaction chamber of the MOCVD equipment is adjusted to 1150-1160 ℃, trimethylaluminum, tert-butyl phosphorus and ammonia gas are introduced, a first AlPN barrier layer 7 with the thickness of 20-40nm grows in the groove 6 of the P-HEMT active region, and the lower surface of the first AlPN barrier layer 7 is in contact with the upper surface of the GaN buffer layer 4. The first AlPN barrier layer 7 has a low v/iii ratio (mole fraction ratio of the group v element N and the group iii element Ga or Al) so that the P element replaces N vacancy, reducing tensile stress. In this embodiment, the V/III ratio of the first AlPN barrier layer 7 is greater than or equal to 1000.
Then, the temperature of the reaction chamber of the MOCVD equipment is adjusted to 1070 ℃ to 1085 ℃, trimethyl gallium, tertiary butyl phosphorus and ammonia gas are introduced, and a first GaPN channel layer 8 with the thickness of 10nm to 30nm is grown on the first AlPN barrier layer 7. The V/III ratio of the first GaPN channel layer 8 is lower than that of the first AlPN barrier layer 7, so that the P element replaces Ga vacancy, and the compressive stress is reduced. In this embodiment, the depth of the P-HEMT active region recess 6 is equal to the sum of the thicknesses of the first AlPN barrier layer 7 and the first GaPN channel layer 8.
S5: and etching an N-HEMT active region groove 9 on the SiN isolation layer 5, and respectively forming a second GaPN channel layer 10 and a second AlPN barrier layer 11 in the N-HEMT active region groove 9 from bottom to top.
Specifically, first, a SiN material is deposited on the upper surface of the sample wafer obtained in step S4 as a hard mask, the N-HEMT active region pattern is subjected to photolithography and the SiN isolation layer 5 in the N-HEMT active region pattern is etched away, so as to form an N-HEMT active region groove 9 spaced apart from the P-HEMT active region groove 6, as shown in fig. 4d1 and 4d2, where fig. 4d2 is a top view corresponding to fig. 4d 1. In this embodiment, the P-HEMT active region groove 6 and the N-HEMT active region groove 9 are symmetrically formed on both sides of the upper surface of the SiN isolation layer 5, and have the same shape and depth. In other words, the depth of the N-HEMT active region groove 9 is equal to the thickness of the SiN isolation layer 5 so that the lower surface of the N-HEMT active region groove 9 extends to the upper surface of the GaN buffer layer 4, and the P-HEMT active region groove 6 and the N-HEMT active region groove 9 are both grooves with openings at both ends and the width of the grooves is equal to the width of the SiN isolation layer 5.
Further, the temperature of the reaction chamber of the MOCVD equipment is adjusted to 1070 ℃ to 1085 ℃, trimethyl gallium, tertiary butyl phosphorus and ammonia gas are introduced, a second GaPN channel layer 10 with the thickness of 10nm to 30nm is grown in the groove 9 of the active region of the N-HEMT, and the V/III ratio of the second GaPN channel layer 10 is lower than that of the first AlPN barrier layer 7, so that P elements replace Ga vacancies, and the compressive stress is reduced.
Subsequently, the temperature of the reaction chamber of the MOCVD apparatus was adjusted to 1150 deg.C-1160 deg.C, trimethylaluminum, t-butylphosphine and ammonia gas were introduced, and a second AlPN barrier layer 11 with a thickness of 20-40nm was grown on the second GaPN channel layer 10, as shown in FIG. 4 e. The V/III ratio of the second AlPN barrier layer 11 is the same as that of the first AlPN barrier layer 7, so that P element replaces N vacancy, and tensile stress is reduced. In this embodiment, the depth of the N-HEMT active region recess 9 is equal to the sum of the thicknesses of the second AlPN barrier layer 11 and the second GaPN channel layer 10.
S6: a first GaN cap layer 12 is grown on the first GaPN channel layer 8, and a second GaN cap layer 13 is grown on the second AlPN barrier layer 11.
Specifically, on the basis of the previous step, the N-HEMT active region and the P-HEMT active region are etched simultaneously, i.e., the upper surfaces of the first gap N channel layer 8 and the second GaN cap layer 13 are exposed simultaneously, and the growth of the GaN cap layers is performed, and a first GaN cap layer 12 with a thickness of 3nm and a second GaN cap layer 13 with a thickness of 3nm are formed on the first gap N channel layer 8 and the second AlPN barrier layer 11, respectively, as shown in fig. 4 f.
S7: a first source electrode 14, a first drain electrode 15 and a first gate electrode 16 are formed on the first GaN cap layer 12, and a second source electrode 17, a second drain electrode 18 and a second gate electrode 19 are formed on the second GaN cap layer 13, as shown in fig. 4 g.
Specifically, siN is deposited on the first GaN cap layer 12 and the second GaN cap layer 13 as a hard mask, a first source electrode groove, a first drain electrode groove and a first grid electrode groove are respectively etched on the first GaN cap layer 12, and a second source electrode groove, a second drain electrode groove and a second grid electrode groove are respectively etched on the second GaN cap layer 13; and then, depositing Ti/Al/Ni/Au metal on the first source electrode groove and the first drain electrode groove to form ohmic contact of the first source electrode and the first drain electrode, and depositing Ti/Al/Ni/Au metal on the second source electrode groove and the second drain electrode groove to form ohmic contact of the first source electrode and the second drain electrode. And then annealing is carried out, ni/Au metal is deposited in the first grid electrode groove after annealing to make ohmic contact of the first grid electrode, and Ni/Au metal is deposited in the second grid electrode groove to make ohmic contact of the first grid electrode and the second grid electrode.
In the embodiment, two-dimensional hole gas generated by polarization induction in the GaPN/AlPN heterojunction is used as a source of a P-type HEMT carrier, monolithic integration is realized with an N-type HEMT material, the vacancy of a high-performance PMOS transistor can be filled, and the requirement of high-performance CMOS is further met.
EXAMPLE III
On the basis of the above embodiments, this embodiment specifically describes a method for manufacturing a CMOS transistor based on an AlPN/gap pn heterojunction, where the manufacturing process includes:
(1) Placing the pretreated (0001) plane sapphire substrate into MOCVD equipment, and growing a pre-laid aluminum layer on the substrate, wherein the flow rate of trimethylaluminum is 20sccm, and the time is 3 minutes; followed by growth of a 25nm thick first AlN layer at 1100 ℃; then growing a second AlN layer with the thickness of 180nm at 1210 ℃; a GaN buffer layer with a thickness of 1 μm was grown by introducing trimethyl gallium at a flow rate of 50sccm and ammonia at a flow rate of 3500sccm at 1030 ℃.
(2) Depositing an SiN isolation layer, photoetching and etching a P-HEMT active region groove, wherein the depth of the P-HEMT active region groove is equal to the thickness of the SiN isolation layer, introducing trimethylaluminum with the flow rate of 100sccm, tert-butylphosphonium with the flow rate of 30sccm and ammonia gas with the flow rate of 4000sccm at 1150 ℃, and growing a first AlPN barrier layer with the thickness of 20nm, wherein the lower surface of the first AlPN barrier layer is in contact with the upper surface of the GaN buffer layer.
(3) The temperature of a reaction chamber of the MOCVD equipment is adjusted to 1070 ℃, trimethyl gallium, tert-butylphosphine and ammonia gas are introduced to react on the first AlPN barrier layer to generate a first GaPN channel layer with the thickness of 10nm, wherein the flow rate of trimethyl gallium is 500sccm, the flow rate of tert-butylphosphine is 800sccm, and the flow rate of ammonia gas is 50000sccm.
(4) And photoetching and etching a groove of the N-HEMT active area, wherein the depth of the groove of the N-HEMT active area is equal to the thickness of the SiN isolation layer, and introducing trimethyl gallium, tert-butylphosphine and ammonia gas at 1070 ℃ to react to generate a second GaPN channel layer with the thickness of 10nm, wherein the flow of trimethyl gallium is 500sccm, the flow of tert-butylphosphine is 800sccm, and the flow of ammonia gas is 50000sccm. The lower surface of the second GaPN channel layer is in contact with the upper surface of the GaN buffer layer.
(5) The temperature of the reaction chamber was adjusted to 1150 ℃, trimethylaluminum with a flow rate of 100sccm, tertbutylphosphine with a flow rate of 30sccm, and ammonia gas with a flow rate of 4000sccm were introduced to grow a 20nm thick second AlPN barrier layer on the second gap n channel layer.
(6) Depositing a SiN mask, photoetching and etching an N-HEMT active region and a P-HEMT active region, growing a first GaN cap layer on the first GaPN channel layer, growing a second GaN cap layer on the second AlPN barrier layer, etching a first source electrode groove, a first drain electrode groove and a first grid electrode groove on the first GaN cap layer respectively, and etching a second source electrode groove, a second drain electrode groove and a second grid electrode groove on the second GaN cap layer respectively; and then, depositing Ti/Al/Ni/Au metal on the first source electrode groove and the first drain electrode groove to form ohmic contact of the first source electrode and the first drain electrode, and depositing Ti/Al/Ni/Au metal on the second source electrode groove and the second drain electrode groove to form ohmic contact of the first source electrode and the second drain electrode. And then annealing is carried out, ni/Au metal is deposited in the first grid electrode groove after annealing to make ohmic contact of the first grid electrode, and Ni/Au metal is deposited in the second grid electrode groove to make ohmic contact of the first grid electrode and the second grid electrode.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1. A CMOS transistor based on an AlPN/GaPN heterojunction is characterized by comprising a substrate (1), a first AlN layer (2), a second AlN layer (3), a GaN buffer layer (4) and a SiN isolation layer (5) which are arranged from bottom to top in sequence, wherein,
a P-HEMT active region groove (6) and an N-HEMT active region groove (9) are formed in the SiN isolation layer (5), and the P-HEMT active region groove (6) and the N-HEMT active region groove (9) extend from the upper surface of the SiN isolation layer (5) to the upper surface of the GaN buffer layer (4);
a first AlPN barrier layer (7), a first GaPN channel layer (8) and a first GaN cap layer (12) are sequentially arranged in the P-HEMT active region groove (6) from bottom to top; a second GaPN channel layer (10), a second AlPN barrier layer (11) and a second GaN cap layer (13) are sequentially arranged in the N-HEMT active region groove (9) from bottom to top;
the upper surface of the first GaN cap layer (12) is provided with a first source electrode (14), a first drain electrode (15) and a first grid electrode (16) which are spaced from each other; a second source electrode (17), a second drain electrode (18) and a second grid electrode (19) which are spaced from each other are arranged on the upper surface of the second GaN cap layer (13);
the growth temperature of the first AlN layer (2) is lower than the growth temperature of the second AlN layer (3).
2. The AlPN/GaPN heterojunction-based CMOS transistor according to claim 1, wherein the P-HEMT active region recess (6) and the N-HEMT active region recess (9) are symmetrically opened inside the SiN isolation layer (5) and both extend from one side of the SiN isolation layer (5) to the opposite side.
3. The AlPN/gap pn heterojunction based CMOS transistor according to claim 1, wherein the first source (14), the first drain (15) and the first gate (16) are isolated from each other by a SiN material, and the first gate (16) is located between the first source (14) and the first drain (15); the second source (17), the second drain (18) and the second gate (19) are isolated from each other by a SiN material, and the second gate (19) is located between the second source (17) and the second drain (18).
4. The AlPN/gap pn heterojunction based CMOS transistor according to claim 1, further comprising a pre-laid aluminum layer between the substrate (1) and the first AlN layer (2).
5. The AlPN/GaPN heterojunction based CMOS transistor according to claim 1, wherein the surface areas of the first AlPN barrier layer (7) and the first GaPN channel layer (8) are equal, equal to the inner surface area of the P-HEMT active region recess (6); the surface areas of the second GaPN channel layer (10) and the second AlPN barrier layer (11) are equal and equal to the inner surface area of the N-HEMT active region groove (9).
6. The AlPN/GaPN heterojunction based CMOS transistor according to claim 1, wherein the first AlPN barrier layer (7) and the first GaPN channel layer (8) form a heterojunction structure AlPN/GaPN, and the second GaPN channel layer (10) and the second AlPN barrier layer (11) form a heterojunction structure GaPN/AlPN.
7. The AlPN/GaPN heterojunction based CMOS transistor according to claim 1, wherein the thickness of the first AlPN barrier layer (7) is 20-40nm and the thickness of the first GaPN channel layer (8) is 10-30nm; the thickness of the second GaPN channel layer (10) is 10-30nm, and the thickness of the second AlPN barrier layer (11) is 20-40nm.
8. A method of fabricating an AlPN/gap pn heterojunction based CMOS transistor, for fabricating the CMOS transistor of any of claims 1 to 7, the method comprising:
selecting a substrate and carrying out pre-baking treatment on the substrate;
sequentially growing a first AlN layer, a second AlN layer and a GaN buffer layer on the substrate;
depositing and forming a SiN isolation layer on the GaN buffer layer, and etching a groove of an active region of the P-HEMT on the SiN isolation layer;
respectively forming a first AlPN barrier layer and a first GaPN channel layer in the groove of the active region of the P-HEMT from bottom to top;
etching an N-HEMT active region groove on the SiN isolation layer, and respectively forming a second GaPN channel layer and a second AlPN barrier layer in the N-HEMT active region groove from bottom to top;
growing a first GaN cap layer on the first GaPN channel layer, and growing a second GaN cap layer on the second AlPN barrier layer;
and forming a first source electrode, a first drain electrode and a first grid electrode on the first GaN cap layer, and forming a second source electrode, a second drain electrode and a second grid electrode on the second GaN cap layer.
9. The method of claim 8, wherein sequentially growing a first AlN layer, a second AlN layer, and a GaN buffer layer on the substrate comprises:
introducing trimethyl aluminum into a reaction chamber of MOCVD equipment at the temperature of 1050-1150 ℃ to grow a pre-laid aluminum layer with the thickness of 30-100nm on the substrate;
introducing trimethylaluminum and ammonia gas to grow a first AlN layer with the thickness of 20-40nm on the pre-laid aluminum layer;
adjusting the temperature of the reaction chamber to 1150-1250 ℃, and introducing trimethyl aluminum and ammonia gas to grow a second AlN layer with the thickness of 150-200nm on the first AlN layer;
adjusting the temperature of the reaction chamber to 1100-1200 ℃, and introducing trimethyl gallium and ammonia gas to grow a GaN buffer layer with the thickness of 800-1000nm on the second AlN layer.
10. The method of claim 8 or 9, wherein forming a first AlPN barrier layer and a first gap n channel layer in the P-HEMT active region recess from bottom to top respectively comprises:
adjusting the temperature of a reaction chamber of the MOCVD equipment to 1150-1160 ℃, introducing trimethylaluminum, tert-butylphosphine and ammonia gas to react to generate a first AlPN barrier layer with the thickness of 20-40nm, wherein the lower surface of the first AlPN barrier layer is in contact with the upper surface of the GaN buffer layer, the flow of the trimethylaluminum is 100sccm, the flow of the tert-butylphosphine is 30sccm, and the flow of the ammonia gas is 4000sccm;
adjusting the temperature of a reaction chamber of MOCVD equipment to 1070-1085 ℃, introducing trimethyl gallium, tertiary butyl phosphorus and ammonia gas to react on the first AlPN barrier layer to generate a first GaPN channel layer with the thickness of 10-30nm, wherein the flow rate of trimethyl gallium is 500sccm, the flow rate of tertiary butyl phosphorus is 800sccm, and the flow rate of ammonia gas is 50000sccm.
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