CN115274612A

CN115274612A - Integrated circuit

Info

Publication number: CN115274612A
Application number: CN202110477067.4A
Authority: CN
Inventors: 张小敏; 周峻民; 曹梦逸
Original assignee: Shanghai Huawei Technologies Co Ltd
Current assignee: Shanghai Huawei Technologies Co Ltd
Priority date: 2021-04-29
Filing date: 2021-04-29
Publication date: 2022-11-01
Also published as: WO2022228369A1

Abstract

The embodiment of the application discloses an integrated circuit, which comprises a substrate and a first circuit, wherein the first circuit comprises a capacitor and a wiring related to (electrically connected with) the capacitor, the signal current of one plate of the capacitor flows through n conductive structures in the substrate to be led out of the opposite side of the substrate from one surface of the substrate, and the n conductive structures penetrate through the substrate from the second surface of the substrate to the plate, so that the size of the capacitor and the wiring related to the capacitor is favorably reduced, the size of the integrated circuit is favorably reduced, the path length of the plate through which the signal current passes is favorably reduced, the loss of the integrated circuit is favorably reduced, and the Q value of the capacitor is favorably improved.

Description

Integrated circuit

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to an integrated circuit.

Background

An integrated circuit (integrated circuit) is a kind of micro electronic device or component, and the electronic device or component is pushed to be miniaturized and high performance (e.g., low power consumption and high reliability, etc.) in a large step. With the continuous reduction of the size of electronic devices, how to further reduce the size of integrated circuits and improve the performance of integrated circuits has become a key research point in the field of integrated circuits.

An integrated circuit generally integrates a large number of capacitors, and the design of the capacitors and the wiring related to the capacitors greatly affects the size and performance of the integrated circuit.

Disclosure of Invention

Embodiments of the present application provide an integrated circuit, which is configured to provide a design of a capacitor and a wiring related to the capacitor, so as to reduce the size of the integrated circuit and improve the performance of the integrated circuit.

The embodiment of the application provides an integrated circuit, which comprises a substrate and a first circuit, wherein the first circuit comprises a capacitor and n conductive structures; the capacitor comprises a first metal layer, a first dielectric layer and a second metal layer, wherein the first metal layer is positioned on the first surface of the substrate, the first dielectric layer is positioned on the first metal layer, and the second metal layer is positioned on the first dielectric layer; the n conductive structures are positioned in the substrate, and the ith conductive structure in the n conductive structures penetrates through the substrate from the second surface of the substrate to the first metal layer so as to conduct the charging current or the discharging current of the first metal layer, wherein the second surface is positioned on the opposite side of the first surface, n is a positive integer, and i is any positive integer not larger than n.

In the integrated circuit provided by the embodiment of the application, the charging current or the discharging current of the two electrode plates (the first metal layer and the second metal layer) of the capacitor is led out to the two sides of the substrate, which is beneficial to realizing the interconnection of the signal current of the two electrode plates of the capacitor on the two sides of the substrate. In addition, the area occupied by the capacitor and the wiring related to the capacitor (or called as electric connection) in the substrate surface direction is close to or equal to the area of the first metal layer as the polar plate, and compared with the existing integrated circuit, the size of the integrated circuit is favorably reduced. And because the signal current of the second metal layer can be led out to the second surface of the substrate by flowing through the n conductive structures, and the length of the path through which the signal current passes is close to or equal to the thickness of the substrate, compared with the prior art, the method is favorable for reducing the length of the path through which the signal current passes, thereby being favorable for reducing the loss of the integrated circuit, and being favorable for improving the Q value of the capacitor (the capacitor corresponding to the first metal layer, the first dielectric layer and the second metal layer).

When n is greater than 1, the signal current of the first metal layer is conducted from the first surface to the second surface of the substrate by penetrating the substrate through 2 or more than 2 conductive structures, so that the cross-sectional area of a conductive path is increased, the total resistance of the n conductive structures is reduced, and the loss of the signal current is reduced. Compared with 1 conductive structure, in order to achieve the same total cross street area, 2 or more than 2 conductive structures are prepared, so that the cross street area of each conductive structure is reduced. If the conductive structure is a hollow structure, the deformation risk of the first metal layer is reduced, and the reliability of the capacitor is improved. If the conductive structure is a solid structure, the flatness of the end face of the single conductive structure on the first surface is favorably improved by reducing the cross sectional area of the single conductive structure, so that the flatness of the first metal layer is favorably improved, and the reliability of the capacitor is improved.

In one possible implementation, the jth conductive structure of the n conductive structures is a pillar structure, where j is a positive integer no greater than n. The conductive structure with the cylindrical structure is beneficial to reducing the processing difficulty and the preparation cost of the integrated circuit.

In one possible implementation, an extension of the axis of the jth conductive structure passes through the first dielectric layer.

In one possible implementation, the axis of the jth conductive structure is perpendicular to the first surface.

In a possible implementation manner, the ith conductive structure penetrates through the substrate from the second surface of the substrate to the first region of the first metal layer, and the first region is an overlapping region among the first metal layer, the first dielectric layer and the second metal layer. Compared with the second region of the ith conductive structure, the second region of the ith conductive structure penetrates through the substrate from the second surface of the substrate to the first metal layer, the path length of the signal current passing through the ith conductive structure from the second surface of the substrate to the first region of the first metal layer is further reduced, the loss of the integrated circuit is reduced, and the Q value of the capacitor (the capacitor corresponding to the first metal layer, the first dielectric layer and the second metal layer) is improved.

In a possible implementation manner, the thickness of the substrate is greater than that of the capacitor, which is beneficial for the substrate to provide higher support for the capacitor and reduces the risk of damage to the capacitor.

In one possible implementation, the first circuit further includes a third metal layer; the third metal layer is located on the second surface, and the third metal layer is electrically connected with the first metal layer through the n conductive structures.

In one possible implementation, the third metal layer is a ground metal layer or is used to connect active circuits.

In one possible implementation manner, the first circuit further includes a second dielectric layer, a first conductive structure, and a fourth metal layer; the third metal layer is positioned between the substrate and the second dielectric layer, and the second dielectric layer is positioned between the third metal layer and the fourth metal layer; the first conductive structure penetrates through the second dielectric layer, and the third metal layer and the fourth metal layer are electrically connected through the first conductive structure.

In one possible implementation manner, the first circuit further includes a third dielectric layer, a second conductive structure, and a fifth metal layer; the third dielectric layer is positioned on the second metal layer, and the fifth metal layer is positioned on the third dielectric layer; the second conductive structure penetrates through the third dielectric layer, and the fifth metal layer and the second metal layer are electrically connected through the second conductive structure.

In one possible implementation, the first circuit is a radio frequency circuit. The capacitor can be a bypass capacitor or a decoupling capacitor or a filter capacitor in the radio frequency circuit.

In one possible implementation manner, the material of the metal layer mentioned in the embodiment of the present application may be at least one of gold, titanium, nickel, platinum, chromium, aluminum, copper, and tungsten.

In one possible implementation, the material of the substrate mentioned in the embodiments of the present application is a semiconductor (e.g., silicon or germanium, etc.) or an insulator, and may be transparent or opaque.

In one possible implementation manner, the material of the dielectric layer mentioned in this embodiment may include a commonly used metal oxide or a high-k oxide, or a two-dimensional dielectric material such as boron nitride.

In one possible implementation, the material of the conductive structure mentioned in the embodiment of the present application may be a metal material, and the metal material may be at least one of gold, titanium, nickel, platinum, chromium, aluminum, copper, and tungsten, for example.

The embodiment of the present application does not limit the manufacturing process of the integrated circuit, for example, the manufacturing process of the integrated circuit may include a semiconductor manufacturing process or an integrated circuit manufacturing process, for example, one or more of a thin film manufacturing process, an imprinting process, an etching process, and a doping process.

Drawings

FIG. 1 is a schematic diagram of a structure of a conventional integrated circuit;

FIG. 2 is a schematic diagram of another configuration of a prior art integrated circuit;

FIG. 3A is a schematic diagram of one possible structure of an integrated circuit according to an embodiment of the present application;

FIG. 3B is a schematic diagram of one possible first surface of the integrated circuit shown in FIG. 3A;

FIG. 4 is a schematic diagram of another possible structure of an integrated circuit according to an embodiment of the present application;

FIG. 5A is a schematic diagram of another possible structure of an integrated circuit according to an embodiment of the present application;

FIG. 5B is a schematic diagram of one possible first surface of the integrated circuit shown in FIG. 5A;

FIG. 6 is a schematic diagram of another possible structure of an integrated circuit according to an embodiment of the present application;

FIG. 7 is a schematic diagram of another possible structure of an integrated circuit according to an embodiment of the present application.

Detailed Description

The integrated circuit process may be used to prepare various electronic devices or components, and optionally, the integrated circuit prepared by the integrated circuit process may include a radio frequency circuit (or referred to as a radio frequency module), which may be a radio frequency filter or a radio frequency amplifier, etc. Alternatively, the integrated circuit may be or be provided in a terminal device. Alternatively, the integrated circuit may be or be disposed in a network device.

Optionally, the network device may be a device with a wireless transceiving function, and the network device includes but is not limited to: evolved Node B (eNB), radio Network Controller (RNC), node B (NB), base Station Controller (BSC), base Transceiver Station (BTS), home base station (e.g., home evolved NodeB or Home Node B (HNB)), base Band Unit (BBU), access Point (AP) in wireless fidelity (WIFI) system, wireless relay Node, wireless backhaul Node, transmission point (TRP or transmission point, TP), etc., and may also be devices used in 5G, 6G or even 7G systems, such as a gNB in an NR system, or a transmission point (TRP or TP), one or a group (including multiple antenna panels) of antenna panels of a base station in a 5G system, or may also be network nodes constituting a gNB or a transmission point, such as a baseband unit (BBU), or a distributed unit (DU, distributed unit), or a pico base station (pico base station), or a femto base station (femto cell), or a vehicle networking (vehicle to evolution, V2X), or a Road Side Unit (RSU) in a smart driving scenario.

Alternatively, a terminal device may also be referred to as a User Equipment (UE), an access terminal, a subscriber unit, a subscriber station, a mobile station, a remote terminal, a mobile device, a user terminal, a user agent, or a user equipment. The terminal device in the embodiment of the present application may be a mobile phone (mobile phone), a tablet computer (Pad), a computer with a wireless transceiving function, a Virtual Reality (VR) terminal device, an Augmented Reality (AR) terminal device, a wireless terminal in industrial control (industrial control), a wireless terminal in self driving (self driving), a wireless terminal in remote medical (remote medical), a wireless terminal in smart grid (smart grid), a wireless terminal in transportation safety (transportation safety), a wireless terminal in smart city (smart city), a wireless terminal in smart home (smart home), a wireless terminal in the aforementioned V2X car networking, or an RSU of a wireless terminal type, and the like.

At least one capacitor is typically included in the integrated circuit. Fig. 1 shows a structure of a capacitor and a wiring related to the capacitor in a conventional integrated circuit. Referring to fig. 1, an integrated circuit 1 includes a substrate 100, a metal layer 111, a dielectric layer 121, a metal layer 112, a metal layer 113, a dielectric layer 122, and a conductive structure 114 in the dielectric layer 122. Metal layer 111 and metal layer 113 are both located on substrate 100, dielectric layer 121 is located on metal layer 111, metal layer 112 is located on dielectric layer 121, and dielectric layer 122 is located on metal layer 113. The metal layer 111, the dielectric layer 121 and the metal layer 112 form a capacitor, and the metal layer 111 and the metal layer 112 are two plates of the capacitor respectively. The metal layer 111 and the metal layer 113 are electrically connected, the conductive structure 114 is electrically connected to the metal layer 113, and the metal layer 113 and the conductive structure 114 are used to conduct a charge current or a discharge current (or a signal current) of the metal layer 111.

In the capacitor (metal layer 111, dielectric layer 121, and metal layer 112) and the wiring (e.g., metal layer 113 and conductive structure 114) related to the capacitor shown in fig. 1, the charging current or the discharging current of the two plates (metal layer 111 and metal layer 112) of the capacitor are both led out to the same side of the substrate 100, and it is not possible to interconnect the signal currents of the two plates of the capacitor at the two sides of the substrate 100, and it is also difficult to match the capacitor to ground.

Fig. 2 shows a structure of a capacitor and a wiring related to the capacitor in another conventional integrated circuit. Referring to fig. 2, integrated circuit 2 includes substrate 200, metal layer 211, dielectric layer 221, metal layer 212, metal layer 213, and conductive structure 214 in substrate 200. Metal layer 211 and metal layer 213 are both located on substrate 200, dielectric layer 221 is located on metal layer 211, and metal layer 212 is located on dielectric layer 221. The metal layer 211, the dielectric layer 221 and the metal layer 212 form a capacitor, and the metal layer 211 and the metal layer 212 are two plates of the capacitor respectively. The metal layer 211 is electrically connected to the metal layer 213, the conductive structure 214 is electrically connected to the metal layer 213, and the metal layer 213 and the conductive structure 214 serve to conduct a charge current or a discharge current (or a signal current) of the metal layer 211.

The capacitor (metal layer 211, dielectric layer 221, and metal layer 212) and the wiring associated with the capacitor (e.g., metal layer 213 and conductive structure 214) shown in fig. 2, the charging current or the discharging current of the two plates of the capacitor (metal layer 211 and metal layer 212) is conducted to both sides of substrate 200. Although it is advantageous to realize interconnection of signal currents of both plates of the capacitor on both sides of the substrate 200, the area occupied by the capacitor and the wiring related to the capacitor in the surface direction of the substrate 200 includes the area of the metal layer 211 as the plate and the area of the metal layer 213 as the wiring layer, which is disadvantageous to downsizing of the integrated circuit 2. Moreover, since the signal current of the metal layer 211 needs to flow through the metal layer 231 and the conductive structure 214, the path through which the signal current passes is long, which increases the loss of the integrated circuit 2, and is not favorable for improving the quality factor (Q) value of the capacitor (the metal layer 211, the dielectric layer 221, and the metal layer 212).

In order to reduce the size of the integrated circuit and improve the performance (e.g., Q value) of the integrated circuit, embodiments of the present application provide an integrated circuit that may be or be disposed in a terminal device such as that described above. Alternatively, the integrated circuit may be or be provided in a network device such as that described above. For ease of understanding, fig. 3A, fig. 4, fig. 5A, fig. 6, and fig. 7 show several possible structural schematic diagrams of an integrated circuit according to an embodiment of the present application. It should be noted that fig. 3A, fig. 3B, fig. 4, fig. 5A, fig. 5B, fig. 6, and fig. 7 are only examples, and the substrate area of the integrated circuit is not limited to be the same as the area of the capacitor plate in the embodiment of the present application. In addition, the embodiment of the present application does not limit the integrated circuit to include only the structures shown in fig. 3A, fig. 3B, fig. 4, fig. 5A, fig. 5B, fig. 6, or fig. 7, and in practical applications, the integrated circuit may include more structures, such as inductors, resistors, and their related wirings, as needed. Embodiments of the present application are described below in conjunction with the integrated circuits shown in fig. 3A, 3B, 4, 5A, 5B, 6, and 7.

Embodiments of the present application provide an integrated circuit, such as integrated circuit 3 shown in fig. 3A, or integrated circuit 4 provided in fig. 4, or integrated circuit 5 provided in fig. 5A, or integrated circuit 6 provided in fig. 6, or integrated circuit 7 provided in fig. 7. The integrated circuit may include a substrate, such as substrate 300 shown in fig. 3A, or substrate 400 shown in fig. 4, or substrate 500 shown in fig. 5A, or substrate 600 shown in fig. 6, or substrate 700 shown in fig. 7.

The integrated circuit provided by the embodiment of the application can further comprise at least one capacitor. The capacitor includes a first metal layer, such as metal layer 311 shown in fig. 3A, or metal layer 411 shown in fig. 4, or metal layer 511 shown in fig. 5A, or metal layer 611 shown in fig. 6, or metal layer 711 shown in fig. 7. The first metal layer is located on a first surface of the substrate, which may be, for example, the surface 301 of the substrate 300 shown in fig. 3A, or the surface 401 of the substrate 400 shown in fig. 4, or the surface 501 of the substrate 500 shown in fig. 5A, or the surface 601 of the substrate 600 shown in fig. 6, or the surface 701 of the substrate 700 shown in fig. 7.

The capacitor may further include a first dielectric layer, such as dielectric layer 321 shown in fig. 3A, dielectric layer 421 shown in fig. 4, dielectric layer 521 shown in fig. 5A, dielectric layer 621 shown in fig. 6, or dielectric layer 721 shown in fig. 7. The first dielectric layer is located on the aforementioned first metal layer.

The capacitor may also include a second metal layer, which may be, for example, metal layer 312 shown in FIG. 3A, or metal layer 412 shown in FIG. 4, or metal layer 512 shown in FIG. 5A, or metal layer 612 shown in FIG. 6, or metal layer 712 shown in FIG. 7. The second metal layer is located on the aforementioned first dielectric layer, the first dielectric layer is located between the first metal layer and the second metal layer, the first dielectric layer and the second metal layer correspond to a capacitor, and the first metal layer and the second metal layer correspond to two plates of the capacitor respectively.

The integrated circuit provided by the embodiment of the application can further comprise n conductive structures, wherein n is a positive integer. Alternatively, the integrated circuit may include 1 conductive structure, which may be, for example, the conductive structure 313 shown in fig. 3A or the conductive structure 513 shown in fig. 5A. Or, alternatively, the integrated circuit may include 2 conductive structures, and the 2 conductive structures may be, for example, the

conductive structures

413 and 414 shown in fig. 4, or the

conductive structures

613 and 614 shown in fig. 6, or the

conductive structures

713 and 714 shown in fig. 7, respectively.

The n conductive structures may be located in the substrate as mentioned before. For convenience of description, any one of the n conductive structures is referred to as an ith conductive structure, i is a positive integer, and i is not greater than n. The ith conductive structure penetrates through the substrate from the second surface of the substrate to the first metal layer to conduct a charging current or a discharging current (or a signal current) of the first metal layer. Wherein the second surface is located opposite to the first surface, the second surface may be, for example, the surface 302 of the substrate 300 shown in fig. 3A, or the surface 402 of the substrate 400 shown in fig. 4, or the surface 502 of the substrate 500 shown in fig. 5A, or the surface 602 of the substrate 600 shown in fig. 6, or the surface 702 of the substrate 700 shown in fig. 7. In one possible implementation, the ith conductive structure is electrically connected to the first metal layer at the first surface.

Alternatively, the integrated circuit may include 3 conductive structures or more than 3 conductive structures. Furthermore, the embodiments of the present application do not limit that a plurality of conductive structures are located in the same cross section of the substrate.

For convenience of description, one of the n conductive structures is referred to as a jth conductive structure, j being a positive integer no greater than n. In one possible implementation, such as the integrated circuit shown in fig. 3A or fig. 4-7, the jth conductive structure is a pillar structure. It is understood that in this implementation manner, the embodiment of the present application does not limit each conductive structure of the n conductive structures to be a pillar shape, but only needs that at least one conductive structure is a pillar-shaped structure. Optionally, the axis of the columnar structure is perpendicular to the first surface of the substrate.

In the integrated circuit provided by the embodiment of the application, the charging current or the discharging current of the two electrode plates (the first metal layer and the second metal layer) of the capacitor is led out to the two sides of the substrate, which is beneficial to realizing the interconnection of the signal currents of the two electrode plates of the capacitor on the two sides of the substrate. Furthermore, the area occupied by the capacitor and the wiring related to the capacitor in the substrate surface direction is close to or equal to the area of the first metal layer as the plate, which is advantageous for downsizing the integrated circuit compared with the conventional integrated circuit (for example, the integrated circuit shown in fig. 1 or fig. 2). And because the signal current of the second metal layer can be led out to the second surface of the substrate by flowing through the n conductive structures, and the length of the path through which the signal current passes is close to or equal to the thickness of the substrate, compared with the prior art, the method is favorable for reducing the length of the path through which the signal current passes, thereby being favorable for reducing the loss of the integrated circuit, and being favorable for improving the Q value of the capacitor (the capacitor corresponding to the first metal layer, the first dielectric layer and the second metal layer).

In one possible implementation, the cross section of the jth conductive structure on the first surface and/or the second surface of the substrate is a regular shape. Similarly, in this implementation manner, the embodiment of the present application does not limit the cross section of each conductive structure in the n conductive structures to be a regular shape on the first surface and/or the second surface of the substrate, but only needs that the cross section of at least one conductive structure on the first surface and/or the second surface of the substrate is a regular shape. Alternatively, the regular shape may be, for example, a circle as shown in fig. 3B, and the i-th conductive structure may be a cylinder. Alternatively, the regular shape may be an oval, a rectangle, or a diamond, among other shapes. Alternatively, the cross-section of the ith conductive structure at the first surface and/or the second surface of the substrate may be irregular.

In one possible implementation, the jth conductive structure is a solid structure, such as the solid structure 313 shown in fig. 3A and 3B, or the jth conductive structure may be a hollow structure, such as the tubular cylindrical structure 513 shown in fig. 5A and 5B, and the inside of the hollow structure may be air or filled with other materials.

By penetrating the substrate with 2 or more than 2 conductive structures, the signal current of the first metal layer is conducted from the first surface to the second surface of the substrate, the cross-sectional area of the conductive path is increased, the total resistance of the n conductive structures is reduced, and the loss of the signal current is reduced. And, compare with 1 electrically conductive structure, in order to reach the same total cross street area, through preparing 2 or more than 2 electrically conductive structures, be favorable to reducing the cross street area of every electrically conductive structure. If the conductive structure is a hollow structure, the deformation risk of the first metal layer is reduced, and the reliability of the capacitor is improved. If the conductive structure is a solid structure, the flatness of the end face of the first surface of the single conductive structure is favorably improved by reducing the cross sectional area of the single conductive structure, so that the flatness of the first metal layer is favorably improved, and the reliability of the capacitor is improved.

In one possible implementation, an extension of the axis of the jth conductive structure passes through the first dielectric layer, such as the dashed line shown in fig. 3A or fig. 4 or fig. 5A or fig. 6 or fig. 7. In one possible implementation, the axis of the jth conductive structure is perpendicular to the first surface.

In one possible implementation, the area of the first metal layer is larger than that of the first dielectric layer, for example, as shown in fig. 5A, the area of the metal layer 511 is larger than that of the dielectric layer 521. The effective plate area of the capacitor is generally the facing area of the two plates, and in the embodiment of the present application, the overlapping region between the first metal layer, the first dielectric layer and the second metal layer is referred to as a first region, for example, the region 1 shown in fig. 5A. In one possible implementation, the ith conductive structure penetrates through the substrate from the second surface of the substrate to the first region of the first metal layer. Compared with the second region of the ith conductive structure, the second region of the ith conductive structure penetrates through the substrate from the second surface of the substrate to the first metal layer, the path length of the signal current passing through the ith conductive structure from the second surface of the substrate to the first region of the first metal layer is further reduced, the loss of the integrated circuit is reduced, and the Q value of the capacitor (the capacitor corresponding to the first metal layer, the first dielectric layer and the second metal layer) is improved.

In one possible implementation, the thickness of the substrate is greater than the thickness of the capacitor. Optionally, the thickness of the substrate and the thickness of the capacitor are thicknesses measured in the same direction, for example, in a direction perpendicular to the first surface.

In one possible implementation, the first circuit further includes a third metal layer, such as metal layer 514 shown in fig. 5A, or such as metal layer 615 shown in fig. 6, or such as metal layer 715 shown in fig. 7. The third metal layer is located on the second surface of the substrate, and the third metal layer is electrically connected to the first metal layer through the n conductive structures. The third metal layer is located on the second surface of the substrate to facilitate interconnection with other devices, as compared to the n conductive structures. The other device may be, for example, an inductor, resistor or other capacitor, etc., or an active device. Alternatively, in a possible implementation, the third metal layer is a ground metal layer, or the third metal layer is used for grounding.

In a possible implementation manner, the integrated circuit provided in the embodiment of the present application further includes a second dielectric layer, a first conductive structure, and a fourth metal layer. The second dielectric layer is, for example, dielectric layer 722 shown in fig. 7, the first conductive structure is, for example, conductive structure 716 shown in fig. 7, and the fourth metal layer is, for example, metal layer 717 shown in fig. 7. The third metal layer is positioned between the substrate and the second dielectric layer, and the second dielectric layer is positioned between the third metal layer and the fourth metal layer. The first conductive structure penetrates through the second dielectric layer, and the third metal layer and the fourth metal layer are electrically connected through the first conductive structure. In one possible implementation, the first conductive structure is a solid structure, such as the solid structure 313 shown in fig. 3A and 3B, or may be a hollow structure, such as the tubular cylindrical structure 513 shown in fig. 5A and 5B, the interior of which may be air or filled with other materials. The first conductive structure and the fourth metal layer are beneficial to realizing interconnection of the first metal layer and more layers of circuits in the integrated circuit.

In a possible implementation manner, the integrated circuit provided in this embodiment of the present application may further include a third dielectric layer, a second conductive structure, and a fifth metal layer. The third dielectric layer may be, for example, dielectric layer 622 shown in fig. 6, or dielectric layer 722 shown in fig. 7. The second conductive structure may be, for example, the conductive structure 616 shown in fig. 6, or the conductive structure 716 shown in fig. 7. This fifth metal layer may be, for example, metal layer 617 shown in FIG. 6, or metal layer 717 shown in FIG. 7. The third dielectric layer is located on the second metal layer, the fifth metal layer is located on the third dielectric layer, the second conductive structure penetrates through the third dielectric layer, and the fifth metal layer and the second metal layer are electrically connected through the second conductive structure. In one possible implementation, the second conductive structure is a solid structure, such as the solid structure 313 shown in fig. 3A and 3B, or may be a hollow structure, such as the tubular cylindrical structure 513 shown in fig. 5A and 5B, the interior of which may be air or filled with other materials. The second conductive structure and the fifth metal layer are beneficial to realizing interconnection of the second metal layer and more layers of circuits in the integrated circuit.

In this embodiment, a circuit in which the capacitors corresponding to the first metal layer, the first dielectric layer, and the second metal layer are located may be referred to as a first circuit. Optionally, the first circuit may also be considered to include a wiring associated with the capacitor, for example, the first circuit may further include the n conductive structures described above, or, optionally, the first circuit may further include the third metal layer described above, or, optionally, the first circuit may further include the first conductive structure and the fourth metal layer described above, or, optionally, the first circuit may further include the second conductive structure and the fifth metal layer described above. Alternatively, in one possible implementation, the first circuit may also include other devices, such as inductors, capacitors, resistors, or the like, or include active or passive circuits. In a possible implementation manner, the first circuit may be a radio frequency circuit, and the capacitor provided in the embodiment of the present application may be a bypass capacitor, a decoupling capacitor, a filter capacitor, or the like in the radio frequency circuit.

In one possible implementation, the thickness of the first metal layer may be 0.01 to 1000 micrometers. In one possible implementation, the thickness of the first dielectric layer may be 0.001 to 20 microns. In a possible implementation manner, the first dielectric layer may be made of one material or a composite material made of multiple materials, which is beneficial to realizing higher withstand voltage of the capacitor. In one possible implementation, the substrate may have a thickness of 20 to 2000 microns. In one possible implementation, the thickness of the second dielectric layer may be 0.01 to 30 micrometers. In one possible implementation, the thickness of the third dielectric layer may be 0.01 to 30 micrometers.

In one possible implementation, the material of the dielectric layer mentioned in the embodiments of the present application may include a commonly used metal oxide or high-k oxide, or a two-dimensional dielectric material such as boron nitride.

In the embodiments of the present application, words such as "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "such as" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present relevant concepts in a concrete fashion.

The terms "first," "second," "third," "fourth," "fifth," and the like in the description and claims of this application and in the foregoing drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and are merely descriptive of the various embodiments of the application and how objects of the same nature can be distinguished.

In the embodiments of the present application, various illustrations are made for the sake of an understanding of aspects. However, these examples are merely examples and are not meant to be the best mode of carrying out the present application.

The technical solutions provided by the present application are introduced in detail, and the present application applies specific examples to explain the principles and embodiments of the present application, and the descriptions of the above examples are only used to help understand the method and the core ideas of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, the specific implementation manner and the application scope may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. An integrated circuit comprising a substrate and a first circuit comprising a capacitor and n conductive structures;

the capacitor comprises a first metal layer, a first dielectric layer and a second metal layer, wherein the first metal layer is positioned on the first surface of the substrate, the first dielectric layer is positioned on the first metal layer, and the second metal layer is positioned on the first dielectric layer;

the n conductive structures are located in the substrate, and an ith conductive structure of the n conductive structures penetrates through the substrate from a second surface of the substrate to the first metal layer to conduct a charging current or a discharging current of the first metal layer, wherein the second surface is located on the opposite side of the first surface, n is a positive integer, and i is any positive integer not greater than n.

2. The integrated circuit of claim 1, wherein a jth conductive structure of the n conductive structures is a pillar structure, where j is a positive integer no greater than n.

3. The integrated circuit of claim 2, wherein an extension of the axis of the jth conductive structure passes through the first dielectric layer.

4. The integrated circuit of claim 3, wherein an axis of the jth conductive structure is perpendicular to the first surface.

5. The integrated circuit of any of claims 1-4, wherein the ith conductive structure extends through the substrate from the second surface of the substrate to a first region of the first metal layer, the first region being an overlap region between the first metal layer, the first dielectric layer, and the second metal layer.

6. The integrated circuit of any of claims 1-5, wherein a thickness of the substrate is greater than a thickness of the capacitor.

7. The integrated circuit of any of claims 1-6, wherein the first circuit further comprises a third metal layer;

the third metal layer is on the second surface and is electrically connected to the first metal layer through the n conductive structures.

8. The integrated circuit of claim 7, wherein the third metal layer is used for ground.

9. The integrated circuit of claim 7, wherein the first circuit further comprises a second dielectric layer, a first conductive structure, and a fourth metal layer;

the third metal layer is positioned between the substrate and the second dielectric layer, and the second dielectric layer is positioned between the third metal layer and the fourth metal layer;

the first conductive structure penetrates through the second dielectric layer, and the third metal layer and the fourth metal layer are electrically connected through the first conductive structure.

10. The integrated circuit of any of claims 1-9, wherein the first circuit further comprises a third dielectric layer, a second conductive structure, and a fifth metal layer;

the third dielectric layer is positioned on the second metal layer, and the fifth metal layer is positioned on the third dielectric layer;

the second conductive structure penetrates through the third dielectric layer, and the fifth metal layer and the second metal layer are electrically connected through the second conductive structure.

11. The integrated circuit of any of claims 1-10, wherein the first circuit is a radio frequency circuit.