CN115274444A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN115274444A
CN115274444A CN202110483046.3A CN202110483046A CN115274444A CN 115274444 A CN115274444 A CN 115274444A CN 202110483046 A CN202110483046 A CN 202110483046A CN 115274444 A CN115274444 A CN 115274444A
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China
Prior art keywords
side wall
forming
region
sidewall
film
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CN202110483046.3A
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Chinese (zh)
Inventor
任烨
卜伟海
武咏琴
贾会静
苏悦阳
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North Ic Technology Innovation Center Beijing Co ltd
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North Ic Technology Innovation Center Beijing Co ltd
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Priority to CN202110483046.3A priority Critical patent/CN115274444A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode

Abstract

A method of forming a semiconductor structure, comprising: forming a side wall film which is conformally covered on the offset side wall, the grid structure and the substrate, and a first side wall which is positioned on the side wall of the side wall film of the offset side wall; respectively and correspondingly forming a source region and a drain region in the substrate at one side and the other side of the grid structure of the first device region; forming a protective film which is conformally covered on the top surface, the side wall and the side wall film of the first side wall; removing the protective film on the first side wall of the first device area close to the source area to form a protective layer; removing the first side wall close to one side of the source region by taking the protective layer as a mask; removing the side wall film and the protective layer exposed from the first side wall; forming a first lightly doped region in the substrate between the source region of the first device region and the offset side wall; and forming a metal silicide layer on the top surfaces of the source region, the drain region, the first lightly doped region and the gate structure. The embodiment of the invention improves the performance of the TFET device.

Description

Method for forming semiconductor structure
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
Since a conventional CMOS (Complementary Metal Oxide Semiconductor) device is limited by boltzmann, a minimum value exists at a sub-threshold swing room temperature, and thus static power consumption exponentially increases as an operating voltage decreases with further shrinking of the size of the CMOS device. Therefore, CMOS is generally used for high performance technology, and dynamic power consumption is dominant.
Different from a conventional CMOS, a doping type of a source region and a drain region of a TFET (Tunneling Field-effect Transistor) is different, the TFET changes a source region-channel-drain region structure into a P-I-N structure, band-band Tunneling is used as a conduction mechanism, sub-threshold swing limitation can be broken through, extremely low static leakage current and lower working voltage can be realized, and static power consumption is reduced.
Therefore, the TFET device with excellent subthreshold characteristics can be mixed and integrated with a traditional CMOS device to reduce the overall power consumption of a circuit, the high-frequency part of the circuit is completed by the traditional CMOS device, the low-frequency part of the circuit is completed by the TFET device, and the mixed integration mode is widely applied to the Internet of things.
However, the performance of TFET devices still remains to be improved.
Disclosure of Invention
The embodiment of the invention provides a method for forming a semiconductor structure, and aims to improve the performance of a TFET device.
In order to solve the above problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first device region for forming a tunneling field effect transistor; forming a grid structure on the substrate, wherein an offset side wall is formed on the side wall of the grid structure; forming side wall films positioned on the top surface and the side wall of the offset side wall, the top surface of the grid structure and the top surface of the substrate, and a first side wall positioned on the side wall of the side wall film of the offset side wall; after the first side wall is formed, in the first device region, a source region is formed in the substrate on one side of the grid structure, and a drain region is formed in the substrate on the other side of the grid structure, wherein the doping types of the drain region and the source region are different; forming a protective film which is conformally covered on the top surface and the side wall of the first side wall, the offset side wall, the grid structure and the side wall film on the top surface of the substrate; in the first device region, removing the protective film on a first side wall close to one side of the source region, wherein the rest protective film is used as a protective layer; removing the first side wall close to one side of the source region by taking the protective layer as a mask; after the first side wall close to one side of the source region is removed, the protective layer and the side wall film exposed out of the first side wall are removed, and the residual side wall films between the offset side wall and the first side wall and between the substrate and the first side wall are used as second side walls; forming a first lightly doped region in the first device region and in the substrate between the source region and the offset side wall, wherein the doping type of the first lightly doped region is the same as that of the source region; and forming metal silicide layers on the top surfaces of the source region, the drain region, the first lightly doped region and the gate structure.
Optionally, in the step of providing the substrate, the substrate further includes a second device region for forming a metal oxide semiconductor field effect transistor; the method for forming the semiconductor structure further comprises the following steps: forming source-drain doped regions in the gate structure of the second device region and the substrate on two sides of the first side wall after the first side wall is formed and before the protective film is formed; in the step of forming the metal silicide layer, the metal silicide layer is also formed on the top surface of the source-drain doped region.
Optionally, the method for forming the semiconductor structure further includes: and after the offset side wall is formed and before the side wall film is formed, forming second lightly doped regions in the grid structure of the second device region and the substrate on two sides of the offset side wall.
Optionally, after the first side wall is formed and before the source region and the drain region are formed, a source-drain doped region is formed in the gate structure of the second device region and the substrate on both sides of the first side wall.
Optionally, the material of the protective film is the same as that of the side wall film; and in the same step, removing the side wall film and the protective layer exposed from the first side wall.
Optionally, in the step of forming the protective film, a material of the protective film includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, or boron carbonitride.
Optionally, in the step of forming the protective film, the thickness of the protective film is the same as that of the sidewall film.
Optionally, the first side wall and the offset side wall are made of the same material.
Optionally, the material of the first side wall includes one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, and silicon oxycarbonitride; the offset side wall is made of one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide and silicon oxycarbonitride.
Optionally, in the first device region, the step of removing the protective film on the first sidewall near the source region side includes: forming a mask layer on the protective film, wherein the mask layer is provided with a mask opening, and the mask opening is positioned on the top surface and the side wall of the first side wall on one side of the first device area close to the source area; removing the protective film exposed from the mask opening by taking the mask layer as a mask; and removing the mask layer.
Optionally, the process of removing the protective film on the first side wall close to one side of the source region includes a wet etching process.
Optionally, the process of removing the first sidewall on the side of the first device region close to the source region includes a wet etching process.
Optionally, the process of removing the sidewall film and the protective layer exposed by the first sidewall includes a wet etching process.
Optionally, the gate structure includes a gate dielectric layer and a gate layer located on the gate dielectric layer.
Optionally, the material of the gate layer includes polysilicon or amorphous silicon.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming a semiconductor structure according to the embodiments of the present invention, before forming the protective film, a sidewall film on a top surface of the offset sidewall and the gate structure is retained, and accordingly, in the step of forming the protective film, the protective film can conformally cover a top surface and a sidewall of the first sidewall, and the sidewall film on the top surface of the offset sidewall and the gate structure and a top surface of the substrate, so that, compared with a case where only the protective film is formed on the sidewall of the first sidewall, the film on the top surface of the offset sidewall and the gate structure is a stacked structure formed by the sidewall film and the protective film, the film on the top surface of the offset sidewall and the gate structure is thicker, so that in the step of removing the protective film on the sidewall of the first sidewall near one side of the source region, after removing the protective film on the sidewall of the first sidewall near one side of the source region, the film on the top of the gate structure and the offset sidewall can retain a partial thickness, the remaining film on the top of the gate structure and the offset sidewall can protect the offset sidewall film in the step of removing the first sidewall near one side of the source region to prevent the offset region from exposing the silicide layer, thereby facilitating to reduce the offset metal layer near the silicide layer and prevent the silicide layer from exposing the silicide layer, thereby reducing the offset metal layer and reducing the offset metal layer near the silicide layer. The performance of the semiconductor structure is optimized.
In addition, according to the embodiment of the invention, the side wall films positioned on the tops of the offset side wall and the gate structure are reserved before the protective film is formed, and no additional film layer or process step is introduced, so that the process flow is prevented from being greatly changed, and the improvement of process compatibility and cost saving are correspondingly facilitated.
Drawings
Fig. 1 to 10 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 11 to fig. 22 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As is known in the background art, the performance of TFET devices currently needs to be improved. The reason why the performance of the TFET device needs to be improved is analyzed in combination with a method for forming a semiconductor structure. Fig. 1 to 10 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 10 is provided, including a first device region 10i for forming a TFET device and a second device region 10ii for forming a MOS device; a gate structure 20 is formed on the substrate 10, and offset spacers 25 are formed on the sidewalls of the gate structure 20.
With reference to fig. 1, a sidewall film 26 is formed on the top surface of the substrate 10, the top surfaces of the gate structure 20 and the offset sidewall 25, and the sidewall of the offset sidewall 25.
Referring to fig. 2, a first sidewall 27 is formed on a sidewall of the sidewall film 26 located at a sidewall of the offset sidewall 25.
Referring to fig. 3, source and drain doped regions 11 are formed in the substrate 10 at both sides of the gate structure 20 of the second device region 10 ii.
Referring to fig. 4, after the source-drain doped region 11 is formed, the sidewall films 26 on the top surfaces of the substrate 10, the gate structure 20 and the offset sidewall 25 are removed, and the remaining sidewall films 26 between the offset sidewall 25 and the first sidewall 27 and between the top surface of the substrate 10 and the first sidewall 26 are used as second sidewalls 29.
With continued reference to fig. 4, in the first device region 10i, a source region 31 is formed in the substrate 10 on one side of the gate structure 20, and a drain region 32 is formed in the substrate 10 on the other side of the gate structure 20.
Referring to fig. 5, a protective film 12 is formed on the top surface of the substrate 10, the sidewalls and the top surface of the first sidewall 27, the second sidewall 29 and the top surface of the gate structure 20.
Referring to fig. 6, in the first device region 10i, the top surface and the sidewall of the first sidewall 28, the top surface of the second sidewall 29 and a portion of the top surface of the gate structure 20 on a side close to the source region 31 are removed, and the remaining protective film is used as the protective layer 13.
Referring to fig. 7, the first sidewall 27 of the first device region 10i on the side close to the source region 31 is removed by using the protection layer 13 as a mask.
Referring to fig. 8, the protective layer 13 and the second sidewall 29 on the side of the first device region 10i close to the source region 31 are removed, and the substrate 10 between the source region 31 of the first device region 10i and the offset sidewall 25 is exposed.
Referring to fig. 9, a lightly doped region 40 is formed in the substrate 10 between the source region 31 and the offset sidewall 25.
Referring to fig. 10, a metal silicide layer 45 is formed on the source/drain doped region 11, the top surface of the source region 31, the top surface of the drain region 32 and the lightly doped region 40, and the exposed surface of the gate structure 20.
In the forming method, in order to ensure that a sufficient photolithography process window is provided in a photolithography process, in the step of forming the protection layer 13, in the first device region 10i, not only the protection film 12 on the top surface and the sidewall of the first sidewall 27 close to one side of the source region 31 is removed, but also the protection film 12 on the top surface of the second sidewall 29 close to one side of the source region 31 and part of the top surface of the gate structure 20 is removed, so as to expose the top surface of the second sidewall 29 close to one side of the source region 31 and part of the top surface of the gate structure 20, in the step of removing the first sidewall 28 close to one side of the source region 31 in the first device region 10i by using the protection layer 13 as a mask, the top surface of the offset sidewall 25 is exposed, which easily causes the offset sidewall 25 to be damaged, and the height of the offset sidewall 25 close to one side of the source region 31 is reduced, which causes part of the sidewall of the gate structure 20 to be exposed (as shown in the position of the dashed circle in fig. 7).
Accordingly, in the step of forming the metal silicide layer 45, the metal silicide layer 45 is also easily formed on the exposed sidewall of the gate structure 20 near the source region 31 (as shown by a dashed circle in fig. 10), so that the metal silicide layer extends downward to the position of the offset sidewall 25 along the sidewall of the gate structure 20, which will affect the electric field distribution in the gate structure 20, and when the offset sidewall 25 near the source region 31 is seriously damaged, the metal silicide layer 45 on the sidewall of the gate structure 20 is also easily contacted with the metal silicide layer 45 on the source region 31 and the lightly doped region 40, which results in a short circuit between the gate structure 20 and the source region 31.
In particular, in the semiconductor field, the first sidewall 27 and the offset sidewall 25 are usually materials with close etching properties, such as: the materials of the first side wall 27 and the offset side wall 25 are the same, and in the step of removing the first side wall 27 located on the side of the first device region 10i close to the source region 31, the offset side wall 25 is more seriously damaged, and the metal silicide layer 45 more easily extends downwards along the exposed side wall of the gate structure 20, so that the risk that the electric field in the gate structure 20 is influenced and the risk that the gate structure 20 and the source region 31 are short-circuited is higher.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising a first device region for forming a tunneling field effect transistor; forming a grid structure on the substrate, wherein offset side walls are formed on the side walls of the grid structure; forming side wall films positioned on the top surface and the side wall of the offset side wall, the top surface of the grid structure and the top surface of the substrate, and a first side wall positioned on the side wall of the side wall film of the offset side wall; after the first side wall is formed, in the first device region, a source region is formed in the substrate on one side of the grid structure, and a drain region is formed in the substrate on the other side of the grid structure, wherein the doping types of the drain region and the source region are different; forming a protective film which is conformally covered on the top surface and the side wall of the first side wall, the offset side wall, the grid structure and the side wall film on the top surface of the substrate; in the first device region, removing the protective film on a first side wall close to one side of the source region, wherein the rest protective film is used as a protective layer; removing the first side wall close to one side of the source region by taking the protective layer as a mask; after the first side wall close to one side of the source region is removed, the protective layer and the side wall film exposed out of the first side wall are removed, and the residual side wall films between the offset side wall and the first side wall and between the substrate and the first side wall are used as second side walls; forming a first lightly doped region in the first device region and in the substrate between the source region and the offset side wall, wherein the doping type of the first lightly doped region is the same as that of the source region; and forming metal silicide layers on the top surfaces of the source region, the drain region, the first lightly doped region and the gate structure.
In the method for forming a semiconductor structure according to the embodiments of the present invention, before forming the protective film, a sidewall film on a top surface of the offset sidewall and the gate structure is retained, and accordingly, in the step of forming the protective film, the protective film can conformally cover a top surface and a sidewall of the first sidewall, and the sidewall film on the top surface of the offset sidewall and the gate structure and a top surface of the substrate, so that, compared with a case where only the protective film is formed on the sidewall of the first sidewall, the film on the top surface of the offset sidewall and the gate structure is a stacked structure formed by the sidewall film and the protective film, the film on the top surface of the offset sidewall and the gate structure is thicker, so that in the step of removing the protective film on the sidewall of the first sidewall near one side of the source region, after removing the protective film on the sidewall of the first sidewall near one side of the source region, the film on the top of the gate structure and the offset sidewall can retain a partial thickness, the remaining film on the top of the gate structure and the offset sidewall can protect the offset sidewall film in the step of removing the first sidewall near one side of the source region to prevent the offset region from exposing the silicide layer, thereby facilitating to reduce the offset metal layer near the silicide layer and prevent the silicide layer from exposing the silicide layer, thereby reducing the offset metal layer and reducing the offset metal layer near the silicide layer. The performance of the semiconductor structure is optimized.
In addition, according to the embodiment of the invention, the side wall films positioned on the tops of the offset side wall and the gate structure are reserved before the protective film is formed, and no additional film layer or process step is introduced, so that the process flow is prevented from being greatly changed, and the improvement of process compatibility and cost saving are correspondingly facilitated.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
Fig. 11 to fig. 22 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 11, a substrate 100 including a first device region 100T for forming a Tunneling Field-effect Transistor (TFET) is provided.
The substrate 100 is used to provide a process platform for subsequent process steps.
In this embodiment, for example, the substrate 100 is used to form a planar field effect transistor, and the substrate 100 is a planar substrate. In other embodiments, the substrate may also be a three-dimensional substrate according to the type of transistor actually formed.
The first device region 100T is used to form a Tunneling Field Effect Transistor (TFET).
In this embodiment, the substrate 100 further includes a second device region 100M for forming a Metal Oxide Semiconductor Field-effect Transistor (MOSFET).
The second device region 100M is used to form a Metal Oxide Semiconductor (MOS) field effect transistor, and the first device region 100T is isolated from the second device region 100M.
In this embodiment, a well region 160 is further formed in the substrate 100 of the second device region 100M.
The well region 160 has a different doping type than the source and drain doped regions of the MOS transistor. As an example, the second device region 100M is used to form an NMOS transistor, and the well region 160 is a P-type well region.
For this reason, in this embodiment, an isolation structure 110 is further formed in the substrate 100 at the boundary between the first device region 100T and the second device region 100M, and the isolation structure 110 is used to implement isolation between the first device region 100T and the second device region 100M.
In this embodiment, the isolation structure 110 is made of an insulating material. As an example, the isolation structure 110 is a Shallow Trench Isolation (STI), and the material of the isolation structure 110 is silicon oxide.
In this embodiment, a trench (not labeled) is formed in the substrate 100 at the boundary between the first device region 100T and the second device region 100M, and the isolation structure 110 is formed in the trench.
In this embodiment, an adhesion layer 120 is further formed on the sidewall and the bottom of the trench, and the isolation structure 110 is located on the adhesion layer 120 and fills the trench. The adhesion layer 120 is used to improve the smoothness of the sidewall and the bottom of the trench, so as to provide a good interface state for forming the isolation structure 110, and the adhesion layer 120 is also used to improve the adhesion between the isolation structure 110 and the trench.
In this embodiment, the adhesion layer 120 is silicon oxide.
With continued reference to fig. 11, a gate structure 200 is formed on the substrate 100, and offset spacers (offset spacers) 220 are formed on sidewalls of the gate structure 200.
In this embodiment, the gate structure 200 includes a gate dielectric layer 230 and a gate layer 210 on the gate dielectric layer 230.
The gate dielectric layer 230 is used to isolate the gate layer 210 from the conductive channel.
In this embodiment, the gate dielectric layer 230 includes a gate oxide layer, and the gate oxide layer is made of silicon oxide or nitrogen-doped silicon oxide.
Gate layer 210 is used to control the conduction channel on or off during device operation. In this embodiment, the material of the gate layer 210 includes polysilicon or amorphous silicon.
The offset spacers 220 are used for protecting the sidewalls of the gate structure 200; moreover, the offset spacers 220 of the first device region 100T are used to define the formation position of a subsequent first lightly doped region, and the offset spacers 220 of the second device region 100M are used to define the formation position of a subsequent second lightly doped region; in addition, after the first sidewall spacer on the side of the first device region 100T close to the source region and the exposed sidewall spacer film of the first sidewall spacer are subsequently removed, in the process of forming the metal silicide layer, the offset sidewall spacer 220 is located on the sidewall of the gate layer 210, and is further used for blocking the growth of the metal silicide layer on the sidewall of the gate layer 210 of the first device region 100T.
The offset spacer 220 is made of one or more materials selected from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, and silicon oxycarbonitride. As an example, the material of the offset sidewall spacers 220 is silicon nitride.
With reference to fig. 12, in this embodiment, the method for forming the semiconductor structure further includes: after the offset spacers 230 are formed, second lightly doped regions 140 are formed in the substrate 100 at two sides of the gate structure 200 and the offset spacers 220 of the second device region 100M.
The second lightly doped region 140 is used to improve the short channel effect and the hot carrier injection effect of the MOS transistor.
The doping type of the second lightly doped region 140 is the same as the doping type of the source/drain doped region of the MOS transistor. When forming an NMOS transistor, the doping ions of the second lightly doped region 140 are N-type ions, such as: p ions, as ions, or Sb ions; when forming a PMOS transistor, the doping ions of the second lightly doped region 140 are P-type ions, for example: b ions, ga ions, or In ions.
In this embodiment, the step of forming the second lightly doped region 140 includes: forming a first shielding layer (not shown) covering the first device region 100T and the resistive region 100R, the first shielding layer exposing the second device region 100M; performing ion implantation on the gate structure 200 of the second device region 100M and the substrate 100 on both sides of the offset sidewall 220 by using the first shielding layer as a mask to form the second lightly doped region 140; and removing the first shielding layer.
The first blocking layer is used as a mask for performing ion implantation on the gate structure 200 of the second device region 100M and the substrate 100 on both sides of the offset sidewall 220. In this embodiment, the first shielding layer is made of photoresist.
In this embodiment, the process of performing ion implantation into the substrate 100 at two sides of the gate structure 200 and the offset spacers 220 of the second device region 100M is a Lightly Doped Drain (LDD) implantation process.
In this embodiment, the first blocking layer is removed by performing an ashing process and a wet photoresist removal process in sequence.
Referring to fig. 13, a sidewall film 130 on the top and sidewalls of the offset sidewall 220, the top of the gate structure 220, and the top of the substrate 100, and a first sidewall 310 on the sidewall of the sidewall film 130 on the sidewall of the offset sidewall 220 are formed.
The sidewall film 130 and the first sidewall 310 on the sidewall of the offset sidewall 220 form a sidewall structure, and the sidewall structure is used for defining the source/drain doped region of the MOS transistor and the formation positions of the source region and the drain region of the TFET device.
In this embodiment, the material of the first side walls 310 includes one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, and silicon oxycarbonitride.
As an embodiment, the first sidewall 310 has a single-layer structure, the material of the first sidewall 310 is the same as that of the offset sidewall 220, and the material of the first sidewall 310 is silicon nitride.
In this embodiment, the material of the sidewall film 130 includes one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, and silicon oxycarbonitride.
In one embodiment, the sidewall film 130 has a single-layer structure, and the material of the sidewall film 130 is silicon oxide.
As an example, the step of forming the sidewall film 130 and the first sidewall 310 includes: forming the sidewall film 130 on the top surface and the sidewall of the offset sidewall 220, the top surface of the gate structure 220, and the top surface of the substrate 100; forming a conformal (conformal) covered sidewall material layer (not shown) on the sidewall film 130; and etching the side wall material layer by adopting an anisotropic etching process, and reserving the side wall material layer on the side wall of the side wall film 130 to be used as the first side wall 310.
In this embodiment, only the sidewall material layer on the sidewall of the sidewall film 130 is reserved for the first sidewall 310, so as to prevent the thickness of the film layer on the top surface of the substrate 100 from being too large, so as to facilitate subsequent doping of the substrate 100 on both sides of the gate structure 200 of the second device region 100M.
In this embodiment, the side wall material layer is etched by using an anisotropic etching process. The anisotropic etching process has the characteristic of anisotropic etching, and the etching rate in the direction perpendicular to the surface of the substrate 100 is much higher than the etching rate in the direction parallel to the surface of the substrate 100, so that the sidewall material layer on the sidewall of the sidewall film 130 can be reserved to serve as the first sidewall 310 while the sidewall material layer on the top surface of the sidewall film 130 is removed.
Specifically, the anisotropic etching process may be an anisotropic dry etching process.
It should be noted that, in the embodiment, in the process of etching the side wall material layer by using the anisotropic etching process, the side wall film 130 located on the top surfaces of the gate structure 200, the offset side wall 220 and the substrate 100 is not over-etched, so that the thickness reduction of the side wall film 130 located on the top surfaces of the gate structure 200 and the offset side wall 220 is prevented, and further, it is ensured that in the subsequent etching process, the side wall film 130 located on the top surface of the offset side wall 220 can be at least partially preserved in thickness, so that in the process of removing the first side wall 310 close to one side of the source region 250, the top end of the offset side wall 220 close to one side of the source region 250 plays a role in protection.
Referring to fig. 14, in this embodiment, the method for forming the semiconductor structure further includes: after the first sidewall 310 is formed, a source-drain doped region 240 is formed in the gate structure 200 of the second device region 100M and the substrate 100 on both sides of the first sidewall 310.
The source drain doped region 240 is used as a source or a drain of the MOS transistor to provide a source of carriers when the MOS transistor is in operation.
In this embodiment, the doping depth of the source/drain doping region 240 is greater than the doping depth of the second lightly doped region 140, and the doping type of the source/drain doping region 240 is the same as the doping type of the second lightly doped region 140, so that the source/drain doping region 240 covers a part of the second lightly doped region 140.
When forming an NMOS transistor, the doped ions In the source/drain doped region 240 are N-type ions, where the N-type ions include P ions, as ions, or Sb ions, and when forming a PMOS transistor, the doped ions In the source/drain doped region 240 are P-type ions, where the P-type ions include B ions, ga ions, or In ions.
In this embodiment, the step of forming the source/drain doped region 240 includes: forming a second shielding layer 180 covering the first device region 100T, the second shielding layer 180 exposing the second device region 100M; performing ion doping on the gate structure 200 of the second device region 100M and the substrate 100 on both sides of the first sidewall 310 by using the second shielding layer 180 as a mask to form the source-drain doped region 240; the second blocking layer 180 is removed.
The second shielding layer 180 is used as a mask for ion doping the gate structure 200 of the second device region 100M and the substrate 100 on both sides of the first sidewall 310. In this embodiment, the second shielding layer 180 is made of photoresist.
In this embodiment, an ion implantation process is adopted to perform ion doping on the gate structure 200 of the second device region 100M and the substrate 100 on both sides of the first sidewall 310.
In this embodiment, the second blocking layer 180 is removed by performing an ashing process and a wet photoresist removal process in sequence.
Referring to fig. 15 to 16, after the first sidewall spacers 310 are formed, in the first device region 100T, a source region 250 is formed in the substrate 100 on one side of the gate structure 200, and a drain region 260 is formed in the substrate 100 on the other side of the gate structure 200, where doping types of the drain region 260 and the source region 250 are different.
The drain region 260 and the source region 250 are respectively used as a drain and a source of the TFET device.
The doping type of the drain region 260 is different from that of the source region 250, so that a P-I-N (P-Intrinsic-N) structure is formed, and band-to-band tunneling is used as a conduction mechanism.
As an example, the TFET device is a P-type TFET device, the doping ions of the drain region 260 are P-type ions, and the doping ions of the source region 250 are N-type ions. In other embodiments, when forming an N-type TFET device, the dopant ions of the drain region are N-type ions and the dopant ions of the source region are P-type ions.
The doping type of the drain region 260 is different from that of the source region 250, and thus, the drain region 260 and the source region 250 are formed in different steps, respectively.
As an example, the step of forming the source region 250 includes: as shown in fig. 15, in the second device region 100M and the third shielding layer 190, the third shielding layer 190 further covers the substrate 100 on the other side of the gate structure 200 in the first device region 100T; performing ion implantation on the substrate 100 by using the third shielding layer 190 as a mask, and forming a source region 250 in the substrate 100 on the side of the gate structure 200 of the first device region 100T; the third shielding layer 190 is removed.
In this embodiment, the source region 250 and the drain region 260 of the TFET device are formed after the source-drain doped region 240 of the MOS transistor is formed. However, the sequence of forming the source and drain doped regions 240 and forming the source and drain regions 250 and 260 is not limited thereto.
Referring to fig. 17, a protective film 150 is formed to conformally cover the top and sidewalls of the first sidewall 310, the offset sidewall 220, the gate structure 200 and the sidewall film 130 on the top surface of the substrate 100.
The protective film 150 is used for forming a protective layer through a subsequent etching process, and the protective layer is used as a mask for subsequently removing the first sidewall 310 on the side of the first device region 100T close to the source region 250.
In this embodiment, before forming the protective film 150, the sidewall film 130 on the top surfaces of the offset sidewall 220 and the gate structure 200 is retained, and accordingly, the protective film 150 can conformally cover the top surface and the sidewall of the first sidewall 310, and the sidewall film 130 on the top surfaces of the offset sidewall 220, the gate structure 200 and the substrate 100, so that, compared with the protective film 150 formed on the sidewall of the first sidewall 310, the film layer on the top surfaces of the offset sidewall 220 and the gate structure 200 is a laminated structure formed by the sidewall film 130 and the protective film 150, and the film layer on the top surfaces of the offset sidewall 220 and the gate structure 200 is thicker, so that in the subsequent step of removing the protective film 150 on the sidewall of the first sidewall 310 on the side close to the source region 250, after removing the protective film 150 on the sidewall of the first sidewall 310 on the side close to the source region 250, the film layer on the top portions of the gate structure 200 and the offset sidewall 220 can also retain a partial thickness.
In this embodiment, the protective film 150 is made of a material having an etching selectivity with the material of the first sidewall 310. Specifically, in this embodiment, the material of the protection film 150 is the same as the material of the sidewall film 130, so that after the first sidewall 310 on the side of the first device region 100T close to the source region 250 is subsequently removed, the sidewall film 130 on the side of the protection film 150 and the first device region 100T close to the source region 250 can be removed in the same step, which is beneficial to simplifying the process steps and improving the process compatibility.
In this embodiment, the material of the protection film 150 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, or boron carbonitride. Specifically, in this embodiment, the material of the protection film 150 is the same as the material of the sidewall film 130, and the material of the protection film 150 is silicon oxide.
The thickness of the protective film 150 is not necessarily too small, nor too large. If the thickness of the protective film 150 is too small, the protective film 150 is easily removed by etching in the subsequent process of removing the sidewall 150 of the first device region 100T on the side close to the source region 250, so that the protective film 150 is difficult to protect the first sidewall 310 of the first device region 100T on the side close to the drain region 250 and the second device region 100M; if the thickness of the protection film 150 is too large, the difficulty of the subsequent process for removing the protection film 150 is large, the time required for removing the protection film 150 is too long, the risk of damage to other film structures is easily increased, the thickness consistency of the protection film 150 is also easily poor, and further, the original thin area of the protection film 150 is easily over-etched in the subsequent process for removing the protection layer.
Therefore, in this embodiment, the difference between the thickness of the protection film 150 and the thickness of the sidewall film 130 is smaller.
As an example, the thickness of the protective film 150 is the same as that of the sidewall film 130, for example: the thickness of the protective film 150 is
Figure BDA0003049157220000131
The thickness of the protective layer 310 is the same as that of the sidewall film 130, so that the protective layer 310 can be removed simultaneously in the subsequent process of removing the sidewall film 130 exposed from the first sidewall 310, the generation of the residue of the protective film 150 is avoided, the influence on the first sidewall 310 and the second device region 100M on the side of the first device region 100T close to the drain region 260 is further eliminated, and the process integration level and the process compatibility are improved.
In the present embodiment, the process of forming the protective film 150 includes a Low Pressure Chemical Vapor Deposition (LPCVD) process. In this embodiment, the material of the protection film 150 is silicon oxide, the precursor used in the low pressure chemical vapor deposition process includes TEOS (Tetra-Ethyl-Ortho-Silicate), the TEOS is liquid at normal temperature, and the silicon oxide is formed by using the TEOS through the low pressure chemical vapor deposition process, which is beneficial to improving the thickness uniformity, conformality, and film quality of the protection film 150.
In other embodiments, the protective film may be formed by other suitable deposition processes, such as: a High Aspect Ratio (HARP) Process, a Plasma Enhanced (PE) deposition Process, a High-Density Plasma (HDP) Process, a Spin-on Coating (SOC) Process, and the like.
Referring to fig. 18, in the first device region 100T, the protective film 150 on the first sidewall 310 on the side close to the source region 250 is removed, and the remaining protective film 150 is used as a protective layer 350.
The protection layer 350 is used as a mask for subsequently removing the sidewall 150 of the first device region 100T on the side close to the source region 250, and is used for protecting the sidewall 150 of the first device region 100T on the side close to the drain region 260, the second device region 100M, and the resistance region 100R, so as to reduce the influence on the sidewall 150 of the first device region 100T on the side close to the drain region 260, the second device region 100M, and the resistance region 100R, and improve process compatibility.
In this embodiment, in the step of forming the protection film 150, the protection film 150 conformally covers the top surface and the side wall of the first side wall 310, the offset side wall 220, the gate structure 200, and the side wall film 130 on the top surface of the substrate 100, and compared with the case where only the protection film 150 is formed on the side wall of the first side wall 310, the film layers on the top surfaces of the offset side wall 220 and the gate structure 200 are a stacked structure formed by the side wall film 130 and the protection film 150, and the film layers on the top surfaces of the offset side wall 220 and the gate structure 200 are thicker, so that in the step of removing the protection film 150 on the side wall of the first side wall 310 close to the source region 250, after the protection film 150 on the side wall of the first side wall 310 close to the source region 250 is removed, the film layers on the tops of the gate structure 200 and the offset side wall 220 can also have a partial thickness, so that the remaining film layers on the tops of the gate structure 200 and the offset side wall 220 can protect the offset side wall 220 in the step of subsequently removing the first side wall 310 close to the source region 250, so as to prevent the offset side wall 220 close to the source region 250 in the first device region 100T from being damaged.
In this embodiment, in the first device region 100T, the step of removing the protective film 150 on the first sidewall 310 on the side close to the source region 250 includes: forming a mask layer 330 on the protection film 150, wherein the mask layer 330 has a mask opening (not labeled) located above a top surface and a sidewall of the first sidewall 310 on a side of the first device region 100T close to the source region 250; removing the protective film 150 exposed from the mask opening by using the mask layer 330 as a mask; the masking layer 330 is removed.
The mask layer 320 is used as a mask for patterning the protective film 320 to define the shape and position of the protective layer. In this embodiment, the material of the mask layer 320 is photoresist.
In this embodiment, in order to ensure that the photolithography process for forming the mask layer 330 has a sufficient process window, in the process of forming the mask layer 330, the mask opening is also located at the top of a portion of the first device region 100T gate structure 200 close to the source region 250 and above the top of the offset sidewall 220.
Correspondingly, in the process of removing the protective film 150 exposed by the mask layer 330 as a mask, the etching amount of the protective film 150 is controlled to ensure that the side wall films 130 on the top of the gate structure 200 and the top of the offset side wall 220 close to the source region 250 are not removed while the protective film 150 on the first side wall 310 close to the source region 250 is removed.
In this embodiment, the process of removing the protective film 150 on the first sidewall 310 near one side of the source region 250 includes a wet etching process. The wet etching process has the characteristic of isotropic etching so as to remove the protective film 150 exposed by the mask opening and located on the top surface of the sidewall film 130 and the sidewall of the first sidewall 310, and the wet etching process is simple to operate and low in cost.
Specifically, the etching solution of the wet etching process may be a hydrofluoric acid solution.
In other embodiments, an isotropic dry etching process may be further used to remove the protective film 150 on the first sidewall 310 near one side of the source region 250.
Referring to fig. 19, the first sidewall 310 on a side close to the source region 250 is removed using the protection layer 350 as a mask.
In this embodiment, in the process of forming the protection layer 350, the film layer on the top of the gate structure 200 and the offset spacer 220 may further have a partial thickness, and the remaining film layer on the top of the gate structure 200 and the offset spacer 220 may protect the top of the offset spacer 220 in the step of removing the first spacer 310 near one side of the source region 250, so as to prevent the offset spacer 220 near one side of the source region 250 in the first device region 100T from being damaged, thereby correspondingly facilitating to ensure the integrity of the offset spacer 220 near one side of the source region 250, and reducing the risk of exposing a partial sidewall of the gate structure 200 due to the reduction in height of the offset spacer 220 near one side of the source region 250, and further facilitating to prevent a subsequent metal silicide layer from being formed on the exposed sidewall of the gate structure 200.
In this embodiment, the process of removing the first sidewall spacers 310 on the side of the first device region 100T close to the source region 250 includes a wet etching process. In this embodiment, the first sidewall 310 is made of silicon nitride, and the etching solution of the wet etching process may be a phosphoric acid solution.
Referring to fig. 20, after removing the first sidewall 310 near one side of the source region 250, the sidewall film 130 and the protection layer 350 exposed by the first sidewall 310 are removed, and the remaining sidewall films 130 between the offset sidewall 220 and the first sidewall 310 and between the substrate 100 and the first sidewall 310 are used as the second sidewall 320.
After removing the first sidewall 310 close to the source region 250, the sidewall film 130 exposed from the first sidewall 310, and the protective layer 350, the substrate 100 between the source region 250 of the first device region 100T and the offset sidewall 220 is exposed, so that the substrate 100 between the source region 250 of the first device region 100T and the offset sidewall 220 is doped subsequently to form a first lightly doped region, and accordingly, in the subsequent formation of the metal silicide layer, the metal silicide layer can also be formed on the top surface of the first lightly doped region.
In this embodiment, the material of the protection layer 350 is the same as that of the sidewall film 130; in the same step, the sidewall film 130 and the protection layer 350 exposed by the first sidewall 310 are removed, so that an additional step of removing the protection layer 350 is not required, the process flow is simplified, and the process integration degree and compatibility are improved.
In this embodiment, a wet etching process is adopted to remove the sidewall film 130 and the protection layer 350 exposed by the first sidewall 310. The wet etching process has the characteristic of isotropic etching, and is easy to etch and remove the film layer on the structure with the step morphology, so that the probability of generating residues on the protective layer 350 and the side wall film 130 of the first device region 100T close to the source region 250 is reduced. In this embodiment, the material of the sidewall film 130 and the protection layer 350 is silicon oxide, and the etching solution of the wet etching process is a hydrofluoric acid solution.
Referring to fig. 21, in the first device region 100T, a first lightly doped region 270 is formed in the substrate 100 between the source region 250 and the offset sidewall spacers 220, and the doping type of the first lightly doped region 270 is the same as that of the source region 250.
The first lightly doped region 270 is used to form a junction interface with a steep concentration gradient between a source region and a channel of the TFET device, so as to improve the performance of the TFET by utilizing a band-to-band tunneling effect.
In this embodiment, the doping depth of the first lightly doped region 270 is less than the doping depth of the source region 250, the doping type of the first lightly doped region 270 is the same as the doping type of the TFET source region 250, and the doping concentration of the first lightly doped region 270 is lower than the doping concentration of the source region 250.
When forming an N-type TFET, the dopant ions of the first lightly doped region 270 are P-type ions, such as: b ions, ga ions, or In ions; when forming a P-type TFET, the dopant ions of the first lightly doped region 270 are N-type ions, for example: p ions, as ions or Sb ions.
In this embodiment, the step of forming the first lightly doped region 270 includes: forming a fourth shielding layer (not shown) covering the drain region 260 and the second device region 100M, wherein the fourth shielding layer exposes the substrate 100 on the side of the gate structure 200 of the first device region 100T close to the source region 250; performing ion implantation on the substrate 100 on the side, close to the source region 250, of the first device region 100T gate structure 200 by using the fourth shielding layer as a mask to form the first lightly doped region 270; and removing the fourth shielding layer.
The fourth shielding layer is used as a mask for ion implantation of the substrate 100 on the side of the gate structure 200 of the first device region 100T close to the source region 250. In this embodiment, the fourth shielding layer is made of photoresist.
In this embodiment, the ion implantation process performed on the substrate 100 at the side of the gate structure 200 of the first device region 100T close to the source region 250 is a Lightly Doped Drain (LDD) implantation process.
In this embodiment, the fourth shielding layer is removed by performing an ashing process and a wet photoresist removal process in sequence.
Referring to fig. 22, a metal silicide layer 340 is formed on the source region 250, the drain region 260, the first lightly doped region 270, and the top surface of the gate structure 200.
As can be seen from the foregoing description, the remaining film layer on the top of the gate structure 200 and the offset sidewall 220 can protect the top of the offset sidewall 220 in the step of removing the first sidewall 310 near one side of the source region 250, so as to prevent the offset sidewall 220 near one side of the source region 250 in the first device region 100T from being damaged, which is beneficial to correspondingly ensuring the integrity of the offset sidewall 220 near one side of the source region 250, and reducing the risk of exposing a part of the sidewall of the gate structure 200 due to the reduction of the height of the offset sidewall 220 near one side of the source region 250, so as to further facilitate preventing the metal silicide layer 340 from being formed on the exposed sidewall of the gate structure 200, which is beneficial to correspondingly preventing the metal silicide layer 340 from affecting the electric field distribution inside the gate structure 200, and preventing the problem of short-circuiting the metal silicide layer on the first lightly doped region and the source region due to the extension of the metal silicide layer 340 along the sidewall of the gate structure 200, thereby optimizing the performance of the semiconductor structure.
In this embodiment, the metal silicide layer 340 is further formed on the top surface of the source/drain doped region 240 of the second device region 100M, so that the metal silicide layer 340 is formed on the first device region 100T and the second device region 100M in the same step, and the process integration level and compatibility of forming a TFET device and a MOS device are improved.
The metal silicide layer 340 is located on the top surfaces of the source region 250, the drain region 260, the gate structure 200, and the source-drain doped region 240, and is used to reduce Contact resistance between the source region 250, the drain region 260, the gate structure 200, the source-drain doped region 240, and a corresponding Contact plug (Contact, CT).
In this embodiment, the metal silicide layer 340 is further located on the top surface of the first lightly doped region 270, and the metal silicide layer 340 is further in contact with the first lightly doped region 270, so that the junction interface of the first lightly doped region 270 of the TFET device is pushed towards the lower side of the gate structure 200 through impurity segregation of the metal silicide and silicon, and the tunneling efficiency of the TFET device is further improved.
In this embodiment, the material of the metal silicide layer 340 may be a nickel silicide, a cobalt silicide, or a titanium silicide.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the invention, as defined in the appended claims.

Claims (15)

1. A method of forming a semiconductor structure, comprising:
providing a substrate comprising a first device region for forming a tunneling field effect transistor;
forming a grid structure on the substrate, wherein an offset side wall is formed on the side wall of the grid structure;
forming side wall films positioned on the top surface and the side wall of the offset side wall, the top surface of the grid structure and the top surface of the substrate, and a first side wall positioned on the side wall of the side wall film of the offset side wall;
after the first side wall is formed, in the first device region, a source region is formed in the substrate on one side of the grid structure, and a drain region is formed in the substrate on the other side of the grid structure, wherein the doping types of the drain region and the source region are different;
forming a protective film which is conformally covered on the top surface and the side wall of the first side wall, the offset side wall, the grid structure and the side wall film on the top surface of the substrate;
in the first device region, removing the protective film on a first side wall close to one side of the source region, wherein the rest protective film is used as a protective layer;
removing the first side wall close to one side of the source region by taking the protective layer as a mask;
after removing the first side wall close to one side of the source region, removing the side wall film and the protective layer exposed from the first side wall, wherein the rest side wall films positioned between the offset side wall and the first side wall and between the substrate and the first side wall are used as second side walls;
forming a first lightly doped region in the first device region and in the substrate between the source region and the offset side wall, wherein the doping type of the first lightly doped region is the same as that of the source region;
and forming a metal silicide layer on the top surfaces of the source region, the drain region, the first lightly doped region and the gate structure.
2. The method of forming a semiconductor structure of claim 1, wherein in the step of providing a substrate, the substrate further comprises a second device region for forming a metal oxide semiconductor field effect transistor;
the method for forming the semiconductor structure further comprises the following steps: forming source-drain doped regions in the gate structure of the second device region and the substrate on two sides of the first side wall after the first side wall is formed and before the protective film is formed;
in the step of forming the metal silicide layer, the metal silicide layer is also formed on the top surface of the source-drain doped region.
3. The method of forming a semiconductor structure of claim 2, further comprising: and after the offset side wall is formed and before the side wall film is formed, forming second lightly doped regions in the grid structure of the second device region and the substrate on two sides of the offset side wall.
4. The method for forming the semiconductor structure according to claim 2, wherein after the first side wall is formed and before the source region and the drain region are formed, a source-drain doped region is formed in the substrate on both sides of the gate structure and the first side wall of the second device region.
5. The method of forming a semiconductor structure according to claim 1, wherein a material of the protective film is the same as a material of the sidewall film;
and in the same step, removing the side wall film and the protective layer exposed from the first side wall.
6. The method for forming a semiconductor structure according to claim 1 or 4, wherein in the step of forming the protective film, a material of the protective film includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, or boron carbonitride.
7. The method for forming a semiconductor structure according to claim 1 or 4, wherein in the step of forming the protective film, a thickness of the protective film is the same as a thickness of the sidewall film.
8. The method for forming the semiconductor structure according to claim 1, wherein the first side wall and the offset side wall are made of the same material.
9. The method according to claim 1 or 8, wherein the material of the first side wall comprises one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide and silicon oxycarbonitride;
the offset side wall is made of one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide and silicon oxycarbonitride.
10. The method of forming a semiconductor structure of claim 1, wherein in the first device region, the step of removing the protective film on the first sidewall adjacent to the source region side comprises: forming a mask layer on the protective film, wherein the mask layer is provided with a mask opening, and the mask opening is positioned on the top surface and the side wall of the first side wall on one side of the first device area close to the source area; removing the protective film exposed from the mask opening by taking the mask layer as a mask; and removing the mask layer.
11. The method of forming a semiconductor structure of claim 1, wherein the process of removing the protective film on the first sidewall adjacent to the source region side comprises a wet etching process.
12. The method for forming the semiconductor structure according to claim 1, wherein the step of removing the first sidewall on the side of the first device region close to the source region comprises a wet etching process.
13. The method of forming a semiconductor structure of claim 1, wherein the process of removing the sidewall film and the protective layer exposed by the first sidewall comprises a wet etching process.
14. The method of forming a semiconductor structure of claim 1, wherein the gate structure comprises a gate dielectric layer and a gate layer over the gate dielectric layer.
15. The method of forming a semiconductor structure of claim 14, wherein the material of the gate layer comprises polysilicon or amorphous silicon.
CN202110483046.3A 2021-04-30 2021-04-30 Method for forming semiconductor structure Pending CN115274444A (en)

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