CN115274434A - High-performance voltage stabilizing diode prepared by optimizing surface dielectric structure and method - Google Patents
High-performance voltage stabilizing diode prepared by optimizing surface dielectric structure and method Download PDFInfo
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Abstract
The invention provides a method for preparing a high-performance voltage stabilizing diode by optimizing a surface dielectric structure, which is characterized in that an oxide layer which is left in the previous process and contains defects and charges is selectively removed by adding a special photoetching and etching process, so that the factors of the breakdown voltage of the voltage stabilizing diode, which is caused by the charged charges in the surface oxide layer, changing along with time and temperature are eliminated; an oxide layer grows again at low temperature, the influence of the former procedure on the oxide layer on the surface of the device is eliminated, the optimization of the surface dielectric layer structure of the p-n junction of the voltage regulator diode is realized, and the stability of the breakdown voltage of the voltage regulator diode is improved; in the aging process of continuously adding the reverse bias current, the breakdown voltage of the device is almost unchanged; the method is compatible with a bipolar process in the prior art, has no obvious influence on the performance of the original bipolar device, and can obviously improve the stability of the breakdown voltage of the voltage stabilizing diode.
Description
Technical Field
The invention belongs to the technical field of voltage regulator diode preparation, and particularly relates to a high-performance voltage regulator diode prepared by optimizing a surface dielectric structure and a method.
Background
The voltage stabilizing diode is widely applied to the design of a reference structure of an analog circuit, a linear voltage stabilizing power supply is provided for the circuit, and the stability of breakdown voltage of the linear voltage stabilizing power supply directly influences the function of a product. Through test verification, after aging tests at a certain time and temperature, breakdown voltage of the voltage stabilizing diode manufactured by the conventional process can greatly drift along with time, and finally circuit parameter mutation and even superscript are caused, so that early failure of a product is caused.
The drift degree of breakdown voltage of the voltage regulator diode is related to the manufacturing process of an integrated circuit, and after an epitaxial layer grows in the conventional bipolar simulation process, a large amount of defects and charged charges are generated in a surface oxide layer of a device through a plurality of process steps such as plasma etching, high-energy ion implantation and the like. Under the condition of both high temperature and high voltage, the defects and the charged charges can modulate the width of a depletion layer of a surface p-n junction, so that the breakdown voltage of the voltage regulator diode drifts.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a high-performance voltage stabilizing diode prepared by optimizing a surface dielectric structure and a method thereof, which can obviously improve the stability of the breakdown voltage of the voltage stabilizing diode.
The invention is realized by the following technical scheme:
a method for preparing a high-performance voltage stabilizing diode by optimizing a surface dielectric structure comprises the following steps:
after forming a PN junction of the voltage stabilizing diode, removing all defects on the surface of the voltage stabilizing diode, and cleaning;
growing a silicon dioxide layer on the surface of the cleaned PN junction of the voltage stabilizing diode in a low-temperature oxidation furnace tube again;
and depositing an interlayer medium USG, forming a voltage stabilizing diode contact hole by adopting wet etching, photoetching and etching metal to form a metal lead, photoetching and etching a passivation layer medium to form a pressure welding point, and finishing the preparation of the high-performance voltage stabilizing diode.
Further, if an integrated circuit with a capacitor is required, a capacitor area window is formed on an N + type emitter region in an area outside the PN junction of the voltage stabilizing diode through photoetching, a silicon nitride capacitor dielectric layer is deposited, and the silicon nitride capacitor dielectric layer in the area outside the capacitor area window is removed through photoetching.
Further, the silicon nitride capacitance dielectric layer in the area outside the window of the capacitance area is removed by adopting a capacitance reverse etching photoetching plate.
Furthermore, the silicon nitride capacitance medium layer is obtained by adopting a CVD (chemical vapor deposition) method.
Further, the thickness of the silicon nitride capacitor dielectric layer is 50nm-100nm.
Further, all defects on the surface of the PN junction of the voltage stabilizing diode comprise charged charges and silicon oxide with defects;
the defect removing process is completed by adopting a layer of photoetching and etching process.
Further, SPM, HF and APM cleaning liquids are adopted when the surface of the PN junction of the voltage stabilizing diode is cleaned.
Further, when the silicon dioxide layer grows again, a low-temperature oxidation furnace tube with the temperature of 800-850 ℃ is selected; and the regrown silicon dioxide layer is no more than 100nm thick.
Further, the interlayer dielectric USG is obtained by a CVD chemical vapor deposition method.
A high-performance voltage stabilizing diode prepared by optimizing a surface dielectric structure comprises
The device comprises a P-type substrate and an N-epitaxial layer arranged on the upper side of the P-type substrate, wherein a voltage stabilizing diode P-type base region and an N + type emitter region are embedded in the surface of the N-epitaxial layer, which is far away from the P-type substrate;
an N + type emitter region is embedded in the P-type base region of the voltage-stabilizing diode, metal leads are arranged on the surface of the P-type base region of the voltage-stabilizing diode and the upper side of the embedded N + type emitter region, and a silicon dioxide layer covers the region, provided with the metal leads, on the surface of the P-type base region of the voltage-stabilizing diode;
a silicon nitride dielectric layer is arranged on the upper side of the N + type emitting region, and metal leads are arranged on the upper side of the N + type emitting region and the upper side of the silicon nitride dielectric layer positioned on the upper side of the N + type emitting region;
silicon oxide covers the region on the upper side of the N-epitaxial layer, wherein the region is not embedded with the voltage-stabilizing diode P-type base region and the N + type emitter region; the top of each metal lead is connected with a passivation layer, and an interlayer dielectric USG is filled between the silicon oxide and the passivation layers.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention provides a method for preparing a high-performance voltage stabilizing diode by optimizing a surface dielectric structure, which comprises the steps of selectively removing an oxide layer which is left in the previous process and contains defects and charges by adding a special photoetching and etching process, thereby eliminating the factors of the breakdown voltage of the voltage stabilizing diode, which are caused by the charged charges in the surface oxide layer, along with the change of time and temperature; an oxide layer grows again at low temperature, the influence of the previous working procedure on the oxide layer on the surface of the device is eliminated, the optimization of the structure of the surface dielectric layer of the p-n junction of the voltage regulator diode is realized, and the stability of the breakdown voltage of the voltage regulator diode is improved; in the aging process of continuously adding the reverse bias current, the breakdown voltage of the device is almost unchanged; the method is compatible with a bipolar process in the prior art, has no obvious influence on the performance of the original bipolar device, and can obviously improve the stability of the breakdown voltage of the voltage stabilizing diode.
Drawings
FIG. 1 is a cross-sectional view of a P-type region with a PN junction diode formed in the base region in an embodiment of the present application;
FIG. 2 is a cross-sectional view of an N-type region of a PN junction diode formed in an emitter region and a lower plate region of a capacitor in an embodiment of the present application;
FIG. 3 is a cross-sectional view of a thin silicon dioxide layer grown on a surface of a Zener diode by removing a front oxide layer by photolithography and etching according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a window of a capacitor area etched by photolithography in accordance with an embodiment of the present invention;
FIG. 5 illustrates CVD deposition of capacitor dielectric silicon nitride in an embodiment of the present application;
FIG. 6 is a cross-sectional view of a portion of a capacitor region of silicon nitride remaining after a silicon nitride etch back mask is used in an embodiment of the present invention;
FIG. 7 shows a CVD deposited interlayer dielectric USG according to an embodiment of the present application;
FIG. 8 is a cross-sectional view of a metal lead formed by lithographically etching a contact hole and depositing metal in an embodiment of the present application;
FIG. 9 is a cross-sectional view of a zener diode including a capacitor formed after deposition of a passivation layer in an embodiment of the present application;
FIG. 10 is a cross-sectional view of a Zener diode without a capacitor according to an embodiment of the present application.
In the figure: the device comprises a P-type substrate 1, an N-epitaxial layer 2, a voltage stabilizing diode P-type base region 3, an N + type emitter region 4, a metal lead 9, a silicon dioxide layer 6, a silicon nitride dielectric layer 7, silicon oxide 5, a passivation layer 10 and an interlayer dielectric USG8.
Detailed Description
The present invention will now be described in further detail with reference to specific examples, which are intended to be illustrative, but not limiting, of the invention.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in other sequences than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The invention provides a method for preparing a high-performance voltage stabilizing diode by optimizing a surface medium structure, which comprises the following steps of:
after the voltage stabilizing diode PN junction is formed, removing all defects on the surface of the voltage stabilizing diode PN junction, and cleaning;
growing a silicon dioxide layer 6 on the surface of the cleaned PN junction of the voltage stabilizing diode again in a low-temperature oxidation furnace tube;
and depositing an interlayer medium USG8, forming a voltage stabilizing diode contact hole by adopting wet etching, photoetching and etching metal to form a metal lead, photoetching and etching a passivation layer medium to form a pressure welding point, and finishing the preparation of the high-performance voltage stabilizing diode.
Preferably, if an integrated circuit with a capacitor is required, a capacitor area window is formed on one N + type emission area 4 in an area outside a PN junction of the voltage stabilizing diode through photoetching, a silicon nitride capacitor dielectric layer 7 is deposited, the silicon nitride capacitor dielectric layer 7 in the area outside the capacitor area window is removed through photoetching, and further, a capacitor reverse-etching photoetching mask is adopted for the silicon nitride capacitor dielectric layer 7 in the area outside the capacitor area window; further, the silicon nitride capacitor dielectric layer 7 is obtained by a CVD chemical vapor deposition method; the thickness of the silicon nitride capacitor dielectric layer 7 is 50nm-100nm.
Preferably, all defects on the surface of the PN junction of the voltage stabilizing diode comprise charged charges and silicon oxide with defects;
the defect removing process is completed by adopting a layer of photoetching and etching process.
Preferably, SPM, HF and APM cleaning liquids are adopted when the surface of the PN junction of the voltage regulator diode is cleaned.
Preferably, when the silicon dioxide layer 6 is regrown, a low-temperature oxidation furnace tube with the temperature of 800-850 ℃ is selected; and the regrown silicon dioxide layer 6 is no more than 100nm thick.
Preferably, the interlayer dielectric USG8 is obtained by CVD chemical vapor deposition.
A preferred embodiment provided by the present invention comprises the steps of:
growing a 9-11 mu m N-epitaxial layer 2 by using a P type <111> silicon wafer with the resistivity of 8-13 omega-cm as a raw material, wherein the resistivity of the N-epitaxial layer 2 is 3.5-4.0 omega-cm;
photoetching and etching the epitaxial layer through a series of processes to form a P-type base region injection window, and thermally growing a 100nm base region high-energy ion injection blocking oxide layer at 900 ℃; wherein the injection conditions are as follows: the implanted impurity is boron element, the implantation energy is 60keV, and the implantation dosage is 3E14cm-2-4E14cm-2Then, completing the activation and redistribution of P-type impurities under the annealing condition of 30min at the temperature of 1150 ℃ to form a P-type base region 3 of the voltage stabilizing diode, as shown in fig. 1;
forming an N + type emitter region doping window and a capacitor lower plate window by photoetching, and completing the preparation of a high-concentration N + type emitter region 4 by phosphorus pre-deposition at 900 ℃ and phosphorus impurity re-diffusion at 950 ℃ so as to form a voltage-stabilizing diode structure as shown in figure 2;
photoetching and etching to form a voltage stabilizing diode area window, cleaning for 15 minutes by adopting an HF acid solution of 3;
selecting a low-temperature oxidation furnace tube, and regrowing a 100nm thin silicon dioxide layer 6 at the temperature of 850 ℃, as shown in figure 4;
photoetching and etching to form a capacitor area window, and depositing a silicon nitride dielectric layer 7 with the thickness of 50nm-100nm by LPCVD (low pressure chemical vapor deposition), as shown in FIG. 5;
and adding a layer of capacitance reverse etching photoetching plate, and etching the silicon nitride dielectric layer 7 by adopting a dry method. Optimizing the etching process, so that the over-etching amount of the lower silicon dioxide layer is less than or equal to 10nm in the etching process, only the silicon nitride dielectric layer 7 in the capacitance area is left, the stress of silicon nitride introduced into the wafer is eliminated, and the capacitance structure with the dielectric layer of silicon nitride of 50nm-100nm is formed, as shown in fig. 6;
depositing interlayer dielectric USG8 with a certain thickness by CVD, and forming P and N contact holes of a voltage stabilizing diode and contact holes of an upper electrode and a lower electrode of a capacitor by wet etching, as shown in FIG. 7;
depositing 2 mu m of metal aluminum, and photoetching and etching the metal to form a metal lead 9 of the device; then annealed at a temperature of 450 ℃ for 30 minutes as shown in FIG. 8;
a 600nm passivation layer 10 is deposited, the passivation layer 10 is lithographically etched to form a bonding pad, and annealed at 350 c for 20 minutes, as shown in fig. 9.
The application provides a high-performance voltage-stabilizing diode prepared by optimizing a surface medium structure, as shown in fig. 9, the high-performance voltage-stabilizing diode comprises a P-type substrate 1 and an N-epitaxial layer 2 arranged on the upper side of the P-type substrate 1, wherein a P-type base region 3 and an N + type emitting region 4 of the voltage-stabilizing diode are embedded in the surface of one side, far away from the P-type substrate 1, of the N-epitaxial layer 2;
an N + type emitter region 4 is embedded in the voltage-stabilizing diode P-type base region 3, metal lead wires are arranged on the surface of the voltage-stabilizing diode P-type base region 3 and the upper side of the embedded N + type emitter region 4, and a silicon dioxide layer 6 covers the area, provided with the metal lead wires 9, on the surface of the voltage-stabilizing diode P-type base region 3;
a silicon nitride dielectric layer 7 is arranged on the upper side of the part of the N + type emitting region 4, and metal aluminum 9 is arranged on the upper side of the N + type emitting region 4 and the upper side of the silicon nitride dielectric layer 7 positioned on the upper side of the N + type emitting region 4;
the silicon oxide 5 covers the region on the upper side of the N-epitaxial layer 2 where the voltage-stabilizing diode P-type base region 3 and the N + type emitter region 4 are not embedded; the bottom and the top of each metal lead 9 are connected with a passivation layer 10, and an interlayer dielectric USG8 is filled between the silicon oxide 5 and the passivation layer 10.
Further, if the high-performance zener diode obtained in the integrated circuit process preparation without the capacitor is as shown in fig. 10, the structure of the high-performance zener diode only includes one P-type base region 3, and the N + type emitter region 4 is embedded therein.
The breakdown voltage test results of the zener diode prepared by the present application and the conventional diode in the prior art under the condition of continuously applying the current of 600 muA are shown in the table 1 at the initial value of 10 minutes and 20 minutes.
Table 1 power-up test results of zener diodes prepared in the present application and conventional zener diodes
As can be seen from table 1, the breakdown voltage of the diodes prepared by the conventional process was changed to 40mV and 48.9mV at the time of power-up for 10 minutes and 20 minutes, but the zener diodes prepared by the present application were changed to only 8.3mV and 7.5mV.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for preparing a high-performance voltage stabilizing diode by optimizing a surface medium structure is characterized by comprising the following steps:
after forming a PN junction of the voltage stabilizing diode, removing all defects on the surface of the voltage stabilizing diode, and cleaning;
growing a silicon dioxide layer (6) on the surface of the cleaned PN junction of the voltage stabilizing diode in a low-temperature oxidation furnace tube again;
depositing an interlayer medium USG (8), forming a voltage stabilizing diode contact hole by adopting wet etching, photoetching and etching metal to form a metal lead, photoetching and etching a passivation layer medium to form a pressure welding point, and finishing the preparation of the high-performance voltage stabilizing diode.
2. The method for manufacturing a high performance zener diode by optimizing the surface dielectric structure as claimed in claim 1 wherein if an integrated circuit with a capacitor is required, a capacitor region window is formed by photolithography etching on an N + type emitter region (4) in a region other than the PN junction of the zener diode, and a silicon nitride capacitor dielectric layer (7) is deposited, and the silicon nitride capacitor dielectric layer (7) in a region other than the capacitor region window is removed by photolithography etching.
3. The method for preparing a high-performance zener diode by optimizing the surface dielectric structure according to claim 2, wherein the silicon nitride capacitor dielectric layer (7) except the region outside the window of the capacitor region is removed by using a capacitor reverse etching reticle.
4. The method for preparing a high-performance zener diode by optimizing the surface dielectric structure according to claim 2, wherein the silicon nitride capacitor dielectric layer (7) is obtained by a CVD chemical vapor deposition method.
5. The method for preparing a high-performance zener diode by optimizing the surface dielectric structure according to claim 2 wherein the thickness of the silicon nitride capacitor dielectric layer (7) is 50nm to 100nm.
6. The method for manufacturing a high performance zener diode by optimizing the surface dielectric structure of claim 1 wherein all defects on the surface of the PN junction of the zener diode include charged charges and silicon oxide with defects;
the defect removing process is completed by adopting a layer of photoetching and etching process.
7. The method for preparing a high-performance zener diode by optimizing the surface dielectric structure according to claim 1, wherein the cleaning solution for the PN junction surface of the zener diode is SPM, HF and APM.
8. The method for preparing the high-performance voltage stabilizing diode by optimizing the surface dielectric structure according to claim 1, wherein when the silicon dioxide layer (6) is re-grown, a low-temperature oxidation furnace tube with the temperature of 800-850 ℃ is selected; and the regrown silicon dioxide layer (6) is no more than 100nm thick.
9. The method for preparing a high-performance zener diode by optimizing the surface dielectric structure according to claim 1, wherein the interlayer dielectric USG (8) is obtained by CVD chemical vapor deposition.
10. A method for preparing a high-performance voltage stabilizing diode by optimizing a surface dielectric structure is based on any one of claims 1 to 9, and comprises the following steps
The device comprises a P-type substrate (1) and an N-epitaxial layer (2) arranged on the upper side of the P-type substrate (1), wherein a voltage stabilizing diode P-type base region (3) and an N + type emitter region (4) are embedded in the surface of one side, far away from the P-type substrate (1), of the N-epitaxial layer (2);
an N + type emitter region (4) is embedded in the P-type base region (3) of the voltage-stabilizing diode, metal leads (9) are arranged on the surface of the P-type base region (3) of the voltage-stabilizing diode and the upper side of the embedded N + type emitter region (4), and a silicon dioxide layer (6) covers the region, provided with the metal leads (9), on the surface of the P-type base region (3) of the voltage-stabilizing diode;
a silicon nitride dielectric layer (7) is arranged on the upper side of the part of the N + type emitting region (4), and metal leads (9) are arranged on the upper side of the N + type emitting region (4) and the upper side of the silicon nitride dielectric layer (7) positioned on the upper side of the N + type emitting region (4);
silicon oxide (5) covers the region, in which the voltage-stabilizing diode P-type base region (3) and the N + type emitter region (4) are not embedded, on the upper side of the N-epitaxial layer (2); the top of each metal lead (9) is connected with a passivation layer (10), and an interlayer dielectric USG (8) is filled between the silicon oxide (5) and the passivation layer (10).
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