CN115273741A

CN115273741A - Display panel, display device, and pixel driving method

Info

Publication number: CN115273741A
Application number: CN202210926825.0A
Authority: CN
Inventors: 袁粲; 李永谦; 董学; 袁志东
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2022-08-03
Filing date: 2022-08-03
Publication date: 2022-11-01

Abstract

The embodiment of the application discloses a display panel, a display device and a pixel driving method. In one embodiment, a display panel includes a plurality of pixels each including two light emitting devices, and a pixel circuit driving the pixels, the pixel circuit including: a data writing unit; a driving unit including a second transistor and a third transistor, gates of the second and third transistors being shared and electrically connected to the first node, a second pole of the second transistor being electrically connected to an anode of the first light emitting device, and a second pole of the third transistor being electrically connected to an anode of the second light emitting device; the memory cell includes a first capacitor and a second capacitor, first poles of the first and second capacitors are common and electrically connected to the first node, a second pole of the first capacitor is electrically connected to an anode of the first light emitting device, and the second pole is electrically connected to an anode of the second light emitting device. In this embodiment, by providing two light-emitting paths having a common anode relationship, dark spot failure can be avoided with a simple configuration.

Description

Display panel, display device, and pixel driving method

Technical Field

The application relates to the field of display technology. And more particularly, to a display panel, a display device, and a pixel driving method.

Background

In the display field, a display device formed by the OLED technology has a fast response speed while maximizing a contrast ratio, and thus the OLED display device is expected to become a next-generation display mainstream product.

Generally, a display area of an OLED display panel includes pixels arranged in an array, each pixel is a light emitting device, and the pixel circuits are one-to-one pixel circuits that drive the light emitting devices to emit light.

Therefore, it is desirable to provide a display product capable of effectively avoiding the display dark spot failure caused by the above problems.

Disclosure of Invention

An object of the present application is to provide a display panel, a method for manufacturing the same, and a display device, so as to solve at least one of the problems in the prior art.

In order to achieve the purpose, the following technical scheme is adopted in the application:

a first aspect of the present application provides a display panel including a plurality of pixels arranged in an array and a pixel circuit driving the pixels, each pixel including two light emitting devices, the pixel circuit including: data write unit, drive unit, memory cell, wherein:

a data writing unit including a first transistor having a first electrode electrically connected to the data signal terminal, a second electrode electrically connected to the first node, and a control electrode electrically connected to the first control terminal;

a driving unit including second and third transistors, first electrodes of the second and third transistors being electrically connected to the first power signal terminal, gates being common and electrically connected to the first node, a second electrode of the second transistor being electrically connected to an anode of the first light emitting device, and a second electrode of the third transistor being electrically connected to an anode of the second light emitting device;

the memory cell includes a first capacitor and a second capacitor, first poles of the first and second capacitors are common and electrically connected to the first node, a second pole of the first capacitor is electrically connected to an anode of the first light emitting device, and a second pole of the second capacitor is electrically connected to an anode of the second light emitting device.

In some optional embodiments, the pixel circuit further comprises a sensing unit, and the reset unit comprises: and first poles of the fourth transistor and the fifth transistor are electrically connected to the sensing terminal, the control electrode is electrically connected to the second control terminal, a second pole of the fourth transistor is electrically connected to a second pole of the second transistor, and a second pole of the fifth transistor is electrically connected to a second pole of the third transistor.

In some alternative embodiments, the device comprises a driving circuit layer formed on a substrate, the driving circuit layer comprises a metal shielding layer, a gate layer and a source drain layer which are arranged in a stacked manner,

the first electrode of the first capacitor is formed in the gate layer, the second electrode comprises a first sub-portion and a second sub-portion, the first sub-portion is formed in the metal shielding layer, the second sub-portion is formed in the source drain layer, the first sub-portion is electrically connected with the second sub-portion,

the first electrode of the second capacitor is formed in the gate layer, the second electrode includes a third sub-portion and a fourth sub-portion, the third sub-portion is formed in the metal shielding layer, the fourth sub-portion is formed in the source/drain layer, the third sub-portion is electrically connected to the fourth sub-portion,

and the second pole of the first capacitor is electrically isolated from the second pole of the second capacitor.

In some alternative embodiments, the first light emitting device comprises a first anode, the second light emitting device comprises a second anode,

the display panel further comprises a light emitting layer disposed on the driving circuit layer, the light emitting layer comprising an anode layer,

the first anode and the second anode are formed in the anode layer and electrically isolated, the first anode covering the second sub-portion and the second anode covering the fourth sub-portion.

In some alternative embodiments, including an array of pixel opening areas and a transparent area surrounding the pixel opening areas,

the first light emitting device includes a first anode, the second light emitting device includes a second anode,

the first anode includes a first anode via through to the second pole of the first capacitor, the second anode includes a second anode via through to the second pole of the second capacitor,

the first anode through hole and the second anode through hole are arranged in the transparent area.

In some alternative embodiments, a driving circuit layer formed on the substrate is included, and the pixel circuit is disposed in the driving circuit layer, wherein

The second transistor and the third transistor are arranged in parallel and have gates in common, and the fourth transistor and the fifth transistor are arranged in parallel and have gates in common.

In some alternative embodiments, the display device comprises a plurality of pixel units arranged in an array, each pixel unit comprises four pixels, and the data input end of the pixel circuit of each pixel is respectively connected to the data lines corresponding to red, green, blue and white.

In some optional embodiments, the light-emitting layer further comprises a driving circuit layer formed on the substrate and a light-emitting layer formed on the driving circuit layer,

the light-emitting layer comprises pixels arranged in an array, the light-emitting layer comprises an anode, an auxiliary electrode and a cathode, the auxiliary electrode and the anode are arranged in the same layer,

the auxiliary electrode comprises a first sublayer, a second sublayer and a third sublayer, and the end faces of the first sublayer and the third sublayer extend beyond the second sublayer to be electrically connected with the cathode.

A second aspect of the present application provides a display device comprising the display panel described above.

A third aspect of the present application provides a pixel driving method for the display panel described above, comprising:

each pixel circuit controls a data signal written into the data signal terminal in response to a signal of the first control terminal to enable the second transistor in the driving unit to generate a first driving current to drive the first light emitting device to emit light, and simultaneously the third transistor generates a second driving current to drive the second light emitting device to emit light,

when one of the light emitting devices generates a dark spot, the other light emitting device continues to emit light under the control of the signal of the first control terminal.

The beneficial effect of this application is as follows:

the display panel comprises a display panel body, a display device and a pixel driving method, wherein each pixel comprises two light-emitting devices, independent light-emitting paths for driving the two light-emitting devices are arranged in a pixel circuit, the driving unit comprises a first transistor and a second transistor which are respectively used as driving transistors of two light-emitting paths, and a storage unit comprising a first capacitor and a second capacitor.

Drawings

The following describes embodiments of the present application in further detail with reference to the accompanying drawings.

FIG. 1 shows a schematic circuit schematic of adjacent four pixel circuits in a display panel according to an embodiment of the present application;

fig. 2 shows a schematic layout of a partial region of a display panel according to an embodiment of the present application;

FIGS. 3a to 3d show exploded views of the layouts of the layers of the region in the large dashed box in FIG. 2;

fig. 4 to 8 show schematic layouts of a partial region of a display panel according to an embodiment of the present application.

Detailed Description

In order to more clearly explain the present application, the present application is further described below with reference to the following examples and the accompanying drawings. Like parts in the drawings are denoted by the same or similar reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not intended to limit the scope of the present application.

It should be noted that, when a module "comprises," comprising, "or the like" is described as "having," "including," or "including," it means that the module includes other elements in addition to the first element, the second element, and/or the third element. In addition, the ordinal numbers "first", "second", and "third" in this application are not intended to limit the particular sequence, but merely to distinguish between the various parts.

The terms "formed on (8230)", "formed on (828230)", "formed on (8230)", "disposed on (8230)", "formed on (8230)") and "disposed on (8230)", as used herein, mean that one layer is directly formed or disposed on another layer, or that one layer is indirectly formed or disposed on another layer, i.e., that another layer is present between the two layers.

In addition, in the present application, the term "disposed on the same layer" is used to mean that two layers, components, members, elements or portions can be formed by the same manufacturing process (e.g., patterning process, etc.), and the two layers, components, members, elements or portions are generally formed of the same material. For example, two or more functional layers are arranged in the same layer, which means that the functional layers arranged in the same layer can be formed by using the same material layer and using the same manufacturing process, so that the manufacturing process of the display substrate can be simplified.

The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and drain of the transistors used herein are symmetrical, the source and drain may be interchanged. In the embodiment of the present invention, the gate of the transistor is referred to as a control terminal, one of the source and the drain is referred to as a first pole, and the other is referred to as a second pole. In the embodiments of the present invention, the first electrode of the transistor is referred to as a source, and the second electrode is referred to as a drain. In addition, the embodiments of the present invention may use a transistor including a P-type transistor or an N-type transistor, and for convenience of description, the P-type transistor is taken as an example to be described below. It should be understood by those skilled in the art that when the transistor is N-type, the specific structure of the circuit is not affected, and the potential of the driving transistor only needs to be adjusted appropriately.

In view of the above problems, an embodiment of the present application provides a display panel including a plurality of pixels arranged in an array, each pixel including two light emitting devices, and a pixel circuit driving the pixels, the pixel circuit including: data write unit, drive unit, memory cell, wherein:

the data writing unit comprises a first transistor, a first pole of the first transistor is electrically connected to the data signal end, a second pole of the first transistor is electrically connected to the first node, and a control pole of the first transistor is electrically connected to the first control end;

In this embodiment, each pixel includes two light emitting devices, and an independent light emitting path including a driving circuit for driving the two light emitting devices is provided in the pixel circuit, specifically, by providing that the data input unit includes a first transistor, the driving unit includes a first transistor and a second transistor which are respectively used as driving transistors of two light emitting paths, and a storage unit including a first capacitor and a second capacitor, when each pixel is lighted, if a dark spot problem occurs in one light emitting device, the light emitting device in the other path can continue to emit light, so that a dark spot defect in a display process can be avoided, and the service life and the display effect of the display device can be improved; in addition, the first electrodes of the first capacitor and the second capacitor are shared, so that at least one data input transistor can be saved, the structure is simple, and the size of the driving circuit is reduced.

In a specific embodiment, referring to fig. 1, which exemplarily shows four pixels in a display panel and four pixel circuits driving the four pixels, it can be seen that the display panel includes a plurality of pixels arranged in an array and a pixel circuit driving the pixels. The following describes the structure of each pixel and the pixel circuit for driving each pixel, taking the pixel circuit and the pixel located at the upper left corner as an example.

Referring to fig. 1, in the embodiment of the present application, each pixel includes two light emitting devices, i.e., a first light emitting device D1 and a second light emitting device D2. It will be understood by those skilled in the art that the present application is not intended to limit the type of light emitting device, and although each light emitting device is shown as an Organic Light Emitting Diode (OLED) in the example of fig. 1, it is not intended to be limited thereto, and the light emitting device may be one of a MiniLED and a micro led in practical applications, or other devices capable of driving two independent devices using the pixel circuit described below.

As shown with continued reference to fig. 1, each pixel circuit includes: the device comprises a data writing unit, a driving unit and a storage unit. The data input unit comprises a first transistor T1, the driving unit comprises a second transistor T2 and a third transistor T3, and the storage unit comprises a first capacitor C1 and a second capacitor C2. The gates of the second transistor T2 and the third transistor T3 are shared, and the first poles of the first capacitor C1 and the second capacitor C2 are shared, so that the two light emitting paths are simultaneously controlled by the data input through the first transistor T1, and thus two independent light emitting paths are not required to be provided for data input, that is, the two independent light emitting paths are realized by only 5 transistors and two capacitors to control the two independent first light emitting device D1 and the second light emitting device D2 to emit light. That is to say, the first electrodes of the first capacitor and the second capacitor are arranged to be shared, and the grid electrodes of the second transistor and the third transistor are electrically connected together, so that one data input transistor can be saved, the structure is simple, and the size of the driving circuit is reduced.

Specifically, with continued reference to fig. 1, a first pole of the first transistor T1 is electrically connected to the Data signal terminal Data _ w, a second pole is electrically connected to the first node N1, and a control pole is electrically connected to the first control terminal G1; first poles of the second transistor T2 and the third transistor T3 are electrically connected to the first power signal terminal VDD, gates of the second transistor T2 and the third transistor T3 are shared and electrically connected to the first node N1, a second pole of the second transistor is electrically connected to an anode of the first light emitting device D1, and a second pole of the third transistor T3 is electrically connected to an anode of the second light emitting device D2; first poles of the first and second capacitors C1 and C2 are commonly used and electrically connected to the first node N1, a second pole of the first capacitor C1 is electrically connected to an anode of the first light emitting device D1, and the second pole is electrically connected to an anode of the second light emitting device D2. The anode of the first light emitting device D1 is electrically connected to the second pole of the second transistor T2, and the cathode is electrically connected to the second power signal terminal VSS, and the anode of the second light emitting device D2 is electrically connected to the second pole of the third transistor T3, and the cathode is electrically connected to the second power signal terminal VSS.

With the above arrangement, a first light emitting path from the first power signal terminal VDD to the first light emitting device D1 through the second transistor T2 and then to the second power signal terminal VSS, and a second light emitting path from the first power signal terminal VDD to the second light emitting device D2 through the third transistor T3 and then to the second power signal terminal VSS are formed under the control of the data signal input from the first transistor T1 of the data input unit. As can be seen from the circuit diagram shown in fig. 1, except for the shared first transistor T1, the first light emitting path and the second light emitting path are completely independent, so that when a pixel formed by the first light emitting device D1 and the second light emitting device D2 is normally displayed, the first light emitting device D1 and the second light emitting device D2 are simultaneously turned on to emit light, when any one of the light emitting devices is turned off due to poor light emission caused by particle phenomenon, the turned-off faulty path does not affect the other independent light emitting path, the other light emitting device can be normally turned on, and the probability of occurrence of dark spots of two light emitting devices in the same pixel is extremely low, so that it is ensured that the failure of one light emitting device does not affect the normal display of the display panel image by the above arrangement, thereby ensuring the display effect and the service life of the display product.

It should be noted that, when the pixel includes two light emitting devices, because the two light emitting devices are simultaneously turned on, in order to make the display effect of the pixel the same as that of one light emitting device in the conventional display panel, the magnitude of the Data signal accessed by the Data signal terminal Data _ w should be 1/2 of the signal value in the normal display, so that the brightness of the light emitted by the first light emitting device D1 and the second light emitting device D2 is about 1/2 of the normal brightness, and the same brightness as the normal display will be obtained in the simultaneous turning on, which is not described herein again. In addition, it should be understood that two independent light-emitting paths are provided in the present application, so that when a dark spot of one light-emitting device is detected, a data signal value input by the data input terminal is controlled to be a signal value during normal display, and thus, when only one light-emitting device is turned on, the light-emitting effect of two light-emitting devices can still be obtained.

In further detail, with continued reference to fig. 1, the pixel circuit further includes a sensing unit including: fourth and fifth transistors T4 and T5, first poles of the fourth and fifth transistors T4 and T5 being electrically connected to the sensing terminal Sense, the control pole being electrically connected to the second control terminal G2, a second pole of the fourth transistor T4 being electrically connected to a second pole of the second transistor T2, and a second pole of the fifth transistor T5 being electrically connected to a second pole of the third transistor T3.

The sensing unit is used for enabling the sensing terminal Sense to be in a floating state without any signal when the sensing unit is in a blanking or shutdown state, controlling the second transistor T2 and the third transistor T3 to be conducted through the first transistor T1, charging equivalent parasitic capacitors of the fourth transistor T4 and the fifth transistor T5, stopping when the equivalent parasitic capacitors are charged to threshold voltages Vth of the second transistor T2 and the third transistor T3, sensing the sensing terminal Sense to obtain the threshold voltages Vth of the second transistor T2 and the third transistor T3, and setting a sensing signal Vth input by the sensing terminal Sense to a first terminal of the second transistor T2 and a second terminal of the third transistor T3 based on a second control signal input by the second control terminal G2 in a data input stage when an image is displayed, so that the second transistor T2 and the third transistor T3 can be compensated.

In addition, one pixel unit in this example is shown in the partial circuit diagram shown in fig. 1, that is, the display panel includes a plurality of pixel units arranged in an array, alternatively, each pixel unit includes four pixels with reference to fig. 1, and the Data input terminals of the pixel circuit of each pixel are connected to the Data lines Data _ r, data _ g, data _ b, and Data _ w corresponding to red, green, blue, and white, respectively. Through the arrangement, each pixel unit comprises eight light-emitting devices corresponding to four color pixels and a pixel circuit for driving the pixels, each pixel circuit is controlled by the data lines corresponding to different colors and emits light under the control of the data signals accessed by the data lines, and therefore the normal display of each pixel unit in the display panel according to the specified color can be ensured.

However, it should be understood by those skilled in the art that the number of pixels and the types of pixels included in the above one pixel unit are only exemplary, that is, in some specific applications, the pixel unit may also include other numbers of pixels and the pixel type collocation in the pixel unit may also be different, and will not be described herein again.

In consideration of the fact that each pixel comprises two mutually independent light emitting channels, in order to save wiring resources and space resources within a limited display area range of a display panel, in addition to arranging a first capacitor and a second capacitor sharing a first pole in a circuit schematic diagram, and a second transistor T2 and a third transistor T3 sharing a grid electrode enable data input control to be completed through a transistor of a data input unit, so that the number of transistors is simplified, and wiring complexity is reduced.

Specifically, referring to fig. 2, the display panel includes a driving circuit layer formed on a substrate, pixel circuits are disposed in the driving circuit layer, and a partial layout of the driving circuit layer of the pixel circuits corresponding to two pixels is schematically illustrated, that is, a pixel circuit corresponding to a white pixel driven by a Data signal terminal Data _ W and a pixel circuit corresponding to a green pixel driven by a Data signal terminal Data _ G, where the pixel circuit of the white pixel is denoted by W and the pixel circuit of the green pixel is denoted by G.

In this embodiment, the second transistor and the third transistor are arranged in parallel and have their gates in common, and the fourth transistor and the fifth transistor are arranged in parallel and have their gates in common.

As can be seen from fig. 2, in the pixel circuit of the white pixel, the second transistor W _ T2 and the third transistor W _ T3 are arranged in parallel and gate-shared, and the fourth transistor W _ T4 and the fifth transistor W _ T5 are arranged in parallel and gate-shared; in the pixel circuit of the green pixel, the second transistor G _ T2 and the third transistor G _ T3 are arranged in parallel and have gates in common, and the fourth transistor G _ T4 and the fifth transistor G _ T5 are arranged in parallel and have gates in common, so that the arrangement of the transistors in each pixel circuit can be made more compact by arranging two transistors controlled by the same gate signal in parallel and having a common gate, additional wiring in the interval arrangement is avoided, the arrangement of the transistors is optimized, and the overall size of the pixel circuit is reduced.

Specifically, referring to fig. 2, the arrangement direction of the second transistor T2 and the third transistor T3 is perpendicular to the arrangement direction of the fourth transistor T4 and the fifth transistor T5, for example, the arrangement direction of the second transistor T2 and the third transistor T3 is the same as the arrangement direction of the gate lines G1 and G2, and the arrangement direction of the fourth transistor T4 and the fifth transistor T5 is the same as the arrangement direction of the first power signal terminal VDD and the Data signal terminal Data _ w, so that the gate lines G1 and G2 arranged vertically and horizontally, and the first power signal terminal VDD and the Data signal terminal Data _ w, etc. can be electrically connected with shorter connection wirings, thereby simplifying the wiring space in the pixel circuit, improving the space utilization, and further reducing the size of the pixel circuit.

It should be understood by those skilled in the art that although the transistor arrangement is illustrated as white pixels and green pixels in this example, the arrangement is not limited thereto, and the arrangement in the pixel circuits of other pixels is similar to this, and is not described again here.

Fig. 3a to 3d are exploded views showing the layout of each layer of the region circled by a large dotted frame in fig. 2, and the driving circuit layer includes: the display panel further comprises a light emitting layer arranged on the driving circuit layer, and the light emitting layer comprises an anode layer. The first pole of the first capacitor C1 is formed in the gate layer, the second pole includes a first sub-portion and a second sub-portion, the first pole of the second capacitor C2 is formed in the gate layer, and the second pole includes a third sub-portion and a fourth sub-portion.

Fig. 3a shows a metal shielding layer in an area, where the metal shielding layer may be formed in a first sub-portion and a third sub-portion, S1 represents the first sub-portion, S2 represents the third sub-portion, and an unmarked area may be a connection line portion in a circuit.

Fig. 3b shows the gate layer in the region, where the part marked G represents the first pole arranged in the gate layer, and the first capacitor C1 and the second capacitor C2 share the first pole G. Other regions not shown may be the traces formed in the gate layer and the gate lines G1 and G2 supplying the gate signals to the second and third transistors T2 and T3, and the fourth and fifth transistors T4 and T5.

Fig. 3c illustrates the source and drain layer in a region in which the second sub-portion and the fourth sub-portion are formed, wherein the portion labeled S1 represents the second sub-portion and the region labeled S2 represents the fourth sub-portion.

Although not specifically shown, an insulating dielectric layer for isolating each layer is further included between the metal shielding layer, the gate layer, and the source/drain layer, and the number of layers of the insulating dielectric layer may be one or more, and is not particularly limited. The first sub-portion and the second sub-portion are electrically connected by a via penetrating through each of the dielectric layers, and the third sub-portion and the fourth sub-portion are electrically connected by a via penetrating through each of the dielectric layers. Therefore, the first capacitor C1 in the embodiment of the present application is a sandwich structure formed by the first sub-portion, the first pole, and the second sub-portion, and the second capacitor C2 is a sandwich structure formed by the third sub-portion, the first pole, and the fourth sub-portion.

S1 and S2 are intended to represent electrically connected parts, wherein, with reference to fig. 3a to 3C, the first sub-section is electrically connected with the second sub-section to form a first pole of the first capacitor C1, the third sub-section and the fourth sub-section are electrically connected to form a second pole of the second capacitor C2, and the second pole of the first capacitor C1 is electrically isolated from the second pole of the second capacitor C2.

As shown in fig. 3a to 3C, the areas of the first sub-portion and the second sub-portion are different, and the areas of the third sub-portion and the fourth sub-portion are different, but those skilled in the art will understand that the total capacitance of the first capacitor C1 formed by the first sub-portion, the second sub-portion and the first pole G should be the same as the total capacitance of the second capacitor C2 formed by the third sub-portion, the fourth sub-portion and the first pole G1, so that each path is identical. Through the arrangement of the sandwich structure, when the local area in the source-drain layer is insufficient, the equivalent electrode size between the second sub-part and the first electrode G is smaller than that between the fourth sub-part and the first electrode G, the size of the first sub-part is larger than that of the third sub-part in the metal shielding layer which is more sufficient in the local area, so that the final equivalent electrode sizes of the first capacitor C1 and the second capacitor C2 are completely the same, and equal capacitance values are obtained, namely, the sandwich structure is more favorable for the compact layout of a pixel circuit, and the miniaturization is facilitated.

In addition, continuing to refer to fig. 3d, fig. 3d further illustrates an anode layer disposed in the light emitting layer corresponding to the area within the large dashed box circle in fig. 2, the anode layer including a first anode and a second anode. Where S1 denotes a first anode, S2 denotes a second anode, the first anode covers the second subsection, and the second anode covers the fourth subsection.

Considering that one pixel includes two light emitting devices and the anode of each light emitting device would need to be electrically connected to the capacitor through a via, the via would occupy the space of the light emitting region, affecting the aperture ratio, compared to the case of only one light emitting device.

Therefore, in particular, in the embodiment of the present application, the position of the through hole connecting the anode and the capacitor is adjusted.

Specifically, the display panel includes pixel opening areas (pixel circuit corresponding areas in the drawing) arranged in an array and a transparent area surrounding the pixel opening areas, the first light emitting device D1 includes a first anode, and the second light emitting device D2 includes a second anode. Referring to fig. 2, the first anode includes a first anode via hole 104-1 penetrating to the second pole of the first capacitor C1, the second anode includes a second anode via hole 104-2 penetrating to the second pole of the second capacitor, and the first anode via hole 104-1 and the second anode via hole 104-2 are disposed in the transparent region.

Through the arrangement, the first anode through hole 104-1 and the second anode through hole 104-2 which occupy larger space are prevented from being arranged in the transparent area, so that the first anode through hole 104-1 and the second anode through hole 104-2 are prevented from influencing the size of the opening area, and the brightness of the light-emitting area is improved.

In some embodiments, referring to fig. 2 to 3d, the first anode via 104-1 and the second anode via 104-2 are located at a side of the first power signal terminal VDD trace away from the second transistor, which is more favorable for forming a via space layout and can prevent the vias from forming short circuits with the first power signal terminal VDD and the Data signal terminal Data (e.g., data-W).

In some embodiments, referring to fig. 2 to 3d, in the W and R pixels, taking the W pixel as an example for description, the second pole of the first capacitor C1 extends from the pixel opening area to the first anode via 104-1, and the second pole of the first capacitor C1 overlaps at least one of the first power signal terminal VDD and the Data-W signal line, for example: the second pole of the first capacitor C1 is overlapped with the first power signal terminal VDD to form an overlapped capacitor, and the first power signal terminal VDD is a fixed voltage, which is beneficial to the stability of the first capacitor C1. Similarly, the second pole of the second capacitor C2 extends from the pixel opening region to the second anode via 104-2, and the second pole of the second capacitor C2 overlaps at least one of the first power signal terminal VDD and the Data-w signal line, for example: the second pole of the second capacitor C21 overlaps the first power signal terminal VDD to form an overlap capacitor, and the first power signal terminal VDD is a fixed voltage, which is beneficial to the stability of the second capacitor C2.

In some embodiments, referring to fig. 2 to 3d, in the G and B pixels, taking the G pixel as an example, the second pole of the first capacitor C1 extends from the pixel opening region to the first anode via hole (corresponding to G _ S1), and the second pole of the first capacitor C1 overlaps with at least one of the auxiliary electrode line Aux _ on and the Data signal line (e.g., data-B), for example: the second pole of the first capacitor C1 overlaps the auxiliary electrode line Aux _ on to form an overlap capacitor, and the auxiliary electrode line Aux _ on is a fixed voltage (e.g., VSS), which is beneficial to the stability of the first capacitor C1. Similarly, the second pole of the second capacitor C2 extends from the pixel opening region to the second anode via hole (corresponding to G _ S2), and the second pole of the second capacitor C2 overlaps with at least one of the auxiliary electrode line Aux _ on, the Data signal line (e.g., data-b), for example: the second pole of the second capacitor C21 overlaps the auxiliary electrode line Aux _ on to form an overlapping capacitor, and the auxiliary electrode line Aux _ on is a fixed voltage (e.g., VSS), which is beneficial to the stability of the second capacitor C21.

In some embodiments, referring to fig. 2-3 d, the W pixel and the R pixel are arranged up and down, the R pixel and the B pixel are arranged up and down, data-W and Data-R are respectively located at two sides of the second transistors of the W pixel and the R pixel, and Data-g and Data-B are respectively located at two sides of the second transistors of the R pixel and the B pixel, which is beneficial to improving the aperture ratio of the pixel opening area and reducing the overlap of signal lines.

In some embodiments, as shown in fig. 2 to 3d, the sensing line sense is located between the W pixel and the G pixel, and is located between the R pixel and the B pixel, so that 4 pixels are shared, which is beneficial to reducing the use of signal lines.

In some embodiments, referring to fig. 2 to 3d, in the W pixel, the gate line G1 is closer to the second transistor of the W pixel than the gate line G2, so as to reduce the overlap between the gate line G1 and other signal lines, and further facilitate the stability of the Data signal (the gate line G1 is an input for controlling the Data signal).

In order to further understand the relationship between the layers of the display panel in the embodiment of the present application, the following is further described in detail with reference to the layouts of fig. 4 to 8.

Referring to fig. 4, the driving circuit layer of the display panel includes a metal light shielding layer 101 and an active layer 102 formed on the light shielding layer, wherein the material of the metal light shielding layer 101 may be an opaque metal such as copper, aluminum, and the like. The active layer 102 is made of a semiconductor material, and the doping type and concentration are different depending on the type of each transistor, and are not limited herein. The position of each active region in the active layer 102 defines the specific position of the transistor, and as can be seen from fig. 4, the first transistor is a separately arranged transistor, and the other transistors are arranged two by two.

Referring to fig. 5, the gate layer 103 is disposed on the metal light-shielding layer 101, and the gate layer 103 includes a gate 103-1, and as can be seen, the transistors arranged side by side share the gate 103-1. In addition, the gate layer 103 further includes a gate line G1 and a gate line G2, and as can be seen from fig. 1, the gate line G1 provides a gate signal for the first transistor T1, and the gate line G2 provides a gate signal for the fourth transistor T4 and the fifth transistor T5.

In some embodiments, such as fig. 5, the gate line G2 forms a ring shape, which is advantageous for forming a plurality of path branches at the fourth transistor and the fifth transistor controlling each pixel. Similarly, the gate line G1 may also form a ring shape, which is beneficial to form a plurality of path branches in the first transistor controlling each pixel.

Referring to fig. 6, a via layer and a dielectric layer are provided on the gate layer 103, and a first anode via 104-1 and a second anode via 104-2 are formed in the via layer and the dielectric layer. Of course, it should be understood by those skilled in the art that this is merely an example, and in practical applications, the dielectric layer may be only one layer or multiple layers, and will not be described herein again. In addition, other types of vias may also be formed in the via layer and the dielectric layer, for example, a via formed through the via layer into the active layer 102, a via formed through to the gate layer, and the like.

Referring to fig. 7, a source drain layer 105 is disposed on the dielectric layer, and a source drain is formed in the source drain layer 105.

Referring to fig. 8, a transparent organic layer is formed on the source-drain layer 105, the transparent organic layer defining a pixel opening area and a transparent area, and an area of a white solid-line frame in the drawing is the transparent area defined by the transparent organic layer.

It should be noted that, in the above layout, the relationship between the active layer, the gate layer, and the source/drain layer is only described by taking a transistor with a top gate structure as an example, but the present application is not limited thereto.

In addition, although not further shown, an inorganic protective layer (PVX) may be further disposed on the transparent organic layer, and the inorganic protective layer (PVX) may be formed on the pad regions of the first and second anodes and the pad regions of the source-drain electrodes to protect the metal layer.

Considering that the material resistance of the cathode material is large when the top emission is performed, the voltage drop of the cathode equivalent resistance is large, and in order to reduce the voltage drop, optionally, in some embodiments, the light emitting layer includes pixels arranged in an array, and although not specifically shown, the light emitting layer includes an anode, an auxiliary electrode and a cathode, and the anode and the auxiliary electrode are disposed at the same layer. The auxiliary electrode comprises a first sublayer, a second sublayer and a third sublayer, and end faces of the first sublayer and the third sublayer extend beyond the second sublayer to be electrically connected with the cathode. The auxiliary electrode is connected with a low-level signal through an auxiliary electrode line Aux _ on, and the low-level signal is the same as the cathode signal.

In other words, the sectional view of the auxiliary electrode formed by the three-layer structure is i-shaped, by arranging the i-shaped auxiliary electrode between the anode and the cathode, the cross section formed by the first sublayer, the third sublayer and the second sublayer in the i-shaped auxiliary electrode is utilized, so that the organic light-emitting layer and the cathode also form the cross section, and the end surface of the cathode is coated with the organic light-emitting layer when the cross section is formed, so that the electrical connection relationship between the cathode and the auxiliary electrode is formed by utilizing the i-shaped cross section. Preferably, the material of the first sublayer and the third sublayer is indium tin oxide, and the material of the second sublayer is a low-resistance metal such as aluminum, copper or aluminum alloy. By arranging the auxiliary electrode, the low-resistance auxiliary electrode and the cathode are in parallel connection, most of current is conducted to the low-level auxiliary signal line through the auxiliary electrode, and cathode voltage drop (IR drop) is effectively reduced.

Based on the same inventive concept, embodiments of the present application also provide a display device including the display panel described above.

Since the display panel included in the display device provided in the embodiment of the present application corresponds to the display panels provided in the above-mentioned several embodiments, the foregoing embodiments are also applicable to this embodiment, and detailed description is omitted in this embodiment.

In this embodiment, the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a vehicle-mounted display, a digital photo frame, or a navigator, and by loading the display panel, display defects caused by dark spots of anodes or cathodes of pixel points during a display process can be effectively avoided, and a product yield is provided.

Based on the same inventive concept, embodiments of the present application further provide a pixel driving method for the display panel described above, including:

each pixel circuit controls a data signal written into the data signal terminal in response to a signal of the first control terminal, so that the second transistor in the driving unit generates a first driving current to drive the first light emitting device to emit light, and the third transistor generates a second driving current to drive the second light emitting device to emit light,

Through the arrangement, the first light-emitting device and the second light-emitting device in the two parallel and independent light-emitting channels are driven to emit light at the same time during display, and the other light-emitting device emits light normally when a dark spot occurs on one light-emitting device, so that the display yield is improved.

Aiming at the existing problems at present, a display panel, a display device and a pixel driving method are formulated, each pixel is provided with two light-emitting devices, a pixel circuit is provided with an independent light-emitting path for driving the two light-emitting devices, specifically, a data input unit is provided with a first transistor, a driving unit comprises a first transistor and a second transistor which are respectively used as driving transistors of two light-emitting paths, and a storage unit comprises a first capacitor and a second capacitor, so that when each pixel is lightened, if one light-emitting device has a dark spot problem, the light-emitting device in the other path can continuously emit light, the poor dark spot in the display process can be avoided, and the service life and the display effect of display equipment are improved; in addition, the first electrode of the first capacitor and the first electrode of the second capacitor are shared, so that at least one data input transistor can be saved, the structure is simple, the size of the driving circuit is reduced, and the driving circuit has a wide application prospect.

It should be understood that the above-mentioned examples are given for the purpose of illustrating the present application clearly and not for the purpose of limiting the same, and that various other modifications and variations of the present invention may be made by those skilled in the art in light of the above teachings, and it is not intended to be exhaustive or to limit the invention to the precise form disclosed.

Claims

1. A display panel comprising a plurality of pixels arranged in an array, each of the pixels including two light emitting devices, and a pixel circuit for driving the pixels, the pixel circuit comprising: data write-in unit, drive unit, memory cell, wherein:

the data writing unit comprises a first transistor, wherein a first pole of the first transistor is electrically connected to a data signal end, a second pole of the first transistor is electrically connected to a first node, and a control pole of the first transistor is electrically connected to a first control end;

a driving unit including second and third transistors, first electrodes of the second and third transistors being electrically connected to a first power signal terminal, gates being common and electrically connected to the first node, a second electrode of the second transistor being electrically connected to an anode of a first light emitting device, and a second electrode of the third transistor being electrically connected to an anode of a second light emitting device;

the memory cell includes a first capacitor and a second capacitor, a first pole of the first capacitor and a first pole of the second capacitor are shared and electrically connected to the first node, a second pole of the first capacitor is electrically connected to an anode of the first light emitting device, and a second pole of the second capacitor is electrically connected to an anode of the second light emitting device.

2. The display panel of claim 1, the pixel circuit further comprising a sensing unit comprising: a fourth transistor and a fifth transistor, first poles of the fourth transistor and the fifth transistor being electrically connected to the sensing terminal, the control pole being electrically connected to the second control terminal, a second pole of the fourth transistor being electrically connected to a second pole of the second transistor, a second pole of the fifth transistor being electrically connected to a second pole of the third transistor.

3. The display panel according to claim 1 or 2, comprising a driving circuit layer formed on the substrate, wherein the driving circuit layer comprises a metal shielding layer, a gate layer, and a source drain layer,

the first electrode of the first capacitor is formed in the gate layer, the second electrode comprises a first sub-portion and a second sub-portion, the first sub-portion is formed in the metal shielding layer, the second sub-portion is formed in the source drain layer, and the first sub-portion is electrically connected with the second sub-portion,

the first electrode of the second capacitor is formed in the gate layer, the second electrode includes a third sub-portion and a fourth sub-portion, the third sub-portion is formed in the metal shielding layer, the fourth sub-portion is formed in the source drain layer, the third sub-portion is electrically connected to the fourth sub-portion,

wherein a first pole of the first capacitor is shared with a first pole of the second capacitor, and a second pole of the first capacitor is electrically isolated from a second pole of the second capacitor.

4. The display panel according to claim 3, wherein the first light emitting device comprises a first anode, wherein the second light emitting device comprises a second anode,

the display panel further includes a light emitting layer disposed on the driving circuit layer, the light emitting layer including an anode layer,

the first anode and the second anode are formed in the anode layer and electrically isolated, the first anode overlying the first sub-portion, the second anode overlying the fourth sub-portion.

5. The display panel according to claim 1 or 2, comprising a pixel opening area arranged in an array and a transparent area surrounding the pixel opening area,

the first anode includes a first anode via through to a second pole of the first capacitor, the second anode includes a second anode via through to a second pole of the second capacitor,

the first anode through hole and the second anode through hole are disposed in the transparent region.

6. The display panel according to claim 1 or 2, comprising a driving circuit layer formed on a substrate, the pixel circuit being provided in the driving circuit layer, wherein

7. The display panel according to claim 1, comprising a plurality of pixel units arranged in an array, each of the pixel units comprising four of the pixels, the data input terminals of the pixel circuits of each of the pixels being connected to data lines corresponding to red, green, blue, and white, respectively.

8. The display panel according to claim 1, further comprising a driver circuit layer formed on a substrate and a light-emitting layer formed on the driver circuit layer,

9. A display device characterized by comprising the display panel according to any one of claims 1 to 8.

10. A pixel driving method for a display panel according to any one of claims 1 to 8, comprising:

each pixel circuit controls a data signal written into the data signal terminal in response to a signal of a first control terminal so that a second transistor in the driving unit generates a first driving current to drive the first light emitting device to emit light, and a third transistor generates a second driving current to drive the second light emitting device to emit light,