CN115270705A

CN115270705A - Design rule violation prediction method, device, equipment and storage medium

Info

Publication number: CN115270705A
Application number: CN202211161340.3A
Authority: CN
Inventors: 葛瑞峰; 丁轶群; 曹高晨; 刘铭照; 梁硕; 王磊
Original assignee: Shenzhen Hongxin Micro Nano Technology Co ltd
Current assignee: Shenzhen Hongxin Micro Nano Technology Co ltd
Priority date: 2022-09-23
Filing date: 2022-09-23
Publication date: 2022-11-01
Anticipated expiration: 2042-09-23
Also published as: CN115270705B

Abstract

The application provides a method, a device, equipment and a storage medium for predicting design rule violation, and relates to the technical field of integrated circuits. The method comprises the following steps: dividing the target layout after layout to obtain a plurality of target grid areas of the target layout; according to the pin information and the through hole information of the standard units in each target grid area on a plurality of pin layers, constructing a first characteristic matrix of each target grid area, wherein the first characteristic matrix comprises a pin characteristic matrix and a through hole characteristic matrix corresponding to each pin layer, and the pin characteristic matrix is used for representing pin distribution information and the through hole characteristic matrix is used for representing through hole distribution information; and inputting the first characteristic matrix of each target grid region into a target design rule violation prediction model obtained by pre-training, and outputting a design rule violation result corresponding to each target grid region. By applying the embodiment of the application, the layout efficiency after the design rule meeting the preset condition is obtained can be improved.

Description

Design rule violation prediction method, device, equipment and storage medium

Technical Field

The present application relates to the field of integrated circuit technologies, and in particular, to a method, an apparatus, a device, and a storage medium for predicting a design rule violation.

Background

As the performance requirements of integrated circuits increase, more constraints and Design rules are proposed, and the place of violating the Design rules in the layout is called a Design Rule Violation (DRV).

At present, generally, an EDA (Electronic Design Automation) tool is used to perform Design Rule on a layout, and then a Design Rule Check (DRC) mode is used to detect whether the layout after wiring meets a preset constraint condition. If not, DRV (Design Rule Violation) can be eliminated by adjusting the wiring.

However, since the current DRC is performed after the wiring is completed, if it is determined by the DRC that the wiring needs to be adjusted, the complexity of adjusting the wiring is large, resulting in inefficiency in eliminating the DRV. That is, the layout efficiency after obtaining the design rule satisfying the preset constraint condition is low.

Disclosure of Invention

An object of the present application is to provide a method, an apparatus, a device, and a storage medium for predicting a violation of a design rule, which can improve the layout efficiency after obtaining the design rule satisfying the preset condition.

In order to achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:

in a first aspect, an embodiment of the present application provides a method for predicting a violation of a design rule, where the method includes:

dividing the target layout after layout to obtain a plurality of target grid areas of the target layout;

according to the pin information and the through hole information of the standard units in each target grid area on a plurality of pin layers, constructing a first characteristic matrix of each target grid area, wherein the first characteristic matrix comprises a pin characteristic matrix and a through hole characteristic matrix corresponding to each pin layer, and the pin characteristic matrix is used for representing pin distribution information and the through hole characteristic matrix is used for representing through hole distribution information;

and inputting the first feature matrix of each target grid region into a target design rule violation prediction model obtained by pre-training, and outputting a design rule violation result corresponding to each target grid region.

Optionally, the constructing a first feature matrix of each target grid region according to the pin information and the via information of the standard cells in each target grid region at a plurality of pin layers includes:

dividing the target mesh region into a plurality of pixel blocks;

determining pin pixel values of the pixel blocks in the target grid area at the pin layers according to the areas of the pins of the standard units in the target grid area on the pin layers in the pixel blocks and the areas of the pixel blocks;

determining a through hole pixel value of each pixel block in the target grid area according to the area of the through hole of the standard unit in each pixel block in the target grid area and the area of each pixel block;

and constructing a first characteristic matrix of the target grid region according to the pin pixel values of the pixel blocks in the target grid region on the pin layers and the through hole pixel values of the pixel blocks.

Optionally, the constructing a first feature matrix of the target grid region according to the pin pixel value of each pixel block in each pin layer and the via pixel value of each pixel block in the target grid region includes:

determining a pin characteristic matrix corresponding to each pin layer according to the pin pixel value of each pixel block in each pin layer in the target grid area;

determining the through hole feature matrix according to the through hole pixel values of the pixel blocks in the target grid areas;

and combining the pin characteristic matrix corresponding to each pin layer and the through hole characteristic matrix into the first characteristic matrix.

Optionally, the inputting the first feature matrix of each target grid region into a target design rule violation prediction model obtained by pre-training, and outputting a design rule violation result corresponding to each target grid region includes:

determining a feature vector of each target grid area according to the area of the standard cells, the area of the macro module, the number of the standard cells and the number of the nets in each target grid area;

and inputting the first feature matrix and the feature vector of each target grid region into the target design rule violation prediction model, and outputting a design rule violation result corresponding to each target grid region.

Optionally, the target design rule violation prediction model includes a convolution network and a fully-connected network, and the convolution network is connected to the fully-connected network;

correspondingly, the inputting the first feature matrix and the feature vector of each target grid region into the target design rule violation prediction model and outputting the design rule violation result corresponding to each target grid region includes:

and inputting the first feature matrix of the target grid area into the convolution network to obtain a second feature matrix output by the convolution network, and inputting the second feature matrix and the feature vector of the target grid area into the full-connection network to obtain a design rule violation result corresponding to the target grid area.

Optionally, the inputting the second feature matrix and the feature vector of the target grid area into the fully connected network to obtain a result of violation of the design rule corresponding to the target grid area includes:

inputting the second feature matrix into a first full-connection module in the full-connection network to obtain a first feature vector;

inputting the feature vector of the target grid area into a second full-connection module in the full-connection network to obtain a second feature vector;

and splicing the first feature vector and the second feature vector to obtain a design rule violation result of the target grid region.

Optionally, the dividing the target layout after the layout to obtain a plurality of target grid regions of the target layout includes:

and dividing the target layout according to a preset region size to obtain a plurality of target grid regions of the target layout.

Optionally, before the target layout is divided according to a preset region size to obtain a plurality of target grid regions of the target layout, the method further includes:

and determining the preset area size according to the height of the standard unit with the minimum size in the target layout, wherein the preset area size is larger than the height of the standard unit with the minimum size.

Optionally, before the first feature matrix of each target grid region is input into a target design rule violation prediction model obtained by pre-training and a design rule violation result corresponding to each target grid region is output, the method further includes:

dividing the sample layout after layout to obtain a plurality of sample grid regions of the sample layout;

according to the pin information and the through hole information of the standard units in the sample grid areas on the plurality of pin layers, constructing a feature matrix of each sample grid area, wherein the feature matrix comprises a pin feature matrix and a through hole feature matrix corresponding to each pin layer, and the pin feature matrix is used for representing pin distribution information and the through hole feature matrix is used for representing through hole distribution information;

carrying out design rule detection on the wired sample layout to obtain an actual design rule violation result of each sample grid region, and constructing a sample label of each sample grid region according to the design rule violation result;

and performing iterative training on the initial design rule violation prediction model according to the feature matrix and the sample label of each grid region to obtain a target design rule violation prediction model.

Optionally, the iteratively training the initial design rule violation prediction model according to the feature matrix and the sample label of each grid region to obtain a target design rule violation prediction model includes:

determining a feature vector of each sample grid region according to the area of the standard cells, the area of the macro module, the number of the standard cells and the number of the nets in each sample grid region;

and training an initial design rule violation prediction model according to the feature matrix, the feature vector and the sample label of each target grid region to obtain a target design rule violation prediction model.

In a second aspect, an embodiment of the present application further provides a device for predicting violation of design rule, where the device includes:

the dividing module is used for dividing the target layout after layout to obtain a plurality of target grid areas of the target layout;

the device comprises a construction module, a detection module and a processing module, wherein the construction module is used for constructing a first characteristic matrix of each target grid region according to pin information and through hole information of standard units in each target grid region on a plurality of pin layers, the first characteristic matrix comprises a pin characteristic matrix and a through hole characteristic matrix corresponding to each pin layer, and the pin characteristic matrix is used for representing pin distribution information and the through hole characteristic matrix is used for representing through hole distribution information;

and the output module is used for inputting the first feature matrix of each target grid region into a target design rule violation prediction model obtained by pre-training and outputting a design rule violation result corresponding to each target grid region.

Optionally, the building module is specifically configured to divide the target grid region into a plurality of pixel blocks; determining pin pixel values of the pixel blocks in each pin layer in the target grid area according to the area of the pins of the standard units in the target grid area on each pin layer in each pixel block and the area of each pixel block; determining a through hole pixel value of each pixel block in the target grid area according to the area of the through hole of the standard cell in each pixel block in the target grid area and the area of each pixel block; and constructing a first characteristic matrix of the target grid region according to the pin pixel values of the pixel blocks in the target grid region on the pin layers and the through hole pixel values of the pixel blocks.

Optionally, the building module is further specifically configured to determine a pin feature matrix corresponding to each pin layer according to a pin pixel value of each pixel block in each pin layer in the target grid area; determining the through hole feature matrix according to the through hole pixel values of the pixel blocks in the target grid areas; and combining the pin characteristic matrix corresponding to each pin layer and the through hole characteristic matrix into the first characteristic matrix.

Optionally, the output module is specifically configured to determine the eigenvector of each target grid region according to the area of the standard cell, the area of the macro module, the number of standard cells, and the number of nets in each target grid region; and inputting the first feature matrix and the feature vector of each target grid region into the target design rule violation prediction model, and outputting a design rule violation result corresponding to each target grid region.

correspondingly, the output module is further specifically configured to input the first feature matrix of the target grid area into the convolutional network to obtain a second feature matrix output by the convolutional network, and input the second feature matrix and the feature vector of the target grid area into the fully-connected network to obtain a design rule violation result corresponding to the target grid area.

Optionally, the output module is further specifically configured to input the second feature matrix into a first fully-connected module in the fully-connected network to obtain a first feature vector; inputting the feature vector of the target grid area into a second full-connection module in the full-connection network to obtain a second feature vector; and splicing the first characteristic vector and the second characteristic vector to obtain a design rule violation result of the target grid region.

Optionally, the dividing module is specifically configured to divide the target layout according to a preset region size to obtain a plurality of target grid regions of the target layout.

Optionally, the module further comprises: a determination module;

the determining module is configured to determine the preset region size according to a height of a standard cell with a minimum size in the target layout, where the preset region size is greater than the height of the standard cell with the minimum size.

Optionally, the dividing module is further configured to divide the sample layout after the layout to obtain a plurality of sample grid regions of the sample layout;

the building module is further configured to build a feature matrix of each sample grid region according to pin information and via information of standard cells in each sample grid region on a plurality of pin layers, where the feature matrix includes a pin feature matrix and a via feature matrix corresponding to each pin layer, and the pin feature matrix is used to represent pin distribution information and the via feature matrix is used to represent via distribution information;

the construction module is also used for carrying out design rule detection on the wired sample layout to obtain an actual design rule violation result of each sample grid region, and constructing a sample label of each sample grid region according to the design rule violation result;

and the training module is used for carrying out iterative training on the initial design rule violation prediction model according to the feature matrix and the sample label of each grid area to obtain a target design rule violation prediction model.

Optionally, the training module is specifically configured to determine a feature vector of each sample grid region according to an area of a standard cell, an area of a macro block, the number of standard cells, and the number of nets in each sample grid region; and training an initial design rule violation prediction model according to the feature matrix, the feature vector and the sample label of each target grid region to obtain a target design rule violation prediction model.

In a third aspect, an embodiment of the present application provides an electronic device, including: the design rule violation prediction method comprises a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, when the electronic device runs, the processor and the storage medium communicate through the bus, and the processor executes the machine-readable instructions to execute the steps of the design rule violation prediction method of the first aspect.

In a fourth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to perform the steps of the design rule violation prediction method of the first aspect.

The beneficial effect of this application is:

the embodiment of the application provides a method, a device, equipment and a storage medium for predicting design rule violation, wherein the method comprises the following steps: dividing the target layout after layout to obtain a plurality of target grid regions of the target layout; according to the pin information and the through hole information of the standard units in each target grid area on a plurality of pin layers, constructing a first characteristic matrix of each target grid area, wherein the first characteristic matrix comprises a pin characteristic matrix and a through hole characteristic matrix corresponding to each pin layer, and the pin characteristic matrix is used for representing pin distribution information and the through hole characteristic matrix is used for representing through hole distribution information; and inputting the first characteristic matrix of each target grid region into a target design rule violation prediction model obtained by pre-training, and outputting a design rule violation result corresponding to each target grid region.

By adopting the method for predicting the violation of the design rule provided by the embodiment of the application, after the target layout after layout is divided into a plurality of target grid areas, the pin distribution information of the standard cells in each target grid area on a plurality of pin layers and the through hole distribution information among the pin layers of the through hole characteristic matrix are represented by the built pin characteristic matrix, namely, the pins and the through holes can be discretized according to the pin distribution information of the standard cells in each target grid area on the plurality of pin layers and the through hole distribution information among the pin layers. That is, the first feature matrix of each target grid region carries the pin distribution information and the via distribution information corresponding to the target grid region. And then inputting the first feature matrix of each target grid area into a target design rule violation prediction model, and analyzing and processing the pin distribution information and the through hole distribution information corresponding to each target grid area by the target design rule violation prediction model to obtain a design rule violation result corresponding to each target grid area in a predictable manner.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a schematic flowchart of a method for predicting violation of design rules according to an embodiment of the present disclosure;

FIG. 2 is a schematic flow chart illustrating another method for predicting violation of design rules according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of a first feature matrix of a target grid area according to an embodiment of the present application;

FIG. 4 is a schematic flowchart illustrating a further method for predicting violation of design rules according to an embodiment of the present application;

FIG. 5 is a schematic view of a scenario of a net in a target net area according to an embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of a target design rule violation prediction model according to an embodiment of the present application;

FIG. 7 is a flowchart illustrating a further method for predicting violation of design rules according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a design rule violation prediction method according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

Before explaining the embodiments of the present application in detail, an application scenario of the present application will be described first. The application scenario may specifically be a scenario for predicting a Design Rule Violation (DRV) in the layout, where the design rule violation may be understood as a place in the layout that does not satisfy the design rule and the constraint condition. For example, the design rule may include shapes of via components, distances between wirings, and the like, and the type of the design rule violation includes a cut group space type, and the like, which is not limited in this application.

As can be seen from the description of the background art, design rule Detection (DRC) is performed only after layout routing is completed, and DRV is eliminated by adjusting routing. However, with the development of Very Large Scale Integration (VLSI) process nodes, the transistor size is further reduced, the design rules and constraints of the layout are more and more complex, the time consumed by the wiring itself and the DRV generated by the wiring are more and more, so that the time required for eliminating all DRV by using an EDA tool is greatly increased; meanwhile, many factors in the steps before wiring also affect the DRV, and the factors cannot be eliminated by adjusting the wiring. Overall, the prior art may result in inefficiency in eliminating DRV, that is, the layout efficiency after obtaining the design rule satisfying the preset constraint condition may be low.

Based on the problems, the design rule violation prediction method can predict the design rule violation in the layout based on deep learning and EDA tools. The inventor finds that pin information and through hole information of standard cells (such as components) in a layout are main factors influencing the generation of design rule violation, and further the method can predict and obtain the design rule violation in the layout based on the pin information of the standard cells in the target layout in the layout stage and a target design rule violation prediction model obtained through pre-training, specifically predict and obtain the design rule violation results of each target grid region in the target layout, explain by taking one target grid region as an example, predict and obtain the existence of the design rule violation in the target grid region, or do not exist the design rule violation in the target grid region.

It can be understood that, a worker firstly lays out the layout by using the EDA, that is, each standard cell is laid out in the layout according to a preset position to obtain the laid out layout, and then the laid out layout is automatically wired to obtain the wired layout, wherein the automatic wiring can be divided into two stages, namely, global wiring and detailed wiring. According to the description, the design rule violation can be predicted in the layout stage, so that the problem of low efficiency caused by prediction of the design rule violation in the wiring stage can be solved, and the layout efficiency after the design rule meeting the preset condition is obtained can be improved.

The method for predicting the violation of design rule mentioned in the present application is exemplified as follows with reference to the accompanying drawings. Fig. 1 is a schematic flowchart of a method for predicting violation of design rule according to an embodiment of the present application, where as shown in fig. 1, the method may include:

s101, dividing the target layout after layout to obtain a plurality of target grid regions of the target layout.

For an exemplary purpose, a layout is laid out by using an EDA tool to obtain a target layout after the layout, where the target layout after the layout includes a plurality of standard cells. After the target layout after layout is obtained, the target layout can be divided into a plurality of target grid areas with the same size, and the target grid areas comprise pins of the standard units. It will be appreciated that the target layout may include multiple layers, such as including multiple pin layers, which are layers of pin distributions for standard cells on the target layout. For the pin layer, the target grid area of the target layout represents the target grid area on each pin layer. It should be noted that the number of target mesh areas is not limited in the present application.

S102, constructing a first feature matrix of each target grid area according to the pin information and the through hole information of the standard cells in each target grid area on a plurality of pin layers.

The first characteristic matrix comprises a pin characteristic matrix and a through hole characteristic matrix corresponding to each pin layer, wherein the pin characteristic matrix is used for representing pin distribution information, and the through hole characteristic matrix is used for representing through hole distribution information. That is, the first feature matrix includes a plurality of feature matrices, and each feature matrix can be understood as one channel image.

Here, a target grid area is taken as an example for description, after the target grid area is determined, the pins of the standard cells included in the target grid area can be identified and obtained, and the target grid area may include all the pins of one standard cell, may also include a part of the pins of one standard cell, or includes pins of a plurality of standard cells.

It should be understood that the pins of one standard cell may be distributed over multiple pin layers, such as two pin layers Metal1 and Metal 2. Through holes can be formed between the two pin layers of Metal1 and Metal2, and the positions of the through holes are the positions of the overlapping regions of the pins on the Metal1 pin layer and the pins on the Metal2 pin layer.

That is, after the pins of the standard cells included in the target grid region are identified, the pin information of the standard cells included in the target grid region on the Metal1 pin layer and the Metal2 pin layer, respectively, and the via information between the Metal1 pin layer and the Metal2 pin layer can be further obtained. The pin information may be area information of the pin, and the via information may be area information of the via, for example.

Continuing to take the Metal1 pin layer and the Metal2 pin layer as an example, a pin feature matrix corresponding to the Metal1 pin layer can be constructed and obtained according to the pin information of the Metal1 pin layer, a pin feature matrix corresponding to the Metal2 pin layer can be constructed and obtained according to the pin information of the Metal2 pin layer, and a through hole feature matrix corresponding to the Metal1 pin layer and the Metal2 pin layer is constructed and obtained according to the through hole information between the Metal1 pin layer and the Metal2 pin layer, that is, the first feature matrix of the target grid region includes 3 feature matrices, or the first feature matrix of the target grid region is a three-channel image, feature images represented by the pin feature matrices corresponding to the Metal1 pin layer and the Metal2 pin layer respectively, and feature images represented by the through hole feature matrices corresponding to the Metal1 pin layer and the Metal2 pin layer.

The first feature matrices of other target grid regions of the target layout may be obtained in the manner described above, and will not be further described here.

S103, inputting the first feature matrix of each target grid region into a target design rule violation prediction model obtained by pre-training, and outputting a design rule violation result corresponding to each target grid region.

The frame of the target design rule violation prediction model obtained by the pre-training may be, for example, a frame of a VGG Convolutional Neural network in a Convolutional Neural Network (CNN), and of course, may also be a frame of other types of Convolutional Neural Networks, which is not limited in this application.

Taking a target grid area as an example, inputting the first feature matrix of the target grid area, that is, the aforementioned three-channel image corresponding to the target grid area, into the target design rule violation prediction model, performing feature extraction processing on the three-channel image corresponding to the target grid area by the target design rule violation prediction model, and further outputting a design rule violation result corresponding to the target grid area.

For example, the target design rule violation prediction model may output two results, i.e. 0 or 1, where 0 is used to indicate that the design rule violation result corresponding to the target grid region is no design rule violation, and 0 is used to indicate that the design rule violation result corresponding to the target grid region is that there is a design rule violation.

The target design rule violation prediction model can output the design rule violation results (0 or 1) corresponding to each target grid region, based on which the approximate region of the target layout with the design rule violation can be predicted and obtained, and the number of the design rule violations in the target layout can also be predicted and obtained. This also allows for more accurate consideration of routability during the routing phase of the target layout, significantly reducing routing time and the number of DRVs.

To sum up, in the design rule violation prediction method provided by the application, after the target layout after layout is divided into a plurality of target grid regions, the pin distribution information of the standard cells in each target grid region on a plurality of pin layers and the through hole distribution information between each pin layer of the through hole feature matrix are represented by using the constructed pin feature matrix, that is, the pins and the through holes can be discretized according to the pin distribution information of the standard cells in each target grid region on the plurality of pin layers and the through hole distribution information between each pin layer. That is to say, the first feature matrix of each target grid region carries the pin distribution information and the via hole distribution information corresponding to the target grid region. And then inputting the first feature matrix of each target grid area into a target design rule violation prediction model, and analyzing and processing the pin distribution information and the through hole distribution information corresponding to each target grid area by the target design rule violation prediction model to obtain a design rule violation result corresponding to each target grid area in a predictable manner.

Therefore, after the target layout is laid out or before the target layout is wired, design rule violation on the target layout can be predicted, pin information and through hole information which influence main factors for generating the design rule violation are converted into a first feature matrix which can be understood by a target design rule violation prediction model, so that the distribution condition of the design rule violation of the target layout can be obtained after the layout, the phenomenon that the design rule violation is detected in a DRC mode carried by an EDA tool after the wiring is carried out is avoided, and the layout efficiency after the design rule meeting the preset condition is obtained can be improved.

Fig. 2 is a schematic flowchart of another method for predicting violation of design rule according to an embodiment of the present disclosure. As shown in fig. 2, optionally, the constructing a first feature matrix of each target grid region according to the pin information and the via information of the standard cells in each target grid region at the multiple pin layers includes:

s201, dividing the target grid area into a plurality of pixel blocks.

One target grid area is used as an example for explanation here, and other target grid areas are similar. As can be seen from the above description, the same grid area can be mapped on different pin layers, so that dividing the target grid area into a plurality of pixel blocks is equivalent to dividing the target grid area on each pin layer into a plurality of pixel blocks.

Assuming that the pin layers are Metal1 (M1) pin layer and Metal2 (M2) pin layer, respectively, the pin distribution condition (M1 pin) of the standard cell in the M1 pin layer, the pin distribution condition (M2 pin) in the M2 pin layer, and the via distribution condition (via) between the M1 pin layer and the M2 pin layer can be as shown in fig. 3, where fig. 3 is a schematic diagram of a first feature matrix of a target grid region provided in this embodiment of the present application. As can be seen from fig. 3, one target grid area may correspond to a pin distribution area of the M1 pin layer, a pin distribution area of the M2 pin layer, and a via distribution area between the M1 pin layer and the M2 pin layer. Taking the pin distribution condition (M1 pin) of the M1 pin layer as an example for explanation, the pin distribution area of the M1 pin layer may be divided into 4 × 4 pixel blocks, and of course, may also be divided into other numbers of pixel blocks, which is not limited in this application.

S202, determining the pin pixel value of each pixel block in each pin layer in the target grid area according to the area of the pin of the standard unit in the target grid area in each pin layer in each pixel block and the area of each pixel block.

S203, determining the through hole pixel value of each pixel block in the target grid area according to the area of the through hole of the standard cell in the target grid area in each pixel block and the area of each pixel block.

Continuing the above example, M1 pin includes 16 pixel blocks, some pixel blocks include pins, and some pixel blocks do not include pins. For example, the lead regions included in each pixel block may be identified, and the area of each lead region may be calculated. After the area of each lead region is obtained, the ratio of the area of each lead region to the area of the corresponding pixel block can be used as the lead pixel value of each pixel block in the M1 lead layer. The pin pixel values of the M1 pin layer may be the eigenvalues in the pin characterization matrix shown in fig. 3.

Referring to the manner of determining the pin pixel value of the M1 pin layer, the pin pixel value of the M2 pin layer and the via pixel value of each pixel block in the target grid area can be obtained, which will not be described in detail herein.

S204, constructing a first feature matrix of the target grid region according to the pin pixel values of the pixel blocks in the target grid region on the pin layers and the through hole pixel values of the pixel blocks.

Optionally, determining a pin feature matrix corresponding to each pin layer according to the pin pixel value of each pixel block in each pin layer in the target grid area; determining a through hole characteristic matrix according to the through hole pixel value of each pixel block in each target grid area; and combining the pin characteristic matrix and the through hole characteristic matrix corresponding to each pin layer into a first characteristic matrix.

The M1 pin feature matrix corresponding to the M1 pin layer may be of the type shown in fig. 3, an M2 pin feature matrix corresponding to the M2 pin layer and a via feature matrix corresponding to via may be obtained, and a three-channel feature map composed of the M1 pin feature matrix, the M2 pin feature matrix and the via feature matrix is used as the first feature matrix.

Fig. 4 is a schematic flowchart of another design rule violation prediction method according to an embodiment of the present application. As shown in fig. 4, optionally, the inputting the first feature matrix of each target grid region into a target design rule violation prediction model obtained through pre-training and outputting a design rule violation result corresponding to each target grid region includes:

s401, determining the feature vector of each target grid area according to the area of the standard cells, the area of the macro module, the number of the standard cells and the number of the nets in each target grid area.

In an implementation embodiment, a target grid area is taken as an example, and after the target grid area is determined, the area of a standard cell, the area of a macro block (macro), the number of standard cells, and the number of nets in the target grid area can be identified, where the area of a standard cell is the sum of the areas of pins of the standard cell in the target grid area, the area of a macro block (macro) is the area of macro blocks of the standard cell in the target grid area, and a macro block can be understood as a predefined area in a target layout, in which standard cells are not allowed to be set, routing is not allowed, and the like.

The number of nets can be divided into a global net (global net) number and a local net (local net) number. The global net is used to indicate a net connecting pins inside and outside the target mesh region, and the local net is used to indicate a net connecting only pins in the target mesh region. Fig. 5 is a scene schematic diagram of nets in a target grid area according to an embodiment of the present disclosure, and as can be seen from fig. 5, a global net is a net connected to a pin a in the target grid area, that is, the number of global nets is 1; the local nets are nets connecting the pins B and C in the target grid area, that is, the number of the local nets is 1.

And constructing the area of the standard unit, the area of the macro module, the number of the standard units and the number of the wire nets corresponding to the target grid region into a feature vector according to a preset sequence, and taking the feature vector as the feature vector of the target grid region. With reference to the above description, the feature vectors of the target mesh regions can be obtained finally, and will not be described in detail here.

It should be noted that the feature vector of the target mesh region may further include net length information, etc., which is not limited in this application.

S402, inputting the first feature matrix and the feature vector of each target grid region into a target design rule violation prediction model, and outputting a design rule violation result corresponding to each target grid region.

For example, the first feature matrix and the feature vector of each target grid region may be respectively input into a network (a convolutional network or a fully connected network) corresponding to the target design rule violation prediction model, and the target design rule violation prediction model analyzes the first feature matrix and the feature vector of the target grid region and outputs a design rule violation result corresponding to each target grid region.

Therefore, the pin distribution information and the through hole distribution information corresponding to the target grid region are referred to, the area of the standard unit, the area of the macro module, the number of the standard units and the number of the wire nets corresponding to the target grid region are referred to, the layout characteristics of the target grid region can be extracted more completely by the target design rule violation prediction model, and the difference between the predicted design rule violation result and the real result is reduced.

Fig. 6 is a schematic structural diagram of a target design rule violation prediction model according to an embodiment of the present application. As shown in fig. 6, the target design rule violation prediction model includes a convolutional network 601 and a fully connected network 602, and the convolutional network 601 is connected to the fully connected network 602. The convolutional network 601 may be a VGG network structure, including multiple convolutional layers (3 × 3 conv) and multiple Pooling layers (e.g., max-Pooling). As can be seen in fig. 6, the first layer in convolutional network 601 is a convolutional layer, which includes 32 convolutional kernels, each convolutional kernel is 3 x 3 in size, and the other convolutional layers are similar. Multiple fully-connected layers, such as FC-512, FC-64, etc., may be included in the fully-connected network 602. It should be noted that the present application does not limit the structure of the target design rule violation prediction model.

Optionally, the inputting the first feature matrix and the feature vector of each target grid region into the target design rule violation prediction model and outputting the design rule violation result corresponding to each target grid region includes: and inputting the first feature matrix of the target grid area into the convolution network to obtain a second feature matrix output by the convolution network, and inputting the second feature matrix and the feature vector of the target grid area into the full-connection network to obtain a design rule violation result corresponding to the target grid area.

Referring to fig. 6, the first feature matrix of the target mesh region is input into the first convolutional layer in the convolutional network 601, the first convolutional layer performs feature extraction on the first feature matrix, and then passes through the pooling layer, the second convolutional layer, and the like, and the second feature matrix output by the last pooling layer in the convolutional network 601 connected to the fully-connected network 602.

In one example, the second feature matrix is input into a first fully-connected module in the fully-connected network to obtain a first feature vector; inputting the feature vector of the target grid area into a second full-connection module in the full-connection network to obtain a second feature vector; and splicing the first characteristic vector and the second characteristic vector to obtain a design rule violation result of the target grid region.

Exemplarily, inputting the second feature matrix to the FC-512 full connection layer in the first full connection module, and after full connection processing, outputting the first feature vector by the FC-32 full connection layer in the first full connection module; and inputting the feature vector of the target grid area into an FC-18 full connection layer in a second full connection module, and outputting a second feature vector by an FC-12 full connection layer in the second full connection module after full connection processing. After the first feature vector and the second feature vector are obtained, the first feature vector and the second feature vector can be spliced, and the splicing specifically can be convolution product, so that the design rule violation result of the target grid area can be obtained.

Optionally, the dividing the target layout after the layout to obtain the multiple target grid regions of the target layout includes: and dividing the target layout according to the preset size of the region to obtain a plurality of target grid regions of the target layout.

For example, the target layout may be segmented based on a preset region size to obtain target mesh regions with sizes respectively equal to the preset region size, that is, the sizes of the target mesh regions included in the target layout are respectively equal to the preset region size.

The preset area size can be determined according to the height of the standard cell with the minimum size in the target layout, and the preset area size is larger than the height of the standard cell with the minimum size. According to the above description, standard cells are arranged in the target layout after layout, and the height of the standard cell with the minimum size can be determined according to the size of each standard cell. Assuming that the height of the standard cell of the minimum size is 1row, the preset area size may be 4rows, i.e., all of the target grid areas are 4rows. Therefore, each target grid region can comprise a plurality of standard cells as much as possible, and based on the standard cells, more pin distribution information and through hole distribution information can be carried in the first feature matrix of the target grid region constructed in the later stage, so that the accuracy of the design rule violation results corresponding to each target grid region predicted by the target design rule violation prediction model can be improved.

Fig. 7 is a schematic flowchart of another design rule violation prediction method according to an embodiment of the present application. As shown in fig. 7, optionally, before the first feature matrix of each target grid region is input into a target design rule violation prediction model obtained through pre-training and a design rule violation result corresponding to each target grid region is output, the method further includes:

and S701, segmenting the sample layout after layout to obtain a plurality of sample grid regions of the sample layout.

S702, constructing a characteristic matrix of each sample grid area according to the pin information and the through hole information of the standard units in the various grid areas on the plurality of pin layers.

The characteristic matrix comprises a pin characteristic matrix and a through hole characteristic matrix corresponding to each pin layer, wherein the pin characteristic matrix is used for representing pin distribution information, and the through hole characteristic matrix is used for representing through hole distribution information.

It will be appreciated that the sample layout may include a plurality of sample layouts, each processed in a similar manner. A sample layout is taken as an example for description, the specific content of the feature matrix of each sample grid region included in the sample layout for dividing the sample layout and constructing the sample layout can refer to the related part content of the target layout, and the description is not repeated here.

S703, carrying out design rule detection on the wired sample layout to obtain an actual design rule violation result of each sample grid region, and constructing a sample label of each sample grid region according to the design rule violation result.

Illustratively, firstly, the features in the training samples corresponding to each sample grid region are obtained according to the sample layout after layout, then, an EDA tool is used for automatically wiring the sample layout after layout to obtain the sample layout after wiring, a design rule detection function carried by the EDA tool is used for detecting to obtain the actual design rule violation results of the sample layout, further, the actual design rule violation results of each sample grid region in the sample layout can be obtained, and the actual design rule violation results of each sample grid region can be used as the labels in the training samples corresponding to each sample grid region.

And S704, performing iterative training on the initial design rule violation prediction model according to the feature matrix and the sample label of each grid area to obtain a target design rule violation prediction model.

According to the above description, the training samples corresponding to each sample grid region include the feature matrix as a feature and the sample labels as labels, and the training samples corresponding to each sample grid region are respectively input into the initial design rule violation prediction model, wherein the feature matrix is used as the input of the initial design rule violation prediction model, and the sample labels are used as the output of the initial design rule violation prediction model to train the initial design rule violation prediction model, and when the training stop condition is satisfied, the target design rule violation prediction model is obtained through training.

Optionally, the iteratively training the initial design rule violation prediction model according to the feature matrix and the sample label of each grid region to obtain the target design rule violation prediction model includes: determining the characteristic vector of each sample grid region according to the area of the standard cells, the area of the macro module, the number of the standard cells and the number of the nets in each grid region; and training the initial design rule violation prediction model according to the feature matrix, the feature vector and the sample label of each target grid region to obtain a target design rule violation prediction model.

The feature vector for determining each sample grid region can be described with reference to the relevant portion of each target grid region, and will not be further described here. According to the method and the device, the initial design rule violation prediction model is trained by using the feature matrix and the feature vector of the target grid region, so that the trained target design rule violation prediction model has the function of extracting more finished layout features, namely the accuracy of the target design rule violation prediction model is improved.

Fig. 8 is a schematic structural diagram of a design rule violation prediction method according to an embodiment of the present application. As shown in fig. 8, the apparatus includes:

a dividing module 801, configured to divide the target layout after layout to obtain multiple target grid regions of the target layout;

a building module 802, configured to build a first feature matrix of each target grid region according to pin information and via information of standard cells in each target grid region on multiple pin layers, where the first feature matrix includes a pin feature matrix and a via feature matrix corresponding to each pin layer, and the pin feature matrix is used to represent pin distribution information and the via feature matrix is used to represent via distribution information;

the output module 803 is configured to input the first feature matrix of each target grid region into a target design rule violation prediction model obtained through pre-training, and output a design rule violation result corresponding to each target grid region.

Optionally, the building module 802 is specifically configured to divide the target grid region into a plurality of pixel blocks; determining pin pixel values of the pixel blocks in each pin layer in the target grid area according to the areas of the pins of the standard units in the target grid area on the pin layers in the pixel blocks and the areas of the pixel blocks; determining the through hole pixel value of each pixel block in the target grid area according to the area of the through hole of the standard cell in the target grid area in each pixel block and the area of each pixel block; and constructing a first characteristic matrix of the target grid region according to the pin pixel values of the pixel blocks in the pin layers and the through hole pixel values of the pixel blocks in the target grid region.

Optionally, the constructing module 802 is further specifically configured to determine a pin feature matrix corresponding to each pin layer according to the pin pixel value of each pixel block in each pin layer in the target grid area; determining a through hole characteristic matrix according to the through hole pixel value of each pixel block in each target grid area; and combining the pin characteristic matrix and the through hole characteristic matrix corresponding to each pin layer into a first characteristic matrix.

Optionally, the output module 803 is specifically configured to determine the feature vector of each target grid region according to the area of the standard cell, the area of the macro module, the number of the standard cells, and the number of nets in each target grid region; and inputting the first feature matrix and the feature vector of each target grid region into a target design rule violation prediction model, and outputting a design rule violation result corresponding to each target grid region.

correspondingly, the output module 803 is further specifically configured to input the first feature matrix of the target grid area into the convolutional network to obtain a second feature matrix output by the convolutional network, and input the second feature matrix and the feature vector of the target grid area into the fully-connected network to obtain a design rule violation result corresponding to the target grid area.

Optionally, the output module 803 is further specifically configured to input the second feature matrix into a first fully-connected module in a fully-connected network to obtain a first feature vector; inputting the feature vector of the target grid area into a second full-connection module in the full-connection network to obtain a second feature vector; and splicing the first characteristic vector and the second characteristic vector to obtain a design rule violation result of the target grid region.

Optionally, the dividing module 801 is specifically configured to divide the target layout according to a preset region size to obtain a plurality of target grid regions of the target layout.

Optionally, the module further comprises: a determining module;

the determining module is used for determining a preset area size according to the height of the standard unit with the minimum size in the target layout, wherein the preset area size is larger than the height of the standard unit with the minimum size.

Optionally, the dividing module 801 is further configured to divide the sample layout after layout to obtain a plurality of sample grid regions of the sample layout;

the building module 802 is further configured to build a feature matrix of each sample grid region according to pin information and via information of standard cells in various grid regions at multiple pin layers, where the feature matrix includes a pin feature matrix and a via feature matrix corresponding to each pin layer, and the pin feature matrix is used to represent pin distribution information and the via feature matrix is used to represent via distribution information;

the construction module 802 is further configured to perform design rule detection on the wired sample layout to obtain an actual design rule violation result of each sample grid region, and construct a sample label of each sample grid region according to the design rule violation result;

Optionally, the training module is specifically configured to determine a feature vector of each sample grid region according to the area of the standard cell, the area of the macro module, the number of standard cells, and the number of nets in each sample grid region; and training the initial design rule violation prediction model according to the feature matrix, the feature vector and the sample label of each target grid region to obtain a target design rule violation prediction model.

The above-mentioned apparatus is used for executing the method provided by the foregoing embodiment, and the implementation principle and technical effect are similar, which are not described herein again.

The above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs), among others. For another example, when one of the above modules is implemented in the form of a Processing element scheduler code, the Processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. As another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

Fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application, and as shown in fig. 9, the electronic device may include: a processor 901, a storage medium 902 and a bus 903, wherein the storage medium 902 stores machine-readable instructions executable by the processor 901, when the electronic device is operated, the processor 901 communicates with the storage medium 902 through the bus 903, and the processor 901 executes the machine-readable instructions to execute the steps of the above-mentioned method embodiments. The specific implementation and technical effects are similar, and are not described herein again.

Optionally, the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the computer program performs the steps of the above method embodiments.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or in the form of hardware plus a software functional unit.

The integrated unit implemented in the form of a software functional unit may be stored in a computer-readable storage medium. The software functional unit is stored in a storage medium and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to perform some steps of the methods according to the embodiments of the present application. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

It is noted that, in this document, relational terms such as "first" and "second," and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for predicting design rule violations, the method comprising:

according to the pin information and the through hole information of the standard units in each target grid area on a plurality of pin layers, constructing a first feature matrix of each target grid area, wherein the first feature matrix comprises a pin feature matrix and a through hole feature matrix corresponding to each pin layer, and the pin feature matrix is used for representing pin distribution information and the through hole feature matrix is used for representing through hole distribution information;

2. The method of claim 1, wherein constructing a first feature matrix for each of the target grid areas from pin information and via information for standard cells in each of the target grid areas at a plurality of pin levels comprises:

dividing the target mesh region into a plurality of pixel blocks;

determining pin pixel values of the pixel blocks in each pin layer in the target grid area according to the area of the pins of the standard units in the target grid area on each pin layer in each pixel block and the area of each pixel block;

and constructing a first characteristic matrix of the target grid region according to the pin pixel values of the pixel blocks in the target grid region at the pin layers and the through hole pixel values of the pixel blocks.

3. The method of claim 2, wherein constructing the first feature matrix of the target grid region according to the pin pixel values of the pixel blocks in the target grid region at the pin layers and the via pixel values of the pixel blocks comprises:

determining a pin characteristic matrix corresponding to each pin layer according to the pin pixel value of each pixel block in the target grid area at each pin layer;

4. The method according to claim 1, wherein the inputting the first feature matrix of each target grid region into a target design rule violation prediction model obtained by pre-training and outputting a design rule violation result corresponding to each target grid region comprises:

determining a feature vector of each target grid region according to the area of the standard cells, the area of the macro module, the number of the standard cells and the number of the nets in each target grid region;

5. The method of claim 4, wherein the target design rule violation prediction model comprises a convolutional network and a fully-connected network, and the convolutional network is connected to the fully-connected network;

inputting the first feature matrix and the feature vector of each target grid region into the target design rule violation prediction model, and outputting a design rule violation result corresponding to each target grid region, including:

6. The method according to claim 5, wherein the inputting the second feature matrix and the feature vector of the target grid area into the fully-connected network to obtain a result of the violation of the design rule corresponding to the target grid area comprises:

and splicing the first characteristic vector and the second characteristic vector to obtain a design rule violation result of the target grid region.

7. The method according to claim 1, wherein the dividing the target layout after the layout to obtain a plurality of target grid regions of the target layout comprises:

8. The method according to claim 7, wherein before the target layout is divided according to a preset region size to obtain a plurality of target grid regions of the target layout, the method further comprises:

9. The method according to any one of claims 1 to 8, wherein before the first feature matrix of each target grid region is input into a target design rule violation prediction model obtained by pre-training and a design rule violation result corresponding to each target grid region is output, the method further comprises:

10. The method according to claim 9, wherein iteratively training an initial design rule violation prediction model according to the feature matrix and the sample label of each grid region to obtain a target design rule violation prediction model comprises:

determining a feature vector of each sample grid region according to the area of the standard cells, the area of the macro blocks, the number of the standard cells and the number of the nets in each sample grid region;

11. An apparatus for predicting design rule violations, the apparatus comprising:

12. An electronic device, comprising: a processor, a storage medium and a bus, the storage medium storing machine-readable instructions executable by the processor, the processor and the storage medium communicating via the bus when the electronic device is operating, the processor executing the machine-readable instructions to perform the steps of the design rule violation prediction method according to any one of claims 1-10.

13. A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of the method for predicting design rule violations as set forth in any one of claims 1-10.