CN115238639B - Global wiring prediction method, device, equipment and storage medium - Google Patents
Global wiring prediction method, device, equipment and storage medium Download PDFInfo
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Abstract
The application provides a global wiring prediction method, a global wiring prediction device, global wiring equipment and a storage medium, and relates to the technical field of data processing. The method comprises the following steps: performing feature extraction on a chip to be predicted, and determining a feature vector of the chip to be predicted; the feature vector of the chip to be predicted comprises: the number of pins, the number of macromodules and the number of nets; and analyzing the characteristic vector of the chip to be predicted by adopting a preset prediction model, and determining the wiring distribution corresponding to the chip to be predicted. Compared with the prior art, the problem of inaccurate wiring requirement estimation is avoided.
Description
Technical Field
The present application relates to the field of data processing technologies, and in particular, to a method, an apparatus, a device, and a storage medium for predicting global routing.
Background
After the front-end synthesis is completed, the digital chip is converted into a gate-level netlist. To convert the gate-level netlist into a physical chip requires digital back-end EDA software to place a reasonable place for each device, a stage called placement. In routability-driven placement, the most critical is the implementation of a fast router.
A fast router may be an algorithm for routing demand estimation. In the prior art, the method can be obtained through probability estimation or mode wiring hypothesis; wherein: probability estimation means that for a connecting line connecting two pins, a rectangle determined by the two pins is divided into small rectangles, all probabilities of all the connecting lines are superposed on the probability that the connecting line passes through all the small rectangles, and which regions in the current chip are all expected to pass through by the connecting line can be obtained, and the regions are regions which cannot be wired. The pattern wiring is assumed to be that all the traces are led to be in an "L" shape or an "inverse L" shape, and then the trace requirements of each area can be obtained as well.
However, the above-described routing approaches are all simplified possible routing paths, and essentially reduce the solution space of feasible solutions, which are inaccurate for routing requirement estimation.
Disclosure of Invention
The present application aims to provide a global routing prediction method, apparatus, device and storage medium to solve the problem of inaccurate routing requirement estimation in the prior art.
In order to achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:
in a first aspect, an embodiment of the present application provides a global routing prediction method, where the method includes:
performing feature extraction on a chip to be predicted, and determining a feature vector of the chip to be predicted; the feature vector of the chip to be predicted comprises: the number of pins, the number of macro modules and the number of nets;
and analyzing the characteristic vector of the chip to be predicted by adopting a preset prediction model, and determining the corresponding wiring distribution of the chip to be predicted.
Optionally, the performing feature extraction on the chip to be predicted to determine the feature vector of the chip to be predicted includes:
carrying out grid division on the chip to be predicted according to the size of a preset grid to obtain a plurality of sub-grids corresponding to the chip to be predicted;
extracting the features of each sub-grid, and determining the feature vector of each sub-grid; and the feature vector of each sub-grid forms the feature vector of the chip to be predicted.
Optionally, before the mesh division is performed on the chip to be predicted according to the size of a preset mesh to obtain a plurality of sub-meshes corresponding to the chip to be predicted, the method further includes:
determining whether the area of the chip to be predicted is an integral multiple of the area of a preset grid or not;
if not, determining the width value of a first supplementary grid frame according to the area of the preset grid and the area of the chip to be predicted;
supplementing the first supplementary grid frame outside the boundary of the chip to be predicted so as to enable the area of the supplemented chip to be predicted to be integral multiple of the size of the preset grid; wherein the feature vector of the first supplementary mesh frame is 0.
Optionally, the grid division is performed on the chip to be predicted according to a preset grid size to obtain a plurality of sub-grids corresponding to the chip to be predicted, including:
determining the size of a segmentation grid according to the preset grid size and a first preset constant value;
and carrying out mesh division on the chip to be predicted according to the size of the division mesh.
Optionally, before the mesh partitioning is performed on the chip to be predicted according to the size of the segmentation mesh, the method further includes:
supplementing a second supplementary grid frame with a preset width on the outer side of the chip to be predicted; wherein the feature vector of the second supplementary mesh frame is 0.
Optionally, before the feature extraction is performed on the chip to be predicted and the feature vector of the chip to be predicted is determined, the method includes:
performing feature extraction on each sample chip in a sample set to be trained, and determining a feature vector and a routing track quantity of each sample chip; the feature vectors of the sample chip include: pin characteristics, macro module characteristics and wire mesh characteristics;
analyzing the characteristic vector of the sample chip by adopting a to-be-trained prediction model, and determining the distribution quantity of the wiring corresponding to the sample chip;
and if the difference value between the wiring track quantity and the wiring distribution quantity is greater than or equal to a preset threshold value, determining that the to-be-trained prediction model is trained.
Optionally, the trace track amount of the sample chip includes: the transverse routing track quantity and the longitudinal routing track quantity; the determining the distribution quantity of the wires corresponding to the sample chip includes:
determining the distribution quantity of transverse wirings and the distribution quantity of longitudinal wirings corresponding to the sample chip;
if the difference between the amount of the routing tracks and the distribution amount of the routing tracks is greater than or equal to a preset threshold, determining that the training of the predictive model to be trained is completed, including:
and if the difference between the transverse wiring track quantity and the transverse wiring distribution quantity is greater than or equal to a preset threshold value, and the difference between the longitudinal wiring track quantity and the longitudinal wiring distribution quantity is greater than or equal to a preset threshold value, determining that the to-be-trained predictive model is trained.
In a second aspect, another embodiment of the present application provides an apparatus for predicting global routing, including: a determination module and an analysis module, wherein:
the determining module is used for extracting the features of the chip to be predicted and determining the feature vector of the chip to be predicted; the feature vector of the chip to be predicted comprises: the number of pins, the number of macro modules and the number of nets;
the analysis module is used for analyzing the characteristic vector of the chip to be predicted by adopting a preset prediction model and determining the wiring distribution corresponding to the chip to be predicted.
Optionally, the apparatus further comprises: the dividing module is used for carrying out grid division on the chip to be predicted according to the size of a preset grid to obtain a plurality of sub-grids corresponding to the chip to be predicted;
the determining module is configured to perform feature extraction on each of the sub-grids, and determine a feature vector of each of the sub-grids; and the feature vector of each sub-grid forms the feature vector of the chip to be predicted.
Optionally, the apparatus further comprises: a supplementary module, wherein:
the determining module is specifically configured to determine whether the area of the chip to be predicted is an integral multiple of the area of a preset grid; if not, determining the width value of a first supplementary grid frame according to the area of the preset grid and the area of the chip to be predicted;
the supplement module is used for supplementing the first supplement grid frame outside the boundary of the chip to be predicted so as to enable the area of the supplemented chip to be predicted to be integral multiple of the size of the preset grid; wherein the feature vector of the first supplemental mesh border is 0.
Optionally, the determining module is specifically configured to determine the size of the segmentation mesh according to the preset mesh size and a first preset constant value;
the dividing module is specifically configured to perform mesh division on the chip to be predicted according to the size of the divided mesh.
The supplement module is specifically used for supplementing a second supplement grid frame with a preset width on the outer side of the chip to be predicted; wherein the feature vector of the second supplementary mesh frame is 0.
Optionally, the determining module is specifically configured to perform feature extraction on each sample chip in the sample set to be trained, and determine a feature vector and a trace track quantity of each sample chip; the feature vectors of the sample chip include: pin characteristics, macro module characteristics and net characteristics; analyzing the characteristic vector of the sample chip by adopting a prediction model to be trained, and determining the distribution quantity of the corresponding wiring of the sample chip; and if the difference value between the wiring track quantity and the wiring distribution quantity is greater than or equal to a preset threshold value, determining that the to-be-trained prediction model is trained.
Optionally, the determining module is specifically configured to determine a horizontal wiring distribution number and a vertical wiring distribution number corresponding to the sample chip; and if the difference between the transverse wiring track quantity and the transverse wiring distribution quantity is greater than or equal to a preset threshold value, and the difference between the longitudinal wiring track quantity and the longitudinal wiring distribution quantity is greater than or equal to a preset threshold value, determining that the to-be-trained predictive model is trained completely.
In a third aspect, another embodiment of the present application provides a global routing prediction apparatus, including: a processor, a storage medium and a bus, the storage medium storing machine-readable instructions executable by the processor, the processor and the storage medium communicating via the bus when the globally wired prediction device is run, the processor executing the machine-readable instructions to perform the steps of the method according to any of the first aspects above.
In a fourth aspect, another embodiment of the present application provides a storage medium, on which a computer program is stored, and the computer program is executed by a processor to perform the steps of the method according to any one of the above first aspects.
The beneficial effect of this application is: by adopting the global wiring prediction method provided by the application, after the characteristic vectors such as the number of pins, the number of macro modules, the number of nets and the like of the chip to be predicted are extracted, the extracted characteristic vectors are analyzed by adopting the preset prediction model, and the wiring distribution of the chip to be predicted is determined.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic flowchart of a global routing prediction method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of the boundaries of a net and pins according to an embodiment of the present application;
fig. 3 is a schematic flowchart of a global routing prediction method according to another embodiment of the present application;
FIG. 4 is a schematic diagram of a sub-grid of a chip to be predicted according to an embodiment of the present application;
fig. 5 is a schematic flowchart of a global routing prediction method according to another embodiment of the present application;
fig. 6 is a schematic structural diagram of a global routing prediction apparatus according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a global routing prediction apparatus according to another embodiment of the present application;
fig. 8 is a schematic structural diagram of a global routing prediction apparatus according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments.
The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
Additionally, the flowcharts used in this application illustrate operations implemented according to some embodiments of the present application. It should be understood that the operations of the flow diagrams may be performed out of order, and steps without logical context may be performed in reverse order or simultaneously. One skilled in the art, under the guidance of this application, may add one or more other operations to, or remove one or more operations from, the flowchart.
The following explains a global routing prediction method provided in the embodiments of the present application with reference to a plurality of specific application examples. Fig. 1 is a schematic flowchart of a global routing prediction method according to an embodiment of the present application, and as shown in fig. 1, the method includes:
s101: and performing feature extraction on the chip to be predicted, and determining a feature vector of the chip to be predicted.
The feature vector of the chip to be predicted comprises: pin count, macroblock count, and net count.
Considering that no excessive information can be extracted in the layout stage of the wiring distribution, the basic features of the chip to be predicted, which need to be extracted before prediction, are only: the boundary of a pin (pin bbox), the boundary of a macro module (macro bbox) and the boundary of a wire network (net bbox); and then determining the pin number, the macro module number and the net number of the chip to be predicted based on the extracted basic characteristics.
Fig. 2 is a schematic diagram of the boundaries of the nets and pins according to an embodiment of the present application, in which, since the nets only exist logically in the layout stage, the union of the boundaries of the pins constituting the nets is used as the boundary of the nets, and as shown in fig. 2, assuming that the nets need to connect several pins of gray small blocks, the outermost large square frame is the boundary of the nets. The specific implementation method only needs to divide the boundary intervals of all pins in the chip to be predicted into a transverse one-dimensional interval and a longitudinal one-dimensional interval respectively, and then the transverse one-dimensional intervals are combined to obtain the transverse boundary interval of the wire net, and then the longitudinal one-dimensional intervals are combined to obtain the longitudinal boundary interval of the wire net.
S102: and analyzing the characteristic vector of the chip to be predicted by adopting a preset prediction model, and determining the corresponding wiring distribution of the chip to be predicted.
The preset prediction model is obtained by training according to the real wired sample chip, so that the wiring distribution corresponding to the chip to be predicted, which is obtained through the preset prediction model, is closer to the real wiring distribution, and the obtained wiring distribution is more reasonable.
By adopting the global wiring prediction method provided by the application, after the characteristic vectors such as the number of pins, the number of macro modules, the number of nets and the like of the chip to be predicted are extracted, the extracted characteristic vectors are analyzed by adopting the preset prediction model, and the wiring distribution of the chip to be predicted is determined.
Optionally, on the basis of the foregoing embodiment, an embodiment of the present application may further provide a global routing prediction method, and an implementation process of determining a feature vector of a chip to be predicted in the foregoing method is described as follows with reference to the accompanying drawings. Fig. 3 is a flowchart illustrating a global routing prediction method according to another embodiment of the present application, and as shown in fig. 3, S101 may include:
s111: and carrying out grid division on the chip to be predicted according to the size of the preset grid to obtain a plurality of sub-grids corresponding to the chip to be predicted.
The grid is a global cell, and the grid is a result of cutting the chip into small cells. Routing is allowed for a certain number of track tracks (tracks) on each grid, the number of track tracks being called supply and the routing requirement being called need. When the number of routing requirements exceeds the number of trace tracks, i.e. the number of allowed routes is less than the number of routing requirements, congestion may occur during the routing process (congestion). Therefore, the mesh concept is introduced in the application, and the congestion problem can be conveniently described under the mesh concept.
After the concept of the grid is provided, the pin number, the macro module number and the line network number can be processed into the feature vectors of different sub-grids, and the sum of the feature vectors of all sub-grids under a chip to be predicted forms the feature vector of the chip to be predicted.
Fig. 4 is a schematic diagram of a sub-grid of a chip to be predicted according to an embodiment of the present application, and as shown in fig. 4, an area formed by a solid line part is the whole chip to be predicted, and a small rectangle formed by each dotted line is each sub-grid.
In an embodiment of the present application, in order to ensure that an integer number of sub-grids are obtained, in the embodiment of the present application, before performing grid division on a chip to be predicted, the method further includes: determining whether the area of a chip to be predicted is an integral multiple of the area of a preset grid or not; if yes, the chip to be predicted can be directly segmented, and a plurality of sub-grids corresponding to the chip to be predicted are obtained.
If not, the result shows that the integral number of sub-grids cannot be obtained when the area of the current chip to be predicted is divided according to the area of the preset grid.
At this time, the width value of the first supplementary grid frame can be determined according to the area of the preset grid and the area of the chip to be predicted; in one embodiment of the present application, the width of the first supplemental mesh bezel may be, for example: the supplemented area of the chip to be predicted is the minimum width of integral multiple of the area of the preset grid; it should be understood that the foregoing embodiments are merely exemplary, and the setting of the width of the specific first supplemental grid frame may be flexibly adjusted according to the needs of the user, and is not limited to the foregoing embodiments.
Supplementing a first supplementary grid frame outside the boundary of the chip to be predicted so as to enable the area of the supplemented chip to be predicted to be integral multiple of the size of the preset grid; the first supplementary grid frame is only used for supplementing the area of the chip to be predicted, so that the supplemented area of the chip to be predicted is integral multiple of the preset grid size, and the first supplementary grid frame does not contain any feature vector information, so that the feature vector of the first supplementary grid frame is 0.
In the embodiment of the application, in order to ensure that no artificial boundary is introduced when a chip to be detected is segmented, in the segmentation process, the size of each segmentation grid is not the preset grid size, but the segmentation grid size is determined according to the preset grid size and a first preset constant value; and then, carrying out mesh division on the chip to be predicted according to the size of the division mesh.
In the segmentation process, although the chip to be predicted is segmented by the size of the segmented mesh, the segmentation result, that is, the size of each sub-mesh is the preset mesh size, and the manner of determining each sub-mesh may be, for example, after the chip to be predicted is segmented by the size of the segmented mesh, each mesh obtained by the segmentation may be restored according to a first preset constant value, and each restored sub-mesh is determined to be a sub-mesh corresponding to the chip to be predicted.
It should be noted that, in order to ensure consistency between the boundary grid on the chip to be predicted and other non-boundary grids, a circle of second supplementary grid frame needs to be added to the periphery of the boundary of the chip to be predicted; for the chip to be predicted with the first supplementary grid frame added, adding a second supplementary grid frame at the periphery of the first supplementary grid frame; for a chip to be predicted without the first supplementary grid, directly adding a second supplementary grid frame at the periphery of the boundary of the chip to be predicted; the feature vector of the second supplementary grid frame is also 0 because the second supplementary grid frame is only used for ensuring the consistency of the boundary grid and other non-boundary grids.
S112: and (5) extracting the features of each sub-grid, and determining the feature vector of each sub-grid.
That is, in the embodiment of the present application, the predicted basic unit is a plurality of sub-grids corresponding to the chip to be predicted, all data of the chip to be predicted need to be processed as feature vectors of each sub-grid, and the prediction result is also directed at the wiring distribution of each grid, and an intersection of the wiring distributions of each sub-grid forms the wiring distribution corresponding to the current chip to be predicted; and the feature vector of each sub-grid forms the feature vector of the chip to be predicted.
In the embodiment of the present application, the statistical manner for the feature vector may be, for example: for the statistics of the number of the pins in each sub-grid, if the central point of the boundary of the pin is determined to be in one sub-grid, the sub-grid is determined to have the pin, namely the number of the pins in the sub-grid is increased by one; the statistics of the number of nets in each sub-grid are by the following rules: recording the area of the boundary of the net as S, and adding 1/S to the net number of all sub-grids covered by the boundary of the net; the boundaries of the macro blocks are designed in advance by a chip designer, and no standard unit can be placed in the area where the macro blocks are located, namely the macro blocks are used for clearing all the feature vectors of the covered sub-grids, and the area where the macro blocks are located represents that the current area is an infeasible area.
Optionally, on the basis of the foregoing embodiment, the embodiment of the present application may further provide a global routing prediction method, and an implementation process of the foregoing method is described as follows with reference to the accompanying drawings. Fig. 5 is a schematic flowchart of a global routing prediction method according to another embodiment of the present application, and as shown in fig. 5, before S101, the method may further include:
s121: and (3) extracting the characteristics of each sample chip in the sample set to be trained, and determining the characteristic vector and the routing track quantity of each sample chip.
The feature vectors of the sample chip include: pin features, macroblock features, and net features.
In the embodiment of the present application, the eigenvector of each sample chip is also determined according to the eigenvector of each sub-grid under each sample chip, and each grid has a 16-dimensional vector, which respectively represents the number of pins, the number of wires, the number of transverse routing tracks, and the number of longitudinal routing tracks that fall within the grid and whose central diameter is 5x, 10x, and 23x grids; it should be understood that the range of the grid is merely an example, and the specific grid range may also be 3x, 6x, 10x or any grid range, and is not limited to the range given in the above embodiments.
After the data is processed, if the sample chip has maxX grids in the transverse direction and maxY grids in the longitudinal direction, the feature vector corresponding to the chip obtained at this time is a tensor with one dimension (16, maxX, maxY); if the intermediate result is directly input into the deep neural network, a huge memory is required to store the intermediate result. In order to reduce the memory requirement and increase the parallelism, the whole tensor can be divided into a small tensor prediction considering the locality and the space invariance of the wiring requirement, namely, the sample chip is divided into a plurality of sub grids for prediction.
The specific prediction method is the same as the above method for predicting the chip to be detected, and the details are not repeated herein.
S122: and analyzing the characteristic vectors of the sample chip by adopting the prediction model to be trained, and determining the corresponding wiring distribution quantity of the sample chip.
In an embodiment of the application, the distribution number of wirings includes a horizontal distribution number and a vertical distribution number, and when the distribution number of wirings corresponding to the sample chip is determined, for example, the distribution number of horizontal wirings and the distribution number of vertical wirings corresponding to the sample chip may be determined first, and the distribution number of horizontal wirings, and the relationship between the distribution number of vertical wirings and the distribution number of vertical wirings, and if a difference between the distribution number of horizontal wirings and the distribution number of horizontal wirings is greater than or equal to a preset threshold, and a difference between the distribution number of vertical wirings and the distribution number of vertical wirings is greater than or equal to a preset threshold, it is determined that the training of the prediction model to be trained is completed.
If the difference between the quantity of the transverse wiring tracks and the distribution quantity of the transverse wirings is smaller than a preset threshold value, or the difference between the quantity of the longitudinal wiring tracks and the distribution quantity of the longitudinal wirings is smaller than a preset threshold value; and if the wiring distribution of the current sample chip is not in accordance with the expectation, continuing to optimize the wiring distribution of the sample chip until the wiring distribution of the sample chip is in accordance with the expectation.
S123: and if the difference value between the quantity of the routing tracks and the distribution quantity of the routing lines is greater than or equal to a preset threshold value, determining that the training of the prediction model to be trained is finished.
By adopting the global wiring prediction method provided by the application, the prediction model is trained through a large number of sample chips, so that when the chip to be predicted is predicted through the trained preset prediction model, the obtained wiring distribution is more consistent with the wiring distribution in the actual chip, the characteristic vectors are thinned to the pin number, the macro module number and the network cable number on each grid through the arrangement of the grids, the wiring on each grid is analyzed by utilizing the characteristic vectors on each grid, and the wiring distribution corresponding to the chip to be predicted is determined according to the wiring distribution predicted by each grid on the chip to be predicted, so that the prediction efficiency is high, and the prediction accuracy is high.
The following explains a global routing prediction apparatus provided in the present application with reference to the drawings, where the global routing prediction apparatus can perform any global routing prediction method in fig. 1 to 5, and specific implementation and beneficial effects of the global routing prediction apparatus refer to the above description, which is not described again below.
Fig. 6 is a schematic structural diagram of a global routing prediction apparatus according to an embodiment of the present application, and as shown in fig. 6, the global routing prediction apparatus includes: a determination module 201 and an analysis module 202, wherein:
the determining module 201 is configured to perform feature extraction on a chip to be predicted, and determine a feature vector of the chip to be predicted; the feature vector of the chip to be predicted comprises: pin number, macro block number, and net number.
The analysis module 202 is configured to analyze the feature vector of the chip to be predicted by using a preset prediction model, and determine the wiring distribution corresponding to the chip to be predicted.
Optionally, on the basis of the foregoing embodiments, the present application may further provide a global routing prediction apparatus, as follows, an implementation process of the apparatus given in fig. 6 is described with reference to the accompanying drawings. Fig. 7 is a schematic structural diagram of a global routing prediction apparatus according to another embodiment of the present application, and as shown in fig. 7, the apparatus further includes: the dividing module 203 is configured to perform mesh division on the chip to be predicted according to a preset mesh size to obtain a plurality of sub-meshes corresponding to the chip to be predicted;
the determining module 201 is configured to perform feature extraction on each sub-grid, and determine a feature vector of each sub-grid; and the feature vector of each sub-grid forms the feature vector of the chip to be predicted.
As shown in fig. 7, the apparatus further includes: a replenishment module 204, wherein:
the determining module 201 is specifically configured to determine whether the area of the chip to be predicted is an integral multiple of the area of a preset grid; if not, determining the width value of a first supplementary grid frame according to the area of the preset grid and the area of the chip to be predicted;
the supplementing module 204 is configured to supplement the first supplemental mesh frame outside the boundary of the chip to be predicted, so that the area of the supplemented chip to be predicted is an integral multiple of the size of the preset mesh; wherein the feature vector of the first supplementary mesh frame is 0.
Optionally, the determining module 201 is specifically configured to determine the size of the segmentation mesh according to the preset mesh size and a first preset constant value;
the dividing module 203 is specifically configured to perform mesh division on the chip to be predicted according to the size of the division mesh.
The supplement module 204 is specifically configured to supplement a second supplement grid frame with a preset width on the outer side of the chip to be predicted; wherein the feature vector of the second supplementary mesh frame is 0.
Optionally, the determining module 201 is specifically configured to perform feature extraction on each sample chip in the sample set to be trained, and determine a feature vector and a trace track quantity of each sample chip; the feature vectors of the sample chip include: pin characteristics, macro module characteristics and wire mesh characteristics; analyzing the characteristic vector of the sample chip by adopting a prediction model to be trained, and determining the distribution quantity of the corresponding wiring of the sample chip; and if the difference value between the track quantity of the routing tracks and the distribution quantity of the routing tracks is greater than or equal to a preset threshold value, determining that the training of the prediction model to be trained is finished.
Optionally, the determining module 201 is specifically configured to determine the distribution number of the horizontal wirings and the distribution number of the vertical wirings corresponding to the sample chip; and if the difference between the transverse wiring track quantity and the transverse wiring distribution quantity is greater than or equal to a preset threshold value, and the difference between the longitudinal wiring track quantity and the longitudinal wiring distribution quantity is greater than or equal to a preset threshold value, determining that the to-be-trained predictive model is trained completely.
The above-mentioned apparatus is used for executing the method provided by the foregoing embodiment, and the implementation principle and technical effect are similar, which are not described herein again.
These above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors, or one or more Field Programmable Gate Arrays (FPGAs), etc. For another example, when one of the above modules is implemented in the form of a Processing element scheduler code, the Processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. As another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
Fig. 8 is a schematic structural diagram of a global wired prediction device according to an embodiment of the present application, where the global wired prediction device may be integrated in a terminal device or a chip of the terminal device.
As shown in fig. 8, the global routing prediction apparatus includes: a processor 501, a bus 502, and a storage medium 503.
The processor 501 is used for storing a program, and the processor 501 calls the program stored in the storage medium 503 to execute the method embodiment corresponding to fig. 1-5. The specific implementation and technical effects are similar, and are not described herein again.
Optionally, the present application further provides a program product, for example, a storage medium, on which a computer program is stored, including a program, which, when executed by a processor, performs the corresponding embodiments of the above method.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer-readable storage medium. The software functional unit is stored in a storage medium and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to perform some steps of the methods according to the embodiments of the present application. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
Claims (9)
1. A method for predicting global routing, the method comprising:
performing feature extraction on a chip to be predicted, and determining a feature vector of the chip to be predicted; the feature vector of the chip to be predicted comprises: the number of pins, the number of macromodules and the number of nets; the number of the pins, the number of the macro modules and the number of the nets are determined based on the boundaries of the pins, the boundaries of the macro modules and the boundaries of the nets;
analyzing the characteristic vector of the chip to be predicted by adopting a preset prediction model, and determining the corresponding wiring distribution of the chip to be predicted;
before the feature extraction is carried out on the chip to be predicted and the feature vector of the chip to be predicted is determined, the method comprises the following steps:
performing feature extraction on each sample chip in a sample set to be trained, and determining a feature vector and a routing track quantity of each sample chip; the feature vectors of the sample chip include: pin characteristics, macro module characteristics and net characteristics;
analyzing the characteristic vector of the sample chip by adopting a prediction model to be trained, and determining the distribution quantity of the corresponding wiring of the sample chip;
and if the difference value between the wiring track quantity and the wiring distribution quantity is greater than or equal to a preset threshold value, determining that the to-be-trained prediction model is trained.
2. The method of claim 1, wherein the performing feature extraction on the chip to be predicted and determining the feature vector of the chip to be predicted comprises:
carrying out grid division on the chip to be predicted according to the size of a preset grid to obtain a plurality of sub-grids corresponding to the chip to be predicted;
extracting features of each sub-grid, and determining a feature vector of each sub-grid; and the feature vector of each sub-grid forms the feature vector of the chip to be predicted.
3. The method of claim 2, wherein before the mesh division is performed on the chip to be predicted according to a preset mesh size to obtain a plurality of sub-meshes corresponding to the chip to be predicted, the method further comprises:
determining whether the area of the chip to be predicted is an integral multiple of the area of a preset grid or not;
if not, determining the width value of a first supplementary grid frame according to the area of the preset grid and the area of the chip to be predicted;
supplementing the first supplementary grid frame outside the boundary of the chip to be predicted so as to enable the area of the supplemented chip to be predicted to be integral multiple of the size of the preset grid; wherein the feature vector of the first supplementary mesh frame is 0.
4. The method of claim 2, wherein the mesh partitioning of the chip to be predicted according to a preset mesh size to obtain a plurality of sub-meshes corresponding to the chip to be predicted comprises:
determining the size of a segmentation grid according to the preset grid size and a first preset constant value;
and carrying out mesh division on the chip to be predicted according to the size of the division mesh.
5. The method of claim 4, wherein before said meshing said chip to be predicted according to said split mesh size, said method further comprises:
supplementing a second supplementary grid frame with a preset width on the outer side of the chip to be predicted; wherein the feature vector of the second supplementary mesh frame is 0.
6. The method of claim 1, wherein the sample chip trace track amount comprises: the transverse routing track quantity and the longitudinal routing track quantity; the determining the number of the corresponding wiring distributions of the sample chip includes:
determining the distribution quantity of transverse wirings and the distribution quantity of longitudinal wirings corresponding to the sample chip;
if the difference between the amount of the routing tracks and the distribution amount of the routing tracks is greater than or equal to a preset threshold, determining that the training of the predictive model to be trained is completed, including:
and if the difference between the transverse wiring track quantity and the transverse wiring distribution quantity is greater than or equal to a preset threshold value, and the difference between the longitudinal wiring track quantity and the longitudinal wiring distribution quantity is greater than or equal to a preset threshold value, determining that the to-be-trained predictive model is trained.
7. An apparatus for predicting global routing, the apparatus comprising: a determination module and an analysis module, wherein:
the determining module is used for extracting the features of the chip to be predicted and determining the feature vector of the chip to be predicted; the feature vector of the chip to be predicted comprises: the number of pins, the number of macromodules and the number of nets; the number of the pins, the number of the macro modules and the number of the nets are determined based on the boundaries of the pins, the boundaries of the macro modules and the boundaries of the nets;
the analysis module is used for analyzing the characteristic vector of the chip to be predicted by adopting a preset prediction model and determining the corresponding wiring distribution of the chip to be predicted;
the determining module is specifically configured to perform feature extraction on each sample chip in a sample set to be trained, and determine a feature vector and a routing track quantity of each sample chip; the feature vectors of the sample chip include: pin characteristics, macro module characteristics and wire mesh characteristics; analyzing the characteristic vector of the sample chip by adopting a to-be-trained prediction model, and determining the distribution quantity of the wiring corresponding to the sample chip; and if the difference value between the wiring track quantity and the wiring distribution quantity is greater than or equal to a preset threshold value, determining that the to-be-trained prediction model is trained.
8. A global routed prediction device, the device comprising: a processor, a storage medium and a bus, the storage medium storing machine-readable instructions executable by the processor, the processor and the storage medium communicating via the bus when the globally wired prediction device is operating, the processor executing the machine-readable instructions to perform the method of any of claims 1-6.
9. A storage medium, characterized in that the storage medium has stored thereon a computer program which, when being executed by a processor, carries out the method according to any one of the preceding claims 1-6.
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