CN115270695B - Splitting verification method for circuit layout, double-pattern photoetching method and storage medium - Google Patents
Splitting verification method for circuit layout, double-pattern photoetching method and storage medium Download PDFInfo
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Abstract
The invention discloses a splitting verification method of a circuit layout, a double-graph photoetching method and a storage medium, wherein the splitting verification method of the circuit layout comprises the following steps: scanning and analyzing the circuit layout to obtain all graphs in the circuit layout and preprocessing; inserting all the preprocessed graphics into a grid to obtain a graphics list containing all the graphics, and storing grid addresses and grid indexes of the graphics in the grid; traversing the graph list, distributing graphs without masks to corresponding masks in the double-layer masks according to mask distribution rules in the traversing process, searching whether the same mask space violations exist among the graphs with the masks distributed according to space rules, and recording two graphs with space violations as a pair of conflict nodes if the same mask space violations exist; the conflict loops for each pair of conflict nodes are looked up and all conflict loops are reported. The invention can provide powerful technical support for optimizing the design of the circuit layout.
Description
Technical Field
The invention relates to the technical field of physical design rule verification (DRC) of integrated circuits, in particular to splitting and verifying a circuit layout for double layout.
Background
Integrated circuits (Integrated Circuits, ICs), the number of transistors that can be accommodated on each chip has grown rapidly from the first few transistors to 570 hundreds of millions of transistors today, with the feature sizes of standard cells in each IC being continuously reduced, and the most advanced technology nodes today having reached below 5nm, since Jack Kilby and Robert Noyce of Texas Instruments (TI) in 1958. But problems are also associated therewith. As new fabrication processes approach physical limits, the fabrication of advanced feature size devices presents increasingly serious difficulties and challenges, even with new processes and new materials.
To meet the demands of smaller feature sizes and ever-increasing performance of chips, a multiple pattern lithography (Multiple Patterning Lithography) process was introduced and is considered a technically feasible advanced process node manufacturing approach at the current manufacturing process level. The process divides the original layout patterns on the same layout into a plurality of groups for exposure, so that the original layout patterns with a relatively close distance are divided into different masks, the spacing between the layout patterns in the same mask is increased, the photoetching interference effect between the adjacent patterns of the mask is reduced, and the density of the layout patterns is further improved. The dual exposure pattern technique (Double Patterning Technology, hereinafter referred to as DPT) is used as the most commonly used photolithography technique in multiple pattern photolithography, and divides the pattern into two groups, uses two mask plates to bear the two groups of pattern, and divides the two exposure to improve the resolution after photolithography. Dual pattern lithography can increase the pattern density by about a factor of two compared to conventional exposure processes.
The biggest challenge of the dual-pattern lithography process is how to divide the pattern, so that the pattern can be distributed on two mask plates with minimum lithography interference. In the process of layout decomposition, there may be an undegraded pattern combination, that is, no matter how the patterns are colored, the colors of all adjacent patterns cannot be different, and such pattern combination is called no-conflict.
Therefore, how to provide a solution capable of finding all the conflict-free solutions in the circuit layout, so that the circuit layout can be improved and the conflict-free solutions can be avoided is a technical problem to be solved in the industry.
Disclosure of Invention
In order to solve the technical problem that the design problem of the circuit layout in the prior art cannot be effectively found, the invention provides a splitting verification method, a double-pattern photoetching method and a storage medium of the circuit layout.
The invention provides a splitting verification method of a circuit layout, which comprises the following steps:
step 1, scanning and analyzing a circuit layout to obtain all graphs in the circuit layout and preprocessing the graphs;
step 2, inserting all the preprocessed graphics into the grid to obtain a graphics list containing all the graphics, and storing grid addresses and grid indexes of the graphics in the grid;
and 4, searching the conflict rings of each pair of conflict nodes, and reporting all the conflict rings.
Further, the step 2 specifically includes:
step 2.1, finding the minimum coverage rectangle of the currently processed graph, and recording the grid address related to the minimum coverage rectangle;
step 2.2, traversing whether the grid rectangle related to each grid address collides with the currently processed graph, and if so, associating the currently processed graph with the corresponding grid address.
Further, the step 3 specifically includes:
step 3.1, traversing the graph list, and if the traversed current graph is not allocated with a mask, allocating the current graph to one layer of mask in the double layers of masks;
step 3.2, searching all the comparison patterns which are illegal to the current pattern in terms of the distance rule, if all the comparison pattern lists of the current pattern can be obtained, judging whether the comparison pattern lists have the comparison pattern with the assigned mask and are located on the same mask as the current pattern, recording the current pattern and the comparison pattern as a pair of conflict nodes into the conflict list, and executing the next step; if the current graph does not have the comparison graph list, returning to the previous graph of the current graph, repeating the step 3.2 until the graph in the comparison graph list of the previous graph is traversed, or returning to the step 3.1 until all the graphs in the graph list are allocated with masks, and then executing the step 4;
and 3.3, traversing the comparison graph list, distributing the traversed current comparison graph to another layer of mask in the double masks, enabling the current graph and the comparison graph to be located in different masks, and returning the current comparison graph serving as the current graph to the step 3.2.
Further, the step 4 includes:
finding a distance violation list corresponding to each graph in each pair of conflict nodes according to a distance rule;
performing synchronous traversal on the space violation graphs in the space violation lists of two graphs in a pair of conflict nodes by adopting a depth-first traversal method, and adding the space violation graphs into a conflict ring list of the pair of conflict nodes;
judging whether the currently traversed space violation graph also exists in a space violation list of the other graph in the pair of conflict nodes, and if so, adding the space violation graph into a conflict ring list of the pair of conflict nodes to form a closed loop.
Further, the searching of the conflict ring of the plurality of pairs of conflict nodes in the step 4 is performed in parallel through a plurality of threads.
Further, the preprocessing is to eliminate the overlapping condition between the graphics, and the graphics overlapped with each other are combined into one graphics.
Further, searching all the comparison patterns with the distance violation of the current pattern according to the distance rule is specifically searching all the comparison patterns with the distance violation of the current pattern based on edge amplification.
Before photoetching the circuit layout, the dual graph photoetching method provided by the invention adopts the splitting verification method of the circuit layout to search all conflict rings, improves the design of the circuit layout until the circuit layout has no conflict rings, and then performs photoetching on the circuit board.
The computer readable storage medium is used for storing a computer program, and the computer program executes the splitting verification method of the circuit layout.
The invention stores the patterns through the grid index, the space violation relation among the patterns can only be inquired when the corresponding patterns are processed, and the memory space can be released when the information of the patterns is used up, and the memory space can not be stored all the time, so that compared with the traditional algorithm, a lot of memory space is saved. The method also optimizes the mask distribution flow, distributes the mask while searching the graph, and quickens the solving time; and the mask is distributed in a depth-first mode, so that fewer conflict pairs can be finally obtained compared with the traditional mask distribution in a breadth-first mode, and the solving time of a subsequent conflict searching ring is reduced. Based on grid indexes, after all graph pairs with conflict generated by distributing masks in a layout are found, conflict rings are found for the conflict pair graphs through multithreading. Although the information of each graph interval violation graph is queried again, the conflict graph is not constructed, a large amount of memory space is not needed to store the interval violation relation of the graph, and the solving time can be greatly accelerated through multi-thread parallel acceleration.
Drawings
The invention is described in detail below with reference to examples and figures, wherein:
FIG. 1 is a flow chart of an embodiment of the present invention.
FIG. 2 is a flow chart of a search for a conflict ring in accordance with an embodiment of the present invention.
Fig. 3 is a circuit layout model after preprocessing in accordance with the present invention.
FIG. 4 is a graph comparing differences between edge magnification and vertex magnification.
FIG. 5 is a schematic diagram of a polygon enlargement process according to an embodiment of the invention.
Fig. 6 is a schematic diagram of mesh insertion according to an embodiment of the present invention.
FIG. 7 is a schematic diagram of finding conflicting pairs in accordance with an embodiment of the present invention.
Fig. 8 is a schematic diagram of the node of fig. 7.
FIG. 9 is a diagram of a search for conflict loops according to the present invention.
FIG. 10 is a diagram of two cases of searching for a collision ring according to the present invention.
FIG. 11 is a three-dimensional view of the search for collision rings according to the present invention.
FIG. 12 is a schematic diagram of reporting all violations in accordance with an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Thus, reference throughout this specification to one feature will be used in order to describe one embodiment of the invention, not to imply that each embodiment of the invention must be in the proper motion. Furthermore, it should be noted that the present specification describes a number of features. Although certain features may be combined together to illustrate a possible system design, such features may be used in other combinations not explicitly described. Thus, unless otherwise indicated, the illustrated combinations are not intended to be limiting.
As the most complex and critical process in integrated circuit manufacture, large-scale integrated circuits often require tens of times of photolithography to complete the complete transfer of each layer of patterns; and the mask plate required by photoetching is not separated from layout decomposition, so that the layout decomposition is rapid and high-quality, and becomes a key factor affecting the performance, the yield and the reliability of the integrated circuit. Therefore, layout decomposition has important significance and application value, and can bring great gain to the aspect of integrated circuit manufacturability design. The effectiveness and the speed of the method can improve the reliability of manufacturing chips for the large-scale production of integrated circuits, improve the yield of the chips, promote the economic benefit of enterprises and the conservation of social resources, and research more efficient algorithms becomes necessary. The final objective of the invention is to reduce the generation of conflict-free solution as much as possible while realizing rapid double graph division through an algorithm. The method for splitting and verifying the circuit layout can be used for carrying out quick double graph division on the circuit layout, finding all the conflict-free areas at the same time, then, the conflict-free areas found according to the method can be used for improving the design of the circuit layout, and therefore, the quick double graph division can be realized and the conflict-free areas can be reduced.
As shown in FIG. 1, in the method, all patterns of an original layout are transmitted into a grid based on a grid index structure and a pattern allocation mask algorithm which are studied by oneself, a mask is allocated to the patterns based on a grid index, conflicts are found, and then all violations are reported according to the conflicts.
The DPT requires splitting the graph with the space smaller than the minimum process size in the original layout on two layers of different masks to finish photoetching. In this process, violations from graphic itself to graphic itself are not considered. The invention uses the studied simple graph in graph theory to represent the related situation of the layout, the simple graph refers to the studied simple graph in the "four-color guess" calibration, namely, the graph has no ring and no heavy edge, wherein the ring refers to the edge in the node graph forming one ring, the initial node graph and the end node graph are the same node, and the ring is equivalent to the graph with the self distance less than X min ，X min For minimum process size, heavy sides refer to the fact that the sides existing between the patterns of the same two nodes are not unique, i.e. the spacing between the positions of the patterns is smaller than X min . In the simple graph, one node can be used for representing the corresponding graph in the layout, and the edge between the nodes represents that the distance between the two corresponding graphs in the layout is smaller than X min 。
The splitting verification method of the circuit layout of the invention firstly scans and analyzes the circuit layout to obtain all patterns in the circuit layout, for example, the circuit layout on one mask shown on the left side of the scanning and analyzing figure 3 can obtain 8 different rectangular patterns.
After all the patterns in the circuit layout are scanned, the patterns need to be preprocessed. The preprocessing of the graphics mainly eliminates the overlapping situation between the graphics. For example, since the three rectangles at the top in fig. 3 overlap each other, it is necessary to merge these three patterns into one pattern, and the three rectangles at the bottom right in fig. 3 overlap each other.
After the pretreatment, the original 8 patterns are changed into 5 patterns, as shown in fig. 3.
In some circuit layouts, such as the circuit layout on another mask (also referred to as a reticle) shown on the right side of fig. 3, there may be no overlapping between patterns, so that no duplication elimination is required during preprocessing.
In one embodiment, searching for all of the contrast patterns that violate the pitch of the current pattern according to the pitch rule is specifically searching for all of the contrast patterns that violate the pitch of the current pattern based on edge magnification. Fig. 4 shows the difference between the dot magnification and the side magnification. Placing the polygon pattern into a rectangular area, decomposing the pattern horizontally or vertically, decomposing the pattern into trapezium or rectangle, amplifying all the decomposed patterns, and merging the amplified patterns with overlapping patterns, as shown in fig. 5.
Inserting all the preprocessed graphics into the grid to obtain a graphics list containing all the graphics, and storing grid addresses and grid indexes of the graphics in the grid, wherein no overlapping phenomenon exists among the graphics.
The key of the algorithm provided by the invention is a constructed grid index structure, and each grid index is used for storing information based on a long one-dimensional array, because a computer can read data close to a storage position with a higher probability in reading the data, and the one-dimensional array is adopted, so that the data reading speed is higher. Assuming that the abscissa of the grid is X and the ordinate is Y, the size of a dimension array is x×y, the member type of the one-dimensional array is a graph chain table, in one embodiment, the graph chain table is specifically a chained graph node, if no graph exists in the corresponding grid, the object in the graph chain table is empty, if one or more graphs exist in the corresponding grid, each graph is a graph node (also called a node), the graph chain table links the nodes through lines, the one-dimensional array is segmented, and the starting position of each data block of the one-dimensional array stores the ending address of the data block, so that the one-dimensional array is converted into two dimensions, and the designated index position of the array, namely the designated grid position, can be reached quickly. In specific implementation, the size of the application X is applied, the member type is an array B of pointers, and the pointers of the B [ i ] are addresses of the A [ i ] and the Y [ i ], so that a two-dimensional array B is constructed, and the one-dimensional array A is converted into the two-dimensional array B. Through the abscissa, B [ i ] [ j ] can be directly bound and quickly positioned to the grid cell at the position A [ i ] [ Y ] +j ]. In addition, each grid has graphic information stored in a single linked list at the grid location, and a grid may have some or all of the plurality of graphics, but is stored in the grid whenever it is encountered. As shown in FIG. 6, grid B [1] [1] stores a linked list of graphics { A, B, C }, where A, B, C are unique identifications of graphics, i.e., graphics objects. In addition, each grid has a single linked list of graphics information stored at the location of the grid, for example, there may be some or all of a plurality of graphics in one grid, and then the single linked list of the grid stores the graphics information, which is specifically a unique identification of the graphics.
Inserting the graph into the grid to construct a grid index, namely finding the minimum coverage rectangle of the graph currently processed, recording the grid address related to the minimum coverage rectangle, wherein the grid address range related to the trapezoid B is (X (1-5), Y (1-3)), and is also called as a grid point coordinate range, as shown in fig. 6. And obtaining a grid rectangular area according to the grid point coordinates and the length and width of the grid for each grid. Traversing whether the grid rectangle related to each grid address collides with the currently processed graph, if so, associating the currently processed graph with the corresponding grid address, for example, the grid rectangle of the grid address (2, 1) collides with the image B, and then the grid linked list corresponding to the grid address (2, 1) needs to store the image information of the image B, for example, the grid rectangle of the grid address (5, 3) does not collide with the image B, although the grid address (5, 3) is also recorded in the minimum coverage rectangle of the image B, and by this step, finding that the grid (5, 3) does not collide with the image B, therefore, the grid linked list of the grid (5, 3) does not need to store the image information of the image B.
Traversing the graph list by adopting a depth-first traversing algorithm, distributing graphs without distributed masks to corresponding masks in the double-layer masks according to mask distribution rules in the traversing process, searching whether the same mask interval violation exists between the graphs with distributed masks according to interval rules, recording two graphs with interval violations as a pair of conflict nodes if the same mask interval violations exist, searching conflict rings of each pair of conflict nodes, and reporting all conflict rings. After all the graphics are processed and the grids are inserted, a graphics list containing all the graphics is obtained, the graphics list is traversed, the traversed graphics can be processed only under the condition that no mask is allocated, and for the graphics in the list, the first layer of the two layers of masks is allocated by default. For the pattern currently allocated with a mask, all patterns having a pitch violation with the pattern are searched for according to a regular pitch expansion, and since the pattern may not be a rectangle but a polygon, the method used in the present invention is based on edge magnification instead of dot magnification for the expansion of the polygon, as shown in fig. 4.
Specific mask allocation rules are described below.
Step 3.1, traversing the graph list, and if the traversed current graph is not allocated with a mask, allocating the current graph to one layer of mask in the double layers of masks;
step 3.2, searching all the comparison patterns which are illegal to the current pattern in terms of the distance rule, if all the comparison pattern lists of the current pattern can be obtained, judging whether the comparison pattern lists have the comparison pattern with the assigned mask and are located on the same mask as the current pattern, recording the current pattern and the comparison pattern as a pair of conflict nodes into the conflict list, and executing the next step; if the current graph does not have the comparison graph list, returning to the previous graph of the current graph, repeating the step 3.2 until the graph in the comparison graph list of the previous graph is traversed, or returning to the step 3.1 until all the graphs in the graph list are allocated with masks, and then executing the step of searching for the conflict ring.
And 3.3, traversing the comparison graph list, distributing the traversed current comparison graph to another layer of mask in the double masks, enabling the current graph and the comparison graph to be located in different masks, and returning the current comparison graph serving as the current graph to the step 3.2.
In step 3.2, when step 3.2 is repeated, when the number of stages in which the images are located is returned to step 3.1, assuming that the images traversed according to the image list are called first-stage nodes, traversing the comparison image list of the first-stage nodes according to a depth-first algorithm, traversing the comparison image list of the second-stage nodes possibly also including the comparison image list, and when the comparison image list of the third-stage nodes is traversed, namely traversing the fourth-stage nodes, if the fourth-stage nodes do not include the comparison image list, namely when a certain node does not include the fifth-stage nodes, then returning to step 3.2, and further traversing the next fourth-stage nodes until the fourth-stage nodes are all traversed, returning to the third-stage nodes, continuing traversing the third-stage nodes, and so on, if returning to the first-stage nodes, returning to step 3.1, and continuing traversing the images in the list.
In the above-described returning process, if there is a contrast pattern (node) of the assigned mask in the contrast image list of any level node, and the contrast pattern is on the same mask as the pattern corresponding to that level node, they are recorded as a pair of conflicting nodes into the conflicting list.
In the above-mentioned mask distribution process, because this patent is the algorithm of actually distributing the mask, not directly distribute to the mask material object, therefore in the above-mentioned algorithm process, use and label different colors for the figure to distinguish and distribute to that mask specifically.
And marking the graph after processing, expanding the graph, and filtering the marked graph when inquiring the illegal graph, so as to avoid the situation that A- > B is processed and B- > A is processed. The final result after mask allocation is shown in fig. 7. The flow is represented by a node diagram as shown in fig. 8.
The specific procedure for finding the collision ring is described below.
As shown in fig. 2, a distance violation list corresponding to each graph in each pair of conflict nodes is found according to a distance rule, a depth-first traversal method is adopted to synchronously traverse distance violation graphs in the distance violation lists of two graphs in a pair of conflict nodes, the distance violation graphs are added into the conflict ring lists of the pair of conflict nodes, whether the currently traversed distance violation graph also exists in the distance violation list of the other graph in the pair of conflict nodes is judged, and if so, the distance violation graph is added into the conflict ring lists of the pair of conflict nodes. The invention can adopt a multithreading mode to search conflict rings in parallel for conflict pairs, and to amplify the distance rule value for the graph edges in the conflict pairs, namely, translating the graph edges by Xmin value according to the normal direction, inquiring based on grid indexes to obtain a distance violation graph list of two graphs, traversing the two lists to judge whether a caused graph exists, if so, indicating that a conflict ring is found, and storing the conflict ring. If it is not a consistent pattern, then it is used as the starting point for the next round of search and ends when the following conditions are found: exceeding the maximum search depth; the space violation list of any graph is empty; the two patterns are identical.
In one embodiment, a list is created that stores graphics on the odd ring, the search maximum layer depth is set, and searching for the odd ring beyond this layer depth is no longer performed. Adding the two graphs into the list, expanding the conflict pair two graphs according to the regular interval to obtain respective interval violation lists, judging all graphs of the two lists, judging whether the two lists have one-cause graphs, if so, indicating that an odd ring is found, as shown in fig. 9; adding the corresponding graph into a list storing odd rings, adding the odd rings into an array storing the odd rings, deleting the graph from the list storing the odd rings, continuously traversing the interval violation list of the two graphs, and checking whether other odd rings exist. Setting all the graphs checked in the flow to be accessed, avoiding repeated access, adopting a depth-first search method, selecting one graph for each graph in the two-interval violation list, judging whether other conflict pairs exist or not, and if so, not processing the graphs as shown in fig. 10; the two patterns are taken as new conflict pairs, the layer depth is reduced by one, and the process is repeated to find consistent patterns, as shown in fig. 11; after the search flow is finished, all the graphs are set to be unviewed, so that other conflict pairs are prevented from being influenced.
All violations are eventually reported as shown in fig. 12.
The invention also protects a double graph photoetching method, which searches all conflict rings by adopting the splitting verification method of the circuit layout of the technical scheme before photoetching the circuit layout, improves the design of the circuit layout until the circuit layout does not have the conflict rings, and then performs photoetching on the circuit board.
The invention also protects a computer readable storage medium for storing a computer program which when run performs the method for splitting and verifying the circuit layout of the technical scheme.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (7)
1. The method for splitting and verifying the circuit layout is characterized by comprising the following steps of:
step 1, scanning and analyzing a circuit layout to obtain all graphs in the circuit layout and preprocessing, wherein the preprocessing is to eliminate the overlapping condition between the graphs, and merging the mutually overlapped graphs into one graph;
step 2, inserting all the preprocessed graphics into the grid to obtain a graphics list containing all the graphics, and storing grid addresses and grid indexes of the graphics in the grid, wherein the step comprises the following steps:
step 2.1, finding the minimum coverage rectangle of the currently processed graph, and recording the grid address related to the minimum coverage rectangle;
step 2.2, traversing whether the grid rectangle related to each grid address collides with the currently processed graph, and if so, associating the currently processed graph with the corresponding grid address;
step 3, traversing the graph list by adopting a depth-first traversing algorithm, distributing graphs without distributing masks to corresponding masks in the double-layer masks according to mask distribution rules in the traversing process, searching whether the same mask space violation exists between the graphs distributed with the masks according to space rules, and recording two graphs with space violations as a pair of conflict nodes if the same mask space violations exist;
and 4, searching the conflict rings of each pair of conflict nodes, and reporting all the conflict rings.
2. The method for splitting and verifying a circuit layout according to claim 1, wherein the step 3 specifically comprises:
step 3.1, traversing the graph list, and if the traversed current graph is not allocated with a mask, allocating the current graph to one layer of mask in the double layers of masks;
step 3.2, searching all the comparison patterns which are illegal to the current pattern in terms of the distance rule, if all the comparison pattern lists of the current pattern can be obtained, judging whether the comparison pattern lists have the comparison pattern with the assigned mask and are located on the same mask as the current pattern, recording the current pattern and the comparison pattern as a pair of conflict nodes into the conflict list, and executing the next step; if the current graph does not have the comparison graph list, returning to the previous graph of the current graph, repeating the step 3.2 until the graph in the comparison graph list of the previous graph is traversed, or returning to the step 3.1 until all the graphs in the graph list are allocated with masks, and then executing the step 4;
and 3.3, traversing the comparison graph list, distributing the traversed current comparison graph to another layer of mask in the double masks, enabling the current graph and the comparison graph to be located in different masks, and returning the current comparison graph serving as the current graph to the step 3.2.
3. The method for splitting and verifying a circuit layout according to claim 1, wherein the step 4 comprises:
finding a distance violation list corresponding to each graph in each pair of conflict nodes according to a distance rule;
performing synchronous traversal on the space violation graphs in the space violation lists of two graphs in a pair of conflict nodes by adopting a depth-first traversal method, and adding the space violation graphs into a conflict ring list of the pair of conflict nodes;
judging whether the currently traversed space violation graph also exists in a space violation list of the other graph in the pair of conflict nodes, and if so, adding the space violation graph into a conflict ring list of the pair of conflict nodes to form a closed loop.
4. The method for splitting and verifying a circuit layout according to claim 1, wherein the searching of the conflict ring of the plurality of pairs of conflict nodes in the step 4 is performed in parallel by a plurality of threads.
5. The method for split verification of a circuit layout according to claim 2, wherein searching for all of the contrast patterns with pitch violations of the current pattern according to the pitch rule is specifically searching for all of the contrast patterns with pitch violations of the current pattern based on edge magnification.
6. A dual pattern lithography method, characterized in that, before performing lithography on a circuit layout, a split verification method of the circuit layout according to any one of claims 1 to 5 is used to find all conflict rings, and the design of the circuit layout is improved until the circuit layout has no conflict rings, and then the lithography is performed on the circuit board.
7. A computer readable storage medium storing a computer program, wherein the computer program when run performs a method of split verification of a circuit layout according to any one of claims 1 to 5.
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| Title |
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| 一种新型双重图形技术拆分方法;于丽贤;粟雅娟;韦亚一;;微纳电子技术(第04期);全文 * |
| 光学邻近效应矫正(OPC)技术及其应用;蔡懿慈;周强;洪先龙;石蕊;王旸;;中国科学(E辑:信息科学)(第12期);全文 * |
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