CN115270668B - Special chip of information technology education open source hardware - Google Patents
Special chip of information technology education open source hardware Download PDFInfo
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- CN115270668B CN115270668B CN202210838402.3A CN202210838402A CN115270668B CN 115270668 B CN115270668 B CN 115270668B CN 202210838402 A CN202210838402 A CN 202210838402A CN 115270668 B CN115270668 B CN 115270668B
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Abstract
The invention discloses an information technology education open source hardware special chip, which comprises a symmetric multi-core CPU based on RISC-V, an artificial intelligent acceleration unit, a multimedia unit, a communication unit and a peripheral interface unit, wherein the artificial intelligent acceleration unit, the multimedia unit, the communication unit and the peripheral interface unit are all connected with the symmetric multi-core CPU. The special chip for the information technology education open source hardware adopts the structure, the symmetrical multi-core CPU is designed based on a RISC-V open source instruction system, ARM authorization is not needed, the intelligent education experiment is provided, multiple interfaces are arranged, and complex experiments can be supported and operated.
Description
Technical Field
The invention relates to the technical field of chip design, in particular to a special chip for open source hardware for information technology education.
Background
The main problems faced by the current open source hardware chip for information technology education are as follows:
the teacher needs to additionally carry a plurality of peripheral experiment accessory modules around the existing board card according to the actual teaching experiment requirement. For some SoC chips, there is only one USB interface, and if a chip with a USB interface is required, serial port to USB conversion is required. In terms of display interfaces, some chips have no special MIPI display screen interface, and can only be connected with a parallel interface screen according to chip resources, so that excessive chip pin resources are occupied. If a plurality of I2C, SPI, UART peripheral sensors are connected, a plurality of chips do not have a plurality of interface resources, and a plurality of external sensor modules cannot be connected at the same time, so that experiments of parallel modules cannot be performed. The rising of artificial intelligence education brings about the influence that a chip of open source hardware lacks a complex machine learning and deep learning algorithm hardware acceleration unit, so that teaching tools have to calculate by means of a cloud or PC (personal computer) end, and the inconvenience of education is brought.
In artificial intelligence education, the chip needs convolutional neural network hardware acceleration, and the chip of Broadcom Botong company of the current popular open source hardware raspberry group, the chip of Nordic company of Microbit and the ESP32 series of Shanghai Le Xin company are all chips with popular open source hardware. However, the system has no artificial intelligence acceleration function, and can not run complex visual algorithms for artificial intelligence education.
Disclosure of Invention
The invention aims to provide an information technology education open source hardware special chip, which is used for designing a symmetrical multi-core CPU based on a RISC-V open source instruction system, does not need ARM authorization, is not limited, has an artificial intelligence algorithm acceleration function, provides artificial intelligence education experiments separated from a cloud, is provided with various interfaces, and can support and run complex experiments.
In order to achieve the above purpose, the invention provides a special chip for open source hardware for information technology education, which comprises a symmetric multi-core CPU based on RISC-V, an artificial intelligent acceleration unit, a multimedia unit, a communication unit and a peripheral interface unit, wherein the artificial intelligent acceleration unit, the multimedia unit, the communication unit and the peripheral interface unit are all connected with the symmetric multi-core CPU.
Preferably, the communication unit comprises a WiFi module and a Bluetooth module, and the WiFi module and the Bluetooth module are connected with the symmetrical multi-core CPU.
Preferably, the peripheral interface unit includes a USB interface, a UART interface, an SPI bus interface, an I2C bus interface, a PWM pulse width modulation signal interface, and an MIPI high-speed input/output interface, and at least one of the USB interface, the UART interface, the SPI bus interface, the I2C bus interface, the PWM pulse width modulation signal interface, and the MIPI high-speed input/output interface is provided.
Preferably, the multimedia unit includes a display interface, a camera interface, an audio processing interface, and a SHA256 computing module.
Preferably, the symmetric multi-core CPU comprises 4 RISC-V cores, RAM for temporary storage of boot code, and ROM for storing boot code and configuration code.
Preferably, the artificial intelligence acceleration unit comprises an NPU processor, an ITCM and a DTCM, and is used for executing a deep learning algorithm, performing natural language processing when finishing an image, wherein the ITCM and the DTCM are connected with a RISC-V core through an AHB bus, the AHB bus is connected with an APB switching bridge, peripheral interface units, communication units and multimedia units are all connected with the APB bus, the APB bus is connected with the APB switching bridge, and the communication units are connected with the APB bus through SDIO interfaces.
Preferably, a debug interface is also provided.
Therefore, the special chip for the open source hardware for the information technology education, which adopts the structure, has the following beneficial effects:
(1) The symmetric multi-core CPU is designed based on a RISC-V open source instruction system, ARM authorization is not needed, and the method is not limited.
(2) The artificial intelligence convolutional neural network algorithm acceleration function is provided, and an artificial intelligence education experiment separated from the cloud is provided.
(3) The peripheral interface unit comprises a USB interface, a UART interface, an SPI bus interface, an I2C bus interface, a PWM pulse width modulation signal interface and an MIPI high-speed input/output interface, and the multimedia unit comprises a display interface, a camera interface, an audio processing interface and an SHA256 computing module, is provided with various interfaces, and can support and run complex experiments.
(4) The communication unit comprises a WiFi module and a Bluetooth module, and different communication modules are selected according to actual conditions.
The technical scheme of the invention is further described in detail through the drawings and the embodiments.
Drawings
FIG. 1 is a schematic diagram of a special chip for open source hardware for information technology education;
fig. 2 is a diagram of internal connection of a chip dedicated to open source hardware for information technology education according to the present invention.
Detailed Description
Examples
Fig. 1 is a schematic structural diagram of an information technology education open source hardware special chip of the present invention, and fig. 2 is an internal connection diagram of an information technology education open source hardware special chip of the present invention, as shown in the figure, the information technology education open source hardware special chip comprises a symmetric multi-core CPU based on RISC-V, an artificial intelligence accelerating unit, a multimedia unit, a communication unit and a peripheral interface unit, wherein the artificial accelerating unit, the multimedia unit, the communication unit and the peripheral interface unit are all connected with the symmetric multi-core CPU.
The communication unit comprises a WiFi module and a Bluetooth module, wherein the WiFi module and the Bluetooth module are connected with the symmetrical multi-core CPU, and provide high-speed WiFi network access and Bluetooth communication functions for the chip. By utilizing the quick connection characteristic of the WIFI technology, the WIFI technology can be configured into a TCP or UDP server or a client through software, and when in use, a user can build a local web server by utilizing the WIFI unit, so that a network programming learning target is completed; bluetooth units can use their low power and fast connection characteristics for connecting to other peripherals, transmitting or receiving data when in use.
The peripheral interface unit comprises a USB interface, a UART interface, an SPI bus interface, an I2C bus interface, a PWM pulse width modulation signal interface and an MIPI high-speed input/output interface, wherein at least one of the USB interface, the UART interface, the SPI bus interface, the I2C bus interface, the PWM pulse width modulation signal interface and the MIPI high-speed input/output interface is arranged, so that the requirements of customer creating education, robot education, scientific education, programming education and artificial intelligence education are met by the functions of the chip, a plurality of interfaces are arranged, and complex experiments can be supported and operated. According to the actual functional scene, SPI bus interface, I2C and I2S bus interface, UART universal asynchronous receiving and transmitting interface can be used. In addition, with a PWM pulse width modulation controller, a user can control speed of an electric motor, an LED, or the like using an IO interface supporting pulse width modulation.
The multimedia unit includes a display interface, a camera interface, an audio processing interface, and a SHA256 computing module. When in use, the display interface can be connected with a display screen, so that a system GUI is displayed; the audio processing interface can be connected with audio output equipment to play media sound; the camera can be connected with a high-resolution camera for acquiring image information.
The symmetrical multi-core CPU comprises 4 RISC-V cores, RAM and ROM, wherein the RAM is used for temporary storage of starting codes, the ROM is used for storing the starting codes and configuration codes, a central processing unit based on RISC-V (open source reduced instruction set architecture) architecture provides 64-bit data processing and computing power, and each core provides a floating point type data processing unit which can assist the central processing unit to process image data.
The artificial intelligent acceleration unit comprises an NPU processor, an ITCM and a DTCM, and is used for executing a deep learning algorithm, processing image data and the deep learning algorithm at a high speed which cannot be achieved by the symmetrical multi-core CPU when the image and the natural language are processed, executing the deep learning algorithm when the image and the natural language are used, and completing image recognition and natural language processing, so that an AI processing scene can be completed at a high speed and high efficiency. The ITCM and the DTCM are connected with the RISC-V core through an AHB bus, the AHB bus is connected with an APB switching bridge, the peripheral interface unit, the communication unit and the multimedia unit are all connected with the APB bus, the APB bus is connected with the APB switching bridge, and the communication unit is connected with the APB bus through an SDIO interface.
The artificial intelligence acceleration unit is used for realizing hardware acceleration of the deep learning algorithm. At present, the artificial intelligence education experiment which can be landed mainly comprises visual image processing and natural language processing. If the automatic navigation trolley with the SLAM function based on image processing is operated, a programming robot and the like which can perform offline processing on a point cloud image can be identified, and the information education equipment uses machine learning algorithms, especially deep learning algorithms, so that an ideal special chip for information technology education has the function of a general embedded processor and also has an artificial intelligent acceleration function so as to be convenient for directly operating a deep learning algorithm model at the chip end and the edge end. The chip realizes Tensor by VHDL language based on an open source instruction set based on RISC-V. Hardware implementation based on Tensor is separated from coprocessors such as GPU, DSP and the like, and a framework of a convolution network of TensorFlow, caffe, pytorch can be operated at a chip end.
The chip is also provided with a debugging interface for developing and debugging the chip, and can be matched with external software to configure a chip starting mode or inject codes and the like.
Therefore, the invention adopts the special chip for the information technology education open source hardware with the structure, designs the symmetrical multi-core CPU based on the RISC-V open source instruction system, does not need ARM authorization, is not limited, has the acceleration function of an artificial intelligent algorithm, provides the artificial intelligent education experiment separated from the cloud, is provided with various interfaces, and can support and operate complex experiments.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention and not for limiting it, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that: the technical scheme of the invention can be modified or replaced by the same, and the modified technical scheme cannot deviate from the spirit and scope of the technical scheme of the invention.
Claims (4)
1. A special chip of information technology education open source hardware, its characterized in that: the system comprises a symmetric multi-core CPU based on RISC-V, an artificial intelligent acceleration unit, a multimedia unit, a communication unit and a peripheral interface unit, wherein the artificial intelligent acceleration unit, the multimedia unit, the communication unit and the peripheral interface unit are all connected with the symmetric multi-core CPU; the symmetrical multi-core CPU comprises 4 RISC-V cores, a RAM and a ROM, wherein the RAM is used for temporarily storing starting codes, and the ROM is used for storing the starting codes and configuration codes;
the multimedia unit comprises a display interface, a camera interface, an audio processing interface and an SHA256 computing module;
the communication unit comprises a WiFi module and a Bluetooth module, and the WiFi module and the Bluetooth module are connected with the symmetrical multi-core CPU;
the artificial intelligent acceleration unit comprises an NPU processor, an ITCM and a DTCM, wherein the ITCM and the DTCM are connected with a RISC-V core through an AHB bus when an image is completed and natural language processing is performed, the AHB bus is connected with an APB switching bridge, peripheral interface units, communication units and multimedia units are all connected with the APB bus, the APB bus is connected with the APB switching bridge, and the communication units are connected with the APB bus through an SDIO interface.
2. The information technology education open source hardware dedicated chip according to claim 1, wherein: the peripheral interface unit comprises a USB interface, a UART interface, an SPI bus interface, an I2C bus interface, a PWM pulse width modulation signal interface and an MIPI high-speed input/output interface, wherein at least one of the USB interface, the UART interface, the SPI bus interface, the I2C bus interface, the PWM pulse width modulation signal interface and the MIPI high-speed input/output interface is arranged.
3. The information technology education open source hardware dedicated chip according to claim 1, wherein: a debug interface is also provided.
4. The information technology education open source hardware dedicated chip according to claim 1, wherein: on the basis of a symmetric multi-core CPU open source instruction set based on RISC-V, a VHDL language is used for realizing a Tensor and running a frame of a TensorFlow, caffe, pytorch convolution network.
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