CN113760816A - RISC-VCPU and AI core heterogeneous communication system and design method - Google Patents
RISC-VCPU and AI core heterogeneous communication system and design method Download PDFInfo
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Abstract
The invention discloses a RISC-VCPU and AI core heterogeneous communication system and a design method, comprising a RISC-V CPU, an AI core, an AI expansion module, an MEM module, a first bus and a second bus; the RISC-V CPU, the AI core and the MEM module are all in communication connection with a first bus, the AI expansion module is arranged in the RISC-V CPU, and the AI expansion module is in communication connection with the AI core through a second bus. The invention utilizes the open source characteristic of RISC-V to customize AI extension instruction, reduces time delay and improves the real-time of the system.
Description
Technical Field
The invention relates to the technical field of heterogeneous communication design, in particular to a RISC-V CPU and AI core heterogeneous communication system and a design method.
Background
At present, a multi-core heterogeneous architecture becomes a typical technical route of an artificial intelligence chip, and because the application generally comprises a data stream processing task with heavy calculation load, the task is expressed as channel filtering, channel estimation, modulation and demodulation and the like of a digital baseband in a communication SoC, and the task is expressed as filtering smoothing, conversion, feature extraction and the like of an image in a machine vision processor, a special artificial intelligence acceleration core can be integrated in design, and various artificial intelligence algorithms are completed.
The instruction sets of ARM, MIPS and the like belong to business cores, instructions are not completely opened, and RISC-V belongs to an open source instruction set, so that a perfect instruction extension method is provided. The design method of heterogeneous communication between the CPU core and the AI core is different, the ARM core and the MIPS core have no open source, the problems of insufficient technical support, inadmissible authorization and the like exist in the instruction expansion, the system architecture has insufficient expandability, and the RISC-V friendly design concept is suitable for the expansion of the system architecture, so that the system efficiency is improved. These are all linked together through the bus, as shown in fig. 1, the communication between the CPU and the AI core needs to be connected through the bus, and the data access is obtained from the MEM and DDR memories through the bus, which increases the data transmission time and reduces the real-time performance of the system.
Disclosure of Invention
The invention aims to provide a RISC-VCPU and AI core heterogeneous communication system and a design method thereof, which are used for overcoming the defects of the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
RISC-VCPU and AI core heterogeneous communication system, including RISC-V CPU, AI core, AI expansion module, MEM module, first bus and second bus;
the RISC-V CPU, the AI core and the MEM module are all in communication connection with a first bus, the AI expansion module is arranged in the RISC-V CPU, and the AI expansion module is in communication connection with the AI core through a second bus.
Further, the AI core incorporates a multiplication unit, an addition unit, a division unit, and an FFT unit.
Further, the MEM module is a DDR module, an SDRAM module, or a FLASH module.
Further, the first bus is an AMBA bus.
Further, the second bus is an LB bus.
The RISC-VCPU and AI core heterogeneous communication design method comprises the following steps:
the RISC-V CPU, the AI core and the MEM module are in communication connection with a first bus;
an AI extension module is arranged in the RISC-V CPU and is connected with the AI core through a second bus in a communication way.
Further, the AI core incorporates a multiplication unit, an addition unit, a division unit, and an FFT unit.
Further, the MEM module is a DDR module, an SDRAM module, or a FLASH module.
Further, the first bus is an AMBA bus.
Further, the second bus is an LB bus.
Compared with the prior art, the invention has the following beneficial technical effects:
according to the invention, the AI extension module is arranged in the RISC-V CPU, the AI extension module is in communication connection with the AI core by using the second bus, so that the heterogeneous design of the RISC-V CPU and the AI core is increased, the open source characteristic of the RISC-V is borrowed, the AI extension instruction is customized, and the AI extension instruction is called under a specific electric power service scene, so that the direct interaction of the RISC-V CPU and the AI core is realized, the time delay is reduced, and the real-time performance of the system is improved.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention.
FIG. 1 is a diagram of a conventional CPU and AI core heterogeneous design;
FIG. 2 is a diagram of the RISC-V CPU and AI core heterogeneous communication design of the present invention;
fig. 3 is a structural diagram of the terminal to which the present invention is applied.
Detailed Description
The invention is described in further detail below with reference to the figures and specific examples.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Referring to fig. 2, the RISC-VCPU and AI core heterogeneous communication system includes a RISC-V CPU, an AI core, an AI extension module, a MEM module, a first bus, and a second bus; the RISC-V CPU, the AI core and the MEM module are all in communication connection with a first bus, the DDR module is in communication connection with the MEM module, the AI expansion module is arranged in the RISC-V CPU and is in communication connection with the AI core through a second bus, a multiplication unit, an addition unit, a division unit and an FFT unit are arranged in the AI core, the MEM module is a DDR module, an SDRAM module or a FLASH module, the first bus is an AMBA bus, and the second bus is an LB bus.
The RISC-V CPU of the invention is a CPU based on RISC-V open source instruction set, has very strong instruction expansion ability, RISC-V is regarded as the open source CPU instruction set framework of the world level, adopted the BSD agreement, the requirement of this agreement is very loose, when using RISC-V to make further improvement, there is no authorized restriction, can carry on the arbitrary improvement according to the demand of the design.
The AI kernel of the invention contains logical units of multiplication and addition, and the like, and specifically comprises multiple operators of multiplication, addition, division, FFT and the like, thereby realizing the rapid execution of the AI algorithm and accelerating the operation speed of the artificial intelligence algorithm.
The RISC-V CPU of the invention has two channels, one channel is a customized LB bus, an AI expansion module is arranged in the RISC-V open source instruction expansion mode according to the characteristics of an AI core and the requirements of services, the AI expansion module is used for customizing an AI expansion instruction, the reading bottleneck of an MEM module is bypassed, the improvement of calculation power is realized, the delay of the system is reduced, and the system efficiency is improved. The LB bus realizes the adaptation of the interface and the butt joint of the time sequence according to the architecture of the RISC-V and the architecture of the AI core, and reduces the reading and writing pressure of the RISC-V CPU and the MEM.
The other channel is an AMBA bus, which is a traditional communication mode, data transmission is carried out by utilizing the AMBA bus, and the interaction between the RISC-V CPU and the AI core is realized by sharing and processing data in the MEM module through the AMBA bus. RISC-V CPU reads the instruction in MEM module, realize the operation of the business program; the AI core realizes the storage of various artificial intelligence parameters through an MEM module. And when the service scene requires low time delay, the LB bus is started, the time delay is reduced, the processing speed is increased, and the AMBA bus can be adopted for transmission interaction under the condition of no special requirement.
The RISC-V CPU, the AI core, the AI expansion module and the LB bus form an AI chip together, and in the process of developing national network nationwide production equipment, the AI chip is used for developing various terminals, such as an operation and distribution integrated fusion terminal and a power transmission line intelligent gateway, so that the safety and the processing performance of the equipment are improved.
Referring to fig. 3, the invention can be used in an artificial intelligence chip, in hardware, the RISC-V CPU and the AI core together form an artificial intelligence chip, and the remote communication unit and the local communication unit adopt a modular design, can be replaced and selected according to requirements, are convenient to replace, and meet the interchangeability requirement; the embedded operating system is adopted, Ubuntulinux is supported, version can be controlled, online upgrading can be achieved, and the operating system supports independent development and operation of upper-layer application APP.
The communication interface between the remote communication unit and the Internet of things management platform comprises:
a 4G module: supporting a full-network communication mode, TDD-LTE, FDD-LTE, and a wireless public network;
and 5G module: the wireless public network supports the whole network communication mode;
private network LTE (optional): support for LTE230, support for LTE 1800;
big dipper (optional): supporting a short message mode;
optical fiber: support kilomega;
ethernet (remote): above 100 Mbps.
The communication interface between the camera and the hardware structure adopts Ethernet (camera): above 100 Mbps.
The communication interface of the maintenance port and the hardware structure adopts RS-232:9600bps-115200 bps.
The communication interface between the local communication unit and the meteorological device adopts RS-485:1200bps-9600 bps; the communication interface between the local communication unit and the sensor (waving, temperature) adopts RS-485:1200bps-9600bps or micropower wireless: based on 433MHz, Lora or ZigBee is adopted; the communication interface between the local communication unit and the inspection terminal adopts WIFI: 2.4GHz wireless; the communication interface between the local communication unit and the video relay adopts a wireless bridge: 5.8 GHz.
The AI chip comprises a RISC-V CPU and an AI core, data acquired by the camera enters the AI chip through an Ethernet port, the light-weight Yolo recognition algorithm is operated, the AI expansion module decomposes the light-weight Yolo recognition algorithm into a plurality of expansion instructions in the process of operating the light-weight Yolo recognition algorithm, the RISC-V CPU transmits the expansion instructions to the AI core through an LB bus, and the AI core operates the expansion instructions to complete the light-weight Yolo recognition algorithm, so that the image processing time can be effectively reduced by about 20%.
The invention realizes the rapid interaction between the RISC-V CPU and the AI core by adding the LB bus between the RISC-V CPU and the AI core and expanding the customized AI instruction, bypasses the data sharing of the MEM module, can rapidly complete the AI task, reduces the time delay of the system and improves the processing efficiency of the chip.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
Finally, it should be noted that: although the present invention has been described in detail with reference to the above embodiments, those skilled in the art will appreciate that various changes, modifications and equivalents can be made in the embodiments of the invention without departing from the scope of the invention as defined by the appended claims.
Claims (10)
- RISC-VCPU and AI core heterogeneous communication system, characterized by, including RISC-V CPU, AI core, AI extension module, MEM module, first bus and second bus;the RISC-V CPU, the AI core and the MEM module are all in communication connection with a first bus, the AI expansion module is arranged in the RISC-V CPU, and the AI expansion module is in communication connection with the AI core through a second bus.
- 2. The RISC-VCPU and AI core heterogeneous communication system of claim 1, wherein the AI core has a multiplication unit, an addition unit, a division unit, and an FFT operation unit built therein.
- 3. The RISC-VCPU and AI core heterogeneous communication system of claim 1, wherein the MEM module is a DDR module, an SDRAM module, or a FLASH module.
- 4. The RISC-VCPU and AI core heterogeneous communication system of claim 1, wherein the first bus is an AMBA bus.
- 5. The RISC-VCPU and AI core heterogeneous communication system of claim 1, wherein the second bus is an LB bus.
- The RISC-VCPU and AI core heterogeneous communication design method is characterized by comprising the following steps:the RISC-V CPU, the AI core and the MEM module are in communication connection with a first bus;an AI extension module is arranged in the RISC-V CPU and is connected with the AI core through a second bus in a communication way.
- 7. The RISC-VCPU and AI core heterogeneous communication design method of claim 6, wherein said AI core has built-in multiply operation unit, add operation unit, divide operation unit and FFT operation unit.
- 8. The RISC-VCPU and AI core heterogeneous communication design method of claim 6, wherein said MEM module is a DDR module, SDRAM module or FLASH module.
- 9. The RISC-VCPU and AI core heterogeneous communication design method of claim 6, wherein the first bus is an AMBA bus.
- 10. The RISC-VCPU and AI core heterogeneous communication design method of claim 6, wherein the second bus is LB bus.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115270668A (en) * | 2022-07-18 | 2022-11-01 | 北京师范大学 | Chip special for open source hardware of information technology education |
| CN115903613A (en) * | 2022-12-15 | 2023-04-04 | 鹏城实验室 | RISC-V core based industrial control and communication chip architecture |
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| CN202975676U (en) * | 2012-12-28 | 2013-06-05 | 中国电子科技集团公司第五十四研究所 | Independent controllable high-performance embedded control platform device |
| CN106843127A (en) * | 2017-02-28 | 2017-06-13 | 深圳市麦格米特控制技术有限公司 | A kind of Medium PLC system |
| CN111209247A (en) * | 2019-12-30 | 2020-05-29 | 西安智多晶微电子有限公司 | Integrated circuit computing device and computing processing system |
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- 2021-09-07 CN CN202111045857.1A patent/CN113760816A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN202975676U (en) * | 2012-12-28 | 2013-06-05 | 中国电子科技集团公司第五十四研究所 | Independent controllable high-performance embedded control platform device |
| CN106843127A (en) * | 2017-02-28 | 2017-06-13 | 深圳市麦格米特控制技术有限公司 | A kind of Medium PLC system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115270668A (en) * | 2022-07-18 | 2022-11-01 | 北京师范大学 | Chip special for open source hardware of information technology education |
| CN115903613A (en) * | 2022-12-15 | 2023-04-04 | 鹏城实验室 | RISC-V core based industrial control and communication chip architecture |
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