CN115268570B - IRIG-B code time setting system - Google Patents
IRIG-B code time setting system Download PDFInfo
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- CN115268570B CN115268570B CN202210935401.0A CN202210935401A CN115268570B CN 115268570 B CN115268570 B CN 115268570B CN 202210935401 A CN202210935401 A CN 202210935401A CN 115268570 B CN115268570 B CN 115268570B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
Abstract
The invention discloses an IRIG-B code time setting system which provides millisecond and/or microsecond time reporting for application. The invention realizes that on the basis of the traditional IRIG-B code time reporting, the fractional dimension local time is generated in a time increment accumulation mode, thereby realizing millisecond and microsecond time reporting.
Description
Technical Field
The invention relates to the technical field of time service, in particular to an IRIG-B code time synchronization system.
Background
The control operations in some systems require clock synchronization, such as monitoring, relay protection, etc. systems in the power industry. The synchronizing clocks in these systems are typically obtained by an IRIG-B code time setting device. The IRIG-B code time setting device generates year, month, day, time, minute and second time information by receiving the Beidou/GPS time service signals. With the progress of the age, some system control has the requirement of finer time granularity time-reporting, and the addition of millisecond and microsecond time-reporting has important practical significance on the basis of the traditional IRIG-B code time-reporting.
Disclosure of Invention
Aiming at the technical problems, the invention provides an IRIG-B code time synchronization system, which adopts the following technical scheme:
an IRIG-B code time setting system provides millisecond and/or microsecond time reporting for an application, and comprises an IRIG-B code decoder, a date and time generator, a control register, time setting driving software, an error generator, an adaptive tracker, a millisecond microsecond generator and an application interface.
Furthermore, the IRIG-B code decoder is used for carrying out window sampling statistics on the input IRIG-B signal, and the window level value is the level with a large accumulated value, so that the filtering shaping of the short-time interference of the signal is realized.
Further, the date and time generator is used for processing leap years and leap seconds, and generating adult, month, day, time, minute and second according to the BCD code.
Further, the error generator is configured to generate an error μ, and calculate the error μ according to (formula-1) at a time when the IRIG-B code decoder outputs an IRIG-B code frame header;
wherein:
mu error
CLK: a working clock other than the time setting driving software;
m: the current value of the millisecond microsecond generator is initially 0;
s: the whole second count value of the millisecond microsecond generator is determined by the CLK frequency and the number of bits of M and is set by the time synchronization driving software.
Further, the adaptive tracker is configured to generate a time increment Z; in closed loop control, calculating according to the formula (2) and the formula (3); during open loop control, the initial value Y of the integral loop is directly output 0 ；
Wherein:
i-proportional integral adjusting integral coefficient, set by time setting driving software;
p-proportional integral adjusting proportional coefficient, set by time setting driving software;
y-proportional integral regulating integral ring current value, initial value Y 0 Setting by time setting driving software;
z-proportional integral adjustment output value, increment per CLK time;
t-time.
Further, the millisecond microsecond generator generates a fractional dimension local time M according to a time increment Z output by the self-adaptive tracker and generates millisecond microsecond according to a BCD code;
wherein MOD is a modulo operation.
Further, the control register stores and outputs control information of the time setting driving software configuration.
Further, the time setting driving software configures and controls the work of each module in the CPLD/FPGA through a local bus, and reads time to a time using system.
Further, the time setting driving software sets leap years and leap seconds control enabling bits in the control register through a local bus.
The invention realizes that on the basis of the traditional IRIG-B code time reporting, the fractional dimension local time is generated in a time increment accumulation mode, thereby realizing millisecond and microsecond time reporting.
Drawings
Fig. 1: the invention discloses an IRIG-B code time setting system block diagram.
Detailed Description
In order to make the objects, features and advantages of the present invention more comprehensible, the technical solutions in the embodiments of the present invention are described in detail below with reference to the accompanying drawings, and it is apparent that the embodiments described below are only some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
An IRIG-B code time synchronization system comprises eight modules, namely: IRIG-B code decoder (1), date time generator (2), control register (3), time setting driving software (4), error generator (5), adaptive tracker (6), millisecond microsecond generator (7) and application interface (8).
The specific implementation method of the system is described below by taking CPLD/FPGA implementation as an example, and the system can be implemented by cpu through software.
For convenience of description, the following variables are defined.
Clk—working clock other than time tick driver software (4);
m-millisecond microsecond generator (7) current value, initial value is 0;
s-a millisecond microsecond generator (7) counts the whole second, and the counter time driving software (4) is set according to the CLK frequency and the bit number of M;
i-proportional integral adjusting integral coefficient, set by time setting driving software (4);
p-proportional integral adjusting proportional coefficient, set by the time setting driving software (4);
y-proportional integral regulating integral ring current value, initial value Y 0 Is set by time setting driving software (4);
z-proportional integral adjustment output value, increment per CLK time;
mu-error;
t-time.
Wherein MOD is a modulo operation.
(1) The application interface (8) is connected to the time application device via a local bus, by means of which the whole CPLD/FPGA, the configuration control register (3), the reading time and the status information can be initialized.
(2) The time synchronization driver (9) is installed on the time application device, which reads/writes the entire cpld/fpga through the application interface (8). The leap year and leap second control enabling bit in the control register (3) is set according to the instruction of the national time service center, and the date and time generator (2) generates leap year and leap second according to the control of the enabling bit.
(3) The control register (3) stores and outputs control information configured by the time synchronization driving software (4), such as: initial value of current year, initial value Y of integration ring of self-adaptive tracker 0 Control information such as proportional integral adjustment integral coefficient I, proportional integral adjustment proportional coefficient P, open/closed loop and the like.
(4) The IRIG-B time-to-TTL level signal is generated by a receiving device, and the receiving device receives the Beidou/GPS time service satellite signal and outputs the IRIG-B time-to-TTL level signal, so that various mature products are available for selection in the market, and the description is omitted.
(5) The IRIG-B code decoder (1) carries out window sampling statistics on an input IRIG-B time TTL level signal, takes a level signal with a large accumulated value as the window level value, realizes signal filtering and shaping, outputs the frame head position of the IRIG-B code to the error generator (5), and sends the decoded field values of year, month, day, time, minute and second to the date and time generator (2).
(6) The date and time generator (2) processes leap years, leap seconds and the like, generates adult, month, day, time, minute and second according to the BCD code, and outputs the data and the second to the application interface (8).
(7) An error generator (5) generates an error mu, calculates the error mu according to the expression (1) at the time when the IRIG-B code decoder (1) outputs the IRIG-B code frame header, and outputs the error mu to an adaptive tracker (6).
(8) An adaptive tracker (6) generates a time increment Z. During closed-loop control, calculating according to the formula (2) and the formula (3); during open loop control, the initial value Y of the integral loop is directly output 0 。
(9) The millisecond microsecond generator (7) generates fractional dimension local time M according to the formula (4) according to the time increment Z output by the self-adaptive tracker (6), generates millisecond microsecond according to the BCD code and outputs the millisecond microsecond to the application interface (8), and M outputs the millisecond microsecond to the error generator (5), so that millisecond and microsecond time reporting is achieved.
Finally, it should be noted that: the above embodiments are only for illustrating the present invention and not for limiting the technical solution described in the present invention; thus, while the invention has been described in detail with reference to the various embodiments described above, it will be understood by those skilled in the art that the invention may be modified or equivalents; all technical solutions and modifications thereof that do not depart from the spirit and scope of the present invention are intended to be included in the scope of the appended claims.
Claims (7)
1. An IRIG-B code time synchronization system, characterized in that: the device comprises an IRIG-B code decoder (1), a date and time generator (2), a control register (3), time setting driving software (4), an error generator (5), an adaptive tracker (6), a millisecond microsecond generator (7) and an application interface (8), wherein the error generator (5) is used for generating an error mu, and the error mu is calculated according to a formula-1 at the moment when the IRIG-B code decoder (1) outputs an IRIG-B code frame head;
wherein:
mu is error;
CLK: -a working clock other than said time tick driver software (4);
m: the current value of the millisecond microsecond generator (7) is initially 0;
s: the whole second count value of the millisecond microsecond generator (7) is set by the time setting driving software (4) according to the CLK frequency and the number of bits of M;
-said adaptive tracker (6) is adapted to generate a time increment Z; in closed loop control, calculating according to the formula (2) and the formula (3); during open loop control, the initial value Y of the integral loop is directly output 0 ；
Wherein:
i-proportional integral adjusting integral coefficient, set by time setting driving software (4);
p-proportional integral adjusting proportional coefficient, set by the time setting driving software (4);
y-proportional integral regulating integral ring current value, initial value Y 0 Is set by time setting driving software (4);
z-proportional integral adjustment output value, increment per CLK time;
t-time; the millisecond microsecond generator (7) generates fractional-dimensional local time M according to a formula-4 according to a time increment Z output by the adaptive tracker (6), and generates millisecond and/or microsecond according to a BCD code;
wherein MOD is a modulo operation.
2. The IRIG-B code time synchronization system according to claim 1, characterized in that: the IRIG-B code decoder (1) is used for carrying out window sampling statistics on an input IRIG-B signal, and the level with a large accumulated value is the level value of the window, so that the filtering shaping of the short-time interference of the signal is realized.
3. The IRIG-B code time synchronization system according to claim 1, characterized in that: the date and time generator (2) is used for processing leap years and/or leap seconds and generating time data according to the BCD code.
4. The IRIG-B code time synchronization system according to claim 3, characterized in that: the time data consists of year, month, day, time, minute and second.
5. The IRIG-B code time synchronization system according to claim 1, characterized in that: the control register (3) stores and outputs control information configured by the time setting driving software (4).
6. The IRIG-B code time synchronization system according to claim 1, characterized in that: the time setting driving software (4) configures and controls the work of each module in the CPLD or the FPGA through a local bus, and reads time to a time using system.
7. The IRIG-B code time synchronization system of claim 6, wherein: the time setting driving software (4) sets leap years and leap seconds control enabling bits in the control register (3) through a local bus.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101895383A (en) * | 2010-07-07 | 2010-11-24 | 中国人民解放军国防科学技术大学 | External clock synchronization system and control flow thereof |
| EP3614176A1 (en) * | 2018-08-24 | 2020-02-26 | Baidu USA LLC | A hardware centralized time synchronization hub for an autonomous driving vehicle |
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| WO2008002653A2 (en) * | 2006-06-28 | 2008-01-03 | University Of Utah Research Foundation | System and method for precise absolute time event generation and capture |
| CN102411344B (en) * | 2011-06-27 | 2013-08-21 | 北京日立控制系统有限公司 | Clock synchronization method for distributed control system |
| US8508270B2 (en) * | 2011-07-28 | 2013-08-13 | Intel Corporation | System and method for adjusting a characteristic of a periodic signal with use of a filtered bias voltage |
| CN111970080B (en) * | 2020-08-28 | 2023-04-14 | 石家庄科林电气股份有限公司 | Time synchronization method for master and slave equipment |
| CN112578662A (en) * | 2020-12-04 | 2021-03-30 | 中国船舶重工集团公司第七一五研究所 | Method for realizing millisecond timing by using GPS second pulse synchronization system time |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101895383A (en) * | 2010-07-07 | 2010-11-24 | 中国人民解放军国防科学技术大学 | External clock synchronization system and control flow thereof |
| EP3614176A1 (en) * | 2018-08-24 | 2020-02-26 | Baidu USA LLC | A hardware centralized time synchronization hub for an autonomous driving vehicle |
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