CN115268541A - Analog phase compensation system for digital low dropout linear regulator - Google Patents

Analog phase compensation system for digital low dropout linear regulator Download PDF

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CN115268541A
CN115268541A CN202210506995.3A CN202210506995A CN115268541A CN 115268541 A CN115268541 A CN 115268541A CN 202210506995 A CN202210506995 A CN 202210506995A CN 115268541 A CN115268541 A CN 115268541A
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transistor
input
shift register
drain
dynamic comparator
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CN115268541B (en
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贺林
张俊晖
施恒壮
蔡志匡
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Nanjing University of Posts and Telecommunications
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses a phase compensation system for a digital low dropout linear regulator, which comprises a dynamic comparator, a bidirectional shift register, a PMOS (P-channel metal oxide semiconductor) power transistor array, a load capacitor, a load current source, an analog feedforward path and PMOS auxiliary feedforward; the analog feedforward path comprises a capacitor and a resistor, the second end of the capacitor is connected with the first end of the resistor, and the second end of the resistor is connected with a reference voltage VREF(ii) a The dynamic comparator is a four-input dynamic comparator. The invention solves the problem of large output voltage ripple caused by large limit ring oscillation in the digital low dropout linear regulator.

Description

Analog phase compensation system for digital low dropout linear regulator
Technical Field
The invention relates to an electric variable adjusting technology, in particular to a phase compensation system for a digital low dropout linear regulator.
Background
In the field of digital low dropout linear regulators, due to the discreteness of PMOS power transistor arrays and comparators, when the digital low dropout linear regulator reaches a steady state, ripple near the magnitude of a reference voltage is contained in an output voltage, which is called Limit Cycle Oscillation (LCO). The smaller the Limit Cycle Oscillation (LCO), the more stable the digital low dropout linear regulator. LCO is periodic with a period 2M times the period of the clock signal Clk provided by the clock sampling frequency Fs, where the ratio M is a positive integer (M is called the modulus of LCO), i.e. the smaller M, the more stable the digital ldo is.
Fig. 1 and fig. 2 are a schematic diagram of a conventional digital low dropout regulator and an equivalent circuit. Includes a dynamic comparator 100, a bi-directional shift register 102, a PMOS power transistor array 104, and a load capacitor and load current source 106, wherein the dynamic comparator 100 is used to monitor the entire voltage regulator output VOUTAnd a reference voltage VREFThe difference between them. The output voltage ripple is large due to the large limit ring oscillation in the traditional digital low dropout linear regulator.
Disclosure of Invention
In order to solve the above problem, the present invention provides a phase compensation system for a digital low dropout regulator to solve the problem of large ripple of output voltage caused by large limit cycle oscillation in the digital low dropout regulator.
In order to achieve the above object, the present invention is achieved by the following technical means.
A phase compensation system for a digital low dropout linear regulator comprises a dynamic comparator, a bidirectional shift register, a PMOS power transistor array, a load capacitor, a load current source, an analog feedforward path and a PMOS auxiliary feedforward; the analog feedforward path comprises a capacitor and a resistor, the second end of the capacitor is connected with the first end of the resistor, and the second end of the resistor is connected with a reference voltage VREF(ii) a The dynamic comparator is a four-input dynamic comparator; the first end of the capacitor is connected with a main input pair of the four-input dynamic comparator, a branch circuit between the capacitor and the resistor is connected with an auxiliary input pair of the four-input dynamic comparator, the size of an auxiliary input differential pair of the four-input dynamic comparator is different from that of a main input, the output end of the four-input dynamic comparator is respectively connected with the input end of the bidirectional shift register and the input end of the PMOS auxiliary feedforward, the output end of the bidirectional shift register is connected with the input end of the PMOS power transistor array, the output end of the PMOS power transistor array is connected with the output end of the PMOS auxiliary feedforward, the input ends of the load capacitor and the load current source are grounded, and the output ends of the load capacitor and the load current source are respectively connected with the PMOS power transistor array and the analog feedforward path and serve as the output end of the system.
The invention further improves the following steps: the signal transfer function L(s) of the analog feedforward path is
Figure RE-GDA0003848759610000021
The total input of the four-input dynamic comparator (200) has a transfer function of
H(s)＝1+γL(s) (2)
Phase lag
Figure RE-GDA0003848759610000022
Is composed of
Figure RE-GDA0003848759610000023
Wherein s is a complex frequency in the Laplace transform,
Figure RE-GDA0003848759610000024
ω1angular frequency, ω, determined for resistor R1 and capacitor C1 in analog feedforwardsBeing the angular frequency, omega, of the clock signal0For the dominant pole of the output stage, γ is the extra gain provided by the auxiliary input of the comparator, α is the delay length of the delay between the comparator and the register, M is the modulus of LCO, k is ωs/ω0And beta is the number of PMOS tubes in PMOS auxiliary feedforward.
The invention further improves the following steps: the PMOS auxiliary feedforward comprises a plurality of P-type MOS tubes, the grid electrodes of the P-type MOS tubes are connected with the output end of the four-input dynamic comparator, and the drain electrodes of the P-type MOS tubes in the PMOS power transistor array are connected with the drain electrodes of the P-type MOS tubes.
The invention further improves the following steps: the four-input dynamic comparator comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor and a thirteenth transistor; wherein the gate of the ninth transistor is the first input of the four-input dynamic comparatorEnd-connected capacitor in analog feedforward path and output end V of systemOUTThe grid of the tenth transistor is a branch circuit between the second input end of the four-input dynamic comparator and the capacitor and the resistor in the analog feedforward path (210), the drain of the ninth transistor is connected with the drain of the tenth transistor, the connection nodes are respectively connected with the drain of the first transistor and the source of the seventh transistor, the grid of the eleventh transistor is a branch circuit between the third input end of the four-input dynamic comparator and the reference voltage VREFThe fourth input end of the dynamic comparator with four inputs of the grid of the twelfth transistor is connected with the reference voltage VREFThe drain of the eleventh transistor is connected with the drain of the twelfth transistor, the connection node is respectively connected with the drain of the sixth transistor and the source of the eighth transistor, the sources of the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor are respectively connected with the drain of the thirteenth transistor, the grid of the first transistor is connected with the grid of the second transistor, the grid of the fifth transistor is connected with the grid of the sixth transistor, the grid and the drain of the third transistor are respectively connected with the grid and the drain of the seventh transistor, the grid and the drain of the fourth transistor are respectively connected with the grid and the drain of the eighth transistor, and the sources of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are connected with the working voltage V of the four-input dynamic comparatorDDThe clock signal Clk is respectively connected with the grid electrode of the thirteenth transistor, the connecting node of the grid electrode of the first transistor and the grid electrode of the second transistor, the connecting node of the grid electrode of the fifth transistor and the grid electrode of the sixth transistor, the grid electrode of the third transistor is respectively connected with the connecting node of the grid electrode of the seventh transistor, the connecting node of the drain electrode of the fourth transistor and the drain electrode of the eighth transistor, and the drain electrode of the fifth transistor, wherein the connecting nodes are the connecting node of the first output end of the four-input dynamic comparator accessed to the input end of the bidirectional shift register and the PMOS auxiliary feedforward input end, the grid electrode of the fourth transistor is respectively connected with the connecting node of the grid electrode of the eighth transistor, the connecting node of the drain electrode of the third transistor and the drain electrode of the seventh transistor, and the drain electrode of the second transistor, and the connecting nodes are the second output end of the four-input dynamic comparator accessed to the input end of the bidirectional shift registerAnd a PMOS auxiliary feedforward input.
The invention further improves the following steps: the bidirectional shift register is composed of a plurality of shift register units which are connected in series, each shift register unit comprises a D trigger and an alternative data selector, the input end of the D trigger of each shift register unit is connected with the output end of the alternative data selector, the clock end of the D trigger of each shift register unit is connected with a clock signal, the clock end of each shift register unit is connected with the output end of a four-input dynamic comparator, the first input end of the alternative data selector of the first shift register unit is connected with a first constant value signal, the second input end of the alternative data selector of the last shift register unit is connected with a second constant value signal, the first input end of the second to the last shift register unit is connected with the output end of the D trigger of the last shift register unit, the second input end of the first to the last shift register unit is connected with the output end of the D trigger of the next shift register unit, and the output end of the D trigger of each shift register unit is connected with a corresponding PMOS power transistor in a PMOS power transistor array.
The invention further improves the following steps: the PMOS power transistor array comprises a plurality of P-type MOS tubes, the grid electrode of each P-type MOS tube is respectively connected with the output end of the corresponding D trigger of the bidirectional shift register, and the drain electrode of each P-type MOS tube is connected with the drain electrode of the corresponding P-type MOS tube in the PMOS auxiliary feedforward.
The invention further improves the following steps: the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are P-type MOS transistors, and the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor and the thirteenth transistor are N-type MOS transistors.
The beneficial effects of the invention are: the invention adds an additional analog feedforward path and a PMOS auxiliary feedforward path, and changes a comparator in the traditional digital low dropout linear regulator into a multi-input comparator, wherein the analog feedforward path comprises a passive phase lead network formed by a resistor and a capacitor, and the PMOS auxiliary feedforward path comprises a plurality of P-type MOS (metal oxide semiconductor) tubes, so that the additional analog feedforward path is directly applied to the auxiliary input of the comparator, and finally the mode of limit ring oscillation is reduced.
Drawings
Fig. 1 is a schematic diagram of a digital low dropout regulator in the prior art.
Fig. 2 is a schematic diagram of an equivalent model of a digital low dropout linear regulator in the prior art.
Fig. 3 is a schematic diagram of an analog phase compensation system for a digital low dropout regulator according to the present invention.
FIG. 4 is a schematic diagram of a four-input dynamic comparator according to the present invention.
FIG. 5 is a diagram of a bidirectional shift register according to the present invention.
Fig. 6 is a schematic diagram of an equivalent model of the system shown in fig. 3.
Fig. 7 is a schematic diagram of phase shift curves of voltage stabilizing systems in the prior art.
Fig. 8 is a schematic diagram of phase shift curves of the voltage stabilizing systems according to the present invention.
Detailed Description
In the following description, for purposes of explanation, numerous implementation details are set forth in order to provide a thorough understanding of the embodiments of the invention. It should be understood, however, that these implementation details are not to be interpreted as limiting the invention. That is, in some embodiments of the invention, such practical details are not necessary.
Referring to fig. 3, an analog phase compensation system for a digital low dropout linear regulator includes a four-input dynamic comparator 200, a bidirectional shift register 202, a PMOS power transistor array 204, a PMOS auxiliary feed-forward 206, a load capacitor and load current source 208, and an analog feed-forward path 210. Where the analog feed-forward path 210 includes a passive phase lead network formed by a resistor R1 and a capacitor C1.
With reference to fig. 3, the input pair of the four-input dynamic comparator is divided into two pairs, the main input pair 1+ and 1-acts as the dynamic comparator in the conventional digital low dropout linear regulator, and the auxiliary input pair 2+ and 2-, the analog feedforward path is directly applied to the auxiliary input of the comparatorThe auxiliary input differential pair may be sized differently than the main input to adjust the gain of the analog feedforward path. The auxiliary input differential pair may be sized differently than the main input to adjust the gain of the feed-forward path. The resistor R1 and the capacitor C1 are connected into the whole system structure through an auxiliary input pair to form an analog phase advance network
Figure RE-GDA0003848759610000051
And finally realizing analog compensation.
With reference to fig. 4, the four-input dynamic comparator 200 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9, a tenth transistor Q10, an eleventh transistor Q11, a twelfth transistor Q12, and a thirteenth transistor Q13. The gate of the ninth transistor Q9 is the first input terminal 1+ of the dynamic comparator connected to the capacitor C1 in the additional analog feedforward path and the output terminal V of the whole digital low dropout linear regulatorOUTA connected branch 212, a gate of the tenth transistor Q10 being a second input terminal 2+ of the dynamic comparator connected to a branch 214 intermediate the capacitor C1 and the resistor R1 in the additional feed-forward path, a drain of the ninth transistor Q9 being connected to a drain of the tenth transistor Q10, and the connection nodes being connected to a drain of the first transistor Q1 and a source of the seventh transistor Q7, respectively, a gate of the eleventh transistor Q11 being a third input terminal 2-of the dynamic comparator connected to a reference voltage VREFThe gate of the twelfth transistor Q12 is the fourth input terminal 1-of the dynamic comparator connected to the reference voltage VREFA drain of the eleventh transistor Q11 is connected to a drain of the twelfth transistor Q12, and the connection node is connected to a drain of the sixth transistor Q6 and a source of the eighth transistor Q8, respectively, sources of the ninth transistor Q9, the tenth transistor Q10, the eleventh transistor Q11, and the twelfth transistor Q12 are connected to a drain of the thirteenth transistor Q13, a gate Q1 of the first transistor is connected to a gate of the second transistor Q2, a gate of the fifth transistor Q5 is connected to a gate of the sixth transistor Q6, and a gate and a drain of the third transistor Q3 are connected to a gate and a drain of the seventh transistor Q7, respectivelyThe grid electrode and the drain electrode of the fourth transistor Q4 are respectively connected with the grid electrode and the drain electrode of the eighth transistor Q8, and the source electrodes of the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5 and the sixth transistor Q6 are connected with the working voltage V of the dynamic comparatorDDThe clock signal Clk connects the gate of the thirteenth transistor Q13, the connection node between the gate of the first transistor Q1 and the gate of the second transistor Q2, the connection node between the gate of the fifth transistor Q5 and the gate of the sixth transistor Q6, the connection node between the gate of the third transistor Q3 and the gate of the seventh transistor Q7, the connection node between the drain of the fourth transistor Q4 and the drain of the eighth transistor Q8, and the drain of the fifth transistor Q5, respectively, and the connection nodes are such that the first output terminal P + of the dynamic comparator is connected to the input terminal of the bidirectional shift register and the gate of the P-type MOS transistor in the PMOS auxiliary feed forward, the connection node between the gate of the fourth transistor Q4 and the gate of the eighth transistor Q8, the connection node between the drain of the third transistor Q3 and the drain of the seventh transistor Q7, and the drain of the second transistor Q2, and the second output terminal P-of the dynamic comparator is also connected to the input terminal of the bidirectional shift register and the gate of the P-type MOS transistor in the PMOS auxiliary feed forward
With reference to fig. 5, the bidirectional shift register 202 is composed of a plurality of shift register units connected in series, each shift register unit includes a D flip-flop and an alternative data selector, the input of the D flip-flop of each shift register unit is connected to the output of the alternative data selector, the clock of the D flip-flop of each shift register unit is connected to the clock signal, the clock of each shift register unit is connected to the output of the four-input dynamic comparator (200), the first input of the alternative data selector of the first shift register unit is connected to the first constant signal (low level shown in fig. 5), the second input of the alternative data selector of the last shift register unit is connected to the second constant signal (high level shown in fig. 5), the first input of the second to last shift register unit is connected to the output of the D flip-flop of the last shift register unit, the second input of the first to last shift register unit is connected to the output of the D flip-flop of the next shift register unit, and the output of the D flip-flop of the shift register unit is connected to the corresponding PMOS power transistor array (204).
Fig. 2 is a schematic diagram of a steady-state model equivalent to the conventional digital low dropout linear regulator, and as can be seen from the diagram, the equivalent steady-state model schematic diagram includes a comparator section 110, a Delay section Delay, a discrete time integrator section 112, a zeroth-order keeper section 114, a first-order device section 116, and the comparator section 110. The delay between the comparator and the bidirectional shift register is z-αWhere α is the delay length of the delay between the comparator and the register, depending on the actual circuit implementation. The dynamic comparator is modeled as an ideal relay 110 with zero dead band and clock sampling. In steady state, a limit cycle oscillation of modulo M is established, assuming the comparator input is x (t), with y (t) representing the non-sampled comparator output and y' (t) representing the sampled output. With reasonable accuracy, x (t) can be approximated as a sinusoidal function, as long as φ is in the (0, π/M) range, the sampled output y' (t) will remain unchanged. In other words, the phase of the comparator output is preserved with respect to the clock edge, or more precisely, shifted from t =0 by one clock cycle. Comparing the phase between y '(t) and x (t), the principal component of y' (t) is shifted from x (t) by π/M- φ. The frequency of the limit cycle oscillation is therefore determined only by the phase characteristics of the linear part of the loop. The delay between the comparator and the bidirectional shift register is z-αCorresponding to a phase shift of a/M.
The transfer function of the bidirectional shift register is shown below
Figure RE-GDA0003848759610000071
The transfer function of the zeroth order keeper is as follows
Figure RE-GDA0003848759610000072
The transfer functions of the output stage and the load are as follows
Figure RE-GDA0003848759610000073
Wherein KDCIs the gain of the output stage, ω0Is the dominant pole of the output stage, the total phase shift of the linear part of the loop is at the LCO frequency
Figure RE-GDA0003848759610000074
When is calculated as
Figure RE-GDA0003848759610000075
To maintain the LCO, the following conditions must be satisfied
Figure RE-GDA0003848759610000076
Simplifying the above equation can lead to a phase lag
Figure RE-GDA0003848759610000077
Figure RE-GDA0003848759610000078
Mode M of LCO only
Figure RE-GDA0003848759610000079
In that
Figure RE-GDA00038487596100000710
Is present within the boundary of (1), that is to say only when
Figure RE-GDA00038487596100000711
Within which the corresponding M is true. From the formula
Figure RE-GDA00038487596100000712
Increases with increasing alpha, which in turn shifts as can be seen from fig. 7Movable part
Figure RE-GDA00038487596100000713
And the intersection between the boundary curves. The coincident mode M will also increase (as shown by the dashed line in fig. 7). Let omegas/ω0K, it is also clear from the above equation
Figure RE-GDA00038487596100000714
Increases with increasing k and also increases the modulus of coincidence M. This means that if a large load capacitor is used to filter out the output ripple, the modulus M of the LCO will increase, making the output ripple more severe. To reduce the amplitude of the LCO, the boundary range must be reduced
Figure RE-GDA00038487596100000715
The modulus M in (1). The present embodiment provides a compensation technique that can be implemented by pull-down
Figure RE-GDA00038487596100000716
The curve achieves a reduction in M.
With reference to fig. 3 and 6, the structure and equivalent model of the compensation scheme proposed by the present system are compared with the structure and equivalent model of the conventional digital low dropout linear regulator, and have more digital feedforward compensation and analog feedforward compensation, i.e. the PMOS auxiliary feedforward 206 and the analog feedforward path 210, corresponding to the amplification branch 130 and the analog phase-advance network 220 in the equivalent model.
In conjunction with fig. 3 and 6, the digital feed-forward compensation is in parallel with the PMOS power transistor array 204 by adding a PMOS auxiliary feed-forward 206. Digital feed forward compensation adds a zero to the linear portion of the feedback loop, causing a phase lead. After digital feedforward compensation
Figure RE-GDA0003848759610000087
Is composed of
Figure RE-GDA0003848759610000081
And transmitCompared with conventional techniques, after digital feedforward
Figure RE-GDA0003848759610000082
Reduce
Figure RE-GDA0003848759610000083
So M is smaller. The digital feed forward compensation scheme reduces the conforming modulus M. For smaller capacitive loads (e.g. k = 1), the conforming mode M can already be reduced to a minimum value of 1. However, if the capacitive load is large (e.g., k = 30), M can only be taken to be 2 at a minimum. In conjunction with FIGS. 7 and 8, there are several different M's at the same time so that
Figure RE-GDA0003848759610000088
Within the bounds, the smallest M of these may also be such that
Figure RE-GDA0003848759610000089
Very close to the upper boundary, i.e. the phase margin is too small. Due to the prevalence of noise and interference, the phase of an LCO may deviate from its ideal position if derived from
Figure RE-GDA00038487596100000810
The phase margin to the boundary is too small and random phase deviations can corrupt the LCO of this mode. In this case, the steady-state output of the digital low dropout regulator may exhibit chaotic behavior. To obtain stable steady-state oscillation with mode 1,
Figure RE-GDA00038487596100000811
there must be sufficient phase margin with the boundary,
Figure RE-GDA00038487596100000812
it is necessary to have as few conforming modes M as possible.
This embodiment further reduces M by simulating feedforward. With reference to fig. 3 and 6, the transfer function of the simulated phase advance network formed by simulating the feedforward path is as follows
Figure RE-GDA0003848759610000084
Wherein
Figure RE-GDA0003848759610000085
In case the auxiliary input provides an additional gain γ, the transfer function of the total input of the comparator is as follows
Figure RE-GDA0003848759610000086
Phase lag
Figure RE-GDA0003848759610000095
Recalculate as follows
Figure RE-GDA0003848759610000091
Where s is the complex frequency in the Laplace transform,
Figure RE-GDA0003848759610000092
ω1angular frequency, ω, determined for resistor R1 and capacitor C1 in analog feedforwardsBeing the angular frequency, omega, of the clock signal0For the dominant pole of the output stage, γ is the extra gain provided by the auxiliary input of the comparator, α is the delay length of the delay between the comparator and the register, M is the modulus of LCO, k is ωs/ω0And beta is the number of PMOS tubes in PMOS auxiliary feedforward.
In formula (3), arctan is an increasing function, and the gain is positive when
Figure RE-GDA0003848759610000093
The larger the value of y, i.e.,
Figure RE-GDA0003848759610000096
the smaller, the smaller M.
Referring to fig. 7 and 8, the phase compensation technique of this embodimentAnd the conventional digital low dropout linear regulator can not only reduce the consistent modulus M to the minimum integer 1 but also obviously increase the phase margin of the modulus 1 when the capacitance load is large (k = 30). Specifically, in conjunction with fig. 7, the mode M of the LCO of the conventional art only corresponds to
Figure RE-GDA0003848759610000097
At 0<φ<The upper boundary is pi/M, pi is 1, pi/2 is 2, and the lower boundary is 0. By
Figure RE-GDA0003848759610000094
It can be seen that k = ωs/ω0Then, both α and k are given a certain value, so only M is a variable, and when α is 1 and 0.5, the first term is greater than or equal to π when M is 1, plus the positive value of the second term arctan must exceed the upper bound, so that M cannot be 1 at this time, and lco is not small enough. With reference to fig. 8, conv is a conventional curve without compensation, digital is a curve with digital compensation, and deployed is a curve after i add analog compensation, and k =30 can also achieve M =1 after the technical compensation of the embodiment.
The working process of the embodiment is specifically as follows: fs is the clock sampling frequency and provides the clock signal Clk for the four-input dynamic comparator 200 and the bidirectional shift register 202. When the clock signal Clk arrives, the four-input dynamic comparator 200 and the bidirectional shift register 202 start to operate. The input pair of the four-input dynamic comparator 200 is divided into two pairs, the main input pair 1+ and 1-acts as the dynamic comparator in the traditional digital low dropout linear regulator, and the output V of the regulator begins to be compared when the clock signal comesOUTAnd a reference voltage VREFThereby monitoring the difference therebetween. In addition to the pair of auxiliary inputs 2+ and 2-, which are applied directly to the auxiliary inputs of the comparator, the differential pair of auxiliary inputs may be sized differently from the main input to adjust the gain of the analog feedforward path. The output of the four-input dynamic comparator 200 is fed to the bi-directional shift register over one clock cycle202, by the serial-in-parallel-out feature, the output of the bi-directional shift register 202 becomes several, thereby controlling the number of PMOS power transistors in the PMOS power transistor array 204 to be turned on. Load capacitor CLPlaced at the regulator output node to reduce output voltage ripple.
The above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, but equivalent modifications or changes made by those skilled in the art according to the disclosure of the present invention should be included in the scope of the present invention as set forth in the appended claims.

Claims (7)

1. A phase compensation system for a digital low dropout linear regulator comprising a dynamic comparator, a bi-directional shift register (202), a PMOS power transistor array (204), a load capacitor, and a load current source (208),
further comprising an analog feedforward path (210) and a PMOS auxiliary feedforward (206);
the analog feedforward path (210) comprises a capacitor (C1) and a resistor (R1), wherein the second end of the capacitor (C1) is connected with the first end of the resistor (R1), and the second end of the resistor (R1) is connected with a reference voltage VREF；
The dynamic comparator is a four-input dynamic comparator (200);
the first end of the capacitor (C1) is connected with the main input pair of the four-input dynamic comparator (200),
the branch between the capacitor (C1) and the resistor (R1) is connected with the auxiliary input pair of the four-input dynamic comparator (200),
the auxiliary input differential pair of the four-input dynamic comparator (200) is of a different size than the main input,
the output end of the four-input dynamic comparator (200) is respectively connected with the input end of the bidirectional shift register (202) and the input end of the PMOS auxiliary feedforward (206),
the output end of the bidirectional shift register (202) is connected with the input end of the PMOS power transistor array (204),
the output of the PMOS power transistor array (204) is connected with the output end of the PMOS auxiliary feedforward (206),
the load capacitor and load current source (208) inputs are grounded, and the outputs are connected to the PMOS power transistor array (204) and the analog feed-forward path (210) respectively and serve as the system outputs.
2. The system of claim 1, wherein the signal transfer function L(s) of the analog feedforward path (210) is
Figure FDA0003637783430000011
The total input transfer function of the four-input dynamic comparator (200) is
H(s)＝1+γL(s) (2)
Phase lag
Figure FDA0003637783430000012
Is composed of
Figure FDA0003637783430000013
Where s is the complex frequency in the Laplace transform,
Figure FDA0003637783430000021
ω1angular frequency, ω, determined for resistor R1 and capacitor C1 in analog feedforwardsBeing the angular frequency, omega, of the clock signal0For the dominant pole of the output stage, γ is the additional gain provided by the auxiliary input of the comparator, α is the delay length of the delay between the comparator and the register, M is the modulus of LCO, k is ωs/ω0And beta is the number of PMOS tubes in PMOS auxiliary feedforward.
3. The system of claim 1 or 2, wherein the PMOS auxiliary feed-forward (206) comprises P-type MOS transistors, the gates of the P-type MOS transistors are connected to the output of the four-input dynamic comparator (200), and the drains of the P-type MOS transistors in the PMOS power transistor array (204).
4. The system of claim 3, wherein the four-input dynamic comparator (200) comprises a first transistor (Q1), a second transistor (Q2), a third transistor (Q3), a fourth transistor (Q4), a fifth transistor (Q5), a sixth transistor (Q6), a seventh transistor (Q7), an eighth transistor (Q8), a ninth transistor (Q9), a tenth transistor (Q10), an eleventh transistor (Q11), a twelfth transistor (Q12), a thirteenth transistor (Q13); wherein
The ninth transistor (Q9) has a gate that is the first input of the four-input dynamic comparator (200) connected to the capacitor (C1) in the analog feedforward path (210) and the output V of the systemOUT，
The gate of the tenth transistor (Q10) is a branch of the four-input dynamic comparator (200) having a second input connected between the capacitor (C1) and the resistor (R1) in the analog feedforward path (210),
the drain of the ninth transistor (Q9) is connected to the drain of the tenth transistor (Q10), and the connection node is connected to the drain of the first transistor (Q1) and the source of the seventh transistor (Q7), respectively,
the grid electrode of the eleventh transistor (Q11) is a third input end of the four-input dynamic comparator (200) which is connected with the reference voltage VREF，
The grid electrode of the twelfth transistor (Q12) is a fourth input end of the four-input dynamic comparator (200) which is connected with the reference voltage VREF，
The drain of the eleventh transistor (Q11) is connected to the drain of the twelfth transistor (Q12), and the connection nodes are connected to the drain of the sixth transistor (Q6) and the source of the eighth transistor (Q8), respectively,
the sources of the ninth transistor (Q9), the tenth transistor (Q10), the eleventh transistor (Q11) and the twelfth transistor (Q12) are all connected with the drain of the thirteenth transistor (Q13),
the grid electrode (Q1) of the first transistor is connected with the grid electrode of the second transistor (Q2),
the grid electrode of the fifth transistor (Q5) is connected with the grid electrode of the sixth transistor (Q6),
the grid and the drain of the third transistor (Q3) are respectively connected with the grid and the drain of the seventh transistor (Q7),
the grid and the drain of the fourth transistor (Q4) are respectively connected with the grid and the drain of the eighth transistor (Q8),
the sources of the first transistor (Q1), the second transistor (Q2), the third transistor (Q3), the fourth transistor (Q4), the fifth transistor (Q5) and the sixth transistor (Q6) are connected with the working voltage V of the four-input dynamic comparator (200)DD，
The clock signal Clk is respectively connected with a connecting node of the grid of the thirteenth transistor (Q13), the grid of the first transistor (Q1) and the grid of the second transistor (Q2), and a connecting node of the grid of the fifth transistor (Q5) and the grid of the sixth transistor (Q6),
the grid electrode of the third transistor (Q3) is respectively connected with the connection node of the grid electrode of the seventh transistor (Q7), the connection node of the drain electrode of the fourth transistor (Q4) and the drain electrode of the eighth transistor (Q8) and the drain electrode of the fifth transistor (Q5), and the connection node is that the first output end of the four-input dynamic comparator (200) is connected with the input end of the bidirectional shift register (202) and the input end of the PMOS auxiliary feedforward (206),
the grid electrode of the fourth transistor (Q4) is respectively connected with the connection node of the grid electrode of the eighth transistor (Q8), the connection node of the drain electrode of the third transistor (Q3) and the drain electrode of the seventh transistor (Q7) and the drain electrode of the second transistor (Q2), and the connection node is that the second output end of the four-input dynamic comparator (200) is connected with the input end of the bidirectional shift register (202) and the input end of the PMOS auxiliary feedforward (206).
5. The system of claim 3, wherein the bi-directional shift register (202) is comprised of a plurality of shift register cells connected in series, each shift register cell comprising a D flip-flop and an alternative data selector,
the input end of the D trigger of each stage of shift register unit is connected with the output end of the alternative data selector,
the D flip-flop clock of each stage of the shift register unit is terminated with a clock signal,
the clock end of each stage of the shift register unit is connected with the output end of the four-input dynamic comparator (200),
the first input end of the alternative data selector of the first stage shift register unit is connected with the first constant value signal,
the second input end of the alternative data selector of the last stage of shift register unit is connected with the second constant value signal,
the first input end of the shift register unit from the second stage to the last stage is connected with the output end of the trigger of the shift register unit D of the previous stage,
the second input end of the shift register unit from the first stage to the second last stage is connected with the output end of the trigger D of the shift register unit of the next stage,
the output end of the D trigger of each stage of the shift register unit is connected with a corresponding PMOS power transistor in the PMOS power transistor array (204).
6. The system of claim 3, wherein the PMOS power transistor array (204) comprises a plurality of P-type MOS transistors, a gate of each P-type MOS transistor is connected to the output terminal of the corresponding D flip-flop of the bidirectional shift register (202), and a drain of each P-type MOS transistor is connected to a drain of a corresponding P-type MOS transistor in the PMOS auxiliary feed-forward (206).
7. The system according to claim 4, wherein the first transistor (Q1), the second transistor (Q2), the third transistor (Q3), the fourth transistor (Q4), the fifth transistor (Q5) and the sixth transistor (Q6) are P-type MOS transistors, and the seventh transistor (Q7), the eighth transistor (Q8), the ninth transistor (Q9), the tenth transistor (Q10), the eleventh transistor (Q11), the twelfth transistor (Q12) and the thirteenth transistor (Q13) are N-type MOS transistors.
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