CN115250061A

CN115250061A - Voltage transformation circuit and electronic equipment

Info

Publication number: CN115250061A
Application number: CN202211163405.8A
Authority: CN
Inventors: 毛鸿; 戴兴科
Original assignee: Shenzhen Weiyuan Semiconductor Co ltd
Current assignee: Shenzhen Weiyuan Semiconductor Co ltd
Priority date: 2022-09-23
Filing date: 2022-09-23
Publication date: 2022-10-28
Anticipated expiration: 2042-09-23
Also published as: CN115250061B

Abstract

The application is suitable for power technical field, provides a vary voltage circuit and electronic equipment, includes: the three-level voltage reduction unit is used for performing voltage reduction processing on the received voltage signal based on the first switch driving signal and outputting the voltage signal after being started; the voltage regulating unit comprises a regulating capacitor and is used for controlling the regulating capacitor and the flying capacitor in the three-level voltage reduction unit to be alternately switched between a series connection state and a parallel connection state based on a second switch driving signal after being started; the voltage transformation control unit is used for firstly starting the voltage regulation unit when the voltage transformation circuit is electrified, and then starting the three-level voltage reduction unit after a first preset time after the voltage regulation unit is started; and the voltage regulating unit is used for switching off the three-level voltage reduction unit firstly when the voltage transformation circuit is powered off and switching off the voltage regulating unit after a second preset time after the three-level voltage reduction unit is switched off. The transformer circuit is low in cost and high in electric energy conversion efficiency.

Description

Voltage transformation circuit and electronic device

Technical Field

The application belongs to the technical field of power supplies, and particularly relates to a voltage transformation circuit and electronic equipment.

Background

The three-level buck converter is a voltage transformation circuit commonly used in electronic devices, and can convert a high voltage input from a power port of the electronic device into a low voltage required for charging a battery to charge the battery. The structure of a three-level buck converter is generally shown in fig. 1A, in which a power transistor Q1 and a power transistor Q4 are respectively driven by a pair of complementary driving signals, a power transistor Q2 and a power transistor Q3 are respectively driven by another pair of complementary driving signals, and the two pairs of complementary driving signals have the same duty ratio and are 180 degrees out of phase.

In order to enable each device in the three-level buck converter to work in a low-voltage state all the time, the voltage at two ends of the flying capacitor Cfly needs to be precharged to about half of the input voltage before each power tube is conducted, and thus, when the three-level buck converter is in a steady state, the voltage between two conducting ends of each power tube is also about half of the input voltage, so that the three-level buck converter can adopt a device with lower voltage resistance, and the cost of the three-level buck converter can be reduced. However, in practical applications, due to asymmetry of the on-resistance of each power transistor or the driving circuit, the voltage at the two ends of the flying capacitor Cfly often deviates from a half of the input voltage to a greater extent, which not only causes some devices to work under higher voltage stress, but also causes the current ripple flowing through the output inductor Lo to increase, thereby reducing the power conversion efficiency of the three-level buck converter. In the prior art, the duty ratio of the driving signal is usually adjusted to solve the problem, however, the adjustment capability of the method is poor when the duty ratio is about 50%, and the current ripple flowing through the output inductor Lo is still increased, which cannot effectively improve the electric energy conversion efficiency of the three-level buck converter.

Disclosure of Invention

In view of this, embodiments of the present application provide a voltage transformation circuit and an electronic device, so as to solve the technical problem that the existing three-level step-down transformer cannot effectively improve the electric energy conversion efficiency while reducing the cost.

In a first aspect, an embodiment of the present application provides a voltage transformation circuit, including:

the three-level voltage reduction unit comprises a flying capacitor, an output inductor, a first power tube, a second power tube, a third power tube and a fourth power tube which are sequentially connected between the input end of the three-level voltage reduction unit and the ground in series, the flying capacitor is connected between a common junction of the first power tube and the second power tube and a common junction of the third power tube and the fourth power tube, and the output inductor is connected between a common junction of the second power tube and the third power tube and the output end of the three-level voltage reduction unit; the three-level voltage reduction unit is used for carrying out voltage reduction processing on the voltage signal received by the input end based on a first switch driving signal after being started and outputting the voltage signal after voltage reduction processing;

the voltage regulating unit is connected between the input end of the three-level voltage reduction unit and the ground, and is connected with the flying capacitor; the voltage regulating unit comprises a regulating capacitor; the voltage adjusting unit is used for controlling the adjusting capacitor and the flying capacitor to be alternately switched between a series connection state and a parallel connection state based on a second switch driving signal after being started; the series connection state refers to a connection state that the flying capacitor and the adjusting capacitor are sequentially connected in series between the input end and the ground;

the voltage transformation control unit is connected with the three-level voltage reduction unit and the voltage regulation unit, and is used for starting the voltage regulation unit firstly when the voltage transformation circuit is powered on and starting the three-level voltage reduction unit after a first preset time after the voltage regulation unit is started; and the voltage regulating unit is used for switching off the three-level voltage reduction unit firstly when the voltage transformation circuit is powered off, and switching off the voltage regulating unit after a second preset time after the three-level voltage reduction unit is switched off.

In a second aspect, an embodiment of the present application provides an electronic device, including a power port, a battery, and the transformer circuit according to any optional implementation manner of the first aspect, where an input end of the transformer circuit is connected to the power port, and an output end of the transformer circuit is connected to the battery; the input end of the three-level voltage reduction unit is used as the input end of the transformation circuit, and the output end of the three-level voltage reduction unit is used as the output end of the transformation circuit.

The transformer circuit and the electronic equipment provided by the embodiment of the application have the following beneficial effects:

according to the voltage transformation circuit provided by the embodiment of the application, the voltage regulation unit and the voltage transformation control unit are configured for the three-level voltage reduction unit; the voltage adjusting unit comprises an adjusting capacitor, and can control the adjusting capacitor and the flying capacitor to be alternately switched between a series connection state and a parallel connection state based on a second switch driving signal after being started; the sum of the voltages at the two ends of the regulating capacitor and the flying capacitor in series connection is the input voltage of the three-level voltage reduction unit, and the voltages at the two ends of the regulating capacitor and the flying capacitor in parallel connection are equal, so that when the voltage regulating unit works independently, the voltages at the two ends of the regulating capacitor and the two ends of the flying capacitor can be about half of the input voltage of the three-level voltage reduction unit; therefore, when the voltage transformation control unit is powered on the voltage transformation circuit, the voltage regulation unit is firstly started to pre-charge the voltages at the two ends of the flying capacitor to about half of the voltage of the input end of the three-level voltage reduction unit, and the three-level voltage reduction unit is started after the voltage regulation unit is started for a first preset time, so that the voltages at the two ends of the flying capacitor of the three-level voltage reduction unit are pre-charged to about half of the input voltage when the three-level voltage reduction unit is started, and the voltages at the two ends of the flying capacitor are always clamped to about half of the input voltage in the whole working process of the three-level voltage reduction unit; in addition, when the voltage transformation circuit is powered off, the voltage transformation control unit firstly closes the three-level voltage reduction unit, and then closes the voltage regulation unit after a second preset time after the three-level voltage reduction unit is closed, so that the voltage at two ends of the flying capacitor is about the input voltage when the three-level voltage reduction unit is closed. Therefore, the voltage stress of each device in the three-level voltage reduction unit can be always kept about half of the input voltage by the transformation circuit, the ripple of the current flowing through the output inductor is reduced, the electric energy conversion efficiency of the three-level voltage reduction unit is improved, the device with lower voltage resistance can be adopted by the three-level voltage reduction unit, and the cost of the transformation circuit is reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without inventive labor.

FIG. 1A is a schematic diagram of a conventional three-level buck converter;

FIG. 1B is a diagram illustrating driving signals of each power transistor in a conventional three-level buck converter;

fig. 2 is a schematic structural diagram of a voltage transformation circuit according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a voltage transformation circuit according to another embodiment of the present application;

fig. 4 is a schematic circuit diagram of a voltage transformation circuit according to an embodiment of the present disclosure;

fig. 5A is a schematic waveform diagram of driving signals of power transistors in a transformer circuit in a switching period according to an embodiment of the present disclosure;

fig. 5B is a schematic waveform diagram of driving signals of each power transistor in a transformer circuit in a switching period according to another embodiment of the present application;

fig. 6 is a schematic circuit diagram of a voltage transformation circuit according to another embodiment of the present application;

fig. 7A is a schematic waveform diagram of driving signals of power transistors in a transformer circuit in a switching period according to another embodiment of the present application;

fig. 7B is a schematic waveform diagram of driving signals of power transistors in a transformer circuit in a switching period according to another embodiment of the present application;

fig. 8 is a timing diagram illustrating operation of each unit in a transformer circuit according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

It is to be understood that the terminology used in the embodiments of the present application is for the purpose of describing particular embodiments of the present application only and is not intended to be limiting of the application. In the description of the embodiments of the present application, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a definition of "a first" or "a second" feature may explicitly or implicitly include one or more of the features. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless otherwise specifically stated.

At present, more and more electronic devices powered by rechargeable batteries are used, most of the electronic devices are powered by one battery, and because the charging voltage required by one battery is generally low, and the voltage obtained from a charger by a power port of the electronic device during charging is generally high, a step-down voltage-changing circuit is generally arranged in the electronic device and used for converting a high voltage input by the power port of the electronic device into a low voltage required by battery charging to charge the battery. With the wide application of the fast charging technology to the electronic device, the voltage that can be obtained from the charger when the electronic device is charged is higher and higher, which makes the input voltage of the step-down type voltage transformation circuit higher and higher, and the output voltage of the step-down type voltage transformation circuit is relatively smaller (usually, the charging voltage required by the battery), so that the input-output voltage difference of the step-down type voltage transformation circuit is larger and larger. In the step-down transformer circuit, the larger the input/output voltage difference is, the lower the electric energy conversion efficiency is.

The three-level buck converter is a direct current-direct current (DC-DC) buck type voltage transformation circuit capable of improving the efficiency of electric energy conversion. Fig. 1A shows the structure of a conventional three-level buck converter. As shown in fig. 1A, a conventional three-level buck converter generally includes a first power transistor Q1, a second power transistor Q2, a third power transistor Q3, a fourth power transistor Q4, a flying capacitor Cfly, and an output inductor L0. The first power tube Q1, the second power tube Q2, the third power tube Q3 and the fourth power tube Q4 are sequentially connected between the input end of the three-level buck converter and the ground in series, the first end of the flying capacitor Cfly is connected with the common junction of the first power tube Q1 and the second power tube Q2, the second end of the flying capacitor Cfly is connected with the common junction of the third power tube Q3 and the fourth power tube Q4, the first end of the output inductor L0 is connected with the common junction of the second power tube Q2 and the third power tube Q3, and the second end of the output inductor L0 is used as the output end of the three-level buck converter. Fig. 1B is a schematic diagram of driving signals of respective power transistors in a conventional three-level buck converter. As shown in fig. 1B, the first power transistor Q1 and the fourth power transistor Q4 are respectively driven by a pair of complementary driving signals, the first power transistor Q1 is an active transistor, and the fourth power transistor Q4 is a synchronous rectifier; the second power tube Q2 and the third power tube Q3 are respectively driven by another pair of complementary driving signals, the second power tube Q2 is an active tube, and the third power tube Q3 is a synchronous rectifier tube. The first power tube Q1 and the second power tube Q2 are equivalent to main tubes of the two-phase buck converter, and the phase difference of driving signals of the two power tubes is 180 degrees; similarly, the phases of the driving signals of the third power transistor Q3 and the fourth power transistor Q4 are also different by 180 degrees.

When the three-level buck converter is in a stable state, the duty ratio of the first power tube Q1 is close to the duty ratio of the second power tube Q2, the output voltage Vout of the three-level buck converter is determined by the input voltage Vin and the duty ratio of the first power tube Q1 (or the second power tube Q2), and ideally, the duty ratio of the first power tube Q1 and the duty ratio of the second power tube Q2 can be changed from 0% to 100%. In addition, when the three-level buck converter is in a stable state, the voltage at two ends of the flying capacitor Cfly is half of the input voltage Vin, and the voltage between two conducting ends of each power tube is also half of the input voltage Vin, that is, when the three-level buck converter is in a stable state, the voltage stress applied to each device is only half of the input voltage Vin, so that the three-level buck converter can adopt a device with lower voltage resistance, and the cost of the three-level buck converter can be reduced. However, in practical applications, when the three-level buck converter is powered on, the voltage across the flying capacitor Cfly is 0, and if the three-level buck converter is started in such a situation, the voltage stress applied to some devices is close to the input voltage Vin, which requires that each device has higher voltage resistance, thereby increasing the cost of the three-level buck converter.

In order to enable each device in the three-level buck converter to work in a low-voltage state all the time and further reduce the cost of the three-level buck converter, the conventional solution is to pre-charge the voltage at two ends of the flying capacitor Cfly to about half of the input voltage Vin before each power tube is turned on, so that the voltage between two conducting ends of each power tube is also about half of the input voltage Vin when or after the three-level buck converter is turned on. However, in practical applications, due to asymmetry of the on-resistance and/or the driving circuit of each power transistor, the voltage at two ends of the flying capacitor Cfly is often not stabilized at about half of the input voltage Vin, which not only causes some devices to operate under higher voltage stress, but also causes an increase in current ripple flowing through the output inductor L0, thereby reducing the power conversion efficiency of the three-level buck converter. In the prior art, the technical problem of low electric energy conversion efficiency is usually solved by adjusting the duty ratio of the driving signal of each power tube, however, the adjustment capability of this method is poor when the duty ratio is about 50%, which may result in serious asymmetry of the duty ratio of two-phase power tubes, and thus the current ripple flowing through the output inductor L0 may still be increased, and the electric energy conversion efficiency of the three-level buck converter may not be effectively improved.

Based on this, in order to effectively improve the electric energy conversion efficiency of the three-level buck converter while reducing the cost of the three-level buck converter, embodiments of the present application first provide a voltage transformation circuit by configuring a voltage regulation unit and a voltage transformation control unit for a three-level buck unit (i.e., a conventional three-level buck converter); the voltage adjusting unit comprises an adjusting capacitor, and can control the adjusting capacitor and the flying capacitor to be alternately switched between a series connection state and a parallel connection state based on a second switch driving signal after being started; the sum of the voltages at the two ends of the regulating capacitor and the flying capacitor in series is the input voltage of the three-level voltage reduction unit, and the voltages at the two ends of the regulating capacitor and the flying capacitor in parallel are equal, so that when the voltage regulating unit works alone, the voltages at the two ends of the regulating capacitor and the two ends of the flying capacitor can be about half of the input voltage of the three-level voltage reduction unit; therefore, when the voltage transformation control unit is powered on the voltage transformation circuit, the voltage regulation unit is started firstly to pre-charge the voltages at the two ends of the flying capacitor to about half of the voltage of the input end of the three-level voltage reduction unit, and the three-level voltage reduction unit is started after the voltage regulation unit is started for a first preset time, so that the voltages at the two ends of the flying capacitor of the three-level voltage reduction unit are pre-charged to about half of the input voltage when the three-level voltage reduction unit is started, and the voltages at the two ends of the flying capacitor are clamped to about half of the input voltage all the time in the whole working process of the three-level voltage reduction unit; in addition, when the voltage transformation circuit is powered off, the voltage transformation control unit firstly closes the three-level voltage reduction unit, and then closes the voltage regulation unit after a second preset time after the three-level voltage reduction unit is closed, so that the voltage at two ends of the flying capacitor is about the input voltage when the three-level voltage reduction unit is closed. Therefore, the voltage stress of each device in the three-level voltage reduction unit can be always kept about half of the input voltage by the transformation circuit, the ripple of the current flowing through the output inductor is reduced, the electric energy conversion efficiency of the three-level voltage reduction unit is improved, the device with lower voltage resistance can be adopted by the three-level voltage reduction unit, and the cost of the transformation circuit is reduced.

The voltage transformation circuit provided by the embodiment of the application can be particularly a DC-DC step-down type voltage transformation circuit. The voltage transformation circuit can be applied to an electronic device, and particularly can be connected between a power supply port of the electronic device and a battery for converting a high voltage input by the power supply port of the electronic device into a low voltage required by charging the battery to charge the battery. Fig. 2 is a schematic structural diagram of a transformer circuit according to an embodiment of the present disclosure. As shown in fig. 2, the transforming circuit may include a three-level voltage-reducing unit 21, a voltage-adjusting unit 22, and a transformation control unit 23.

Wherein, the input end of the three-level voltage-reducing unit 21 is used as the input end IN of the voltage transformation circuit, and the output end of the three-level voltage-reducing unit 21 is used as the output end OUT of the voltage transformation circuit; the voltage transformation circuit is used for receiving the voltage signal through an input end IN, carrying OUT voltage reduction processing on the received voltage signal and outputting the voltage signal after voltage reduction processing through an output end OUT. Specifically, the three-level voltage-reducing unit 21 may include a flying capacitor Cfly, an output inductor Lo, and a first power transistor Q1, a second power transistor Q2, a third power transistor Q3, and a fourth power transistor Q4 sequentially connected in series between the input terminal of the three-level voltage-reducing unit 21 and the ground. The flying capacitor Cfly is connected between a common junction point of the first power tube Q1 and the second power tube Q2 and a common junction point of the third power tube Q3 and the fourth power tube Q4, and the output inductor Lo is connected between a common junction point of the second power tube Q2 and the third power tube Q3 and an output end of the three-level voltage reduction unit 21. That is, the first conduction end of the first power tube Q1 is used as the input end of the three-level buck unit 21, the second conduction end of the first power tube Q1 is connected to the first conduction end of the second power tube Q2, the second conduction end of the second power tube Q2 is connected to the first conduction end of the third power tube Q3, the second conduction end of the third power tube Q3 is connected to the first conduction end of the fourth power tube Q4, the second conduction end of the fourth power tube Q4 is grounded, the first end of the flying capacitor Cfly is connected to the common point (i.e., the second conduction end of the first power tube Q1) between the first power tube Q1 and the second power tube Q2, the second end of the flying capacitor Cfly is connected to the common point (i.e., the second conduction end of the third power tube Q3) between the third power tube Q3 and the fourth power tube Q4, the first end of the output inductor Lo is connected to the common point (i.e., the second conduction end of the second power tube Q2) between the second power tube Q3, and the output end of the third power tube Q2 is used as the output end of the buck unit 21.

The three-level voltage-reducing unit 21 is configured to perform voltage-reducing processing on a voltage signal received by an input terminal of the three-level voltage-reducing unit 21 based on the first switch driving signal after being turned on, and output the voltage signal after the voltage-reducing processing through an output terminal of the three-level voltage-reducing unit 21. The first switch driving signal may include a first driving signal S1 for driving the first power transistor Q1, a second driving signal S2 for driving the second power transistor Q2, a third driving signal S3 for driving the third power transistor Q3, and a fourth driving signal S4 for driving the fourth power transistor Q4. It should be noted that the first driving signal S1 and the fourth driving signal S4 are a pair of complementary driving signals, and the second driving signal S2 and the third driving signal S3 are also a pair of complementary driving signals; the phase difference between the first driving signal S1 and the second driving signal S2 is 180 degrees, and the phase difference between the third driving signal S3 and the fourth driving signal S4 is also 180 degrees. The duty ratio of the first driving signal S1 and the duty ratio of the second driving signal S2 may be determined according to an actual output voltage of the transformer circuit.

The voltage adjusting unit 22 is connected between the input terminal of the three-level step-down unit 21 and ground, and the voltage adjusting unit 22 is connected to the flying capacitor Cfly. Specifically, the voltage adjusting unit 22 may include an adjusting capacitance Cb. The voltage adjusting unit 22 is configured to control the adjusting capacitor Cb and the flying capacitor Cfly to alternately switch between a series connection state and a parallel connection state based on the second switch driving signal after being turned on. The series connection state refers to a connection state in which the flying capacitor Cfly and the adjusting capacitor Cb are sequentially connected in series between the input end of the three-level voltage reducing unit 21 and the ground.

In a possible implementation manner, as shown in fig. 2, the voltage regulating unit 22 may further include a fifth power tube Q5, a sixth power tube Q6, a seventh power tube Q7, and an eighth power tube Q8, which are sequentially connected in series between the input end of the three-level voltage dropping unit 21 and the ground. That is, the first conduction end of the fifth power transistor Q5 is connected to the input end of the three-level voltage-reducing unit 21, the second conduction end of the fifth power transistor Q5 is connected to the first conduction end of the sixth power transistor Q6, the second conduction end of the sixth power transistor Q6 is connected to the first conduction end of the seventh power transistor Q7, the second conduction end of the seventh power transistor Q7 is connected to the first conduction end of the eighth power transistor Q8, and the second conduction end of the eighth power transistor Q8 is grounded. A first end of the adjusting capacitor Cb is connected to a common point (i.e., the second conducting end of the sixth power transistor Q6) between the sixth power transistor Q6 and the seventh power transistor Q7, a second end of the adjusting capacitor Cb is grounded, a common point (i.e., the second conducting end of the fifth power transistor Q5) between the fifth power transistor Q5 and the sixth power transistor Q6 is connected to the first end of the flying capacitor Cfly, and a common point (i.e., the second conducting end of the seventh power transistor Q7) between the seventh power transistor Q7 and the eighth power transistor Q8 is connected to the second end of the flying capacitor Cfly. Of course, in other implementations, the voltage regulating unit 22 may also adopt other circuit structures, and is not limited herein.

Based on this, the second switching driving signals may include a fifth driving signal S5 for driving the fifth power transistor Q5, a sixth driving signal S6 for driving the sixth power transistor Q6, a seventh driving signal S7 for driving the seventh power transistor Q7, and an eighth driving signal S8 for driving the eighth power transistor Q8. It should be noted that, when the voltage adjusting unit 22 works, the fifth power tube Q5 and the seventh power tube Q7 are driven by the fifth driving signal S5 and the seventh driving signal S7 to be turned on simultaneously, the sixth power tube Q6 and the eighth power tube Q8 are driven by the sixth driving signal S6 and the eighth driving signal S8 to be turned on simultaneously, the fifth power tube Q5/the seventh power tube Q7 and the sixth power tube Q6/the eighth power tube Q8 are alternately turned on, and the time for alternately turning on the fifth power tube Q5/the seventh power tube Q7 and the sixth power tube Q6/the eighth power tube Q8 may be equal or unequal.

The transformation control unit 23 may be connected with the three-level voltage dropping unit 21 and the voltage adjusting unit 22. Specifically, the transformation control unit 23 may be connected to a controlled end of the first power transistor Q1, a controlled end of the second power transistor Q2, a controlled end of the third power transistor Q3, a controlled end of the fourth power transistor Q4, a controlled end of the fifth power transistor Q5, a controlled end of the sixth power transistor Q6, a controlled end of the seventh power transistor Q7, and a controlled end of the eighth power transistor Q8. The voltage transformation control unit 23 is configured to, when the voltage transformation circuit is powered on, start the voltage regulation unit 22 first, and start the three-level voltage reduction unit 21 after a first preset time period after the voltage regulation unit 22 is started; and the voltage regulating unit 22 is used for firstly closing the three-level voltage reducing unit 21 when the voltage transformation circuit is powered off and then closing the voltage regulating unit after a second preset time after the three-level voltage reducing unit 21 is closed.

The first preset time period may be a time period that the voltage across the flying capacitor Cfly can be precharged to about half of the input voltage Vin of the three-level voltage-reducing unit 21. The first preset time length and the second preset time length can be obtained through experimental measurement in advance, and specific values of the first preset time length and the second preset time length are not particularly limited.

It should be noted that the voltage transformation control unit 23 further outputs the second switch driving signal to the voltage adjustment unit 22 when the voltage adjustment unit 22 is turned on, and the voltage transformation control unit 23 further outputs the first switch driving signal to the three-level voltage reduction unit 21 when the three-level voltage reduction unit 21 is turned on. After the voltage adjusting unit 22 is turned on, the fifth power tube Q5 and the seventh power tube Q7 are simultaneously turned on under the driving of the fifth driving signal S5 and the seventh driving signal S7, respectively, at this time, the sixth power tube Q6 and the eighth power tube Q8 are both turned off, and the flying capacitor Cfly and the adjusting capacitor Cb are connected in series between the input end of the three-level voltage dropping unit 21 and the ground, so Vin = V _Cfly +V _Cb Wherein Vin is the input voltage of the three-level voltage-reducing unit 21, V _Cfly Is the voltage across the flying capacitor Cfly, V _Cb To regulate the voltage across capacitor Cb; then, the fifth power tube Q5 and the seventh power tube Q7 are both turned off, the sixth power tube Q6 and the eighth power tube Q8 are respectively driven by the sixth driving signal S6 and the eighth driving signal S8 to be simultaneously turned on, at this time, the flying capacitor Cfly and the adjusting capacitor Cb are connected in parallel, and V _Cfly =V _Cb (ii) a Therefore, when the voltage regulating unit 22 reaches the steady state, the voltage V across the flying capacitor Cfly _Cfly And the voltage V at two ends of the regulating capacitor Cb _Cb Equal to each other, which is half of the input voltage Vin of the three-level voltage-decreasing unit 21.

In a specific application, the first power transistor Q1, the second power transistor Q2, the third power transistor Q3, the fourth power transistor Q4, the fifth power transistor Q5, the sixth power transistor Q6, the seventh power transistor Q7, and the eighth power transistor Q8 may be metal-oxide-semiconductor field-effect transistors (MOSFETs), triodes, or the like, and are specifically set according to actual requirements, and the type of each switching transistor is not particularly limited herein. For example, the first power transistor Q1, the second power transistor Q2, the third power transistor Q3, the fourth power transistor Q4, the fifth power transistor Q5, the sixth power transistor Q6, the seventh power transistor Q7, and the eighth power transistor Q8 may be N-type MOSFETs. For example, when the first switch Q1 is an N-type MOSFET, the drain of the N-type MOSFET is the first conducting terminal of the first switch Q1, the source of the N-type MOSFET is the second conducting terminal of the first switch Q1, and the gate of the N-type MOSFET is the controlled terminal of the first switch Q1.

Fig. 3 is a schematic structural diagram of a transformer circuit according to another embodiment of the present application. As shown in fig. 3, the difference between the present embodiment and the corresponding embodiment in fig. 2 is that the variable voltage control unit 23 in the present embodiment may specifically include a first driving control unit 231, a second driving control unit 232, a start-stop control unit 233, and a clock synchronization unit 234.

The clock end of the first driving control unit 231 and the clock end of the second driving control unit 232 are commonly connected to the clock synchronization end of the clock synchronization unit 234, the first driving control unit 231 is further connected to the controlled end of the first power tube Q1, the controlled end of the second power tube Q2, the controlled end of the third power tube Q3, the controlled end of the fourth power tube Q4, the output end OUT of the voltage transformation circuit, and the first control end of the start-stop control unit 233, and the second driving control unit 232 is further connected to the controlled end of the fifth power tube Q5, the controlled end of the sixth power tube Q6, the controlled end of the seventh power tube Q7, the controlled end of the eighth power tube Q8, and the second control end of the start-stop control unit 233.

Specifically, the clock synchronization unit 234 is configured to generate a clock synchronization signal CLK and output the clock synchronization signal CLK to the first drive control unit 231 and the second drive control unit 232 to synchronize clocks of the first drive control unit 231 and the second drive control unit 232.

The first driving control unit 231 is configured to generate a first switch driving signal and output the first switch driving signal to the three-level voltage reduction unit 21 when receiving the first enable signal EN1 from the start-stop control unit 233 and the value of the first enable signal EN1 is 1; and a step-down unit 21 for stopping outputting the first switch driving signal to the three-level step-down unit when the first enable signal EN1 from the start-stop control unit 233 is received and the value of the first enable signal EN1 is 0.

The second driving control unit 231 is configured to generate a second switch driving signal and output the second switch driving signal to the voltage adjusting unit 22 when receiving the second enable signal EN2 from the start-stop control unit 233 and the value of the second enable signal EN2 is 1; and is configured to stop outputting the second switch driving signal to the voltage adjusting unit 22 when the second enable signal EN2 is received from the start-stop control unit 233 and the value of the second enable signal EN2 is 0.

The start-stop control unit 233 is configured to output a second enable signal with a value of 1 to the second drive control unit 232 first when the voltage transformation circuit is powered on, and output a first enable signal with a value of 1 to the first drive control unit 231 after a first preset time period after the second enable signal with a value of 1 is output; and a second driving control unit 232 for outputting a first enable signal with a value of 0 to the first driving control unit 231 and outputting a second enable signal with a value of 0 after a second preset time period after the first enable signal with a value of 0 is output when the voltage transformation circuit is powered off.

Still referring to fig. 3, in an embodiment of the present application, the first driving control unit 231 may include a first driving signal generating unit 2311 and a first driving unit 2312. A first input end of the first driving signal generating unit 2311 is used as a clock end of the first driving control unit 231, a second input end of the first driving signal generating unit 2311 is connected to the output end OUT of the voltage transformation circuit, a controlled end of the first driving signal generating unit 2311 is connected to a first control end of the start-stop control unit 233, a first output end, a second output end, a third output end and a fourth output end of the first driving signal generating unit 2311 are respectively connected to a first input end, a second input end, a third input end and a fourth input end of the first driving unit 2312, a first output end of the first driving unit 2312 is connected to the controlled end of the first power tube Q1, a second output end of the first driving unit 2312 is connected to the controlled end of the fourth power tube Q4, a third output end of the first driving unit 2312 is connected to the controlled end of the second power tube Q2, and a fourth output end of the first driving unit 2312 is connected to the controlled end of the third power tube Q3.

The first driving signal generating unit 2311 is configured to generate a first switch driving signal based on the clock synchronization signal CLK and a voltage signal at an output terminal of the voltage transforming circuit when receiving the first enable signal from the start-stop control unit 233 and a value of the first enable signal is 1, and output the first switch driving signal to the first driving unit 2312.

The first driving unit 2312 is configured to drive and control the first power transistor Q1, the second power transistor Q2, the third power transistor Q3, and the fourth power transistor Q4 based on the first switching driving signal.

In another specific embodiment of the present application, the second driving control unit 232 may include a second driving signal generating unit 2321 and a second driving unit 2322. An input end of the second driving signal generating unit 2321 serves as a clock end of the second driving control unit 232, a controlled end of the second driving signal generating unit 2321 is connected to the second control end of the start-stop control unit 233, a first output end, a second output end, a third output end and a fourth output end of the second driving signal generating unit 2321 are respectively connected to the first input end, the second input end, the third input end and the fourth input end of the second driving unit 2322, a first output end of the second driving unit 2322 is connected to the controlled end of the fifth power tube Q5, a second output end of the second driving unit 2322 is connected to the controlled end of the seventh power tube Q7, a third output end of the second driving unit 2322 is connected to the controlled end of the sixth power tube Q6, and a fourth output end of the second driving unit 2322 is connected to the controlled end of the eighth power tube Q8.

The second driving signal generating unit 2321 is configured to generate a second switching driving signal based on the clock synchronization signal CLK and output the second switching driving signal to the second driving unit 2322 when the second enable signal is received from the start-stop control unit 233 and the value of the second enable signal is 1.

The second driving unit 2322 is configured to drive and control the fifth power transistor Q5, the sixth power transistor Q6, the seventh power transistor Q7 and the eighth power transistor Q8 based on the second switching driving signal.

Fig. 4 is a schematic circuit diagram of a transformer circuit according to an embodiment of the present disclosure. As shown in fig. 4, in the present embodiment, the first driving signal generating unit 2311 may include an output voltage adjusting unit 23111, a PWM modulating unit 23112, a first inverter U2, a second inverter U4, a first buffer U3 and a second buffer U5.

An output voltage feedback end of the output voltage adjusting unit 23111 serves as a second output end of the first driving signal generating unit 2311, a reference voltage end of the output voltage adjusting unit 23111 is used for receiving a reference voltage signal, an output end of the output voltage adjusting unit 23111 is connected with a first input end of the PWM modulating unit 23112, a second input end of the PWM modulating unit 23112 serves as a first input end of the first driving signal generating unit 2311, a first output end of the PWM modulating unit 23112 is connected with an input end of the first inverter U2 and an input end of the first buffer U3, a second output end of the PWM modulating unit 23112 is connected with an input end of the second inverter U4 and an input end of the second buffer U5, an output end of the first inverter U2 serves as a third output end of the first driving signal generating unit 2311, an output end of the first buffer U3 serves as a second output end of the first driving signal generating unit 2311, and an output end of the second inverter U4 serves as a fourth output end of the first driving signal generating unit 2311. The first output end, the second output end, the third output end and the fourth output end of the first driving signal generating unit 2311 are respectively used for outputting a first driving signal S1, a second driving signal S2, a third driving signal S3 and a fourth driving signal S4.

In a specific application, the output voltage regulating unit 23111 may include an operational amplifier U1. The non-inverting input terminal of the operational amplifier U1 serves as the reference voltage terminal of the output voltage adjusting unit 23111, the inverting input terminal of the operational amplifier U1 serves as the output voltage feedback terminal of the output voltage adjusting unit 23111, and the output terminal of the operational amplifier U1 serves as the output terminal of the output voltage adjusting unit 23111.

The second driving signal generation unit 2312 may include a first frequency divider 23211, a third inverter U7, a first and gate U8, and a fourth inverter U9.

An input end of the first frequency divider 23211 serves as a clock end of the second driving signal generation unit 2312, an output end of the first frequency divider 23211 is connected to a first input end of the first and gate U8, a second input end of the first and gate U8 is connected to an output end of the third inverter U7, an input end of the third inverter U7 is connected to an output end of the second inverter U4, an output end of the first and gate U8 is connected to an input end of the fourth inverter U9, an output end of the first and gate U8 serves as a first output end and a third output end of the second driving signal generation unit 2312 at the same time, and an output end of the fourth inverter U9 serves as a second output end and a fourth output end of the second driving signal generation unit 2312 at the same time. The first output terminal, the second output terminal, the third output terminal and the fourth output terminal of the second driving signal generating unit 2312 are respectively used for outputting a fifth driving signal S5, a sixth driving signal S6, a seventh driving signal S7 and an eighth driving signal S8.

In a particular application, the first frequency divider 23211 may include a first D flip-flop U6. The clock pin CLK1 of the first D flip-flop U6 is used as the input terminal of the first frequency divider 23211, and the data pin D1 and the first output pin of the first D flip-flop U6

Connected to a second output pin of the first D flip-flop U6Q1 serves as the output of the first frequency divider 23211.

The operation principle of the transformer circuit provided by the embodiment of the present application is described in detail below with reference to fig. 4.

As shown in fig. 4, the operational amplifier U1 in the first driving signal generation unit 2311 generates an error voltage signal Verr based on the voltage signal Vout at the output terminal of the voltage transformation circuit and the reference voltage signal Vref, and outputs the error voltage signal Verr to the PWM modulation unit 23112. For example, the error voltage signal Verr may be a difference between the voltage signal Vout at the output of the voltage-varying circuit and the reference voltage signal Vref. The PWM modulation unit 23112 may generate two pulse width modulation signals S1 'and S2' with a phase difference of 180 degrees according to the clock synchronization signal CLK generated by the clock synchronization unit 234 and the error voltage signal Verr, and output the pulse width modulation signal S1 'to the input end of the second inverter U4 and the input end of the second buffer U5, and output the pulse width modulation signal S2' to the input end of the first inverter U2 and the input end of the first buffer U3; the second inverter U4 performs inverse buffering on the pulse width modulation signal S1 'and outputs a fourth driving signal S4, and the second buffer U5 performs buffering on the pulse width modulation signal S1' and outputs a first driving signal S1; the first inverter U2 performs inversion buffering on the pulse width modulation signal S2 'and then outputs a third driving signal S3, and the first buffer U3 performs buffering on the pulse width modulation signal S2' and then outputs a second driving signal S2; the first driving unit 2321 respectively controls the driving of the first power tube Q1, the second power tube Q2, the third power tube Q3 and the fourth power tube Q4 based on the first driving signal S1, the second driving signal S2, the third driving signal S3 and the fourth driving signal S4.

The first frequency divider 23211 in the second driving signal generating unit 2321 performs frequency division processing on the clock synchronization signal CLK from the clock synchronization unit 234 to generate a square wave signal S3 'with a duty ratio of 50%, and outputs the square wave signal S3' to the first input end of the first and gate U8; the third inverter U7 performs inverse buffering on the fourth driving signal S4 from the second inverter U4 and outputs an inverse signal of the fourth driving signal S4

The first and gate U8 inverts the square wave signal S3' and the fourth driving signal S4

Outputting a square wave signal S4' after AND operation; on the one hand, the square wave signal S4 'can be used as the fifth driving signal S5 and the seventh driving signal S7, and on the other hand, the square wave signal S4' is inverted and buffered by the fourth inverter U9 to be used as the sixth driving signal S6 and the eighth driving signal S8.

When the voltage transformation circuit is powered on, the start-stop control unit 233 may output the second enable signal EN2 with a value of 1 to the second drive signal generation unit 2321, and the second drive signal generation unit 2321 receives the second enable signal EN2 with a value of 1 and then outputs the fifth drive signal S5, the sixth drive signal S6, the seventh drive signal S7, and the eighth drive signal S8 to respectively drive the fifth power tube Q5, the sixth power tube Q6, the seventh power tube Q7, and the eighth power tube Q8 to operate, at this time, the first drive signal generation unit 2311 does not output a signal, that is, the three-level voltage reduction unit 21 is in a closed state at this time; after the start-stop control unit 233 outputs the second enable signal EN2 with a value of 1 for a first preset time period, the first enable signal EN1 with a value of 1 may be output to the first driving signal generation unit 2311, and the first driving signal generation unit 2311 outputs the first driving signal S1, the second driving signal S2, the third driving signal S3, and the fourth driving signal S4 after receiving the first enable signal EN1 with a value of 1, so as to respectively drive the first power tube Q1, the second power tube Q2, the third power tube Q3, and the fourth power tube Q4 to operate.

When the transformer is powered off, the start-stop control unit 233 may output the first enable signal EN1 with a value of 0 to the first driving signal generation unit 2311, and at this time, the first driving signal generation unit 2311 does not output a signal to turn off the three-level voltage reduction unit 21; after a second preset time period after the start-stop control unit 233 outputs the first enable signal EN1 with a value of 0, the second enable signal EN2 with a value of 0 may be output to the second driving signal generating unit 2321, and at this time, the second driving signal generating unit 2321 does not output a signal to turn off the voltage adjusting unit 22.

For example, fig. 5A is a waveform diagram of the driving signal of each power tube in the transformer circuit corresponding to fig. 4 in one switching period when the duty ratio of the first power tube Q1 is less than 50%.

As shown in fig. 5A, in the period [ T0, T1] of the current switching cycle, the first driving signal S1, the third driving signal S3, the fifth driving signal S5, and the seventh driving signal S7 are all at a high level, at this time, the first power tube Q1, the third power tube Q3, the fifth power tube Q5, and the seventh power tube Q7 are simultaneously turned on, the voltage signal at the input end of the three-level step-down unit 21 passes through the first power tube Q1, the flying capacitor Cfly, and the third power tube Q3 to charge the output inductor Lo and the output end OUT of the three-level step-down unit 21, and at the same time, the flying capacitor Cfly and the adjusting capacitor Cb are connected in series between the input end of the three-level step-down unit 21 and the ground by the fifth power tube Q5 and the seventh power tube Q7. In this case, the voltage Vsw of the common junction of the second power transistor Q2 and the third power transistor Q3 is about half (i.e., vin/2) of the input voltage Vin of the three-level step-down unit 21, and the current flowing through the output inductor Lo is increased.

In the period of [ T1, T2] of the current switching cycle, the third driving signal S3, the fourth driving signal S4, the sixth driving signal S6, and the eighth driving signal S8 are all at a high level, at this time, the third power tube Q3, the fourth power tube Q4, the sixth power tube Q6, and the eighth power tube Q8 are simultaneously turned on, the output inductor Lo performs follow current discharge through the third power tube Q3 and the fourth power tube Q4, and the flying capacitor Cfly and the adjusting capacitor Cb are connected in parallel by the sixth power tube Q6 and the eighth power tube Q8. In this case, the voltage Vsw of the common node between the second power transistor Q2 and the third power transistor Q3 is 0, and the current flowing through the output inductor Lo is decreased.

In the period of [ T2, T3] of the current switching cycle, the second driving signal S2, the fourth driving signal S4, the sixth driving signal S6, and the eighth driving signal S8 are all at a high level, at this time, the second power tube Q2, the fourth power tube Q4, the sixth power tube Q6, and the eighth power tube Q8 are simultaneously turned on, the flying capacitor Cfly charges the output inductor Lo and the output end OUT of the three-level voltage-reducing unit 21 through the second power tube Q2 and the fourth power tube Q4, and at this time, the flying capacitor Cfly and the adjusting capacitor Cb are connected in parallel by the sixth power tube Q6 and the eighth power tube Q8. In this case, the voltage Vsw of the common junction of the second power transistor Q2 and the third power transistor Q3 is about half (i.e., vin/2) of the input voltage Vin of the three-level step-down unit 21, and the current flowing through the output inductor Lo is increased.

In the period [ T3, T4] of the current switching cycle, the on-off state of each power tube is consistent with the period [ T1, T2], so that in the period [ T3, T4], the flying capacitor Cfly and the adjusting capacitor Cb are also in a parallel connection state. In this case, the voltage Vsw of the common node between the second power transistor Q2 and the third power transistor Q3 is 0, and the current flowing through the output inductor Lo is decreased.

It can be understood that the driving signal of each power transistor in the next switching period is the same as the driving signal of each power transistor in the current switching period, and the description thereof is omitted here.

It can be seen that the flying capacitor Cfly and the regulating capacitor Cb are connected in series during the period T0, T1 of each switching cycle, and are connected in parallel during the period T1, T4 of each switching cycle. When the flying capacitor Cfly and the adjusting capacitor Cb are connected in series, the sum of the voltages at the two ends of the flying capacitor Cfly and the voltages at the two ends of the adjusting capacitor Cb is the input voltage Vin of the three-level voltage dropping unit 21, and when the flying capacitor Cfly and the adjusting capacitor Cb are connected in parallel, the voltages at the two ends of the flying capacitor Cfly are equal to the voltages at the two ends of the adjusting capacitor Cb, therefore, when the voltage adjusting unit 22 works alone, the voltages at the two ends of the flying capacitor Cfly can be about half of the input voltage Vin of the three-level voltage dropping unit 21, based on this, the start control unit 233 starts the voltage adjusting unit 22 when the voltage transforming circuit is powered on, can precharge the voltages at the two ends of the flying capacitor Cfly to about half of the input voltage Vin of the three-level voltage dropping unit 21, and then the start the control unit 233 to start the three-level voltage dropping unit 21 again, can maintain the voltages at the two ends of the flying capacitor Cfly at about half of the input voltage Vin of the three-level voltage dropping unit 21 when and after the three-level voltage dropping unit 21 is started, which not only can reduce the cost of the transforming circuit, but also can improve the efficiency of the transforming circuit.

For example, fig. 5B is a waveform diagram of a driving signal of each power tube in the transformer circuit corresponding to fig. 4 in one switching period when the duty ratio of the first power tube Q1 is greater than 50%.

As shown in fig. 5B, in the period [ T0, T1] of the current switching cycle, the first driving signal S1, the second driving signal S2, the fifth driving signal S5, and the seventh driving signal S7 are all at a high level, at this time, the first power tube Q1, the second power tube Q2, the fifth power tube Q5, and the seventh power tube Q7 are simultaneously turned on, the voltage signal at the input end of the three-level step-down unit 21 passes through the first power tube Q1 and the second power tube Q2 to charge the output inductor Lo and the output end OUT of the three-level step-down unit 21, and at the same time, the fifth power tube Q5 and the seventh power tube Q7 connect the flying capacitor Cfly and the regulating capacitor Cb in series between the input end of the three-level step-down unit 21 and the ground. In this case, the voltage Vsw of the common node of the second power transistor Q2 and the third power transistor Q3 is equal to the input voltage Vin of the three-level step-down unit 21, and the current flowing through the output inductor Lo continuously increases.

In the period of [ T1, T2] of the current switching cycle, the first driving signal S1, the third driving signal S3, the fifth driving signal S5, and the seventh driving signal S7 are all at a high level, at this time, the first power tube Q1, the third power tube Q3, the fifth power tube Q5, and the seventh power tube Q7 are simultaneously turned on, a voltage signal at the input end of the three-level step-down unit 21 passes through the first power tube Q1, the flying capacitor Cfly, the third power tube Q3, and the output inductor Lo to charge the output end OUT of the three-level step-down unit 21, and at the same time, the flying capacitor Cfly and the regulating capacitor Cb are connected in series between the input end of the three-level step-down unit 21 and the ground by the fifth power tube Q5 and the seventh power tube Q7. In this case, the voltage Vsw of the common junction of the second power transistor Q2 and the third power transistor Q3 is about half (i.e., vin/2) of the input voltage Vin of the three-level step-down unit 21, is lower than the voltage Vout of the output terminal of the three-level step-down unit 21, and the current flowing through the output inductor Lo is continuously reduced.

In the period of [ T2, T3] of the current switching cycle, the first driving signal S1, the second driving signal S2, the sixth driving signal S6, and the eighth driving signal S8 are all at a high level, at this time, the first power tube Q1, the second power tube Q2, the sixth power tube Q6, and the eighth power tube Q8 are simultaneously turned on, a voltage signal at the input end of the three-level step-down unit 21 charges the output inductor Lo and the output end OUT of the three-level step-down unit 21 through the first power tube Q1 and the second power tube Q2, and simultaneously, the flying capacitor Cfly and the regulating capacitor Cb are connected in parallel by the sixth power tube Q6 and the eighth power tube Q8. In this case, the voltage Vsw of the common node of the second power transistor Q2 and the third power transistor Q3 is equal to the input voltage Vin of the three-level step-down unit 21, and the current flowing through the output inductor Lo continuously increases.

In the period of [ T3, T4] of the current switching cycle, the second driving signal S2, the fourth driving signal S4, the sixth driving signal S6, and the eighth driving signal S8 are all at a high level, at this time, the second power tube Q2, the fourth power tube Q4, the sixth power tube Q6, and the eighth power tube Q8 are simultaneously turned on, the flying capacitor Cfly charges the output inductor Lo and the output end OUT of the three-level voltage-reducing unit 21 through the second power tube Q2 and the fourth power tube Q4, and at this time, the flying capacitor Cfly and the adjusting capacitor Cb are connected in parallel by the sixth power tube Q6 and the eighth power tube Q8. In this case, the voltage Vsw of the common junction of the second power transistor Q2 and the third power transistor Q3 is about half (i.e., vin/2) of the input voltage Vin of the three-level step-down unit 21, and the current flowing through the output inductor Lo is continuously decreased.

It can be seen that the flying capacitor Cfly and the adjusting capacitor Cb are connected in series during the period T0, T2 of each switching cycle, and are connected in parallel during the period T2, T4 of each switching cycle. Based on the same driving principle as that in fig. 5A, the driving signal corresponding to fig. 5B can reduce the cost of the transformer circuit and improve the power conversion efficiency of the transformer circuit.

In yet another embodiment of the present application, as shown in fig. 6, the second driving signal generating unit 2321 may further include a second frequency divider 23212, a fifth inverter U11, a sixth inverter U12, a second and gate U13, and a third and gate U14.

An input end of the second frequency divider 23212 serves as a clock end of the second driving signal generating unit 2321, a first output end of the second frequency divider 23212 is connected to a first input end of the second and-gate U13, a second output end of the second frequency divider 23212 is connected to a first input end of the third and-gate U14, a second input end of the second and-gate U13 is connected to an output end of the sixth inverter U12, a second input end of the third and-gate U14 is connected to an output end of the fifth inverter U11, an input end of the fifth inverter U11 is connected to an output end of the second buffer U5, an input end of the sixth inverter U12 is connected to an output end of the second inverter U4, an output end of the second and-gate U13 serves as a first output end and a third output end of the second driving signal generating unit 2312 at the same time, and an output end of the third and-gate U14 serves as a second output end and a fourth output end of the second driving signal generating unit 2312 at the same time. It should be noted that the first output terminal, the second output terminal, the third output terminal and the fourth output terminal of the second driving signal generating unit 2312 are respectively used for outputting a fifth driving signal S5, a sixth driving signal S6, a seventh driving signal S7 and an eighth driving signal S8.

In a particular application, the second frequency divider 23212 may include a second D flip-flop U10. The clock pin CLK2 of the second D flip-flop U10 serves as an input terminal of the second frequency divider 23212, and the data pin D1 and the first output pin of the second D flip-flop U10

Connected and the data pin D1 and the first output pin of the second D flip-flop U10

As a second output terminal of the second frequency divider 23212, and a second output pin of the second D flip-flop U10Q2 as a first output of the second frequency divider 23212.

The operation principle of the transformer circuit provided in the embodiment of the present application is described in detail below with reference to fig. 6.

It should be noted that, since the specific structure of the first driving signal generation unit 2311 in fig. 6 is the same as the specific structure of the first driving signal generation unit 2311 in fig. 4, the operation principle of the first driving signal generation unit 2311 in fig. 6 may refer to the description in the embodiment corresponding to fig. 4, and is not repeated herein.

As shown in fig. 6, the first frequency divider 23211 in the second driving signal generating unit 2321 performs frequency division processing on the clock synchronizing signal CLK from the clock synchronizing unit 234 to generate a pair of complementary square wave signals S3 'and S5' with duty ratios of 50%, and outputs the square wave signal S3 'to the first input terminal of the second and gate U13 and the square wave signal S5' to the first input terminal of the third and gate U14; the fifth inverter U11 performs inverse buffering on the first driving signal S1 from the second buffer U5, and outputs an inverse signal of the first driving signal S1

To a second input of the third AND-gate U14, a sixth inverter U12 couples a fourth drive signal from the second inverter U4The signal S4 is subjected to phase inversion buffering and then outputs an inverted signal of the fourth driving signal S4

To a second input of the second and gate U13; the second AND gate U13 inverts the square wave signal S3' and the fourth driving signal S4

Outputting a square wave signal S6 'after performing AND operation, wherein the square wave signal S6' can be used as a fifth driving signal S5 and a seventh driving signal S7; the third and gate U14 provides the square wave signal S5' and the inverse of the first driving signal S1

The and operation is performed to output a square wave signal S7', and the square wave signal S7' can be used as the sixth driving signal S6 and the eighth driving signal S8.

When the voltage transformation circuit is powered on, the start-stop control unit 233 may output the second enable signal EN2 with a value of 1 to the second drive signal generation unit 2321, and after receiving the second enable signal EN2 with a value of 1, the second drive signal generation unit 2321 outputs the fifth drive signal S5, the sixth drive signal S6, the seventh drive signal S7, and the eighth drive signal S8 to respectively drive the fifth power tube Q5, the sixth power tube Q6, the seventh power tube Q7, and the eighth power tube Q8 to operate, at this time, the first drive signal generation unit 2311 does not output a signal, that is, the three-level voltage reduction unit 21 is in a closed state at this time; after the start-stop control unit 233 outputs the second enable signal EN2 with a value of 1 for a first preset time period, the first enable signal EN1 with a value of 1 may be output to the first driving signal generation unit 2311, and the first driving signal generation unit 2311 outputs the first driving signal S1, the second driving signal S2, the third driving signal S3, and the fourth driving signal S4 after receiving the first enable signal EN1 with a value of 1, so as to respectively drive the first power tube Q1, the second power tube Q2, the third power tube Q3, and the fourth power tube Q4 to operate.

When the transformer is powered off, the start-stop control unit 233 may output the first enable signal EN1 with a value of 0 to the first driving signal generation unit 2311, and at this time, the first driving signal generation unit 2311 does not output a signal to turn off the three-level voltage reduction unit 21; after the start-stop control unit 233 outputs the first enable signal EN1 with a value of 0 for a second preset time period, the second enable signal EN2 with a value of 0 may be output to the second driving signal generating unit 2321, and at this time, the second driving signal generating unit 2321 does not output a signal to turn off the voltage adjusting unit 22.

For example, fig. 7A is a waveform diagram of the driving signal of each power tube in the transformer circuit corresponding to fig. 6 in one switching period when the duty ratio of the first power tube Q1 is less than 50%.

As shown in fig. 7A, in the period [ T0, T1] of the current switching cycle, the first driving signal S1, the third driving signal S3, the fifth driving signal S5, and the seventh driving signal S7 are all at a high level, at this time, the first power tube Q1, the third power tube Q3, the fifth power tube Q5, and the seventh power tube Q7 are simultaneously turned on, the voltage signal at the input end of the three-level step-down unit 21 passes through the first power tube Q1, the flying capacitor Cfly, and the third power tube Q3 to charge the output inductor Lo and the output end OUT of the three-level step-down unit 21, and at the same time, the flying capacitor Cfly and the adjusting capacitor Cb are connected in series between the input end of the three-level step-down unit 21 and the ground by the fifth power tube Q5 and the seventh power tube Q7. In this case, the voltage Vsw of the common junction of the second power transistor Q2 and the third power transistor Q3 is about half (i.e., vin/2) of the input voltage Vin of the three-level step-down unit 21, and the current flowing through the output inductor Lo is increased.

In the period [ T1, T2] of the current switching cycle, the third driving signal S3 and the fourth driving signal S4 are both at a high level, at this time, the third power tube Q3 and the fourth power tube Q4 are simultaneously turned on, the remaining power tubes are all turned off, the output inductor Lo carries OUT follow current discharge on the output end OUT of the three-level voltage reduction unit 21 through the third power tube Q3 and the fourth power tube Q4, and at this time, the flying capacitor Cfly is not connected to the regulating capacitor Cb. In this case, the voltage Vsw of the common junction between the second power transistor Q2 and the third power transistor Q3 is 0, and the current flowing through the output inductor Lo decreases.

In the period of [ T3, T4] of the current switching cycle, the third driving signal S3, the fourth driving signal S4, the sixth driving signal S6, and the eighth driving signal S8 are all at a high level, at this time, the third power tube Q3, the fourth power tube Q4, the sixth power tube Q6, and the eighth power tube Q8 are simultaneously turned on, the output inductor Lo performs follow current discharge on the output end OUT of the three-level voltage reduction unit 21 through the third power tube Q3 and the fourth power tube Q4, and the flying capacitor Cfly and the adjusting capacitor Cb are connected in parallel by the sixth power tube Q6 and the eighth power tube Q8. In this case, the voltage Vsw of the common junction between the second power transistor Q2 and the third power transistor Q3 is 0, and the current flowing through the output inductor Lo decreases.

It can be seen that the flying capacitor Cfly and the adjusting capacitor Cb are connected in series during the period of [ T0, T1] of each switching cycle, the flying capacitor Cfly and the adjusting capacitor Cb are not connected during the period of [ T1, T2] of each switching cycle, and the flying capacitor Cfly and the adjusting capacitor Cb are connected in parallel during the period of [ T2, T4] of each switching cycle. When the flying capacitor Cfly and the adjusting capacitor Cb are connected in series, the sum of the voltage across the flying capacitor Cfly and the voltage across the adjusting capacitor Cb is the input voltage Vin of the three-level buck unit 21, and when the flying capacitor Cfly and the adjusting capacitor Cb are connected in parallel, the voltage across the flying capacitor Cfly is equal to the voltage across the adjusting capacitor Cb, therefore, when the voltage adjusting unit 22 works alone, the voltage across the flying capacitor Cfly can be about half of the input voltage Vin of the three-level buck unit 21, and based on this, the start control unit 233 starts the voltage adjusting unit 22 when the voltage transformation circuit is powered on, so that the voltage across the flying capacitor Cfly can be precharged to about half of the input voltage Vin of the three-level buck unit 21, and then the start control unit 233 starts the three-level buck unit 21 again, so that the voltages across the flying capacitor Cfly can be maintained at about half of the input voltage Vin of the three-level buck unit 21 when and after the three-level buck unit 21 is started, thereby not only reducing the cost of the voltage transformation circuit, but also improving the efficiency of the transformation circuit.

Fig. 7B is a schematic waveform diagram of a driving signal of each power tube in the transformer circuit corresponding to fig. 6 in one switching period when the duty ratio of the first power tube Q1 is greater than 50%.

As shown in fig. 7B, in the period [ T0, T1] of the current switching cycle, the first driving signal S1, the second driving signal S2, the fifth driving signal S5, and the seventh driving signal S7 are all at a high level, at this time, the first power tube Q1, the second power tube Q2, the fifth power tube Q5, and the seventh power tube Q7 are simultaneously turned on, the voltage signal at the input end of the three-level step-down unit 21 passes through the first power tube Q1 and the second power tube Q2 to charge the output inductor Lo and the output end OUT of the three-level step-down unit 21, and at the same time, the fifth power tube Q5 and the seventh power tube Q7 connect the flying capacitor Cfly and the regulating capacitor Cb in series between the input end of the three-level step-down unit 21 and the ground. In this case, the voltage Vsw of the common node of the second power transistor Q2 and the third power transistor Q3 is equal to the input voltage Vin of the three-level step-down unit 21, and the current flowing through the output inductor Lo continuously increases.

In the period of [ T1, T2] of the current switching cycle, the first driving signal S1 and the third driving signal S3 are both at a high level, at this time, the first power tube Q1 and the third power tube Q3 are simultaneously turned on, the remaining power tubes are all turned off, the voltage signal at the input end of the three-level voltage reduction unit 21 charges the output end OUT of the three-level voltage reduction unit 21 through the first power tube Q1, the flying capacitor Cfly, the third power tube Q3 and the output inductor Lo, and at this time, the adjustment capacitor Cb does not participate in the work. In this case, the voltage Vsw of the common junction of the second power transistor Q2 and the third power transistor Q3 is about half (i.e., vin/2) of the input voltage Vin of the three-level step-down unit 21, is lower than the voltage Vout of the output terminal of the three-level step-down unit 21, and the current flowing through the output inductor Lo is continuously reduced.

In the period of [ T2, T3] of the current switching cycle, the first driving signal S1 and the second driving signal S2 are both at a high level, at this time, the first power tube Q1 and the second power tube Q2 are simultaneously turned on, the remaining power tubes are all turned off, the voltage signal at the input end of the three-level voltage reduction unit 21 charges the output inductor Lo and the output end OUT of the three-level voltage reduction unit 21 through the first power tube Q1 and the second power tube Q2, and at this time, the adjustment capacitor Cb does not participate in the work. In this case, the voltage Vsw of the common node of the second power transistor Q2 and the third power transistor Q3 is equal to the input voltage Vin of the three-level voltage step-down unit 21, and the current flowing through the output inductor Lo continuously increases.

It can be seen that the flying capacitor Cfly and the adjusting capacitor Cb are connected in series during the period T0, T1 of each switching cycle, and are connected in parallel during the period T3, T4 of each switching cycle. Based on the same driving principle as that in fig. 7A, the driving signal corresponding to fig. 7B can reduce the cost of the transformer circuit and improve the power conversion efficiency of the transformer circuit.

Referring to fig. 8, a timing diagram of operations of units in a transformer circuit according to an embodiment of the present disclosure is shown. As shown in fig. 8, in an implementation manner, for example, in combination with fig. 4, if the voltage transformation circuit is powered on at time T5, the start-stop control unit 233 may output the second enable signal EN2 with a value of 1 to the second driving signal generation unit 2321 at time T5, and output the first enable signal with a value of 0 to the first driving signal generation unit 2311, at this time, the first driving unit 2312 does not output the first switch driving signal, the first and gate U8 in the second driving signal generation unit 2321 directly buffers the square wave signal S3 'to obtain the square wave signal S4', at this time, the fifth driving signal S5, the seventh driving signal S7, the sixth driving signal S6, and the eighth driving signal S8 output by the second driving signal generation unit 2321 are equivalent to the driving signal output by the second driving signal generation unit 2321 when the voltage adjustment unit 22 operates alone, and the fifth driving signal S5 (or the seventh driving signal S7) and the sixth driving signal S6 (or the eighth driving signal S8) are complementary to the driving signal fly (i.e., the voltage across the capacitor, such that the voltage drop across the two ends of the flying voltage Vin 21 may be half of the flying voltage conversion unit.

Based on this, the start-stop control unit 233 may output the second enable signal EN2 with a value of 1 to the second driving signal generation unit 2321 at time T5, and simultaneously output the first enable signal EN1 with a value of 0 to the first driving signal generation unit 2311, so as to adjust the voltage V across the flying capacitor Cfly _Cfly Pre-charged to about half of the input voltage Vin of the three-level voltage-decreasing unit 21 (i.e., vin/2); thereafter, at time T7, the start-stop control unit 233 may output the first enable signal EN1 having a value of 1 to the first driving signal generation unit 2311 to turn on the three-level voltage reduction unit 21 so that the three-level voltage reduction unit 21 is at [ T7, T8 ]]All are in working state in time period, because the working state is [ T7, T8 ]]The voltage regulating unit 22 is also always in working state during the time period, so that the voltage V across the flying capacitor Cfly can be ensured in the working process of the three-level voltage reducing unit 21 _Cfly Is always maintained at about half (i.e., vin/2) of the input voltage Vin of the three-level voltage-reducing unit 21; if the voltage transformation circuit is powered off at time T8, the start-stop control unit 233 may first output the first enable signal EN1 with a value of 0 to the first driving signal generation unit 2311, and then, at time T9, the start-stop control unit 233 may output the second enable signal EN2 with a value of 0 to the second driving signal generation unit 2321, so as to ensure that the voltage V across the flying capacitor Cfly is ensured when the transformer is powered off _Cfly Which is also about half the input voltage Vin of the three-level voltage step-down unit 21 (i.e., vin/2). Through the control, the three-level voltage reduction unit 21 can be safely opened, operated and closed, the ripple of current flowing through the output inductor is reduced, the electric energy conversion efficiency of the three-level voltage reduction unit is improved, the three-level voltage reduction unit can adopt a device with lower voltage resistance, and the cost of a transformation circuit is reduced.

It can be understood that the operation timings of the units in the transformer circuit corresponding to fig. 6 are similar to those in fig. 4, and the operation timings of the units in the transformer circuit corresponding to fig. 6 may specifically refer to the above description, which is not repeated herein.

The embodiment of the application also provides the electronic equipment. Please refer to fig. 9, which is a schematic structural diagram of an electronic device according to an embodiment of the present application, and for convenience of description, only a portion related to the embodiment is shown. As shown in fig. 9, the electronic device 90 may include a power port 901, a transformer circuit 902, and a battery 903. The input end of the transformer circuit 902 is connected to the power port 901, and the output end of the transformer circuit 902 is connected to the battery 903. The transforming circuit 902 may be a transforming circuit in the embodiment corresponding to fig. 2, fig. 3, fig. 4, or fig. 6, and for the structure and function of the transforming circuit 902, reference may be specifically made to the description in the embodiment corresponding to fig. 2, fig. 3, fig. 4, or fig. 6, and details thereof are not repeated here.

An input end of the three-level voltage-reducing unit 21 may serve as an input end of the transformer circuit 902, and an output end of the three-level voltage-reducing unit 21 may serve as an output end of the transformer circuit 902.

In a specific application, the electronic device 90 may include, but is not limited to, a mobile phone, a tablet computer, a notebook computer, etc., and the type of the electronic device 90 is not particularly limited herein.

The power port 901 may specifically be a Universal Serial Bus (USB) interface, for example, a type C USB (i.e., USB type-C) interface.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A voltage transformation circuit, comprising:

2. The transformation circuit according to claim 1, wherein the voltage regulation unit further comprises a fifth power transistor, a sixth power transistor, a seventh power transistor and an eighth power transistor sequentially connected in series between the input terminal of the three-level voltage reduction unit and ground;

the first end of the adjusting capacitor is connected with a common junction of the sixth power tube and the seventh power tube, the second end of the adjusting capacitor is grounded, the common junction of the fifth power tube and the sixth power tube is connected with the first end of the flying capacitor, the first end of the flying capacitor is connected with the common junction of the first power tube and the second power tube, the common junction of the seventh power tube and the eighth power tube is connected with the second end of the flying capacitor, and the second end of the flying capacitor is connected with the common junction of the third power tube and the fourth power tube.

3. The transformation circuit according to claim 2, wherein the transformation control unit comprises:

the first driving control unit is connected with the controlled end of the first power tube, the controlled end of the second power tube, the controlled end of the third power tube, the controlled end of the fourth power tube and the output end of the voltage transformation circuit, and is used for generating a first switch driving signal and outputting the first switch driving signal to the three-level voltage reduction unit when a first enabling signal from a start-stop control unit is received and the value of the first enabling signal is 1; the three-level voltage reduction unit is used for stopping outputting the first switch driving signal to the three-level voltage reduction unit when a first enabling signal from the start-stop control unit is received and the value of the first enabling signal is 0;

the second driving control unit is connected with the controlled end of the fifth power tube, the controlled end of the sixth power tube, the controlled end of the seventh power tube and the controlled end of the eighth power tube, and is configured to generate a second switch driving signal and output the second switch driving signal to the voltage adjusting unit when a second enable signal from the start-stop control unit is received and the value of the second enable signal is 1; the control unit is used for stopping outputting the second switch driving signal to the voltage regulating unit when a second enabling signal from the start-stop control unit is received and the value of the second enabling signal is 0;

the clock synchronization end of the clock synchronization unit is connected with the clock end of the first drive control unit and the clock end of the second drive control unit, and the clock synchronization unit is used for generating a clock synchronization signal and outputting the clock synchronization signal to the first drive control unit and the second drive control unit so as to synchronize the clocks of the first drive control unit and the second drive control unit;

a first control end of the start-stop control unit is connected with the first drive control unit, a second control end of the start-stop control unit is connected with the second drive control unit, and the start-stop control unit is used for firstly outputting the second enable signal with the value of 1 when the voltage transformation circuit is powered on, and outputting the first enable signal with the value of 1 after outputting the first preset time length after outputting the second enable signal with the value of 1; and the output circuit is used for outputting the first enable signal with the value of 0 firstly when the transformation circuit is powered off, and outputting the second enable signal with the value of 0 after the second preset time length after the first enable signal with the value of 0 is output.

4. The transformation circuit according to claim 3, wherein the first driving control unit comprises:

a first input end of the first driving signal generating unit is used as a clock end of the first driving control unit, a second input end of the driving signal generating unit is connected with an output end of the voltage transformation circuit, and a controlled end of the first driving signal generating unit is connected with a first control end of the start-stop control unit; the first driving signal generating unit is used for generating a first switch driving signal based on the clock synchronization signal and a voltage signal at the output end of the voltage transformation circuit when the first enabling signal is received and the value of the first enabling signal is 1, and outputting the first switch driving signal to the first driving unit;

the first input end, the second input end, the third input end and the fourth input end of the first driving unit are respectively connected with the first output end, the second output end, the third output end and the fourth output end of the first driving signal generation unit, the first output end of the first driving unit is connected with the controlled end of the first power tube, the second output end of the first driving unit is connected with the controlled end of the fourth power tube, the third output end of the first driving unit is connected with the controlled end of the second power tube, and the fourth output end of the first driving unit is connected with the controlled end of the third power tube; the first driving unit is used for driving and controlling the first power tube, the second power tube, the third power tube and the fourth power tube based on the first switch driving signal.

5. The transformation circuit according to claim 3, wherein the second driving control unit comprises:

the input end of the second driving signal generating unit is used as the clock end of the second driving control unit, and the controlled end of the second driving signal generating unit is connected with the second control end of the start-stop control unit; the second driving signal generating unit is configured to generate the second switch driving signal based on the clock synchronization signal and output the second switch driving signal to a second driving unit when the second enable signal is received and the value of the second enable signal is 1;

the first input end, the second input end, the third input end and the fourth input end of the second driving unit are respectively connected with the first output end, the second output end, the third output end and the fourth output end of the second driving signal generating unit, the first output end of the second driving unit is connected with the controlled end of the fifth power tube, the second output end of the second driving unit is connected with the controlled end of the seventh power tube, the third output end of the second driving unit is connected with the controlled end of the sixth power tube, and the fourth output end of the second driving unit is connected with the controlled end of the eighth power tube; the second driving unit is configured to drive and control the fifth power transistor, the sixth power transistor, the seventh power transistor, and the eighth power transistor based on the second switch driving signal.

6. The transformer circuit of claim 4, wherein the first driving signal generating unit comprises an output voltage adjusting unit, a PWM modulating unit, a first inverter, a second inverter, a first buffer and a second buffer;

the output voltage feedback end of the output voltage regulating unit is used as the second output end of the first driving signal generating unit, the reference voltage end of the output voltage regulating unit is used for receiving a reference voltage signal, the output end of the output voltage regulating unit is connected with the first input end of the PWM modulating unit, the second input end of the PWM modulating unit is used as the first input end of the first driving signal generating unit, the first output end of the PWM modulating unit is connected with the input end of the first phase inverter and the input end of the first buffer, the second output end of the PWM modulating unit is connected with the input end of the second phase inverter and the input end of the second buffer, the output end of the first phase inverter is used as the third output end of the first driving signal generating unit, the output end of the first buffer is used as the second output end of the first driving signal generating unit, the output end of the second phase inverter is used as the fourth output end of the first driving signal generating unit, and the output end of the second buffer is used as the first output end of the first driving signal generating unit.

7. The transformation circuit according to claim 6, wherein the second driving signal generating unit comprises a first frequency divider, a third inverter, a first AND gate, and a fourth inverter;

the input end of the first frequency divider is used as the clock end of the second driving signal generation unit, the output end of the first frequency divider is connected with the first input end of the first and gate, the second input end of the first and gate is connected with the output end of the third phase inverter, the input end of the third phase inverter is connected with the output end of the second phase inverter, the output end of the first and gate is connected with the input end of the fourth phase inverter, the output end of the first and gate is also used as the first output end and the third output end of the second driving signal generation unit at the same time, and the output end of the fourth phase inverter is also used as the second output end and the fourth output end of the second driving signal generation unit at the same time.

8. The transformation circuit according to claim 6, wherein the second driving signal generating unit comprises a second frequency divider, a fifth inverter, a sixth inverter, a second AND gate, and a third AND gate;

the input end of the second frequency divider is used as the clock end of the second driving signal generation unit, the first output end of the second frequency divider is connected with the first input end of the second and gate, the second output end of the second frequency divider is connected with the first input end of the third and gate, the second input end of the second and gate is connected with the output end of the sixth inverter, the second input end of the third and gate is connected with the output end of the fifth inverter, the input end of the fifth inverter is connected with the output end of the second buffer, the input end of the sixth inverter is connected with the output end of the second inverter, the output ends of the second and gate are simultaneously used as the first output end and the third output end of the second driving signal generation unit, and the output end of the third and gate is simultaneously used as the second output end and the fourth output end of the second driving signal generation unit.

9. The transformation circuit according to claim 6, wherein the output voltage adjustment unit comprises an operational amplifier;

the non-inverting input end of the operational amplifier is used as the reference voltage end of the output voltage regulating unit, the inverting input end of the operational amplifier is used as the output voltage feedback end of the output voltage regulating unit, and the output end of the operational amplifier is used as the output end of the output voltage regulating unit.

10. An electronic device, comprising a power port, a battery, and the transformer circuit of any one of claims 1-9, wherein an input terminal of the transformer circuit is connected to the power port, and an output terminal of the transformer circuit is connected to the battery; the input end of the three-level voltage reduction unit is used as the input end of the transformation circuit, and the output end of the three-level voltage reduction unit is used as the output end of the transformation circuit.