CN115249717A

CN115249717A - TFT substrate, display module and electronic equipment

Info

Publication number: CN115249717A
Application number: CN202111234925.9A
Authority: CN
Inventors: 安亚斌; 苏懿; 贺海明
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2021-08-20
Filing date: 2021-10-22
Publication date: 2022-10-28
Anticipated expiration: 2041-10-22
Also published as: CN115249717B

Abstract

The embodiment of the application provides a TFT substrate, a display module and electronic equipment. The TFT substrate comprises a substrate, a first active layer, a first source drain layer, a first grid electrode, a plurality of data lines and a wiring layer. The wiring layer is arranged on one side, away from the substrate, of the first source drain layer. The wiring layer comprises a plurality of first metal wires. One end of each of the first metal wires is coupled with the data lines, and the other end of each of the first metal wires is coupled with the display driving chip. The wiring layer may replace a lower fan-out area in the display area AA in the electronic device for connecting the data lines and the display driving chip in the TFT substrate to provide the TFT substrate with image signals required for display. Therefore, the display area AA can be fanned out, so that the lower fanout area of the display module of the electronic equipment does not occupy a non-display area, the area of the non-display area can be reduced, and the screen occupation ratio of the electronic equipment is improved.

Description

TFT substrate, display module and electronic equipment

The present application claims priority of the chinese patent application entitled "a TFT panel" filed by the national intellectual property office on 20/8/2021 under the application number 202110962861.8, the entire contents of which are incorporated herein by reference.

Technical Field

The application relates to the technical field of display, especially, relate to a TFT base plate, display module assembly and electronic equipment.

Background

With the continuous development of the full-screen technology, the requirements of electronic equipment on screen occupation ratio are higher and higher. Generally, an electronic device includes a display module for displaying an image. The display module may include a display area (AA) and a non-display area located around the display area AA.

In general, the non-display region includes peripheral driving circuits (e.g., a scanning circuit for supplying a scanning signal, a display driving chip, etc.). In order to increase the screen occupation ratio, the area of the non-display region needs to be compressed. The area of the non-display area can be compressed by a mode of compressing the scanning circuit or by adopting a waterfall screen or a curved screen, and the non-display area is converted from the horizontal direction to the vertical direction. However, there is also a lower fanout (fanout) region between the display area AA and the display driving chip, as shown in fig. 1. The lower fan-out area couples the display driving chip to a Data Line (DL) in the display area AA by way of fan-out, so as to provide an image signal to the display area AA. The area of the lower fan-out area cannot be reduced by compressing or bending, so that the area of a non-display area at a lower frame of the electronic equipment is larger, which greatly influences the improvement of the screen occupation ratio of the electronic equipment.

Disclosure of Invention

The embodiment of the application provides a TFT base plate, a display module assembly and electronic equipment for solve the problem that the area of a non-display area of the electronic equipment is large, and the screen occupation ratio of the electronic equipment is improved.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

in a first aspect, the present application provides a TFT substrate. The TFT substrate has a plurality of sub-pixels arranged in rows and columns. The TFT substrate comprises a substrate, a first active layer, a first source drain layer, a first grid electrode, a plurality of data lines and a wiring layer. The first active layer is arranged on one side of the substrate, and the first active layer is arranged in each sub-pixel. The first source drain layer is arranged on one side, far away from the substrate, of the first active layer. The first source drain layer includes a first source and a first drain within each sub-pixel, and the first source and the first drain within each sub-pixel are coupled to the first active layer within the sub-pixel. The first grid electrode is arranged corresponding to the first active layer and is positioned between the first active layer and the first source drain layer. The plurality of data lines are positioned on the first source drain layer and are respectively coupled with the first source electrodes or the first drain electrodes in the plurality of rows of sub-pixels. The wiring layer is arranged on one side, far away from the substrate, of the first source drain layer. The wiring layer comprises a plurality of first metal wires. One end of each first metal wire is coupled with the corresponding data line, and the other end of each first metal wire is used for being coupled with the display driving chip.

Based on the TFT substrate. The TFT substrate is provided with a wiring layer instead of a lower fan-out area in a display area AA in the electronic equipment, and the wiring layer is used for connecting a data line in the TFT substrate and a display driving chip so as to provide an image signal required by display for the TFT substrate. Therefore, the display area AA can be fanned out, so that the lower fanout area of the display module of the electronic equipment does not occupy a non-display area, the area of the non-display area can be reduced, and the screen occupation ratio of the electronic equipment is improved.

In one possible implementation manner, different first metal wires of the plurality of first metal wires are spaced apart from each other. It should be understood that different first metal traces are used for connecting different data lines, so as to avoid the display quality problem caused by data crosstalk, and to improve the reliability and stability of the electronic device.

In a possible implementation manner, the display driving chip is located at one side edge of the TFT substrate, and the first metal trace extends in an "L" shape. Therefore, the first metal wires different from each other in the plurality of first metal wires can be separated from each other, and the first metal wires can be conveniently wired.

In one possible implementation manner, the plurality of first metal traces form a first region on the TFT substrate. The routing layer also includes a plurality of second metal traces in a second region of the TFT substrate. The second region is a region on the TFT substrate except the first region. The second metal wire is disconnected from the first metal wire. Therefore, after the second metal trace is added to the wiring layer, the problem of non-uniform display caused by light reflection of the metal trace (i.e., the first metal trace) in the display area AA can be effectively reduced, and the display quality of the electronic device can be improved. In addition, the load of the pixel circuit can be uniformized, and the display quality of the display area AA can be improved.

In a possible implementation manner, different second metal wires of the plurality of second metal wires are spaced apart from each other. Therefore, the logic function of each pixel circuit in the whole TFT substrate can be ensured, the display problem caused by crosstalk is avoided, and the reliability and the stability of the electronic equipment are improved.

In a possible implementation manner, the first metal trace extends in an "L" shape. Each second metal wire comprises a first sub-wire and a second sub-wire. The extending direction of one side of the first sub-trace and the first metal trace is the same. The extending direction of the second sub-routing is consistent with the extending direction of the other side of the L-shaped first metal routing. Therefore, the arrangement directions of the first metal traces and the second metal traces are consistent (i.e. long-range order) when viewed from the whole display area AA, so that the first metal traces and the second metal traces are uniformly arranged, thereby effectively reducing the problem of non-uniform display caused by light reflection of the metal traces (such as the first metal traces) in the display area AA and improving the display quality of the electronic device.

In one possible implementation, the TFT substrate further includes a light emitting device. The light-emitting device is arranged on one side, away from the substrate, of the wiring layer and is coupled with the first source drain layer. It should be understood that the first active layer, the first gate electrode, the first source electrode, and the first drain electrode may form a transistor of the pixel circuit. The pixel circuit for different types may comprise a plurality of different transistors, each of the source and drain of the plurality of different transistors being located in the first source drain layer. The light-emitting device is coupled to the first source/drain layer, which means that the light-emitting device is coupled to a source or a drain of a transistor in the first source/drain layer. Therefore, the light-emitting device can also be arranged in the TFT substrate and coupled with the first source drain layer to realize the light-emitting of the light-emitting device, so that each sub-pixel in the display module can display according to a preset gray scale, and the gray scale displayed by each sub-pixel forms an image.

In a possible implementation manner, the TFT substrate further includes a second source/drain layer. The second source drain layer is arranged between the first source drain layer and the wiring layer. The light emitting device is coupled with the first source drain layer through the second source drain layer. Therefore, the resolution ratio of the display module can be improved, and the display quality is improved.

In one possible implementation, the TFT substrate further includes a light emitting device. The light emitting device is arranged on one side of the wiring layer far away from the substrate. The light-emitting device is coupled with the first source drain layer through a second metal wire. After the second metal wire is arranged in the wiring layer, the light-emitting device can be coupled with the first source drain layer through the second metal wire, so that the load of the power wire is reduced, and the voltage drop (IR drop) is reduced.

In a possible implementation manner, the TFT substrate further includes a second source/drain layer. The second source drain electrode layer is arranged between the first source drain electrode layer and the wiring layer. The first source drain layer is coupled with the second source drain layer, and the second source drain layer is coupled with the second metal wire. Similarly, after the resolution is improved by the second source drain layer, the second source drain layer may be coupled with the second metal trace, so as to couple the light emitting device with the first source drain layer, so as to reduce the load of the power trace and reduce the voltage drop (IR drop).

In a second aspect, the present application provides a display module. The display module comprises a display driving chip and the TFT substrate in any one of the possible implementation manners of the first aspect. The display driver chip is coupled to a wiring layer in the TFT substrate.

In a third aspect, the present application provides an electronic device. The electronic device comprises a printed circuit board, a driving chip and the TFT substrate in any one of the possible implementation manners of the first aspect. The printed circuit board includes an application processor. The application processor is coupled with the driving chip. The driving chip comprises a display driving chip; the display driver chip is coupled to a wiring layer in the TFT substrate.

It can be understood that the display module provided by the second aspect and the electronic device described by the third aspect are both associated with the TFT substrate provided by the first aspect, and the beneficial effects achieved by the display module can refer to the beneficial effects in the TFT substrate provided by the first aspect, which are not described herein again.

Drawings

FIG. 1 is a schematic view of a display module with a lower fan-out area;

fig. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;

fig. 3 is a first schematic structural diagram of a display module according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of another electronic device provided in the embodiment of the present application;

fig. 5 is a schematic structural diagram of a display module according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of a display module according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a transistor according to an embodiment of the present disclosure;

fig. 8 is a schematic circuit structure diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 9 is a first schematic structural diagram of a TFT substrate according to an embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of a TFT substrate according to an embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of a display module according to an embodiment of the present disclosure;

FIG. 12 is an enlarged view of a portion of FIG. 11 at A;

fig. 13 is a schematic structural diagram of a display module according to an embodiment of the present disclosure;

FIG. 14 is an enlarged view of a portion of FIG. 13 at A;

fig. 15 is a schematic structural diagram of a TFT substrate according to an embodiment of the present disclosure;

fig. 16 is a schematic structural diagram of a TFT substrate according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments.

In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or as implying any indication of the number of technical features indicated. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.

In the description of the present application, the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "vertical", "lateral", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and for simplicity in description, and do not indicate or imply that the referred device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application.

In the present application, unless expressly stated or limited otherwise, the term "coupled" is to be construed broadly, e.g., "coupled" may be a fixed connection, a removable connection, or an integral part; may be directly connected or indirectly connected through an intermediate. Furthermore, the terms "coupled" or "coupling" may be a manner of making electrical connections that communicate signals. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

The embodiment of the application provides electronic equipment. The electronic device includes a mobile phone (mobile phone), a tablet computer (pad), a computer, an intelligent wearable product (e.g., a smart watch, a smart bracelet), a set top box, a media player, a portable electronic device, a Virtual Reality (VR) terminal device, an Augmented Reality (AR) terminal device, and other electronic products with a display interface. The embodiment of the present application does not specifically limit the specific form of the electronic device.

For convenience of description, the electronic device 01 is taken as a mobile phone shown in fig. 2 as an example. The electronic device 01 includes a display module 10, a middle frame 11 and a rear housing 12. The middle frame 11 is located between the display module 10 and the rear case 12. The display module 10 and the rear shell 12 are respectively connected with the middle frame 11. The accommodating cavity formed between the rear case 12 and the middle frame 11 is used for accommodating a battery, a camera module (not shown in fig. 2), and electronic components such as a Printed Circuit Board (PCB) shown in fig. 2.

It should be understood that the structure of the electronic device 01 is not limited to the structure of the display module 10, the middle frame 11, and the rear housing 12, and may also include other structures, such as a small board, a battery cover, a Subscriber Identity Module (SIM), and the like, and the embodiment of the present invention is not limited in particular.

In any of the electronic devices 01, the display module 10 is mainly used for displaying images, videos, and the like. As shown in fig. 3, the display module 10 includes a supporting backplane 101, a pixel circuit 102, a peripheral driving circuit 103, a light emitting device 104, and a top packaging layer 105. The supporting back plate 101 is used for supporting the pixel circuit 102, the peripheral driving circuit 103 and the light emitting device 104. The top encapsulation layer 105 is used to encapsulate the pixel circuit 102, the peripheral driving circuit 103, and the light emitting device 104. The pixel circuit 102 and the peripheral driving circuit 103 are both fabricated on the same plane of one side of the supporting backplane, and the peripheral driving circuit is located around the pixel circuit 102. The light emitting device 104 is located on a side of the pixel circuit 102 away from the supporting backplane 101. The pixel circuit 102 is used for driving the light emitting device 102 to emit light, so that the display module 10 can display an image. The peripheral driver circuit 103 is used for a processor in the electronic device 01 to control the operation of the pixel circuit 102.

In this case, as shown in fig. 4, the display module 10 may include a display area (AA) (also referred to as a pixel area) and a non-display area located around the display area AA. The display area AA includes a plurality of sub pixels (sub pixels) 30 arranged in rows and columns. In which a pixel circuit 102 and a light emitting device 104 as shown in fig. 2 are disposed in each sub-pixel 30. The pixel circuit 102 is used for driving the light emitting device 104 to emit light, so that each sub-pixel 30 in the display module 10 can display according to a preset gray scale. The non-display area includes a scan circuit and a driving chip 20. The scanning circuit provides scanning signals required for image display for the display area AA. The driving chip may include a Display Driver Integrated Circuit (DDIC) and a scan circuit driving chip. In this case, taking the OLED display as an example, the pixel circuits in the same row of pixels are coupled to the display driving chip through the same Data Line (DL) for providing the image signal to the display area AA. The scan circuit driving chip is coupled to the scan circuit through a Scan Line (SL), and is configured to control the scan circuit to output a scan signal to the display area AA. The scanning circuit and the driving chip 20 may constitute a peripheral driving circuit 103 as shown in fig. 3.

In some embodiments of the present application, the light emitting device 104 is a Liquid Crystal Display (LCD), an organic light-emitting diode (OLED), a flexible light-emitting diode (FLED), a Miniled, a Micro led, a Micro-o led, a quantum dot light-emitting diode (QLED), or the like. For convenience of description, the light emitting device 104 is taken as an OLED for illustration.

In addition, as shown in fig. 4, the electronic device 01 further includes a Printed Circuit Board (PCB) (or a driving system board), and an Application Processor (AP) (e.g., a CPU) and a power management chip (power IC) mounted on the PCB. The driver chip 20 in fig. 4 is coupled to the AP through a Flexible Printed Circuit (FPC).

Thus, the AP provides display data for the display driver chip and the display module to display actual image information. The power management chip provides working voltage for the display driving chip and the display module. The FPC provides a signal transmission connection path between the PCB and the display module, the FPC is connected with the PCB through a connector, and the FPC at the other end is bound (bound) on the display module through an anisotropic conductive film. The driving chip is used for receiving the signals transmitted by the PCB and transmitting the signals to the display module according to specific time sequence control. For example, after the display data outputted from the AP passes through the driving chip 20, the display data is converted into a data voltage Vdata, and the data voltage Vdata is transmitted to the pixel circuits coupled to the data lines DL. Next, each pixel circuit generates a driving current I matched to the data voltage Vdata through the data voltage Vdata on the data line DL to drive the OLED device in the pixel to emit light.

The pixel circuits, the OLED devices, and the data lines DL of the pixels in the display module 10 may be fabricated on a substrate (i.e., the supporting backplane 101). The base substrate may be made of a flexible resin material. In this case, the OLED display may be used as a folding display. Alternatively, the substrate in the OLED display screen may also be made of a relatively hard material, such as glass. In this case, the OLED display is a hard display.

It should be noted that, along with the improvement of the electronic device screen ratio requirement, the display module 10 for the electronic device needs to reduce the non-display area, for example, a mode of compressing the scanning circuit or an area of a non-display area compressed by a waterfall screen or a curved screen may be adopted, and the non-display area is converted from the horizontal direction to the vertical direction, that is, the non-display area is bent downward. However, as shown in fig. 5, there is a lower fanout (fanout) region between the display area AA and the driving chip 20 in the display module 10, and the lower fanout region couples the driving chip 20 and the data lines DL in the display area AA by way of fanout to provide image signals to the display area AA. The area of the lower fan-out area cannot be reduced by compressing or bending, so that the area of the non-display area at the lower frame of the electronic device is usually larger, which greatly affects the improvement of the screen occupation ratio of the electronic device.

Based on this, some embodiments of the present application provide a TFT substrate. The TFT substrate may adjust a lower fan-out region into the display area AA, which may be referred to as AA area fan-out (FIAA). Therefore, the lower fan-out area does not occupy the non-display area any more, so that the area of the non-display area can be reduced, and the screen occupation ratio of the electronic equipment is improved.

A TFT substrate provided in some embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be understood that the TFT substrate includes the supporting backplane 101, the pixel circuit 102 and the light emitting device 104 shown in fig. 3, i.e., the display area AA in the display module 10 shown in fig. 4.

As shown in fig. 6, each sub-pixel 30 in the display area AA of the display module includes a pixel circuit 102 and a light emitting device 104. The pixel circuit 102 is coupled to the scan circuit through a scan line SL for receiving a scan signal of the scan circuit, and the pixel circuit 102 is further coupled to the display driver chip through a data line DL for receiving an image signal of the display driver chip to drive the light emitting device 104 to emit light, so that each sub-pixel 30 in the display area AA can display according to a preset gray scale. The gray levels displayed by the individual sub-pixels 30 may form an image.

In some embodiments of the present application, the pixel circuit 102 may include a plurality of transistors, which may be Thin Film Transistors (TFTs), and at least one capacitor.

Any one of the transistors may include a gate (gate, g), an Active Layer (AL), and a first electrode, such as a source(s), and a second electrode, such as a drain (d), as shown in fig. 7 (a cross-sectional view of the transistor). Alternatively, the first pole of the transistor may be the drain d and the second pole may be the source s. For convenience of illustration, the first pole of the transistor is taken as the source s, and the second pole is taken as the drain d.

The active layer AL is made of a semiconductor material. When a voltage applied to the gate electrode g of the transistor is capable of turning on the transistor, the active layer AL is converted from an insulator to a conductor, so that the source s and the drain g of the transistor are coupled. When the transistor cannot be turned on by a voltage applied to the gate electrode g of the transistor, the active layer AL is in an insulating state, and the source s and the drain d of the transistor are disconnected.

The active layer of the transistor is made of a different material, and the transistor has different properties. For example, when the material forming the active layer of the transistor is polysilicon (e.g., low temperature polysilicon, LTPS), the low temperature polysilicon is generally applied to the case where the switching frequency is fast (e.g., the electronic device 01 is in the on state) due to the high electron mobility of the polysilicon transistor, so as to improve the switching efficiency. The low-temperature polysilicon is polysilicon deposited in a low-temperature environment (e.g., a temperature lower than 600 ℃).

Alternatively, for another example, when the material forming the active layer of the transistor is a semiconductor oxide (e.g., amorphous indium gallium zinc oxide, IGZO), since the semiconductor oxide transistor has a lower electron mobility than a polysilicon transistor but has a very low off-state current, it is generally applied to a case where the switching frequency is slow (e.g., the electronic device 01 is in a standby state), and can be used to reduce the leakage current, thereby reducing the power consumption. For convenience of description, a transistor whose active layer is made of polysilicon will be referred to as a first transistor, and a transistor whose active layer is made of a semiconductor oxide will be referred to as a second transistor.

Illustratively, in some embodiments, in order to enable the pixel circuit 102 to be turned on quickly when driven at a high frequency (e.g., when the electronic device 01 is in an on state) and to reduce power consumption when driven at a low frequency (e.g., when the electronic device 01 is in a standby state), the pixel circuit 102 includes at least one of the first transistor and the second transistor.

As shown in fig. 8, the pixel circuit 102 may include a driving transistor Td and a switching transistor Tc, and a capacitor Cst. At this time, the pixel circuit 102 has a 2T1C structure. Here, "2T" means two transistors, and "1C" means one storage capacitor.

For example, the gate g of the switching transistor Tc is coupled to a Gate Line (GL), and the gate line GL is coupled to the scan line SL. The source s of the light-on transistor Tc is coupled to a Data Line (DL) for transmitting a data voltage Vdata to the source s of the switching transistor Tc through the data line D. The drain d of the turn-on transistor Tc is coupled to one end of the storage capacitor Cst, and the other end of the storage capacitor Cst is coupled to the power supply VDD. The drain d of the switching transistor Tc is further coupled to the gate g of the driving transistor Td, the source s of the driving transistor Td is coupled to the power source VDD, the drain d of the driving transistor Td is coupled to the anode (anode) of the light emitting device 104, and the cathode (cathode) of the light emitting device 104 is grounded.

The switching transistor Tc is used to be in a turned-on state under the control of a Gate Line (GL), thereby writing the data voltage Vdata into the gate g of the driving transistor Td and the storage capacitor Cst. The storage capacitor Cst may hold the gate voltage of the driving transistor Td so that the gate voltage of the driving transistor Td can be stabilized within one image frame. In this case, the driving transistor Td may generate a driving current according to the data voltage Vdata, so that the light emitting device 104 may emit light according to the driving current.

In some embodiments of the present application, the driving transistor Td in fig. 8 may be the first transistor, for example, the active layer of the driving transistor Td is LTPS, and the switching transistor Tc may be the second transistor, for example, the active layer of the switching transistor is IGZO, in which case, since the electron mobility of the driving transistor Td (i.e., the first transistor) is high, the light emitting device 104 can be quickly turned on when the first transistor is connected to the light emitting device 104, and since the off-state current of the second transistor is very low, when the circuit switch is controlled by using the second transistor as the switching transistor Tc, the leakage current can be reduced, thereby reducing power consumption and increasing the standby time of the device.

Alternatively, in other embodiments of the present application, the driving transistor Td in fig. 8 may be the second transistor, for example, the active layer of the driving transistor Td is IGZO, and the switching transistor Tc may be the first transistor, for example, the active layer of the switching transistor Tc is LTPS.

It should be understood that the pixel circuit 102 is only an example, and in some embodiments, the number of the switching transistors may be increased to eliminate the influence of the threshold voltage (Vth) of the driving transistor Td on the light emitting brightness of the light emitting device 104, so as to improve the uniformity of the brightness of the light emitting device, for example, the pixel circuit 102 may have a 7T1C or 8T1C structure. Of course, in some embodiments, the pixel circuit 102 may also include only one transistor, such as the first transistor or the second transistor. Therefore, the structure of the pixel circuit 102 is not particularly limited in the embodiments of the present application.

For convenience of description, the TFT substrate provided in the present embodiment will be described below with reference to the structure of the pixel circuit 102 being 2T1C, the driving transistor Td in the pixel circuit 102 being the first transistor (e.g., the active layer is LTPS), and the switching transistor Tc being the second transistor (e.g., the active layer is IGZO).

As shown in fig. 9 or fig. 10 (a cross-sectional view taken along a dotted line O-O in fig. 6), the TFT substrate provided in the embodiment of the present application includes a substrate 201, a first transistor (for example, an active layer is LTPS) 202 and a second transistor (for example, an active layer is IGZO) 203 disposed on a side of the substrate 201, and a Pixel Definition Layer (PDL) 204 disposed on a side of the first transistor 202 and the second transistor 203 away from the substrate 201. The pixel defining layer 204 has a plurality of hollow structures. One of the light emitting devices 104 may be disposed in one of the hollow structures in the pixel defining layer 204. The light emitting device 104 may include an anode (anode) 205, a light emitting layer 206, and a cathode 207, which are sequentially stacked from bottom to top.

In an embodiment of the present application, the material constituting the substrate 201 may include a hard material, such as at least one of glass, sapphire, or a metal material. Alternatively, the material constituting the substrate 201 may further include a flexible material, such as a high molecular polymer material. Illustratively, when the material of the substrate 201 includes a flexible material, as shown in fig. 9 or fig. 10, the substrate 201 may include a first substrate layer 2011 (e.g., polyimide (PI)), a first barrier layer 2012 (e.g., silicon oxide, siOx), a second substrate layer 2013 (e.g., PI), and a second barrier layer 2014 (e.g., silicon oxide, siOx), the first substrate layer 2011, the first barrier layer 2012, the second substrate layer 2013, and the second barrier layer 2014 are sequentially stacked.

As can be seen from the above description, the first transistor 202 may include a gate 211, a first electrode (e.g., source s), a second electrode (e.g., drain d) 209, and an active layer 212. As shown in fig. 9 or fig. 10, a first gate insulating layer 213 (e.g., a SiOx layer of silicon oxide) is disposed between the gate electrode 211 and the active layer 212 of the first transistor 202, and the gate electrode 211 of the first transistor 202 is farther away from the substrate 201 than the active layer 212. Thus, the first transistor 202 is a top gate transistor.

Similarly, the second transistor 203 may also include a gate electrode 214 (i.e., a first gate electrode), a first pole (e.g., a source electrode s) (i.e., a first source electrode), a second pole (e.g., a drain electrode d) (i.e., a first drain electrode), and an active layer 215 (i.e., a first active layer). A second gate insulation layer 216 (e.g., a SiOx layer of silicon oxide) is provided between the gate electrode 214 and the active layer 215 of the second transistor 203, and the gate electrode 214 of the second transistor 203 is located further away from the substrate 201 than the active layer 215. Thus, the second transistor 202 is a top gate transistor.

The gate electrode 211 of the first transistor 202 and the gate electrode 214 of the second transistor 203 may be made of molybdenum (Mo), titanium/aluminum/titanium alloy (Ti/Al/Ti), (molybdenum/aluminum/molybdenum alloy) Mo/Al/Mo, titanium (Ti), or the like.

Since the active layer 212 of the first transistor 202 is polysilicon and the active layer 215 of the second transistor 203 is a semiconductor oxide. In order to prevent ion diffusion in the active layer 212 of the first transistor 202 and the active layer 215 of the second transistor 203 from affecting the functions of the transistors, a barrier layer 217 is usually further provided between the first gate insulating layer 213 and the second gate insulating layer 216.

In addition, the TFT substrate further includes a storage capacitor Cst. The storage capacitor Cst may further include a first electrode 223 and a second electrode 224. The first electrode 223 is located on a side surface of the first gate insulating layer 213 away from the substrate 201, and the first electrode 223 and the gate 211 of the first transistor 202 are made of the same material. A third gate insulating layer 225 is further disposed between the first gate insulating layer 213 and the barrier layer 217. The second electrode 224 is located on a side surface of the third gate insulating layer 225 away from the substrate 201, the second electrode 224 is coupled to the first transistor 202, and the second electrode 224 is made of the same material as the gate 211 of the second transistor 203. In this case, the second electrode 224 is an upper plate of the storage capacitor Cst, and the first electrode 222 is a lower plate of the storage capacitor.

An interlayer dielectric layer 218 is provided on the second gate insulating layer 216 and the gate 214 of the second transistor 203 on the side away from the substrate 201 for isolation. The interlayer dielectric layer 218 is covered with an organic film as a first Planarization Layer (PLN) 219 on the side away from the substrate 201.

In general, the source s and the drain d of the first transistor 202, and the source s and the drain d of the second transistor 203 are disposed in the same hierarchical structure. For convenience of description, a hierarchical structure in which the source s and the drain d of the first transistor 202 and the source s and the drain d of the second transistor 203 are located is referred to as a first source-drain layer. A first source drain layer may be fabricated on a side of the first planar layer 219 remote from the substrate 201. The source s and the drain d in the first source/drain layer may be coupled to the active layer of a corresponding transistor (e.g., a first transistor or a second transistor) through a via.

According to fig. 8, the first transistor 202 described above may function as the driving transistor Td shown in fig. 8. Thus, in some embodiments of the present application, as shown in fig. 9, the second pole 209 of the first transistor 202 may be directly coupled to the anode 205 of the light emitting device 104. Alternatively, as shown in fig. 10, the TFT substrate may further include a second source/drain layer 208. The second source drain layer 208 is located on a side of the first source drain layer away from the substrate 201. The second pole 209 of the first transistor 202 may be coupled to the anode 205 of the light emitting device 104 via a second source/drain layer 208. Compared with the case where the second electrode 209 of the first transistor 202 is directly coupled to the anode 205 of the light emitting device 104, the second electrode 209 of the first transistor 202 is coupled to the anode 205 of the light emitting device 104 through the second source/drain layer 208, so that the resolution of the display module formed by the TFT substrate can be improved.

Referring to fig. 8, the second transistor 203 can be used as a switching transistor Tc shown in fig. 8, and a source s of the switching transistor Tc needs to be coupled to the data line DL. In general, the data line DL may be disposed on a first source/drain layer (not shown) in the TFT substrate, and in order to ensure the transmission of signals, a lower fan-out region is adopted in the prior art to couple the data line DL with the driving chip, so that an image signal (i.e., the data voltage Vdata) provided by the driving chip can be transmitted to the switching transistor Tc and then to the driving transistor Td to drive the light emitting device 104 to emit light.

However, in some embodiments of the present application, as shown in fig. 9 or 10, the TFT substrate further includes a wiring layer 210. When the second pole 209 of the first transistor 202 is directly coupled to the anode 205 of the light emitting device 104, as shown in fig. 9, the wiring layer 210 is located between the first source-drain layer and the pixel defining layer 204. For example, a side of the first source-drain layer away from the substrate 201 may be covered with an organic film as the second planarization layer 220. A wiring layer 210 may be formed on the second planar layer 220 on a side remote from the substrate 201. An organic film may be covered as a third flat layer 221 on the side of the wiring layer 210 away from the substrate 201. The pixel defining layer may be located on a side of the third flat layer 221 away from the substrate 201.

When the second electrode 209 of the first transistor 202 is coupled to the anode 205 of the light emitting device 104 through the second source-drain layer 208, as shown in fig. 10, the wiring layer 210 is located between the second source-drain layer 208 and the pixel defining layer 204. Illustratively, a side of the first source drain layer away from the substrate 201 may be covered with an organic film as the second planarization layer 220. A second source drain layer 208 may be fabricated on a side of the second planar layer 220 remote from the substrate 201 for coupling to the first source drain layer (e.g., to the second pole 209 of the first transistor 202) via a via. An organic film may be covered on a side of the second source drain layer 208 away from the substrate 201 as a third flat layer 221. The wiring layer 210 may be formed on a side of the third planarization layer 221 away from the substrate 201. The wiring layer 210 may be covered with an organic film as a fourth planarization layer 222 on a side thereof remote from the substrate 201. The pixel defining layer 204 may be disposed on a side of the fourth planarization layer 222 away from the substrate 201, and the anode 205 of the light emitting device 104 inside the hollow structure of the pixel defining layer 204 may be coupled to the second source/drain layer 208 through a via, so that the second electrode 209 of the first transistor 202 is coupled to the anode 205 of the light emitting device 104.

The wiring layer 210 includes a plurality of first metal traces 2101, the plurality of first metal traces 2101 respectively correspond to a plurality of Data Lines (DL) in the TFT substrate, and the plurality of first metal traces 2101 is configured to connect the plurality of data lines DL in the TFT substrate. As an example, the plurality of data lines DL of the TFT substrate are generally located on the first source/drain layer of the first transistor 202 and can be coupled to the source or drain of the second transistor 203, so that each of the first metal traces 2101 in the wiring layer 210 can be coupled to a corresponding data line DL in the TFT substrate through a via (not shown in the drawings, and the via is filled with a conductive material, such as a metal material). The first metal wires 2101 of the wiring layer 210 may also be coupled to a driving chip through a wire (wire bond), so as to implement fan-out in the display area AA, to implement coupling of the driving chip and the data lines DL in the TFT substrate, thereby reducing the area of the non-display area and increasing the screen area of the electronic device.

In the TFT substrate shown in fig. 9 or 10, the wiring layer 210 only includes the first metal trace 2101 for connecting the data line DL of the TFT substrate to the driving chip. Typically, the driving chip is located at the lower edge of the display AA area, so the first metal trace 2101 in the wiring layer 210 is distributed in the lower area of the display AA area, as shown in fig. 11. The lower area of the AA display area herein also includes both sides of the AA display area, i.e., the lower area of the AA display area is all areas where the lower edge of the AA display area extends toward the middle of the AA display area along both sides of the AA display area). Furthermore, to facilitate routing in the routing layer 210, the different first metal traces 2101 do not cross and are isolated from each other (i.e., spaced apart from each other). Illustratively, as shown in fig. 12 (a partially enlarged view in fig. 11), the vias 230 connecting the first metal traces 2101 on different data lines DL are staggered from each other in the extending direction of the data lines DL. After each first metal trace 2101 is connected to the via hole 230 of the corresponding data line DL, the first metal trace 2101 extends in an "L" shape in the second source/drain layer 210, so that after all the first metal traces 2101 are arranged, all the first metal traces 2101 form a first area similar to a "house" shape. It should be understood that the area formed by the first metal trace 2101 can be in any other shape, such as an inverted triangle, a trapezoid, etc., according to the arrangement between different vias 230.

After the wiring layer 210 formed by the first metal trace 2101 is added, the problem of load inconsistency of pixel circuits between the sub-pixels 30 covered with the first metal trace 2101 and the sub-pixels 30 not covered with the first metal trace 2101 may be caused, which may cause the problem of brightness inconsistency between different sub-pixels 30, thereby reducing the display quality of the electronic device. In addition, the first area formed by the first metal trace 2101 forms a light reflection area compared with the area without the first metal trace 2101, thereby causing a problem of non-uniform display of different sub-pixels 30 in the display area AA.

In some embodiments of the present application, to solve the above-mentioned problem of load non-uniformity of the pixel circuit and the problem of display non-uniformity of different areas, as shown in fig. 13, the second metal trace 2102 may be covered in an area (also referred to as a Dummy area) where the display area AA does not cover the first metal trace 2101 (i.e., the second area). That is, in the TFT substrate, the wiring layer 210 includes a first metal trace 2101 and a second metal trace 2102. Please refer to the above description for the connection relationship of the first metal trace 2101, which is not described herein again. The second metal trace 2102 is not connected to the first metal trace 2101, and does not have any electrical connection relationship (i.e., the second metal trace 2102 is separated from the first metal trace 2101). The arrangement of the second metal traces 2102 may be similar to that of the first metal traces 2101, for example, as shown in fig. 14 (a partial enlarged view in fig. 13), each column of sub-pixels 30 may correspond to one group of second metal traces 2102, and the groups of second metal traces 2102 are not connected to each other and do not have any electrical connection relationship (i.e., are separated from each other). Each set of second metal traces 2102 may be formed by coupling metal traces a (i.e., first sub-traces) and metal traces B (i.e., second sub-traces) that are arranged in a staggered manner. The metal trace a may have the same direction as one side of the "L" shape of the first metal trace 2101, and the metal trace B may have the same direction as the other side of the "L" shape of the first metal trace 2101. Therefore, the arrangement directions of the first metal trace 2101 and the second metal trace 2102 are consistent (i.e., long-range order) in the overall view of the display area AA, so that the first metal trace 2101 and the second metal trace 2102 are uniformly arranged, the problem of non-uniform display caused by light reflection of the metal trace (e.g., the first metal trace 2101) in the display area AA is effectively reduced, and the display quality of the electronic device is improved. In addition, through the arrangement of the second metal routing line 2102, in the local micro-nano circuit (i.e., the pixel circuit), the pixel circuits in different sub-pixels 30 are separated from each other (i.e., short-range disorder), so that the logic function of each pixel circuit in the whole TFT substrate is ensured, the display problem caused by crosstalk is avoided, and the reliability and stability of the electronic device are improved.

After the second metal trace 2102 is disposed on the wiring layer 210, as shown in fig. 15, the anode 205 of the light emitting device 104 may be coupled to the second metal trace 2102 in the wiring layer 210 through a via, and the second metal trace 2102 in the wiring layer 210 is coupled to the first source/drain layer (i.e., coupled to the second diode 209 of the first transistor 202) through a via, so that the second diode 209 of the first transistor 202 is coupled to the anode 205 of the light emitting device 104. Alternatively, as shown in fig. 16, the anode 205 of the light emitting device 104 can be coupled to the second metal trace 2102 in the wiring layer 210 through a via, and the second metal trace 2102 in the wiring layer 210 is coupled to the second source/drain layer 208 through a via, so that the second electrode 209 of the first transistor 202 is coupled to the anode 205 of the light emitting device 104.

It should be understood that in the case where the electronic device is provided with an off-screen camera (i.e. a camera disposed below a display screen), or there is other specially designed area (e.g. a circular corner (connector) of the edge of the electronic device) in the electronic device, after the second metal trace 2102 is disposed on the wiring layer 210, the anode 205 of the light emitting device 104 in this area may also be coupled to the second diode 209 of the first transistor 202 through the second metal trace 2102 and the via.

When the TFT substrate is applied to a large-sized AM-OLED panel or an AM-OLED panel with higher power consumption, after the second metal trace 2102 in the wiring layer 210 is coupled to the second source/drain layer 208 or the second pole 209 of the first transistor 202 through a via, the wiring layer 210 may be used to reduce the load of the power trace in the AM-OLED panel and reduce the voltage drop (IR drop). When the TFT substrate is applied to an LCD panel, the second metal trace 2102 in the wiring layer 210 may be coupled to a common (common) electrode in the LCD panel to optimize problems of Ghost (Ghost), non-uniformity of brightness (mura), and poor loading (loading).

In summary, the wiring layer 210 is disposed in the TFT substrate, and the wiring layer 210 includes the first metal trace 2101 and the second metal trace 2102, so that the problem of non-uniform display caused by light reflection of the metal traces (such as the first metal trace 2101) in the display area AA can be effectively reduced, and the display quality of the electronic device is improved. In addition, the load of the pixel circuit can be uniformized, and the display quality of the display area AA can be improved.

The embodiment of the application also provides a display module. The display module comprises any one of the TFT substrates and the driving chip. Wherein the driving chip may include a display driving chip. The display driving chip is coupled to the data lines of the TFT substrate. The display module has the same technical effects as the TFT substrate provided in the foregoing embodiments, and the details are not repeated herein.

The embodiment of the application also provides the electronic equipment. The electronic device comprises a printed circuit board, a driving chip and any one of the TFT substrates, wherein the printed circuit board comprises an application processor. The application processor is coupled to the driver chip. The driving chip comprises a display driving chip; the display driver chip is coupled to a wiring layer in the TFT substrate. The electronic device has the same technical effects as the TFT substrate provided in the foregoing embodiments, and details are not repeated herein.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A TFT substrate having a plurality of sub-pixels arranged in rows and columns, the TFT substrate comprising:

a substrate;

a first active layer disposed at one side of the substrate; each of the sub-pixels includes the first active layer therein;

the first source drain layer is arranged on one side, far away from the substrate, of the first active layer; the first source drain layer comprises a first source electrode and a first drain electrode in each sub-pixel; the first source and the first drain within each of the sub-pixels are coupled to the first active layer within the sub-pixel;

the first grid electrode is arranged corresponding to the first active layer and is positioned between the first active layer and the first source drain layer;

the data lines are positioned on the first source drain layer and are respectively coupled with the first sources or the first drains in the sub-pixels in multiple rows;

the wiring layer is arranged on one side, away from the substrate, of the first source drain layer; the wiring layer comprises a plurality of first metal wires; one end of each of the first metal wires is coupled to the data lines, and the other end of each of the first metal wires is coupled to the display driving chip.

2. The TFT substrate of claim 1, wherein different ones of the plurality of first metal traces are spaced apart from one another.

3. The TFT substrate according to claim 1 or 2, wherein the display driver chip is located at one side edge of the TFT substrate, and the first metal trace extends in an "L" shape.

4. The TFT substrate according to any one of claims 1-3, wherein the plurality of first metal traces form a first region on the TFT substrate; the routing layer further comprises: a plurality of second metal wires located in a second region of the TFT substrate; the second region is a region on the TFT substrate except the first region; the second metal trace is disconnected from the first metal trace.

5. The TFT substrate of claim 4, wherein different ones of the second metal traces are spaced apart from one another.

6. The TFT substrate according to claim 4 or 5, wherein the first metal trace extends in an "L" shape; each second metal wire comprises a first sub-wire and a second sub-wire; the extending direction of one side of the L shape of the first sub-routing and the first metal routing is consistent; the extending direction of the second sub-routing is consistent with that of the other side of the L-shaped first metal routing.

7. The TFT substrate according to any one of claims 1 to 6, further comprising:

the light-emitting device is arranged on one side, away from the substrate, of the wiring layer; the light emitting device is coupled to the first source drain layer.

8. The TFT substrate of claim 7, further comprising:

the second source drain electrode layer is arranged between the first source drain electrode layer and the wiring layer; the light emitting device is coupled with the first source drain layer through the second source drain layer.

9. The TFT substrate according to any one of claims 4 to 6, further comprising:

the light-emitting device is arranged on one side, away from the substrate, of the wiring layer; the light emitting device is coupled with the first source drain layer through the second metal wiring.

10. The TFT substrate of claim 9, further comprising:

the second source drain layer is arranged between the first source drain layer and the wiring layer; the second source drain layer is coupled with the second metal wire.

11. A display module comprising a display driver chip and the TFT substrate according to any one of claims 1 to 10; the display driving chip is coupled with the wiring layer in the TFT substrate.

12. An electronic device comprising a printed circuit board, a driver chip, and the TFT substrate according to any one of claims 1 to 10;

the printed circuit board includes an application processor; the application processor is coupled with the driving chip;

the driving chip comprises a display driving chip; the display driving chip is coupled with the wiring layer in the TFT substrate.