CN115249613A - Method for manufacturing semiconductor structure - Google Patents
Method for manufacturing semiconductor structure Download PDFInfo
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- CN115249613A CN115249613A CN202110468853.8A CN202110468853A CN115249613A CN 115249613 A CN115249613 A CN 115249613A CN 202110468853 A CN202110468853 A CN 202110468853A CN 115249613 A CN115249613 A CN 115249613A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000000034 method Methods 0.000 title claims description 75
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010410 layer Substances 0.000 claims abstract description 269
- 239000011241 protective layer Substances 0.000 claims abstract description 108
- 229910052751 metal Inorganic materials 0.000 claims abstract description 53
- 239000002184 metal Substances 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000012535 impurity Substances 0.000 claims abstract description 24
- 238000002360 preparation method Methods 0.000 claims abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 16
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 14
- 238000000059 patterning Methods 0.000 claims description 11
- 239000001257 hydrogen Substances 0.000 claims description 10
- 229910052739 hydrogen Inorganic materials 0.000 claims description 10
- 238000005121 nitriding Methods 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 229910052735 hafnium Inorganic materials 0.000 claims description 9
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 8
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 4
- 230000003667 anti-reflective effect Effects 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 2
- 238000000231 atomic layer deposition Methods 0.000 description 12
- 238000002161 passivation Methods 0.000 description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 7
- 239000000460 chlorine Substances 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 5
- 229910052801 chlorine Inorganic materials 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 2
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to a preparation method of a semiconductor structure, which comprises the following steps: providing a substrate; sequentially stacking a grid dielectric layer, a high-K dielectric layer, a metal layer and a first protective layer on the substrate, wherein the temperature of the first protective layer is lower than the preset temperature; and carrying out nitridation treatment on the first protective layer to remove impurity elements in the first protective layer. The HKMG structure is formed by the preparation method of the semiconductor structure, so that the transistor size is reduced; moreover, the metal layer can be prevented from bearing high temperature, so that the performance of the metal layer is prevented from being damaged; and impurity elements in the first protective layer can be removed, and the quality of the first protective layer is improved.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a method for manufacturing a semiconductor structure.
Background
At present, in order to reduce the size of a transistor, a High-K dielectric layer and a Metal Gate (Metal Gate) are often used to form a High-K/Metal Gate (HKMG) structure of the transistor, and a protective layer is further formed on the Metal Gate to prevent the Metal Gate from being damaged. Because the metal gate cannot withstand high temperature, the adjustment (tuning) of the effective work function (eWF) of the metal gate limits the thermal budget (thermal budget) of the process of the protection layer, and the high temperature also causes oxygen (O) element in the high-K dielectric layer to diffuse into the protection layer to increase the resistance, so the temperature when forming the protection layer cannot be too high.
In the conventional technique, the protective layer is a thermal (thermal) furnace tube process with a temperature of 740-700 ℃, and the thermal furnace tube process temperature is too high, which is not suitable for HKMG. Therefore, it is necessary to form the protective layer at a low temperature instead. However, a decrease in the temperature of the protective layer may result in more impurities remaining in the protective layer, thereby reducing the quality of the protective layer.
Disclosure of Invention
Accordingly, it is desirable to provide a method for fabricating a semiconductor structure, which can solve the problem in the prior art that a high temperature process cannot be used for a protection layer, and a low temperature process can cause more impurities to remain in the protection layer, thereby reducing the quality of the protection layer.
In order to achieve the above object, in one aspect, the present invention provides a method for manufacturing a semiconductor structure, including:
providing a substrate;
sequentially stacking a grid dielectric layer, a high-K dielectric layer, a metal layer and a first protective layer on the substrate, wherein the temperature of the first protective layer is lower than the preset temperature;
and carrying out nitridation treatment on the first protective layer to remove impurity elements in the first protective layer.
In one embodiment, the method further comprises the following steps:
forming a mask layer on the first protective layer;
patterning the mask layer;
and sequentially patterning the first protection layer, the metal layer and the high-K dielectric layer based on the patterned mask layer to form a gate structure.
In one embodiment, the patterning the mask layer includes:
forming a photoresist layer on the mask layer;
photoetching the photoresist layer to define a graph of the grid structure;
and patterning the mask layer based on the patterned photoresist layer.
In one embodiment, the forming a mask layer on the first protection layer includes: and sequentially forming a hard mask layer and an anti-reflection layer on the first protective layer in an overlapping manner.
In one embodiment, the antireflective layer comprises a silicon oxynitride layer.
In one embodiment, the method further comprises the following steps:
and forming a second protective layer on the side wall of the grid structure, wherein the second protective layer is connected with the first protective layer.
In one embodiment, the first and second protection layers comprise silicon nitride layers.
In one embodiment, the temperature when the second protection layer is formed is lower than the preset temperature; the preparation method of the semiconductor structure further comprises the following steps:
and nitriding the second protective layer to remove the impurity elements in the second protective layer.
In one embodiment, the first protective layer and/or the second protective layer are formed by a plasma rf process, which includes an ald rf furnace process or a cvd rf chamber process.
In one embodiment, the first protective layer and the second protective layer are formed at a temperature of 450 to 600 degrees.
In one embodiment, the nitriding the first protective layer comprises:
doping hydrogen in a plasma state into the first protective layer;
and doping nitrogen elements into the first protective layer.
In one embodiment, a polysilicon layer is formed between the high-K dielectric layer and the metal layer.
In one embodiment, the substrate comprises a silicon substrate, and/or the metal layer comprises a tungsten layer and a titanium silicide nitride layer.
In one embodiment, when forming the N-type gate structure on the substrate, the gate dielectric layer comprises a silicon dioxide layer, and/or the high-K dielectric layer comprises a hafnium silicate layer, a lanthanum oxide layer, and a titanium nitride layer.
In one embodiment, when the P-type gate structure is formed on the substrate, the gate dielectric layer includes a silicon germanium layer and a silicon dioxide layer, and/or the high-K dielectric layer includes a hafnium silicate layer, an aluminum oxide layer, a first titanium nitride layer, a lanthanum oxide layer, and a second titanium nitride layer.
The preparation method of the semiconductor structure has the following beneficial effects:
according to the preparation method of the semiconductor structure, the grid dielectric layer, the high-K dielectric layer, the metal layer and the first protection layer are sequentially formed on the substrate in an overlapping mode, and the HKMG structure is formed by utilizing the high-K dielectric layer and the metal layer, so that the size of a transistor is reduced; the process temperature of the protective layer on the metal layer is lower than a preset temperature, and the preset temperature can be determined according to the thermal budget of the metal layer, so that the metal layer is prevented from bearing high temperature, and the performance of the metal layer is prevented from being damaged; in addition, the first protective layer is subjected to nitriding treatment, so that impurity elements in the first protective layer can be removed, and the quality of the first protective layer can be improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the descriptions of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the following descriptions are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure provided in an embodiment of the present application;
FIG. 2 is a flow chart of a method of fabricating a semiconductor structure provided in another embodiment of the present application;
fig. 3 to 7 are cross-sectional views of structures obtained at various steps in a method of fabricating a semiconductor structure provided in an embodiment of the present application;
fig. 8 to 11 are schematic views illustrating a nitridation process for the first protection layer according to an embodiment of the present application.
Description of reference numerals:
11. a substrate; 12. a gate dielectric layer; 13. a polysilicon layer; 14. a high-K dielectric layer; 15. a metal layer; 16. a first protective layer; 17. a mask layer; 171. a hard mask layer; 172. an anti-reflection layer; 18. a photoresist layer; 19. and a second protective layer.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatial relational terms, such as "under," "below," "under," "over," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. In addition, the device may comprise additional orientations (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations from the shapes shown are to be expected, for example, due to manufacturing techniques and/or tolerances. Thus, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
Fig. 1 is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. Referring to fig. 1, a method for fabricating a semiconductor structure includes:
step S11, providing a substrate.
And S12, sequentially stacking a grid dielectric layer, a high-K dielectric layer, a metal layer and a first protective layer on the substrate, wherein the temperature of the first protective layer is lower than the preset temperature.
Step S13, performing nitridation on the first protective layer to remove impurity elements in the first protective layer.
The preparation method of the semiconductor structure is characterized in that the gate dielectric layer, the high-K dielectric layer, the metal layer and the first protective layer are sequentially formed on the substrate in an overlapping mode, and the HKMG structure is formed by utilizing the high-K dielectric layer and the metal layer, so that the transistor size is favorably reduced; the process temperature of the protective layer on the metal layer is lower than a preset temperature, and the preset temperature can be determined according to the thermal budget of the metal layer, so that the metal layer is prevented from bearing high temperature, and the performance of the metal layer is prevented from being damaged; in addition, the first protective layer is subjected to nitriding treatment, so that impurity elements in the first protective layer can be removed, and the quality of the first protective layer can be improved.
In step S11, referring to step S11 in fig. 1 and fig. 3, a substrate 11 is provided.
In some examples, substrate 11 may include a silicon (Si) substrate. In other examples, substrate 11 may include a silicon germanium substrate, a gallium nitride substrate, or an indium gallium arsenide substrate. In other examples, the substrate 11 may include a silicon-on-insulator substrate or the like.
In step S12, referring to step S12 in fig. 1 and fig. 4, a gate dielectric layer 12, a high-K dielectric layer 13, a metal layer 15 and a first protection layer 16 are sequentially stacked on the substrate 11.
In some examples, when forming an N-type gate structure on substrate 11, gate dielectric layer 12 may include silicon dioxide (SiO) 2 ) And (3) a layer. When forming a P-type gate structure on the substrate 11, the gate dielectric layer 12 may include a silicon germanium (SiGe) layer and a silicon dioxide layer. A silicon germanium layer may be located between the substrate 11 and the silicon dioxide layer.
In some examples, the high-K dielectric layer 13 may include hafnium silicate (HfSiO) when forming an N-type gate structure on the substrate 11 x ) Layer of lanthanum oxide (La) 2 O 3 ) A layer and a titanium nitride (TiN) layer. A hafnium silicate layer, a lanthanum oxide layer, and a titanium nitride layer may be sequentially stacked on the gate dielectric layer 12. When forming the P-type gate structure on the substrate 11, the high-K dielectric layer 13 may include a hafnium silicate layer, an aluminum oxide (AlO) layer, a first titanium nitride layer, a lanthanum oxide layer, and a second titanium nitride layer. A hafnium silicate layer, an aluminum oxide layer, a first titanium nitride layer, a lanthanum oxide layer, and a second titanium nitride layer may be sequentially stacked on the gate dielectric layer 12.
In some examples, the metal layer 15 may include a tungsten (W) layer and titanium silicon nitride silicide (TiSiN). The titanium silicide nitride layer may be located between the tungsten layer and the high-K dielectric layer 13. In other examples, the metal layer 15 may include a tungsten layer and a titanium nitride layer. The titanium nitride layer may be located between the tungsten layer and the high-K dielectric layer 13.
In some examples, first protective layer 16 may include a silicon nitride (SiN) layer. The silicon nitride material is compact and can play a better protection role, and the silicon nitride material is a common material in a semiconductor process and has better process compatibility. In other examples, first protective layer 16 may include other low-k dielectric layers known to those skilled in the art. A first protective layer 16 is located above the metal layer 15 for protecting the metal layer 15.
In some examples, the gate dielectric layer 12, the high-K dielectric layer 13, and the metal layer 15 may be sequentially formed on the silicon substrate 11 by chemical vapor deposition, atomic layer deposition, or any other processes known to those skilled in the art, and the processes for forming the layers may be the same or different.
In some examples, first protective layer 16 may be formed using a plasma (plasma) Radio Frequency (RF) process. For example, the plasma rf process may include an Atomic Layer Deposition (ALD) rf furnace process or a Chemical Vapor Deposition (CVD) rf chamber (chamber) process. The Plasma Enhanced Atomic Layer Deposition (PEALD) process is softer and less harmful to the metal Layer 15. Moreover, compared with a thermal atomic layer deposition (thermal ALD) process, the temperature of the plasma rf process is lower, so as to meet the thermal budget requirement of the metal gate.
In some examples, the temperature at which first protective layer 16 is formed is 450 to 600 degrees. Alternatively, the temperature at which the first protective layer 16 is formed may be 450 degrees, 500 degrees, 550 degrees, 600 degrees, or the like. The temperature when the first protection layer 16 is formed is lower than a preset temperature, the preset temperature may be determined according to the thermal budget of the metal gate, the high temperature process of the first protection layer 16 is changed to a low temperature process, the preset temperature may be lower than the temperature of the thermal furnace process, the temperature of the thermal furnace process is 700 to 740 degrees, and the preset temperature may be lower than 700 degrees.
In some examples, the method of manufacturing a semiconductor may further include forming a polysilicon layer 14 between the high-K dielectric layer 13 and the metal layer 15. In this embodiment, a composite gate of polysilicon and metal can be formed, so that the gate structure has both the advantages of a polysilicon gate and the advantages of a metal gate.
In step S13, please refer to step S13 in fig. 1, the first protective layer 16 is nitrided to remove the impurity element in the first protective layer 16.
In some examples, the impurity element may include an oxygen element, a hydrogen (H) element, a chlorine (Cl) element, and the like. The formation of the first protective layer 16 in a low temperature process may cause impurity elements in the high-K dielectric layer 13 to rise to the first protective layer 16, thereby easily causing a degradation of the quality of the first protective layer 16. In this embodiment, these impurity elements in the first protective layer 16 can be removed by nitriding treatment, thereby improving the quality of the first protective layer 16.
In some examples, nitriding first protective layer 16 includes doping first protective layer 16 with hydrogen in a plasma state and doping first protective layer 16 with nitrogen. Referring to fig. 8 to 11, fig. 8 shows the impurities of oxygen element and chlorine element in the first protective layer 16. By doping hydrogen in a plasma state into first protective layer 16, hydrogen is combined with oxygen to form water (H) 2 O) and combines with chlorine element to form hydrogen chloride (HCl), and the combined gaseous water and hydrogen chloride overflow first protective layer 16. After removing the impurity elements, voids are generated in the first protective layer 16, and the voids can be filled with the nitrogen elements by doping the first protective layer 16 with the nitrogen elements, so that the impurities in the first protective layer 16 can be removed, and the quality of the first protective layer 16 is improved.
In some examples, referring to fig. 2, the method for fabricating a semiconductor structure further includes steps S14 to S16.
Step S14, a mask layer is formed on the first protective layer.
In some examples, referring to fig. 5, mask layer 17 may be formed by an atomic layer deposition process or the like. The mask layer 17 may include a hard mask layer 171 and an anti-reflection layer 172 sequentially formed on the first protective layer 16. The anti-reflection layer 172 may include a silicon oxynitride (SiON) layer, etc.
Step S15, patterning the mask layer.
In some examples, step S15 may include forming a photoresist layer on mask layer 17, performing photolithography on the photoresist layer to define a pattern of the gate structure, and patterning the mask layer based on the patterned photoresist layer.
Specifically, referring to fig. 5 and 6, a Photoresist (PR) layer 18 may be uniformly coated on the mask layer 17 by spin coating, slit coating, or the like. The photoresist layer 18 is exposed by using a mask, and then steps such as development and baking are performed, so that a pattern defining a gate structure is formed on the photoresist layer 18. The anti-reflection layer 172 and the hard mask layer 171 are sequentially etched based on the patterned photoresist layer 18, so that a pattern of a gate structure is formed on the mask layer 17. The photoresist layer 18 and the antireflective layer 172 may then be removed.
And S16, sequentially patterning the first protective layer, the metal layer and the high-K dielectric layer based on the patterned mask layer to form a grid structure.
Specifically, referring to fig. 5 and 6, the first passivation layer 16, the metal layer 15 and the high-K dielectric layer 13 may be sequentially patterned based on the patterned hard mask layer 171 to form a gate structure. The hard mask layer 171 has high hardness, so that the accuracy of the finally formed gate structure pattern can be improved. When the polysilicon layer 14 is further included between the metal layer 15 and the high-K dielectric layer 13, in step S16, the first protection layer 16, the metal layer 15, the polysilicon layer 14, and the high-K dielectric layer 13 may be sequentially patterned based on the patterned hard mask layer 171 to form a gate structure.
In some examples, the growth of silicon dioxide in the gate structure region may be omitted for subsequent processing of the semiconductor structure, so as to avoid the infiltration of oxygen into the gate structure during the annealing of the silicon dioxide layer, which may affect the metal layer 15 (e.g., the titanium silicide nitride layer in the metal layer 15) and the high-K dielectric layer 13 (e.g., the aluminum-containing layer, the lanthanum-containing layer, and the hafnium-containing layer in the high-K dielectric layer 13), thereby avoiding affecting the performance of the semiconductor device including the gate structure.
In some examples, still referring to fig. 2, the method for fabricating the semiconductor structure further includes a step S17 of forming a second passivation layer on the sidewall of the gate structure, wherein the second passivation layer is connected to the first passivation layer.
Specifically, referring to fig. 7, the second protection layer 19 may be directly deposited on the patterned first protection layer 16 by using processes such as atomic layer deposition, and the deposition thickness may be set according to actual requirements. After deposition, the second protective layer 19 may cover the top surface of the first protective layer 16 and the side surfaces of the entire gate structure, and the first protective layer 16 and the second protective layer 19 in combination can cover the top surface and the side surfaces of the gate structure to protect the gate structure.
In some examples, the material of the second protective layer 19 may be the same as the material of the first protective layer 16, for example, both include a silicon nitride layer.
In some examples, the temperature for forming the second passivation layer 19 is lower than the predetermined temperature, and referring to fig. 2, the method for fabricating the semiconductor structure further includes a step S18 of performing a nitridation process on the second passivation layer to remove the impurity elements in the second passivation layer.
In some examples, the temperature at which the second protective layer 19 is formed is 450 to 600 degrees. Alternatively, the temperature when the second protective layer 19 is formed may be 450 degrees, 500 degrees, 550 degrees, 600 degrees, or the like. The temperature when the second passivation layer 19 is formed is lower than a predetermined temperature, which may be determined according to the thermal budget of the metal gate, and the high temperature process of the second passivation layer 19 is changed to a low temperature process, where the predetermined temperature may be lower than the temperature of the thermal furnace process, the temperature of the thermal furnace process is 700 to 740 degrees, and the predetermined temperature may be lower than 700 degrees.
In some examples, the second protective layer 19 may be formed using a plasma rf process. For example, the plasma RF process may include an atomic layer deposition RF furnace process or a chemical vapor deposition RF chamber process. Compared with plasma enhanced atomic layer deposition, the plasma radio frequency process is softer and has less damage to the metal layer 15. In addition, compared with a thermal atomic layer deposition (thermal ALD) process, the temperature of the plasma rf process is lower, so as to meet the thermal budget requirement of the metal gate.
In some examples, the impurity element may include an oxygen element, a hydrogen (H) element, a chlorine (Cl) element, and the like. The formation of the second passivation layer 19 under the low temperature process can increase the impurity elements in the high-K dielectric layer 13 to the second passivation layer 19, thereby easily causing the quality degradation of the second passivation layer 19. In this embodiment, these impurity elements in the second protective layer 19 can be removed by the nitridation treatment, thereby improving the quality of the second protective layer 19.
In some examples, nitriding the second protective layer 19 may include doping hydrogen element in a plasma state into the second protective layer 19, and doping nitrogen element into the second protective layer 19. In a similar manner to the nitriding treatment of the first protective layer 16, hydrogen elements are doped into the second protective layer 19 in a plasma state so that the hydrogen elements are combined with oxygen elements to form water (H), respectively 2 O) and combines with chlorine element to form hydrogen chloride (HCl), the combined gaseous water and hydrogen chloride overflowing the secondA protective layer 19. After the impurity elements are removed, holes are generated in the second protection layer 19, and the holes can be filled with the nitrogen elements by doping the second protection layer 19 with the nitrogen elements, so that the impurities in the second protection layer 19 can be removed, and the quality of the second protection layer 19 is improved.
It should be understood that although the various steps in the flowcharts of fig. 1 and 2 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 1 and 2 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a portion of the steps or stages in other steps.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent application shall be subject to the appended claims.
Claims (15)
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
sequentially stacking a grid dielectric layer, a high-K dielectric layer, a metal layer and a first protective layer on the substrate, wherein the temperature of the first protective layer is lower than the preset temperature;
and carrying out nitridation treatment on the first protective layer to remove impurity elements in the first protective layer.
2. The method of claim 1, further comprising:
forming a mask layer on the first protective layer;
patterning the mask layer;
and sequentially patterning the first protection layer, the metal layer and the high-K dielectric layer based on the patterned mask layer to form a gate structure.
3. The method of claim 2, wherein the patterning the mask layer comprises:
forming a photoresist layer on the mask layer;
photoetching the photoresist layer to define a pattern of the grid structure;
and patterning the mask layer based on the patterned photoresist layer.
4. The method of claim 3, wherein the forming a mask layer over the first protective layer comprises: and sequentially stacking a hard mask layer and an anti-reflection layer on the first protection layer.
5. The method of claim 4, wherein the anti-reflective layer comprises a silicon oxynitride layer.
6. The method of claim 2, further comprising:
and forming a second protective layer on the side wall of the grid structure, wherein the second protective layer is connected with the first protective layer.
7. The method of claim 6, wherein the first protective layer and the second protective layer each comprise a silicon nitride layer.
8. The method for manufacturing a semiconductor structure according to claim 6, wherein a temperature at which the second protective layer is formed is lower than the predetermined temperature; the preparation method of the semiconductor structure further comprises the following steps:
and nitriding the second protective layer to remove the impurity elements in the second protective layer.
9. The method of claim 8, wherein the first and/or second protective layers are formed by a plasma RF process, the plasma RF process comprising an ALD RF furnace process or a CVD RF chamber process.
10. The method according to claim 8, wherein the first protective layer and the second protective layer are formed at a temperature of 450 to 600 degrees.
11. The method for fabricating a semiconductor structure according to any one of claims 1 to 10, wherein the nitriding of the first protective layer comprises:
doping hydrogen element in a plasma state into the first protective layer;
and doping nitrogen elements into the first protective layer.
12. The method of claim 1, further comprising forming a polysilicon layer between the high-K dielectric layer and the metal layer.
13. The method of claim 1, wherein the substrate comprises a silicon substrate, and/or the metal layer comprises a tungsten layer and a titanium silicide nitride layer.
14. The method of claim 1, wherein said gate dielectric layer comprises a silicon dioxide layer and/or said high-K dielectric layer comprises a hafnium silicate layer, a lanthanum oxide layer and a titanium nitride layer when forming an N-type gate structure on said substrate.
15. The method of claim 1, wherein when forming a P-type gate structure on the substrate, the gate dielectric layer comprises a silicon germanium layer and a silicon dioxide layer, and/or the high-K dielectric layer comprises a hafnium silicate layer, an aluminum oxide layer, a first titanium nitride layer, a lanthanum oxide layer, and a second titanium nitride layer.
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