CN115248570A - Development environment and management development operation method of compiling programmable logic controller - Google Patents

Abstract

A development environment for a compiled programmable logic controller comprising: s1: the ladder diagrams are classified: s2: designing a translation template; s3: designing a drive; s4: generating a C language program; s5: compiling a C language program; s6: the executable file is downloaded. The invention has high efficiency, directly translates the graphics primitives of the ladder diagram into C language, and then compiles and executes the graphics primitives, belongs to direct compilation and execution, and greatly improves the execution efficiency. The invention belongs to a form of low-code development, is suitable for ladder diagrams, and provides a technical idea for low-code development and scientific research personnel based on graphs, so that the mixed programming of the ladder diagrams and C language is easier to realize. Meet the expectations of market applications: for PLC research personnel, the invention is easier to add new functional instructions and can quickly adapt to the application requirements of the market.

Description

Development environment and management development operation method of compiling type programmable logic controller

Technical Field

The invention relates to a development environment and a management development operation method of a compiling programmable logic controller, belonging to the technical field of automatic control or regulation systems.

Background

The PLC can be executed in both a compiled and an interpreted manner. The interpretation execution mode has the advantages of small code length, convenient breakpoint setting during debugging and low efficiency; the compiling execution mode has the advantages of high execution efficiency and good real-time performance without explaining the re-execution process, but has poor portability. Although 2016 proposed a solution for translating statement tables into C language, those skilled in the art would prefer to use ladder programming, so that the technical idea adopted at that time is: firstly, the ladder diagram is converted into a statement table, and then the statement table is converted into C language, so that redundant work is caused, and the research and development efficiency of other functional modules of the programmable logic controller is reduced.

Although various schemes for translating statement tables into C language have been disclosed in the meantime, the technical problem of efficient development of new functional modules of programmable logic controllers still cannot be substantially solved:

chinese patent document CN113760298 discloses a method for embedding C language in PLC ladder diagram in the PLC field, including providing a compiling interface of C language function in configuration software, using a compiling tool to compile C language into a machine language which can be used in an embedded system, and obtaining an entry address of the C function; downloading the generated machine code and the mapping relation to a PLC by using configuration software; in the PLC, a machine code is put into a corresponding physical address, and then the machine code is loaded into the PLC in a scattered loading mode; when a user program calls a C-language function in a ladder diagram of the PLC, the PLC obtains an entry address of the C-function through a downloaded mapping relation, converts the entry address into a function pointer, jumps to the C-function of the user through the function pointer and executes the C-language function. However, in this patent document, the C language is embedded in the ladder diagram, the source ladder diagram program is still unchanged, the execution efficiency is not improved, and only the flexibility of function implementation is improved, but the technical problem to be solved by the present invention still cannot be solved, that is, there is no corresponding technical means for converting the graphical language into the C language from the source of the ladder diagram.

Chinese patent document CN207488786 discloses an industrial automation controller, which uses an ARM chip as a controller and Linux as a system environment to realize PLC control. In the document, an IEC2C parser parses a text configuration file (. ST suffix) describing a PLC control logic into a C language program, and then a PLC compiler compiles the C program into a PLC executable program based on a Linux system, and the PLC executable program is run to realize a PLC function on an ARM chip, thereby controlling an industrial device. However, the document only parses the text configuration file into the C language, and does not make too many parsing steps, so that the technical problem proposed by the present invention still cannot be achieved.

Chinese patent document CN101587445 discloses a PLC compiling and executing method, in which a PLC application program written in a programming language supported by IEC61131-3 is converted into a PLC application program described in a standard C language. And finally, compiling the standard C language description file by a compiling technology to generate an application program module which can be directly executed by the PLC, wherein the application program module can be directly executed in a CPU of the PLC, and the program is not required to be executed while being interpreted. However, in this patent document, a statement table, a ladder diagram, a function block diagram, and the like are converted into an intermediate language, and the intermediate language is analyzed into C language. Obviously, the technical problem addressed by the present invention still cannot be solved due to the existence of intermediate processes in the translation method.

In summary, in order to adapt to various scenes of modern industrial control, a development environment of a programmable logic controller with efficient research and development efficiency is urgently needed.

In addition, a management and development operation method for a development environment of a compiled programmable logic controller is also a technical problem which is always concerned by the technical field: in the prior art, the management and development operation is realized based on an interpretation type programmable logic controller, that is, hardware resource configuration parameters need to be downloaded to a PLC hardware FLASH in advance and then interpreted and executed, so that the technical idea has the main disadvantages that the memory space is occupied, a user cannot customize a driving interface in advance, and once the driving interface changes, a kernel driver needs to be rewritten, thereby greatly reducing the development efficiency.

The traditional method of reading file data again after storing in a file results in inconvenience of classification management of real-time data, inconvenience of real-time calling in user programming, and finally greatly reduced execution efficiency, so that a person skilled in the art has proposed an idea of implementing efficient management and development of a programmable logic controller based on a database, but the following technical reasons are limited:

firstly, for the management development of the programmable logic controller for interpretation execution, the interpretation execution is difficult to merge with a database technology; secondly, according to the existing compiling programmable logic controller, as the statement table is converted into the assembly language, the efficient management and development can not be realized by fusing the database technology; finally, although there is a way to convert statements into C-language interpretations for execution in the prior art, such compiled plc is not mature, and thus no precedent about merging database and plc management development tasks can be found.

Furthermore, if only the pin parameters are configured without configuring the driving interface, the driving interfaces can be kept consistent for the same series of hardware with the same model, but due to different circuit design principles of the hardware, hardware level signals of products designed by different engineers are different, for example, whether the scan input is effective at a low level or effective at a high level, if the upper computer cannot configure the driving interface, the bottom layer driving interface needs to be customized again, the principle of software consistency is violated, and the original purpose of design is violated; while the drive interface configuration is more efficient and easy to call only by being configured through a database.

For this reason, the applicant considered by the above-mentioned research that: although there are technical obstacles to the management and development of implementing an efficient plc based on a database technology, the technical idea meets the design requirements of designers, so the applicant has been constantly researching to realize a technical breakthrough.

Disclosure of Invention

Aiming at the defects of the prior art, the invention discloses a development environment of a compiling type programmable logic controller.

The invention also discloses a software interface framework design method of the development environment.

The invention also discloses a development environment management and development operation method of the compiling programmable logic controller.

The invention also discloses the electronic equipment loaded with the development environment of the compiling programmable logic controller.

The invention also discloses a computer program product for realizing the development environment of the compiling type programmable logic controller.

The detailed technical scheme of the invention is as follows:

a development environment for a compiled plc, comprising:

s1: the ladder diagrams are classified:

the method comprises the following steps: the system comprises a basic instruction, a functional module instruction, a functional unit, a variable management unit and a resource configuration unit;

the basic instruction comprises a bit logic operation instruction, a comparison operation instruction, an arithmetic operation instruction, a shift operation instruction and a data block transmission instruction; the bit logic operation instruction comprises a normally open contact LD, a normally closed contact LDN, a rising edge pulse LDP, a falling edge pulse LDF, a coil output =, a coil set S and a coil reset R; the comparison operation instruction comprises a value greater than GT, a value less than LT, a value greater than or equal to GE, a value less than or equal to LE, a value equal to EQ and a value not equal to NE; the arithmetic operation instruction comprises adding ADD, subtracting SUB, multiplying MUL, dividing DIV and taking the remainder MOD; the shift instruction comprises a left shift SHL, a right shift SHR, a cycle left shift ROL and a cycle right shift ROR; the data block transfer instruction includes an assignment MOV;

the functional module instruction comprises a timer instruction, a counter instruction, a pulse output instruction, a serial port communication instruction, a free protocol instruction, a ModBusRTU protocol instruction and an interrupt instruction; the timer instruction comprises a common timer TP, an on-delay timer TON, a memorial on-delay timer TONR and an off-delay timer TOF; the counters comprise an up counter CU, a down counter CD and a high speed counter HSC; the pulse output comprises Pulse Width Modulation (PWM) and a Pulse Train Output (PTO); the serial port communication instruction comprises serial port setting S _ COM, serial port enabling EN _ COM and serial port disabling DIS _ COM; the free protocol instruction comprises an encapsulation sending SND and an unpacking UPK; the ModBusRTU protocol instruction comprises a modbus protocol encapsulation sending instruction MB _ SND and a modbus protocol unpacking instruction MB _ UPK; the interrupt instruction comprises interrupt enable ENI and interrupt disable DISI;

the functional units comprise subprogram units, interrupt program units, C language program units and functional link library units;

the variable management unit is divided into an I area, a Q area, an M area, an SM area, a V area, an AI area, an AQ area, a T area, a C area, an HC area and an S area according to a storage area; dividing the storage type into a global variable, a local variable and a power failure storage variable; the I area refers to a switching value input mapping area; the Q area is a switching value output mapping area; the M area refers to an auxiliary register mapping area; the V area refers to a user-defined global variable mapping area; the AI area refers to an analog input mapping area; the AQ area refers to an analog quantity output mapping area; the T area is a timer variable mapping area; the C area is a counter variable mapping area; the HC is a high-speed counter variable mapping area; the S area is a sequential control relay mapping area;

the resource configuration unit comprises a pin definition, an HSC definition, an interrupt resource, a communication port and a compiling option; the pin definition configuration comprises a digital quantity input and output pin, an analog quantity input and output pin and a high-speed pulse output pin; the HSC definition configuration refers to high-speed pulse input function pin configuration; the interrupt resource configuration refers to interrupt resources of the PLC, and configurable interrupt types comprise a rising edge, a falling edge, HSC counting completion, HSC direction change, HSC external reset, timed interrupt, PTO counting completion, serial port character receiving completion and serial port sending; the communication port configuration comprises a serial port, a network port and a CAN port; the configuration of the compiling options refers to related configuration options required by compiling the ladder diagram after the ladder diagram is translated into the C language, and the related configuration options comprise a header file containing class interface, a hardware initialization interface, a scanning input interface, a scanning output interface, a coil setting interface and a coil resetting interface;

further comprises the following steps: dividing the basic instruction into a type1 basic condition type and a type2 basic output type; the basic condition type refers to a type of instruction representing conditions in a logic row of the ladder diagram, and comprises an open contact LD, a normally closed contact LDN, a rising edge pulse LDP, a falling edge pulse LDF and a comparison operation instruction of a bit logic operation instruction; the basic output type refers to a type of instructions representing output in a logic row of the ladder diagram, and comprises a coil output =, a coil setting S, a coil resetting R, an arithmetic operation instruction, a shift operation instruction and a data block transmission instruction of a bit logic operation instruction;

all the functional module instructions are used as type3 functional instruction output types, the functional instruction output types refer to an execution function represented in a logic line of a ladder diagram, the function is not only a simple logic operation, but also a functional module is realized like a function, for example, a common timer instruction TP, the functional module can normally work by configuring timing time during programming, but a C language driving part needs to do a large amount of function realization work; the functional instruction output type comprises a timer instruction, a counter instruction, a pulse output instruction and an interrupt instruction;

dividing the functional units into type4 subprogram type and type5 linkage type; the subprogram type comprises a subprogram unit and an interrupt program unit; the link type comprises a C language program unit and a functional link library unit;

all the variable management units are used as type6 variable models, wherein the variable models refer to storage units used in a ladder diagram program and comprise global variables, local variables and power-down storage variables;

dividing the resource configuration unit into a type7 pin configuration model and a type8 driving interface type; the pin configuration model refers to that the configuration corresponds to a hardware port, and comprises a digital quantity input and output pin, an analog quantity input and output pin, a high-speed pulse input and output pin, a serial port, a network port and a CAN port; the drive interface type refers to function interfaces of all functional modules packaged by C language;

s2: designing a translation template: respectively designing a basic condition type template, a basic output type template, a functional instruction output type template, a subprogram type template, a link type template, a variable model template, a pin configuration model template and a driving interface type template according to the ladder diagram classification in the step S1, and correspondingly translating the ladder diagram into a corresponding C language program;

s3: and (3) driving design: the method comprises the following steps of respectively realizing C codes for functions related in the working process of a programmable controller, wherein the functions comprise digital input data reading, digital output data writing, analog input data processing, analog output control, basic timer function realization, basic counter function realization, high-speed pulse input function realization, high-speed pulse output function realization, serial port driving and protocol encapsulation function realization, network port driving and protocol encapsulation function realization and CAN driving and protocol encapsulation function realization;

s4: and (3) generating a C language program: translating the ladder diagram edited by the user into a C language code according to the translation template in the step S2, namely, transferring a main program after the ladder diagram is translated into C; then calling the C code generated by the drive design in the step S3 in the main to form a complete set of C language program;

s5: compiling a C language program: compiling the C language code program into binary executable codes through a compiler;

the C language program compiling adopts 'GCC + Makefile' compiling; the GCC is a short for GCC cross compiling tool, and is a link library generated according to the cross compiling of an actual CPU product, for example, a GCC-arm-none-easy tool adopted by STM 32; the Makefile is a short for customizing a compiling flow according to a CPU product; the compiling process comprises the following steps: defining a target variable, locating a C source code file, locating an S starting file, correlating a compiling tool, processing a special mark, locating an H head file, generating a library, processing and clearing a function pseudo code;

s6: downloading an executable file: and programming the binary executable code into a programmable controller.

According to the present invention, the basic condition type template is an "if (condition)" part in the "if (condition) { function body }" format, for example, a normally open contact of a switch key may be translated into "if (key _ val = = 1)", a normally closed contact of the switch key may be translated into "if (key _ val = = 0)", and a value of the key _ val is implemented by writing a switching value input driver; in particular, the rising edge and falling edge commands need to consider the state memory problem on the basis of the above-mentioned template, for example, the rising edge of the switch key may be translated into "if ((key _ val _ new = = 1) & (key _ val _ old = = 0)) key _ val _ old = key _ val _ new", the falling edge of the switch key may be translated into "if ((key _ val _ new = = 0) & (key _ val _ old = = 1)) key _ val _ old = key _ new", the key _ val _ new refers to the read value of the current switching value, and the key _ val _ old refers to the read value of the switching value of the previous scanning period.

According to the present invention, the basic output type template is preferably a "{ function }" part in "if (condition) { function }" format, for example, coil setting of the indicator lamp Q can be translated into "{ write _ Q, out _ val }", the operation of the write _ Q being realized by programming a switching value output driver, the out _ val being obtained by programming a switching value input driver; for example, an add instruction may translate to "{ C = a + B }", where C must be a variable, and where a and B may be variables or values; particularly, the coil output command needs to consider the dual-coil output problem on the basis of the appellation template, specifically, on the basis of the coil setting, reverse judgment is added, for example, the coil output of the indicator lamp Q can be translated into "{ write _ Q, out _ val, temp _ out _ val; if (| temp _ out _ val) |! write _ Q,! out _ val; temp _ out _ val =0; } "; the temp _ out _ val is an auxiliary memory value of out _ val, the "! The + variable "means that the value of the variable is inverted.

According to a preferred embodiment of the present invention, the function instruction output type template includes: (1) The structure body definition means that variables required by corresponding functions are packaged in one structure body, for example, the structure body content of the related instructions of the timer comprises a start-stop mark, a time base, a counter type, a stop mark, a loading mark, a timing-to-reach mark, a counting variable and a pre-value variable; (2) The method comprises the steps of defining a structure array and a structure array length, wherein the structure array definition refers to the fact that global definition is firstly made in a C file of a timer driver, and the structure array length definition refers to the fact that global definition is firstly made in the C file of the timer driver; (3) The method comprises the steps of a structure array and a structure array length statement, wherein the structure array length statement refers to the fact that a global statement is made in an H file of a timer driver, and the structure array statement refers to the fact that the global statement is made in the H file of the timer driver; (4) Defining and realizing an interface function, wherein the interface function is called in a main loop body when the ladder diagram is translated into the C language; in particular, the functions to be performed in the interrupt are required, and the interface function does not have to be designed.

According to the invention, the subprogram type template is a function interface for generating the ladder diagram subprogram into a C language program for calling a main function or a function associated with the main function; in particular, the interrupt subprogram needs to generate an interrupt function interface of the C language program, and execution is interrupted without calling.

According to the optimization of the invention, the link type template means that a function is packaged into a link port, and other functions directly call the link port; in particular, the link library unit is an already packaged link port, and can be directly called without being packaged again.

According to the invention, the variable model template is preferably defined by the variable definition of the user according to the variable definition rule of the C language, and simultaneously, the PLC variable type and the data type of the C language are translated in a one-to-one correspondence manner, for example, the 'signed integer' of the PLC is translated into the C language which is 'int'; in particular, the power-down save variable needs to save data in a flash to prevent loss of power-down.

According to the invention, the pin configuration model template refers to the configuration that hardware pins of the PLC correspond to pins of the CPU one by one, such as a digital input pin I0.0, and the pin corresponding to the CPU is P1.0; in particular, the encoder mode of the high-speed counter instruction requires 2 or 3 pins, and requires 2 or 3 pins.

According to the present invention, preferably, the drive interface type template refers to a drive interface encapsulated in a bottom layer, and the configuration call is directly performed according to a reference format, for example, a scan input interface is read (% gpio port%,% gpio pin%, 0), where a variable between two percentile numbers belongs to a pin configuration configured by a user in a reference database.

According to a preferred embodiment of the present invention, in step S6, the downloading manner for downloading the executable file includes a wireless manner or a wired manner; the wireless mode refers to an OTA downloading mode; the wired mode refers to a Jlink downloading mode, and is specifically realized by adopting a syntax instruction of JLINK-Commander.

The software interface framework design method of the development environment is characterized by comprising the following steps:

a menu bar, a toolbar, a left tree form, a right tree form, and a middle ladder diagram editing area, as shown in fig. 2;

the menu bar comprises an engineering menu, an editing menu, a compiling menu and a help menu; the project menu comprises new creation, opening, storage and printing; the editing menu comprises undo and reinstate; the compiling menu comprises a building function and a downloading function, wherein the building function is used for converting the target ladder diagram into the C language and compiling the C language into binary executable codes;

the tool bar comprises an engineering tool, an editing tool and a compiling tool; the engineering tools comprise new construction, opening, storage and printing; the editing tool comprises revocation and recovery; the compiling tool comprises a construction function and a downloading function; the toolbar function is consistent with the menu function;

the left tree form comprises a first-level branched ladder diagram program and an element box; the first-level ladder diagram program comprises a second-level branch main program, subprograms, an interrupt program and a quick index; the main program is used for: when the middle ladder diagram editing area is in a subprogram or an interrupt program interface, switching to the editing interface of the main program by clicking the 'main program' editing area; the subroutine is for: when a subprogram is added, the subprogram is created, when a user needs to add the subprogram, right-clicking 'add' can pop up a dialog box for creating the subprogram, the dialog box for creating the subprogram comprises a name, an author, a date, remarks and a confirmation button, referring to the attached figure 3, the created subprogram names are listed below a secondary branch of the subprogram and belong to a tertiary branch, a main interface can be switched to a corresponding subprogram interface by clicking a subprogram index name, and the subprogram can be called by dragging the subprogram name; the interrupt routine is operable to: when an interrupt program needs to be added, an interrupt program dialog box is created, right-clicking 'adding' pops up the interrupt program dialog box, the interrupt program dialog box comprises a name, interrupt resources, a description, an author, a date, remarks and a determination button, referring to the attached drawing 4, the interrupt program name created by a user is listed below a secondary branch of the interrupt program and belongs to a tertiary branch, and a main interface can be switched to a corresponding interrupt program interface by clicking an interrupt program index name; the fast index is to: listing program function index directories of the main program, the subprogram or the interrupt program displayed on the current main interface, referring to fig. 5; the component cartridge is configured to: the instruction primitive list used by the rowed ladder diagram comprises a bit logic operation instruction, a comparison operation instruction, an arithmetic operation instruction, a shift operation instruction, a data block transmission instruction, a timer, pulse output, serial port communication, a ModbusRTU protocol and an interrupt instruction; the system is also used for dragging the instruction primitive corresponding to the instruction to an editing interface area for placing through signal input hardware;

the right tree form comprises a global variable table, a local variable table, a timer list, a counter list, PWM, COM, system variables, IO variable tables and PLC resource allocation buttons; the global variable table comprises user-defined global variables and power-down storage variables and is also used for clicking the global variable table to establish the global variables, for example, clicking a plus button on a row to establish the global variables; the local variable table is used for listing local variables defined by the current main interface program, the table changes along with the switching of the main interface program, and is also used for clicking the local variables newly built by clicking the local variable table and clicking the '+' button of the line to newly build the local variables; the timer list is used for listing timer type variables defined in a program; the counter list is used for listing counter type variables defined by a program; the PWM list is used for listing PWM type variables defined by a program; the COM list is used for listing program definition COM type variables; the system variables are used for listing the globally usable variables which can be used without program definition by the system; the IO variable table is used for: listing IO pin conditions owned by PLC hardware supported by the current engineering, wherein the IO pin conditions comprise a symbol name and a pin name; the PLC resource configuration button is used for PLC hardware configuration, and referring to fig. 6, after clicking, a PLC hardware configuration dialog box is popped up, and the PLC hardware configuration dialog box includes a PLC type list part, a "use this PLC" button, a "rename" button, a "delete this PLC" button, a "add PLC" button, a pin definition list, an HSC definition list, an interrupt resource list, a communication port list, and a compiling option interface; the header of the pin definition list comprises a serial number, a type, a display name, a PLC variable name, a CPU pin, a remark, a CPU port number and a CPU pin number; the HSC definition list header comprises a name, a pin1, a pin2, a direction pin, a reset pin and a description; the interrupt resource list header comprises an event number, a type, a PLC pin, a CPU pin, a description, a gpioPort and a gpioPin; the communication port list header comprises a port name, a type, a sending pin, a receiving pin and a control pin; the compiling option interface comprises a header file include, a hardware initialization interface function, a scanning input interface function, a scanning output interface function, a coil setting interface function and a coil resetting interface function;

the middle ladder diagram editing area, see fig. 7, includes a program name display switching area, a program description, a label definition, a logic line annotation, and a logic line editing area; the program name display switching area is used for: displaying the opened main program subprogram or the interrupted program, switching to a corresponding program interface by clicking the program name, and hiding the program by a right key; the program instructions are for: performing annotation description on a currently edited program, wherein fields comprise program names, authors, dates and annotations and are displayed on the top line of an editing area; the tag definition is used to: the simplified summary of the ladder diagram function is displayed on one side of the logic row of the editing area, and the simplified summary is also used for automatically generating a label under the quick index, specifically, on the left side of the logic row of the editing area, a more complete function simplified summary is provided, and the label can be automatically generated under the quick index and can be quickly positioned; the logical line annotation is to: the method comprises the following steps of (1) carrying out annotation description on a program of a current logic line, and designing the program at the top of each logic line; the logical line editing is to: and programming a ladder diagram in the area, wherein the variable of each instruction is displayed below the corresponding instruction, and simultaneously, the multi-element operation instruction is displayed in a formula form of mathematical calculation.

In the left tree form, a subprogram and an interrupt program can directly perform right key new creation and dragging calling in the tree form structure, and compared with the conventional calling in a menu, the method is more intuitive and easier to learn;

variable display and definition functions are designed in the right tree form, and compared with the conventional method that a variable dialog box is called through a menu for definition, the right tree form is more convenient for a user to program and use and more intuitive to read; a PLC hardware configuration inlet is designed at the IO pin list, so that a user can easily imagine the function, and a beginner can get hands easily;

in the middle ladder diagram editing area, the variable display mode of design is different in comparison with the primitive design mode in conventional ladder diagram programming, and traditional primitive instruction is the function block diagram more, and is in disorder to whole composing like this, and this patent adopts same basic primitive, through the relation of the form expression a plurality of variables of instruction primitive below display formula, and is more directly perceived, easier understanding.

An electronic device loaded with a development environment of a compiled programmable logic controller,

at least one processor; and a memory coupled with the at least one processor, the memory having instructions stored therein that, when executed by the at least one processor, cause the electronic device to perform acts for managing development jobs in a development environment, the acts comprising:

classifying the ladder diagram; designing a translation template: respectively designing a basic condition type template, a basic output type template, a functional instruction output type template, a subprogram type template, a link type template, a variable model template, a pin configuration model template and a driving interface type template according to the classification of the ladder diagram, and correspondingly translating the ladder diagram into a corresponding C language program; and (3) drive design: respectively implementing C codes for functions related to the working process of the programmable controller; and (3) generating a C language program: translating the ladder diagram edited by the user into a C language program according to the translation template in the step S2, and then integrating the ladder diagram with the driving design in the step S3 into a complete C language program; compiling a C language program: compiling the C language program into binary executable codes through a compiler; downloading an executable file: and programming the binary executable code into a programmable controller.

A computer program product implementing a development environment for a compiled programmable logic controller, the computer program product being tangibly stored on a non-transitory computer-readable medium and including machine-executable instructions for performing the method described above.

The development environment management and development operation method of the compiled PLC is characterized by comprising the following steps:

t1: designing a database structure comprises dividing PLC configurable hardware resources into the following database entities and associated database entities;

as shown in the database structure chen's diagram of fig. 12, according to the principle that the same entity attribute of the database is the same, the PLC configurable hardware resource is divided into the following database entities, including: the method comprises the following steps of PLC model, general IO pin configuration, HSC pin configuration, communication resource pin, interrupt source configuration and drive interface configuration;

the PLC model refers to the serial model name of PLC hardware and is visible when a user selects the model; the configuration attributes comprise a CPU type and a PLC model; the CPU type is STM32F103VET6; the PLC model is SK2109;

the general IO pin configuration comprises a configuration switching value IO pin, an analog value IO pin and a high-speed pulse output pin; the common configuration attributes comprise IO types, symbol names, PLC variable names, CPU pins, CPU port numbers, CPU pin numbers and descriptions; the IO types comprise a switching value input type DI, a switching value output type DO, an analog value input type AI, an analog value output type AQ and a high-speed pulse output type PWM; the symbolic name is an alias name given to the pin by the user and can be called in programming; the PLC variable names are I0.0, Q2.1 and PWM0, and can be directly called by a user; the CPU pins such as PA6 and P3.5 have different naming rules of different CPU types; the CPU port number and the CPU pin number are analyzed according to the CPU pin, if the CPU pin is PA6, the CPU port number is 1, the CPU pin number is 6, if the CPU pin is P3.5, the CPU port number is 3, the CPU pin number is 5; the description refers to the functional description of the configuration pin;

the HSC pin configuration refers to high-speed pulse input pin configuration, and has common configuration attributes including HSC name, pin1, pin2, direction pin, reset pin and description; the HSC name is HSC0; the pin1 is a first high-speed pulse input port, such as I0.3/PC6; the pin2 is a second high-speed pulse input port, such as I0.4/PC7; the direction pin refers to an external direction control pin in a working mode that the HSC has a function of controlling the direction, can be shared with the pin2, but is not compatible; the reset pin refers to an external reset pin in a working mode that the HSC has an external reset function; the description refers to the functional description of the HSC configuration pin;

the communication resource pins are used for serial port communication, network port communication and CAN communication, and have common configuration attributes including communication names, communication protocols, PLC pins, CPU port numbers, CPU pin numbers and descriptions; the communication name is an alias configured for the communication and can be called by a user; the communication protocols are different aiming at different communication port protocols, the serial port communication protocol comprises a free protocol and a Modbus protocol, the network port communication protocol comprises ProfiNet and EtherCat, and the CAN communication comprises CANopen and a standard CAN protocol;

the interrupt source configuration has common attributes including an interrupt number, an interrupt type, a PLC pin, a CPU port number, a CPU pin number and a description; the interrupt number is the only code of the interrupt source, such as INT0; the interrupt types comprise a rising edge, a falling edge, a serial port receiving character, a serial port receiving completion, a serial port sending, a timing interrupt of a control time interval, a timing-to-interrupt when the current time is equal to a preset value, a high-speed counting interrupt when the current value is equal to the preset value, a high-speed counting interrupt of direction change, a high-speed counting interrupt of external reset, and a PTO pulse counting completion interrupt;

the drive interface is configured, and the configuration attributes comprise a header file, a hardware initialization interface, a scanning input interface, a scanning output interface, a coil setting interface and a coil resetting interface; the include header file, such as # include "main.h"; the hardware initialization interface, such as PlcInit (); the scan input interface is such as readDIO (% gpioPort%,% gpioPin%, 0), where gpioPort represents a CPU port number, gpioPin represents a CPU pin number, and 0 represents active low; the scanout interface readDIO (% gpio port%,% gpio pin%, 1), where gpio port represents a CPU port number, gpio pin represents a CPU pin number, and 1 represents high level valid; the coil setting interface is such as write (% gpio port%,% gpio pin%, 1), wherein gpio port represents a CPU port number, gpio pin represents a CPU pin number, and 1 represents setting; the coil reset interface is such as write (% gpio port%,% gpio pin%, 0), wherein gpio port represents a CPU port number, gpio pin represents a CPU pin number, and 0 represents reset;

the associated database entity comprising: the PLC model and the IO pin configuration, the HSC pin configuration, the communication resource pin and the interrupt source configuration belong to an incidence relation of 1 to n respectively, the PLC model and the drive interface configuration belong to an incidence relation of 1 to 1, the interrupt source configuration and the general IO pin configuration and the HSC pin configuration belong to an incidence relation of m to n respectively, and specifically, the PLC model and the general IO pin configuration belong to an incidence relation of 1 to n, namely, one to many, and a PLC model can be configured with a plurality of general IO pin configurations; the PLC model and HSC pin configuration belong to an incidence relation of 1 to n, namely one to many PLC models can be configured with a plurality of HSC pin configurations; the PLC models and the communication resource pins belong to an incidence relation of 1 pair n, namely one pair is multiple, and a plurality of communication resource pins can be configured in one PLC model; the PLC models and the interrupt source configurations belong to an incidence relation of 1 pair n, namely one pair is multiple, and one PLC model can be configured with a plurality of interrupt source configurations; the PLC model and the drive interface configuration belong to an incidence relation of 1 to 1, namely, one PLC model can only correspond to one set of drive interfaces, and each drive interface is unique; the interrupt source configuration and the general IO pin configuration belong to an incidence relation of m to n, namely many-to-many, a plurality of interrupt source configuration lists refer to the configuration of the general IO port, and the general IO port configuration can be called in a plurality of interrupt sources; the interrupt source configuration and the HSC pin configuration belong to an incidence relation of m to n, namely many to many, a plurality of interrupt source configuration lists refer to the HSC pin configuration, and one HSC pin configuration can be called in a plurality of interrupt sources;

t2: universal drive design

After the hardware resources of the PLC are configured, the database parameters are called during programming, and before a PLC user main program is formed, a driver is required to be designed to identify the configuration parameters; the generic driver design includes: the method comprises the following steps of designing a general IO driver, a general functional instruction driver and a general interrupt function; the IO comprises DI and DO; the functional instructions include timer instructions, counter instructions, PWM, PTO, HSC, communications.

Preferably, according to the present invention, the general IO driver design includes:

(1-1) defining an IO pin structure: the IO pin structure body is characterized in that a structure body variable is defined based on C language, port information of IO is packaged in the structure body, the IO pin structure body is defined as tPin _ IO and comprises two members, wherein one member is an unsigned 8-bit integer variable gpioPort, and the other member is an unsigned 8-bit integer variable gpioPin; the tPin _ IO is the name of an IO pin structure body; the gpioPort is a port number of a CPU pin; the gpioPin is the pin number of the CPU pin;

(1-2) instantiating an IO pin structure body variable and defining the number of members of the instantiated variable, and instantiating a structure body pointer variable named IOConf according to the IO pin structure body defined in the step (1-1); defining a variable of a loading quantity for the pointer variable, wherein the variable is an unsigned 8-bit integer variable and is named as ioCnt;

(1-3) initializing variables of the quantity of pointer variables of the loaded structure and the pointer variables of the structure, and initializing the variables ioCnt of the quantity of the pointer variables of the loaded structure defined in the step (1-2) according to the quantity of IO variables configured by a user; according to the value of ioCnt and the memory size of the structure tPin _ IO, allocating space for the structure pointer variable ioConf through malloc keywords; finally, initializing member variables gpioPort and gpioPin of a structure pointer variable ioConf according to an IO pin configuration parameter configured by a user;

(1-4) designing an IO pin configuration interface and a read-write IO drive interface, and designing the IO pin configuration interface and the read-write IO drive interface according to the gpioPort, gpioPin and ioCnt initialized in the step (1-3);

the IO pin configuration interface process is as follows: configuring a CPU pin in a cycle from 0 to ioCnt, wherein the configuration content comprises a configuration pin clock, a configuration corresponding pin register and a configuration pin port register; the read-write IO driving interface finds a corresponding port according to the gpioPort and then calls a read-write register to perform corresponding functional operation;

generally, the value of the drive register related to the CPU pin can be obtained by calculation according to a port value port and a pin value pin of the CPU pin, the port value port of the CPU is gpio port, the pin value pin of the CPU is gpio pin, and the values of gpio port and gpio pin are obtained by initialization of parameters configured by a user in step (1-3), so that a universal IO pin configuration interface and a read-write IO drive interface can be packaged; the calculation rules of the calculation are different according to different CPUs, and need to be summarized and obtained according to a CPU chip use manual.

Preferably, according to the present invention, the general functional instruction-driven design includes:

(2-1) defining a functional instruction structure, wherein the functional instruction structure is characterized in that a structure variable is defined based on C language, parameters related to a functional instruction are encapsulated in a structure for convenient management and calling, and the structure is named as tFunc;

(2-2) instantiating a function type instruction structure variable and defining the number of members of the instantiated variable, and instantiating a structure pointer variable named as pFanc according to the function type instruction structure defined in the step (2-1); defining a variable of loading quantity for the pointer variable, wherein the variable is an unsigned 8-bit integer variable and is named as cntFunc;

(2-3) initializing variables for loading the quantity of variables of the structure pointer and the variables of the structure pointer, and initializing the variables cntFunc for loading the quantity of the variables of the structure pointer defined in the step (2-2) according to the quantity of the variables of the function instruction called in the user programming; according to the value of the cntFunc and the memory size of the structure tFunc, distributing space for the structure pointer variable pFanc through malloc keywords; finally, initializing member variables of the structural body pFanc according to the configuration condition of functional instruction parameters called in user programming; preferably, if the functional instruction structure has parameters related to hardware port information, the related configuration data is called to initialize the hardware configuration related member variables of the pFunc;

(2-4) designing and realizing a functional instruction initialization interface and a driving interface, and designing the functional instruction initialization interface and the driving interface according to the pFanc and the cntFunc initialized in the step (2-3); initializing corresponding function registers according to different types of CPU pins used by different functions; the driver interface is invoked when a user configures the driver interface.

Preferably, according to the present invention, the general interrupt function design includes:

(3-1) an interrupt function macro definition, which is to define an interrupt macro first when an interrupt interface is called by a user; the interrupt interface called by the user must be defined in the interrupt resource configuration before being called; the interrupt macro refers to a macro, which is named as USE _ PLCINT _ T0_ TIM and represents certain interrupt, such as timing interrupt, by the macro definition;

(3-2) defining an interrupt service function, and when a user calls an interrupt interface, defining an interrupt service function, such as the interrupt service function named PLCINT _ T0_ IRQHandler () of timed interrupt, wherein the interrupt program written by the user in the ladder diagram programming generates a C language interrupt program after converting the interrupt program from the ladder diagram language to C language, and encapsulates the C language interrupt program in the interrupt service function;

(3-3) declaring an interrupt service function in advance, and declaring the interrupt service function in advance by adopting a conditional compiling method according to the interrupt macro in the step (3-1), so that the interrupt service function can be called in other files conveniently;

(3-4) preprocessing interrupt service basic functions, wherein each interrupt function needs to be processed by some basic functions in advance to cushion the interrupt service functions of a user, such as clock initialization work of timed interrupt; in order to facilitate the implementation of the basic function, the interrupt macro in the step (3-1) is combined, and a conditional compiling mode is adopted for preprocessing, wherein the conditional compiling conditions are all the middle piece macro in the step (3-1), only one conditional compiling is used for declaring an interrupt service function in advance, and the other conditional compiling is used for preprocessing an interrupt service basic function.

The technical advantages of the invention are as follows:

1. for the development environment of the compiled programmable logic controller of the invention:

the efficiency is high, the primitives of the ladder diagram are directly translated into the C language and then compiled and executed, and the method belongs to direct compiling and execution and greatly improves the execution efficiency.

The invention belongs to a form of low-code development, is suitable for ladder diagrams, and provides a technical idea for low-code development and scientific research personnel based on graphs, so that the mixed programming of the ladder diagrams and C language is easier to realize.

Meet the expectations of market applications: for PLC research personnel, the invention is easier to add new functional instructions and can quickly adapt to the application requirements of the market.

2. For the software interface framework design method of the development environment:

the invention records and plays the operation buttons of the newly-built subprogram and the newly-built interrupt program together with the index object, but not in the menu bar and the tool bar, so that the programmer is more convenient to learn and operate; similarly, the PLC resource allocation button is placed together with the IO list, which is also convenient for the programmer to find and use. The description information of the program is placed at the top of the editing area, and the form of a dialog box is not opened by the common technology, so that the program is easier to read; the variable display is placed in the tree-shaped window on the right side instead of the conventional pop-up dialog box, so that the variable display is more convenient for a user to look up; the variable definition position has various modes, a right variable display column can add new variables by clicking "+" or double clicking primitives in the programming process of the ladder diagram, and the operation of a user is more convenient.

The invention designs a universal adaptive dialog box template, so that one design can be used in any occasions; compared with conventional file storage, the database storage mode is adopted, and calling, storage and management are easier; compared with the design of the conventional PLC, the interrupt program function abandons the instruction association mode, and establishes the association in the interrupt program dialog box, so that the interrupt program function is more visual and easier to understand.

3. Aiming at the development environment management development operation method of the invention:

the invention stores the hardware resource information configured by the programming software end into the database, calls the corresponding configuration information in the database when a user programs, generates the PLC execution code, downloads and executes, and does not need to download all parameters into the memory of the PLC, thereby saving the memory space and improving the working efficiency.

According to the hardware resource configuration method based on the database, interrupt resource configuration and drive interface configuration are added, the problem that the same function drive interfaces of different CPUs are inconsistent is solved, and rapid construction of a PLC is facilitated.

The method is designed from three angles of a universal IO driver design, a universal functional instruction driver design and a universal interrupt function design, and adopts a flow design idea, so that the PLC kernel driver can be quickly customized by the flow design.

Drawings

FIG. 1 is a basic flow diagram of the present invention;

FIG. 2 is a schematic diagram of a main interface of the development environment of the present invention, where S1 is a menu bar, S2 is a toolbar, S3 is a left tree form, S4 is a right tree form, and S5 is a middle ladder editing area;

FIG. 3 is a create subroutine dialog box;

FIG. 4 is a create interrupt routine dialog box;

FIG. 5 is a schematic diagram of a fast index;

fig. 6 is a PLC hardware configuration dialog, S6 is a PLC hardware configuration dialog main interface, S7 is a pin definition configuration section, S8 is an interrupt resource configuration section, S9 is a communication port configuration section, and S10 is a compilation option configuration section;

fig. 7 is a schematic diagram of a ladder diagram editing area, S11 is a program name display switching area, S12 is a program description, S13 is a logic line comment, S14 is a tag definition, and S15 is a logic line editing area;

FIG. 8 is a ladder diagram design of the test program of "example 2", S16 being a main program, S17 being a subroutine, S18 being an interrupt program;

FIG. 9 is a schematic diagram of ladder to C code key code for the test program of "embodiment 2"; s19 is a header file, a function statement and a global variable definition code, wherein S19-1 is the header file, S19-2 is a sub-function statement, S19-3 is a digital quantity input output global variable definition, and S19-4 is a coil output memory variable global statement; s20 is main function content, wherein S20-1 is external interrupt pin initialization, S20-2 is space allocation, array length initialization and intra-structure variable initialization of a switching value input and output data structure array, S20-3 is PLC other drive initialization, S20-4 is a main loop area, wherein S20-4-1 is a scanning input variable, and S20-4-2, S20-4-3 and S20-4-4 realize a coil output function;

FIG. 10 is a diagram showing the test program compiling process in example 2;

FIG. 11 is a view showing a test program download process according to "embodiment 2";

FIG. 12 is a diagram of a database structure chen's;

FIG. 13 is a key code diagram of steps (1-1), (1-2), and (1-3) of an embodiment of the general IO driver design;

FIG. 14 is a flowchart of IO configuration work in the steps of an embodiment (1-4) of the general IO driver design;

FIG. 15 is a read IO workflow diagram of the steps of the general IO driver design embodiment (1-4);

FIG. 16 is a schematic diagram of the key code of an embodiment of a generic functional instruction driven design;

FIG. 17 is a key code diagram of a generalized interrupt function design embodiment.

FIG. 18 is a ladder diagram based on GX Works2 in the "comparative test" step U1;

FIG. 19 is a graph showing the result of the operation based on the explanatory PLC in the "comparative test" step U1;

FIG. 20 is a ladder diagram of a newrad according to the invention in a "comparative test" step U2;

FIG. 21 is a graph of the results of the run of a compiled PLC based on the present invention in "Compare test" step U2;

FIG. 22 is a ladder diagram based on GX Works2 in the "comparative test" step U3;

FIG. 23 is a graph showing the operation result based on the explanatory PLC in the "comparative test" step U3;

FIG. 24 is a ladder diagram of a newrad according to the invention in a "comparative test" step U4;

FIG. 25 is a graph of the results of the run of a compiled PLC based on the present invention in "Compare test" step U4;

FIG. 26 is a ladder diagram based on GX Works2 in the "comparative test" step U5;

FIG. 27 is a graph showing the operation result based on the explanatory PLC in the "comparative test" step U5;

FIG. 28 is a ladder diagram of a newrad according to the invention in "comparative test" step U6;

FIG. 29 is a graph showing the operation result of the compiled PLC according to the present invention in the "comparison test" step U6;

FIG. 30 is a comparison chart of the single instruction result analysis in the "comparison test" step U7.

Detailed Description

The invention is described in detail below with reference to the following examples and the accompanying drawings of the specification, but is not limited thereto.

Examples 1,

A development environment for a compiled programmable logic controller, comprising:

as shown in figure 1 of the drawings, in which,

s1: the ladder diagrams are classified:

the method comprises the following steps: the system comprises a basic instruction, a functional module instruction, a functional unit, a variable management unit and a resource configuration unit;

the basic instruction comprises a bit logic operation instruction, a comparison operation instruction, an arithmetic operation instruction, a shift operation instruction and a data block transmission instruction; the bit logic operation instruction comprises a normally open contact LD, a normally closed contact LDN, a rising edge pulse LDP, a falling edge pulse LDF, a coil output =, a coil set S and a coil reset R; the comparison operation instruction comprises a value greater than GT, a value less than LT, a value greater than or equal to GE, a value less than or equal to LE, a value equal to EQ and a value not equal to NE; the arithmetic operation instruction comprises adding ADD, subtracting SUB, multiplying MUL, dividing DIV and taking the remainder MOD; the shift instruction comprises a left shift SHL, a right shift SHR, a cycle left shift ROL and a cycle right shift ROR; the data block transfer instruction includes an assignment MOV;

the functional module instruction comprises a timer instruction, a counter instruction, a pulse output instruction, a serial port communication instruction, a free protocol instruction, a ModBusRTU protocol instruction and an interrupt instruction; the timer instruction comprises a common timer TP, an on-delay timer TON, a memorial on-delay timer TONR and an off-delay timer TOF; the counters comprise an up counter CU, a down counter CD and a high speed counter HSC; the pulse output comprises Pulse Width Modulation (PWM) and a Pulse Train Output (PTO); the serial port communication instruction comprises serial port setting S _ COM, serial port enabling EN _ COM and serial port disabling DIS _ COM; the free protocol instruction comprises an encapsulation sending SND and an unpacking UPK; the ModBusRTU protocol instruction comprises a modbus protocol packaging and sending instruction MB _ SND and a modbus protocol unpacking instruction MB _ UPK; the interrupt instruction comprises interrupt enable ENI and interrupt disable DISI;

the functional units comprise subprogram units, interrupt program units, C language program units and functional link library units;

the variable management unit is divided into an I area, a Q area, an M area, an SM area, a V area, an AI area, an AQ area, a T area, a C area, an HC area and an S area according to storage areas; dividing the storage type into a global variable, a local variable and a power failure storage variable; the I area refers to a switching value input mapping area; the Q area refers to a switching value output mapping area; the M area refers to an auxiliary register mapping area; the V area refers to a user-defined global variable mapping area; the AI area refers to an analog input mapping area; the AQ area refers to an analog quantity output mapping area; the T area is a timer variable mapping area; the C area is a counter variable mapping area; the HC is a high-speed counter variable mapping area; the S area is a sequential control relay mapping area;

the resource configuration unit comprises a pin definition, an HSC definition, an interrupt resource, a communication port and a compiling option; the pin definition configuration comprises a digital quantity input and output pin, an analog quantity input and output pin and a high-speed pulse output pin; the HSC definition configuration refers to high-speed pulse input function pin configuration; the interrupt resource configuration refers to interrupt resources of the PLC, and configurable interrupt types comprise a rising edge, a falling edge, HSC counting completion, HSC direction change, HSC external reset, timed interrupt, PTO counting completion, serial port character receiving completion and serial port sending; the communication port configuration comprises a serial port, a network port and a CAN port; the configuration of the compiling options refers to relevant configuration options required by compiling the ladder diagram after the ladder diagram is translated into the C language, and the relevant configuration options comprise a header file containing class interface, a hardware initialization interface, a scanning input interface, a scanning output interface, a coil setting interface and a coil resetting interface;

further comprises the following steps: dividing the basic instruction into a type1 basic condition type and a type2 basic output type; the basic condition type refers to a type of instruction representing conditions in a logic row of the ladder diagram, and comprises an open contact LD, a normally closed contact LDN, a rising edge pulse LDP, a falling edge pulse LDF and a comparison operation instruction of a bit logic operation instruction; the basic output type refers to a type of instructions representing output in a logic row of the ladder diagram, and comprises a coil output =, a coil setting S, a coil resetting R, an arithmetic operation instruction, a shift operation instruction and a data block transmission instruction of a bit logic operation instruction;

the functional module instructions are all used as type3 functional instruction output types, the functional instruction output types are that an execution function is represented in a logic line of a ladder diagram, the function is not only a simple logic operation, but a functional module is realized like a function, for example, a common timer instruction TP, the functional module can normally work by configuring timing time during programming, but a C language driving part needs to do a large amount of function realization work; the functional instruction output type comprises a timer instruction, a counter instruction, a pulse output instruction and an interrupt instruction;

dividing the functional units into type4 subprogram types and type5 link types; the subprogram type comprises a subprogram unit and an interrupt program unit; the link type comprises a C language program unit and a functional link library unit;

all the variable management units are used as type6 variable models, and the variable models refer to storage units used in a ladder diagram program and comprise global variables, local variables and power failure storage variables;

dividing the resource configuration unit into a type7 pin configuration model and a type8 driving interface type; the pin configuration model means that the configuration corresponds to a hardware port and comprises a digital input/output pin, an analog input/output pin, a high-speed pulse input/output pin, a serial port, a network port and a CAN port; the drive interface type refers to function interfaces of all functional modules packaged by C language;

s2: designing a translation template: respectively designing a basic condition type template, a basic output type template, a functional instruction output type template, a subprogram type template, a link type template, a variable model template, a pin configuration model template and a driving interface type template according to the ladder diagram classification in the step S1, and correspondingly translating the ladder diagram into a corresponding C language program;

s3: and (3) drive design: the method comprises the following steps of respectively realizing C codes for functions related in the working process of a programmable controller, wherein the functions comprise digital input data reading, digital output data writing, analog input data processing, analog output control, basic timer function realization, basic counter function realization, high-speed pulse input function realization, high-speed pulse output function realization, serial port driving and protocol encapsulation function realization, network port driving and protocol encapsulation function realization and CAN driving and protocol encapsulation function realization;

s4: and (3) generating a C language program: translating the ladder diagram edited by the user into a C language code according to the translation template in the step S2, namely, transferring a main program after the ladder diagram is translated into C; then calling the C code generated by the drive design in the step S3 in the main to form a set of complete C language program;

s5: compiling a C language program: compiling the C language code program into binary executable codes through a compiler;

the C language program is compiled by adopting 'GCC + Makefile'; the GCC is a short for GCC cross compiling tool, a link library is generated according to the cross compiling of an actual CPU product, for example, a GCC-arm-none-eabi tool adopted by STM 32; the Makefile is a short for customizing a compiling flow according to a CPU product; the compiling flow comprises the following steps: defining a target variable, locating a C source code file, locating an S starting file, correlating a compiling tool, processing a special mark, locating an H head file, generating a library, processing and clearing a function pseudo code;

s6: downloading an executable file: and programming the binary executable code into a programmable controller.

According to the present invention, the basic condition type template is an "if (condition)" part in the "if (condition) { function body }" format, for example, a normally open contact of a switch key may be translated into "if (key _ val = = 1)", a normally closed contact of the switch key may be translated into "if (key _ val = = 0)", and a value of the key _ val is implemented by writing a switching value input driver; in particular, the rising edge and falling edge commands need to consider the state memory problem on the basis of the above-mentioned template, for example, the rising edge of the switch key may be translated into "if ((key _ val _ new = = 1) & (key _ val _ old = = 0)) key _ val _ old = key _ val _ new", the falling edge of the switch key may be translated into "if ((key _ val _ new = = 0) & (key _ val _ old = = 1)) key _ val _ old = key _ new", the key _ val _ new refers to the read value of the current switching value, and the key _ val _ old refers to the read value of the switching value of the previous scanning period.

The basic output type template is the "{ function }" part in the "if (condition) { function }" format, e.g., coil setting of the indicator lamp Q can be translated into "{ write _ Q, out _ val }", the operation of the write _ Q is realized by programming a switching value output driver, and the out _ val is obtained by programming a switching value input driver; for example, an add instruction may translate into "{ C = a + B }", where C must be a variable, and a and B may be variables or values; in particular, the coil output command needs to consider the dual-coil output problem on the basis of the template, specifically, on the basis of the coil setting, a reverse judgment is added, for example, the coil output of the indicator lamp Q can be translated into "{ write _ Q, out _ val, and temp _ out _ val; if (! temp _ out _ val)! write _ Q,! out _ val; temp _ out _ val =0; } "; the temp _ out _ val is the auxiliary memory value of out _ val, the "! The + variable "means that the value of the variable is inverted.

The functional instruction output type template includes: (1) The structure body definition means that variables required by corresponding functions are packaged in one structure body, for example, the structure body content of the related instructions of the timer comprises a start-stop mark, a time base, a counter type, a stop mark, a loading mark, a timing-to-reach mark, a counting variable and a pre-value variable; (2) The method comprises the steps of defining a structure array and a structure array length, wherein the structure array definition refers to the fact that global definition is firstly made in a C file of a timer driver, and the structure array length definition refers to the fact that global definition is firstly made in the C file of the timer driver; (3) The method comprises the steps of a structure array and structure array length statement, wherein the structure array length statement refers to the fact that a global statement is made in an H file of a timer driver, and the structure array statement refers to the fact that the global statement is made in the H file of the timer driver; (4) Defining and realizing an interface function, wherein the interface function is called in a main loop body when the ladder diagram is translated into the C language; in particular, the functions to be performed in the interrupt are required, and the interface function does not have to be designed.

The subprogram type template refers to a function interface for generating a ladder diagram subprogram into a C language program for calling a main function or a function associated with the main function; in particular, the interrupt subprogram needs to generate an interrupt function interface of the C language program, and interrupts execution without calling.

The link type template is used for encapsulating functions into link ports, and directly calling the link ports by other functions; in particular, the link library unit is an already packaged link port, and can be directly called without being packaged again.

The variable model template is defined according to variable definition rules of C language, and simultaneously, PLC variable types and data types of C language are translated in a one-to-one correspondence mode, for example, the 'signed integer' of PLC is translated into 'int' of C language; in particular, the power-down save variable needs to save data in a flash to prevent power-down loss.

The pin configuration model template refers to the configuration that hardware pins of the PLC correspond to pins of the CPU one by one, for example, a digital quantity input pin I0.0 corresponds to a pin P1.0 of the CPU; in particular, the encoder mode of the high-speed counter instruction requires 2 or 3 pins, and 2 or 3 pins are required to be configured.

The driving interface type template refers to a driving interface packaged at the bottom layer, and is directly configured and called according to a reference format, for example, a scan input interface is read (% gpio port%,% gpio pin%, 0), wherein a variable between two percentiles belongs to a pin configuration configured by a user in a reference database.

In the step S6, the downloading mode of the executable file includes a wireless mode or a wired mode; the wireless mode refers to an OTA downloading mode; the wired mode refers to a Jlink downloading mode, and is specifically realized by adopting a syntax instruction of JLINK-Commander.

Examples 2,

The method for designing the software interface framework of the development environment according to embodiment 1 includes:

a menu bar, a toolbar, a left tree form, a right tree form, and a middle ladder diagram editing area, as shown in fig. 2;

the menu bar comprises an engineering menu, an editing menu, a compiling menu and a help menu; the project menu comprises new creation, opening, storage and printing; the editing menu comprises undo and reinstate; the compiling menu comprises a building function and a downloading function, wherein the building function is used for converting the target ladder diagram into the C language and compiling the C language into binary executable codes;

the tool bar comprises an engineering tool, an editing tool and a compiling tool; the engineering tool comprises new construction, opening, storage and printing; the editing tool comprises revocation and recovery; the compiling tool comprises a construction function and a downloading function; the toolbar function is consistent with the menu function;

the left tree form comprises a first-level branched ladder diagram program and an element box; the first-level ladder diagram program comprises a second-level branch main program, subprograms, an interrupt program and a quick index; the main program is used for: when the middle ladder diagram editing area is in a subprogram or an interrupt program interface, switching to the editing interface of the main program by clicking the 'main program' editing area; the subroutine is for: when a subprogram is added, the subprogram is created, when a user needs to add the subprogram, a right click on 'adding' pops up a dialog box for creating the subprogram, the dialog box for creating the subprogram comprises a name, an author, a date, a remark and a confirmation button, referring to the attached figure 3, the created subprogram name is listed below a secondary branch of the subprogram and belongs to a tertiary branch, a main interface can be switched to a corresponding subprogram interface by clicking a subprogram index name, and the subprogram can be called by dragging the subprogram name; the interrupt routine is to: when an interrupt program needs to be added, an interrupt program dialog box is created, right-clicking 'adding' pops up the interrupt program dialog box, the interrupt program dialog box comprises a name, interrupt resources, a description, an author, a date, remarks and a determination button, referring to the attached drawing 4, the interrupt program name created by a user is listed below a secondary branch of the interrupt program and belongs to a tertiary branch, and a main interface can be switched to a corresponding interrupt program interface by clicking an interrupt program index name; the fast index is used for: listing program function index directories of the main program, the subprogram or the interrupt program displayed on the current main interface, referring to fig. 5; the component cartridge is configured to: the instruction primitive list used by the rowed ladder diagram comprises a bit logic operation instruction, a comparison operation instruction, an arithmetic operation instruction, a shift operation instruction, a data block transmission instruction, a timer, pulse output, serial port communication, a ModbusRTU protocol and an interrupt instruction; the system is also used for dragging the instruction graphics primitives corresponding to the instructions to an editing interface area for placement through signal input hardware;

the right tree form comprises a global variable table, a local variable table, a timer list, a counter list, PWM, COM, system variables, an IO variable table and PLC resource configuration buttons; the global variable table comprises user-defined global variables and power-down storage variables and is also used for clicking the global variable table to build the global variables, for example, clicking a plus button of a row to build the global variables; the local variable table is used for listing local variables defined by the current main interface program, the table changes along with the switching of the main interface program, and is also used for clicking the local variables newly built by clicking the local variable table and clicking the plus button of the line to newly build the local variables; the timer list is used for listing timer type variables defined in a program; the counter list is used for listing counter type variables defined by a program; the PWM list is used for listing PWM type variables defined by a program; the COM list is used for listing program definition COM type variables; the system variables are used for listing the globally usable variables that the system has defined and can be used without program definition; the IO variable table is used for: listing IO pin conditions owned by PLC hardware supported by the current engineering, wherein the IO pin conditions comprise a symbol name and a pin name; the PLC resource configuration button is used for PLC hardware configuration, and referring to fig. 6, after clicking, a PLC hardware configuration dialog box is popped up, and the PLC hardware configuration dialog box includes a PLC type list part, a "use this PLC" button, a "rename" button, a "delete this PLC" button, a "add PLC" button, a pin definition list, an HSC definition list, an interrupt resource list, a communication port list, and a compiling option interface; the header of the pin definition list comprises a serial number, a type, a display name, a PLC variable name, a CPU pin, a remark, a CPU port number and a CPU pin number; the HSC definition list header comprises a name, a pin1, a pin2, a direction pin, a reset pin and a description; the interrupt resource list header comprises an event number, a type, a PLC pin, a CPU pin, a description, a gpioPort and a gpioPin; the communication port list head comprises a port name, a type, a sending pin, a receiving pin and a control pin; the compiling option interface comprises a header file include, a hardware initialization interface function, a scanning input interface function, a scanning output interface function, a coil setting interface function and a coil resetting interface function;

the middle ladder diagram editing area, see fig. 7, includes a program name display switching area, a program description, a label definition, a logic line annotation, and a logic line editing area; the program name display switching area is used for: displaying the opened main program subprogram or the interrupted program, switching to a corresponding program interface by clicking the program name, and hiding the program by right clicking; the program instructions are for: performing comment explanation on the currently edited program, wherein fields comprise program names, authors, dates and comments and are displayed on the top line of an editing area; the tag definition is used to: the simplified summary of the ladder diagram function is displayed on one side of the logic row of the editing area, and the simplified summary is also used for automatically generating a label under the quick index, specifically, on the left side of the logic row of the editing area, a more complete function simplified summary is provided, and the label can be automatically generated under the quick index and can be quickly positioned; the logical line annotation is to: the current logical line program is annotated and designed on top of each logical line. The logical line editing is to: and programming a ladder diagram in the area, wherein the variable of each instruction is displayed below the corresponding instruction, and simultaneously, the multi-element operation instruction is displayed in a formula form of mathematical calculation.

As shown in fig. 8-11, the implementation process of the whole compilation is demonstrated by using the technical solutions described in embodiments 1 and 2, where fig. 8 is a ladder diagram design of a test program, S16 is a main program, S17 is a subroutine, and S18 is an interrupt program; FIG. 9 is a ladder to C code key code diagram of a test program; s19 is a header file, a function statement and a global variable definition code, wherein S19-1 is the header file, S19-2 is a sub-function statement, S19-3 is a digital quantity input output global variable definition, and S19-4 is a coil output memory variable global statement; s20 is main function content, wherein S20-1 is external interrupt pin initialization, S20-2 is space allocation, array length initialization and intra-structure variable initialization of a switching value input and output data structure array, S20-3 is PLC other drive initialization, S20-4 is a main loop area, wherein S20-4-1 is a scanning input variable, and S20-4-2, S20-4-3 and S20-4-4 realize a coil output function; FIG. 10 is a diagram of a test program compilation process; fig. 11 is a schematic diagram of a test program downloading process.

Examples 3,

An electronic device of a development environment loaded with a compiled programmable logic controller, at least one processor; and a memory coupled with the at least one processor, the memory having instructions stored therein that, when executed by the at least one processor, cause the electronic device to perform acts for managing development jobs in a development environment, the acts comprising:

classifying the ladder diagram; designing a translation template: respectively designing a basic condition type template, a basic output type template, a functional instruction output type template, a subprogram type template, a link type template, a variable model template, a pin configuration model template and a driving interface type template according to the classification of the ladder diagram, and correspondingly translating the ladder diagram into a corresponding C language program; and (3) drive design: respectively implementing C codes for functions related to the working process of the programmable controller; and (3) generating a C language program: translating the ladder diagram edited by the user into a C language program according to the translation template in the step S2, and then integrating the ladder diagram with the driving design in the step S3 into a complete C language program; compiling a C language program: compiling the C language program into binary executable codes through a compiler; downloading an executable file: and programming the binary executable code into a programmable controller.

Examples 4,

A computer program product implementing a development environment for a compiled programmable logic controller, the computer program product being tangibly stored on a non-transitory computer-readable medium and comprising machine executable instructions for performing the method described above.

Examples 5,

The development environment management and development operation method of the compiled PLC according to the embodiment 1-2 comprises the following steps:

t1: designing a database structure comprises dividing PLC configurable hardware resources into the following database entities and associated database entities;

as shown in the database structure chen's diagram of fig. 12, according to the principle that the same entity attribute of the database is the same, the PLC configurable hardware resource is divided into the following database entities, including: the method comprises the following steps of PLC model, general IO pin configuration, HSC pin configuration, communication resource pin, interrupt source configuration and drive interface configuration;

the PLC model refers to a serial model name of PLC hardware, and is visible when a user selects the model; the configuration attribute comprises a CPU type and a PLC model; the CPU type is STM32F103VET6; the PLC model is SK2109;

the general IO pin configuration comprises but is not limited to a configuration switching value IO pin, an analog value IO pin and a high-speed pulse output pin; the common configuration attributes comprise IO types, symbol names, PLC variable names, CPU pins, CPU port numbers, CPU pin numbers and descriptions; the IO types comprise but are not limited to a switching value input type DI, a switching value output type DO, an analog value input type AI, an analog value output type AQ and a high-speed pulse output type PWM; the symbolic name is an alias name given to the pin by the user and can be called in programming; the PLC variable names are I0.0, Q2.1 and PWM0, and can be directly called by a user; the CPU pins such as PA6 and P3.5 have different naming rules of different CPU types; the CPU port number and the CPU pin number are analyzed according to the CPU pin, if the CPU pin is PA6, the CPU port number is 1, the CPU pin number is 6, if the CPU pin is P3.5, the CPU port number is 3, and the CPU pin number is 5; the description refers to the functional description of the configuration pin;

the HSC pin configuration refers to high-speed pulse input pin configuration, and has common configuration attributes including HSC name, pin1, pin2, direction pin, reset pin and description; the HSC name is HSC0; the pin1 is a first high-speed pulse input port, such as I0.3/PC6; the pin2 refers to a second high-speed pulse input port, such as I0.4/PC7; the direction pin refers to an external direction control pin in a working mode that the HSC has a function of controlling the direction, can be shared with the pin2, but is not compatible; the reset pin refers to an external reset pin in a working mode that the HSC has an external reset function; the description refers to the functional description of the HSC configuration pin;

the communication resource pins are used for serial port communication, network port communication and CAN communication, and have common configuration attributes including communication names, communication protocols, PLC pins, CPU port numbers, CPU pin numbers and descriptions; the communication name is an alias configured for the communication and can be called by a user; the communication protocols are different aiming at different communication port protocols, the serial port communication protocol comprises but not limited to a free protocol and a Modbus protocol, the network port communication protocol comprises but not limited to ProfiNet and EtherCat, and the CAN communication comprises but not limited to CANopen and a standard CAN protocol;

the interrupt source configuration has common attributes including an interrupt number, an interrupt type, a PLC pin, a CPU port number, a CPU pin number and a description; the interrupt number is the only code of the interrupt source, such as INT0; the interrupt types include but are not limited to a rising edge, a falling edge, a serial port receiving character, a serial port receiving completion, a serial port sending, a timing interrupt of a control time interval, a timing-to-interrupt when the current time is equal to a preset value, a high-speed counting interrupt when the current value is equal to a preset value, a high-speed counting interrupt of direction change, a high-speed counting interrupt of external reset, and a PTO pulse counting completion interrupt;

the configuration of the driving interface includes, but is not limited to, a header file, a hardware initialization interface, a scan input interface, a scan output interface, a coil setting interface, and a coil resetting interface; the include header files, such as # include "main.h"; the hardware initialization interface, such as PlcInit (); the scan input interface is, for example, readDIO (% gpioPort%,% gpioPin%, 0), where gpioPort represents a CPU port number, gpioPin represents a CPU pin number, and 0 represents active low; the scanout interface readDIO (% gpioPort%,% gpioPin%, 1), wherein gpioPort represents a CPU port number, gpioPin represents a CPU pin number, and 1 represents that a high level is effective; the coil setting interface is such as write (% gpioPort%,% gpioPin%, 1), wherein gpioPort represents the CPU port number, gpioPin represents the CPU pin number, and 1 represents setting; the coil reset interface is such as write (% gpio port%,% gpio pin%, 0), wherein gpio port represents a CPU port number, gpio pin represents a CPU pin number, and 0 represents reset;

the associated database entity comprising: the PLC model and the IO pin configuration, the HSC pin configuration, the communication resource pin and the interrupt source configuration belong to an incidence relation of 1 to n respectively, the PLC model and the drive interface configuration belong to an incidence relation of 1 to 1, the interrupt source configuration and the general IO pin configuration and the HSC pin configuration belong to an incidence relation of m to n respectively, specifically, the PLC model and the general IO pin configuration belong to an incidence relation of 1 to n, namely, one to many, and a PLC model can configure a plurality of general IO pin configurations; the PLC model and the HSC pin configuration belong to an incidence relation of 1 to n, namely one to many PLC models can be configured with a plurality of HSC pin configurations; the PLC model and the communication resource pins belong to an incidence relation of 1 to n, namely one to many, and a plurality of communication resource pins can be configured in one PLC model; the PLC models and the interrupt source configurations belong to an incidence relation of 1 pair n, namely one pair is multiple, and one PLC model can be configured with a plurality of interrupt source configurations; the PLC model and the drive interface configuration belong to an incidence relation of 1 to 1, namely, one PLC model can only correspond to one set of drive interfaces, and each drive interface is unique; the interrupt source configuration and the general IO pin configuration belong to an incidence relation of m to n, namely, many to many, a plurality of interrupt source configuration lists refer to the configuration of the general IO port, and one general IO port configuration can be called in a plurality of interrupt sources; the interrupt source configuration and the HSC pin configuration belong to an incidence relation of m to n, namely many to many, a plurality of interrupt source configuration lists refer to the HSC pin configuration, and one HSC pin configuration can be called in a plurality of interrupt sources;

t2: universal drive design

After the hardware resources of the PLC are configured, the database parameters are called during programming, and before a PLC user main program is formed, a driver is required to be designed to identify the configuration parameters; the generic driver design includes: the method comprises the following steps of designing a universal IO driver, a universal functional instruction driver and a universal interrupt function; the IO includes but is not limited to DI, DO; the functional instructions include, but are not limited to, timer instructions, counter instructions, PWM, PTO, HSC, communications.

The generic IO driver design includes:

(1-1) As shown in FIG. 13, an IO pin structure is defined: the IO pin structure body is characterized in that a structure body variable is defined based on C language, port information of IO is packaged in the structure body, the IO pin structure body is defined as tPin _ IO and comprises two members, wherein one member is an unsigned 8-bit integer variable gpioPort, and the other member is an unsigned 8-bit integer variable gpioPin; the tPin _ IO is the name of an IO pin structure body; the gpioPort is a port number of a CPU pin; the gpioPin is the pin number of the CPU pin;

(1-2) instantiating an IO pin structure variable and defining the number of members of the instantiated variable, and instantiating a structure pointer variable named ioConf according to the IO pin structure defined in the step (1-1); defining a variable of a loading quantity for the pointer variable, wherein the variable is an unsigned 8-bit integer variable and is named as ioCnt; as indicated by L2 and L3 in fig. 13;

(1-3) initializing variables of the quantity of pointer variables of the loaded structure and the pointer variables of the structure, and initializing the variables ioCnt of the quantity of the pointer variables of the loaded structure defined in the step (1-2) according to the quantity of IO variables configured by a user; as indicated by L4 in fig. 13; allocating a space for the structure pointer variable ioConf through malloc keywords according to the value of ioCnt and the memory size of the structure tPin _ IO, as shown by L5 in fig. 13; finally, initializing member variables gpioPort and gpioPin of a structure pointer variable ioConf according to an IO pin configuration parameter configured by a user, as shown by L6 in fig. 13;

(1-4) designing an IO pin configuration interface and a read-write IO drive interface, and designing the IO pin configuration interface and the read-write IO drive interface according to the gpioPort, gpioPin and ioCnt initialized in the step (1-3);

the IO pin configuration interface process is as follows: configuring a CPU pin in a cycle from 0 to ioCnt, wherein the configuration content comprises a configuration pin clock, a configuration corresponding pin register and a configuration pin port register; the read-write IO driving interface finds a corresponding port according to the gpioPort and then calls a read-write register to perform corresponding functional operation;

as shown in fig. 14, a configuration work flow chart is explained by taking an STM32F103 series CPU as an example; the read-write IO drive interface finds a corresponding port according to a gpio port, and then calls a read-write register to perform corresponding functional operations, as shown in fig. 15, a read-IO workflow diagram is illustrated by using an STM32F103 series CPU as an example; in fig. 15, the input parameter flag represents an effective level value, if flag is equal to 0, it represents that the low level is effective, i.e. it returns to 1 when the read value of the scan input function pin register is 0, and returns to 0 when the read value of the scan input function pin register is 1; if flag is equal to 1, the high level is effective, namely 1 is returned when the read value of the scan input function pin register is 1, and 0 is returned when the read value of the scan input function pin register is 0; because the input parameters of the scan input function are obtained by the configuration of hardware resources by a user, the drive interface is a general scan input drive interface based on an STM32F103 series CPU;

designing an IO pin configuration interface and a read-write IO driving interface according to the initialized gpioPort, gpioPin and ioCnt in S3;

generally, the value of the drive register related to the CPU pin can be obtained by calculation according to a port value port and a pin value pin of the CPU pin, the port value port of the CPU is gpio port, the pin value pin of the CPU is gpio pin, and the values of gpio port and gpio pin are obtained by initialization of parameters configured by a user in step (1-3), so that a universal IO pin configuration interface and a read-write IO drive interface can be packaged; the calculation rules of the calculation are different according to different CPUs, and need to be summarized and obtained according to a CPU chip use manual. The clock value of the pin as in FIG. 14 can be obtained by shifting "1" left by "gpioPort plus 1" bit; the value of the pin register is obtained by shifting the '1' left by the 'gpioPin' bit; the port register value is obtained by shifting the value of the external time BASE 2 by 10 bits after adding APB2PERIPH _ BASE and gpioPort plus 1.

As shown in fig. 16, taking the PWM function command as an example, the design of the general functional command driver includes:

(2-1) defining a functional instruction structure, wherein the functional instruction structure is characterized in that a structure variable is defined based on C language, parameters related to a functional instruction are encapsulated in a structure for convenient management and calling, and the structure is named as tFunc; as shown by L7 in fig. 16, the structure name is PWM;

(2-2) instantiating a function type instruction structure variable and defining the number of members of the instantiated variable, and instantiating a structure pointer variable named pFanc according to the function type instruction structure defined in the step (2-1); defining a variable of loading quantity for the pointer variable, wherein the variable is an unsigned 8-bit integer variable and is named as cntFunc; as shown in L8 in fig. 16, the structure pointer name is tPwm, and the number variable is pwmCnt;

(2-3) initializing variables for loading the quantity of the variables of the structure pointer, and the variables of the structure pointer, initializing the variables cntFunc for loading the quantity of the variables of the structure pointer defined in the step (2-2) according to the quantity of the variables of the functional instructions called in the user programming; according to the value of the cntFunc and the memory size of the structure tFunc, distributing space for the structure pointer variable pFanc through malloc keywords; finally, initializing member variables of the structural body pFanc according to the configuration condition of the functional instruction parameters called in user programming; preferably, if the functional instruction structure has parameters related to hardware port information, the related configuration data is called to initialize the hardware configuration related member variables of the pFunc;

as shown by L9 in fig. 16:

firstly, initializing the variable pwmCnt of the variable quantity of the pointer of the loading structure body defined in the step (2-2) to be equal to 1 according to the quantity of the variable quantity of the PWM function instruction called in user programming;

according to the value of pwmCNT and the size of the internal memory of the PWM of the structure body, allocating space for the variable tPwm of the structure body pointer through malloc keywords;

finally, initializing member variables of the structure body tPwm according to the configuration condition of functional instruction parameters called in user programming, wherein as shown in L9 in FIG. 16, the period of initializing PWM is 100 milliseconds, the duty ratio is 60 percent, the port pin gpioPort is 1, and the gpioPin is 0;

(2-4) designing and realizing a functional instruction initialization interface and a driving interface, and designing the functional instruction initialization interface and the driving interface according to the pFanc and the cntFunc initialized in the step (2-3); initializing corresponding function registers according to different types of CPU pins used by different functions; the driver interface is invoked when a user configures the driver interface.

And (4) designing a functional instruction initialization interface and a driving interface according to the tPwm and pwmCNT initialized in the step (2-3), wherein the PWM function is high-speed pulse output, and only register parameters need to be initialized, and the corresponding port of the PWM can automatically output pulses, so that the initialization interface and the driving interface of the PWM are the same, as shown by L10 in figure 16, namely PWM _ Config (), and the interface can be called by a user after being configured in a database driving interface.

The general interrupt function design comprises:

(3-1) an interrupt function macro definition, which is to define an interrupt macro first when an interrupt interface is called by a user; the interrupt interface called by the user must be defined in the interrupt resource configuration before being called; the interrupt macro means that the macro definition represents a certain interrupt, such as a macro named USE _ PLCINT _ T0_ TIM for timed interrupt, as shown in L11 in fig. 17;

(3-2) defining an interrupt service function, and when a user calls an interrupt interface, defining an interrupt service function, as shown by L12 in FIG. 17, and as the interrupt service function of the timed interrupt is named PLCINT _ T0_ IRQHandler (), the user generates a C language interrupt program in the ladder diagram programming after converting the interrupt program from the ladder diagram language to the C language, and encapsulates the C language interrupt program in the interrupt service function;

(3-3) pre-declaring an interrupt service function, and pre-declaring the interrupt service function by adopting a conditional compiling method according to the interrupt macro in the step (3-1), so that the interrupt service function is convenient to call in other files, as shown by L13 in FIG. 17;

(3-4) preprocessing interrupt service basic functions, wherein each interrupt function needs to be processed by some basic functions in advance to cushion the interrupt service functions of a user, such as clock initialization work of timed interrupt; in order to realize the basic function, preprocessing is performed in a conditional compiling manner in combination with the interrupt macro in step (3-1), as shown by L14 in fig. 17.

And (3) comparison test:

in order to embody the technical advantages of the invention, the compiled development environment and the interpreted development environment are tested and compared under the same running hardware:

wherein, the experimental conditions are shown in the table 1;

table 1: the invention relates to a concrete operation environment of a compiling development environment and an explaining development environment

The comparative experimental protocol is as follows:

the scanning period of the PLC program is calculated by writing the PLC codes with the same functions and then measuring the DO output time difference of the SK2109 through an oscilloscope, and the detailed testing steps are as follows:

u1: firstly, writing basic codes at a GX Works2 software end, wherein a ladder diagram is shown in figure 18; as can be seen by measuring the output level state of the Y001 port and the time thereof, the code execution period of the three interpretation type PLC is equal to about 75us, and the measurement result is as shown in FIG. 19, the period is named as T0_ GX, namely T0_ GX is approximately equal to 75 mus;

u2: then writing codes with the same functions in the newlad, wherein the ladder diagram is shown in FIG. 20; as can be seen by measuring the output level state of the Q2 port and the time thereof, the code execution period of the newrad PLC is equal to about 3.3 mus, and the measurement result is as shown in FIG. 21, the period is named T0_ newrad, namely T0_ newrad ≈ 3.3 mus;

u3: on the basis of the step U1, 20 explanatory PLC instructions are added, wherein the explanatory PLC instructions comprise 10 ADD instructions and 10 SUB instructions, and a local ladder diagram is shown in FIG. 22; the test output level time is approximately equal to 292 μ s, the measurement result is shown in fig. 23, and the time is named as T1_ GX, namely T1_ GX is approximately equal to 292 μ s;

u4: on the basis of the step U2, adding 20 newrad compiling PLC instructions which comprise 10 ADD instructions and 10 SUB instructions, wherein a partial ladder diagram is shown in FIG. 24; the test output level time is equal to about 4.5 mus, and the measurement result is as shown in fig. 25, the time is named as T1_ newrad, namely T1_ newrad is about 4.5 mus;

u5: on the basis of the step U1, 20 bit logic instructions are added, including 10 SET instructions and 10 RESET instructions, and a partial diagram of a ladder diagram is written as shown in fig. 26; the test output level time is equal to about 130 μ s, and the test result is shown in fig. 27, and the time is named as T2_ GX, i.e. T2_ GX ≈ 130 μ s;

u6: on the basis of the step U2, 20 bit logic instructions are added, including 10 SET instructions and 10 RESET instructions, and a partial diagram of a ladder diagram is written as shown in fig. 28; the test output level time is equal to about 17 mus, the test result is shown in fig. 29, and the time is named as T2_ newrad, namely T2_ newrad ≈ 17 mus;

u7: calculating the ADD and SUB single instruction period of the interpretation type PLC as T _ GX _ ADD through the steps U1 and U3; through the steps U1 and U4, the ADD and SUB single instruction cycle of the compiled PLC are determined to be T _ newlad _ ADD; the bit logic single instruction cycle of the interpretation type PLC is T _ GX _ bit through the steps U1 and U5; through the steps U1 and U6, the bit logic single instruction cycle of the compiled PLC is T _ newlad _ bit;

T_GX_ADD＝(T1_GX-T0_GX)/20＝(292-75)/20＝10.85μs；

T_newlad_ADD＝(T1_newlad-T0_newlad)/20＝(4.5-3.3)/20＝0.06μs；

T_GX_bit＝(T2_GX-T0_GX)/20＝(130-75)/20＝2.75μs；

T_newlad_bit＝(T2_newlad-T0_newlad)/20＝(17-3.3)/20＝0.685μs；

as shown in fig. 30, the comparison of test results shows that, as proved by the single instruction cycle shown in fig. 30, the execution efficiency of the compiled PLC of the present invention is much higher than that of the interpreted PLC under the substantially same technical conditions as the interpreted PLC.

Claims (10)

1. A development environment for a compiled plc, comprising:

s1: the ladder diagrams are classified:

the method comprises the following steps: the system comprises a basic instruction, a functional module instruction, a functional unit, a variable management unit and a resource configuration unit;

further comprises the following steps: dividing the basic instruction into a type1 basic condition type and a type2 basic output type; the base condition type refers to a type of instruction that represents a condition in one logical row of the ladder diagram; the basic output type refers to a type of instruction representing output in one logical row of the ladder diagram;

all the functional module instructions are used as type3 functional instruction output types;

dividing the functional units into type4 subprogram types and type5 link types; the subprogram type comprises a subprogram unit and an interrupt program unit; the link type comprises a C language program unit and a functional link library unit;

all the variable management units are used as type6 variable models;

dividing the resource configuration unit into a type7 pin configuration model and a type8 driving interface type; the drive interface type refers to function interfaces of all functional modules packaged by C language;

s2: designing a translation template: respectively designing a basic condition type template, a basic output type template, a functional instruction output type template, a subprogram type template, a link type template, a variable model template, a pin configuration model template and a driving interface type template according to the ladder diagram classification in the step S1, and correspondingly translating the ladder diagram into a corresponding C language program;

s3: and (3) driving design: respectively implementing C codes for functions related to the working process of the programmable controller;

s4: and (3) generating a C language program: translating the ladder diagram edited by the user into a C language code according to the translation template in the step S2, namely, transferring a main program after the ladder diagram is translated into C; then calling the C code generated by the drive design in the step S3 in the main to form a complete set of C language program;

s5: compiling a C language program: compiling the C language code program into binary executable codes through a compiler;

s6: downloading an executable file: and programming the binary executable code into a programmable controller.

2. The development environment of a compiler-based plc according to claim 1, wherein the basic condition template is an "if (condition)" part in "if (condition) { function }" format;

the basic output type template is a part of { function body } "in the format of' if (condition) { function body }";

the functional instruction output type template includes: (1) Defining a structural body, wherein the structural body means that variables required by corresponding functions are encapsulated in one structural body; (2) The method comprises the steps of defining a structure array and the length of the structure array, wherein the definition of the structure array refers to the fact that global definition is made in a C file of a timer driving program, and the definition of the length of the structure array refers to the fact that global definition is made in the C file of the timer driving program; (3) The method comprises the steps of a structure array and a structure array length statement, wherein the structure array length statement refers to the fact that a global statement is made in an H file of a timer driver, and the structure array statement refers to the fact that the global statement is made in the H file of the timer driver; (4) And defining and realizing an interface function, wherein the interface function is called in a main loop body when the ladder diagram is translated into the C language.

3. The development environment of a compiled PLC of claim 1, wherein the subroutine type template refers to a function interface for generating the ladder diagram subroutine into a C language program for the main function or the function call associated with the main function;

the link type template is used for encapsulating functions into link ports, and directly calling the link ports by other functions;

the variable model template is used for defining the variable definition of a user according to the variable definition rule of the C language and simultaneously performing one-to-one corresponding translation of the PLC variable type and the data type of the C language;

the pin configuration model template refers to the configuration that hardware pins of the PLC correspond to pins of the CPU one by one;

the driving interface type template refers to a driving interface packaged at the bottom layer, and configuration calling is directly carried out according to a quoted format.

4. The development environment of a compiler-based plc according to claim 1, wherein in step S6, the downloading manner of the downloaded executable file includes a wireless manner or a wired manner; the wireless mode refers to an OTA downloading mode; the wired mode refers to a Jlink downloading mode, and is specifically realized by adopting a syntax instruction of JLINK-Commander.

5. The method for designing a software interface framework of a development environment according to any one of claims 1 to 4, comprising:

a menu bar, a tool bar, a left tree form, a right tree form and a middle ladder diagram editing area;

the menu bar comprises an engineering menu, an editing menu, a compiling menu and a help menu; the compiling menu comprises a building function and a downloading function, wherein the building function is used for converting the target ladder diagram into the C language and compiling the C language into binary executable codes;

the toolbar comprises an engineering tool, an editing tool and a compiling tool; the compiling tool comprises a construction function and a downloading function; the toolbar function is consistent with the menu function;

the left tree form comprises a first-level branching ladder diagram program and an element box; the first-level ladder diagram program comprises a second-level branch main program, subprograms, an interrupt program and a quick index; the main program is used for: when the middle ladder diagram editing area is in a subprogram or an interrupt program interface, switching to the editing interface of the main program by clicking the 'main program' editing area; the subroutine is for: when a subprogram is added, the subprogram is created, the main interface is switched to the corresponding subprogram interface by clicking the subprogram index name, and the subprogram is called by dragging the subprogram name; the interrupt routine is to: when an interrupt program needs to be added, an interrupt program dialog box is created, and the main interface is switched to the corresponding interrupt program interface by clicking the interrupt program index name; the fast index is to: listing program function index directories of a main program, a subprogram or an interrupt program displayed on a current main interface; the component cartridge is configured to: listing an instruction primitive list used by the ladder diagram; the system is also used for dragging the instruction primitive corresponding to the instruction to an editing interface area for placing through signal input hardware;

the right tree form comprises a global variable table, a local variable table, a timer list, a counter list, PWM, COM, system variables, an IO variable table and PLC resource configuration buttons; the global variable table comprises user-defined global variables and power-down storage variables and is also used for clicking the global variable table to establish the global variables; the local variable table is used for listing local variables defined by the current main interface program and is also used for establishing new local variables by clicking the local variable table; the timer list is used for listing timer type variables defined in a program; the counter list is used for listing counter type variables defined by a program; the PWM list is used for listing PWM type variables defined by a program; the COM list is used for listing program definition COM type variables; the system variables are used for listing the globally usable variables which can be used without program definition by the system; the IO variable table is used for: listing IO pin conditions of PLC hardware supported by the current engineering, wherein the IO pin conditions comprise symbol names and pin names; the PLC resource configuration button is used for PLC hardware configuration;

the middle ladder diagram editing area, see fig. 7, includes a program name display switching area, a program description, a label definition, a logic line annotation, and a logic line editing area; the program name display switching area is used for: displaying the opened main program subprogram or the interrupted program, switching to a corresponding program interface by clicking the program name, and hiding the program by a right key; the program instructions are for: performing annotation explanation on a currently edited program; the tag definition is used to: a brief overview of the ladder function is displayed on one side of the edit section logic row, and is also used for automatically generating labels below the quick index; the logical line note is to: performing annotation explanation on the program of the current logic line; the logical line editing is to: and programming a ladder diagram in the area, wherein the variable of each instruction is displayed below the corresponding instruction, and simultaneously, the multi-element operation instruction is displayed in a formula form of mathematical calculation.

6. An electronic device loaded with a development environment of a compiled programmable logic controller,

at least one processor; and a memory coupled with the at least one processor, the memory having instructions stored therein that, when executed by the at least one processor, cause the electronic device to perform acts for managing development jobs in a development environment, the acts comprising:

classifying the ladder diagram; designing a translation template: respectively designing a basic condition type template, a basic output type template, a functional instruction output type template, a subprogram type template, a link type template, a variable model template, a pin configuration model template and a driving interface type template according to the classification of the ladder diagram, and correspondingly translating the ladder diagram into a corresponding C language program; and (3) driving design: respectively implementing C codes for functions related to the working process of the programmable controller; and (3) generating a C language program: translating the ladder diagram edited by the user into a C language program according to the translation template in the step S2, and then integrating the ladder diagram with the driving design in the step S3 into a complete C language program; compiling a C language program: compiling the C language program into binary executable codes through a compiler; downloading an executable file: and programming the binary executable code into a programmable controller.

7. A computer program product implementing a development environment for a compiled programmable logic controller, the computer program product being tangibly stored on a non-transitory computer-readable medium and comprising machine executable instructions for performing the method described above.

8. The development environment management development operation method of the compiling programmable logic controller according to any one of claims 1 to 4, comprising:

t1: designing a database structure comprises dividing PLC configurable hardware resources into the following database entities and associated database entities;

partitioning the PLC configurable hardware resources into the following database entities, including: the method comprises the following steps of PLC model, general IO pin configuration, HSC pin configuration, communication resource pin, interrupt source configuration and drive interface configuration;

the associated database entity comprising: the PLC model and IO pin configuration, HSC pin configuration, communication resource pin and interrupt source configuration belong to incidence relations of 1 to n respectively, the PLC model and drive interface configuration belong to incidence relations of 1 to 1, and the interrupt source configuration and general IO pin configuration and HSC pin configuration belong to incidence relations of m to n respectively;

t2: universal drive design

After the hardware resources of the PLC are configured, the database parameters are called during programming, and before a PLC user main program is formed, a driver is required to be designed to identify the configuration parameters; the generic driver design includes: the method comprises the following steps of general IO drive design, general functional instruction drive design and general interrupt function design.

9. The computer program product of claim 8, wherein the generic IO driver design comprises:

(1-1) defining an IO pin structure: the IO pin structure body is characterized in that a structure body variable is defined based on C language, port information of IO is packaged in the structure body, the IO pin structure body is defined as tPin _ IO and comprises two members, wherein one member is an unsigned 8-bit integer variable gpioPort, and the other member is an unsigned 8-bit integer variable gpioPin; the tPin _ IO is the name of an IO pin structure body; the gpioPort is a port number of a CPU pin; the gpioPin is the pin number of the CPU pin;

(1-2) instantiating an IO pin structure variable and defining the number of members of the instantiated variable, and instantiating a structure pointer variable named ioConf according to the IO pin structure defined in the step (1-1); defining a variable of a loading quantity for the pointer variable, wherein the variable is an unsigned 8-bit integer variable and is named as ioCnt;

(1-3) initializing variables for loading the quantity of the structure pointer variables and the structure pointer variables, and initializing the variables ioCnt for loading the quantity of the structure pointer variables defined in the step (1-2) according to the quantity of the IO variables configured by a user; according to the value of ioCnt and the size of the memory of the structure body tPin _ IO, allocating space for the structure body pointer variable ioConf through malloc keywords; finally, initializing member variables gpioPort and gpioPin of a structure pointer variable ioConf according to IO pin configuration parameters configured by a user;

(1-4) designing an IO pin configuration interface and a read-write IO drive interface, and designing the IO pin configuration interface and the read-write IO drive interface according to the gpioPort, gpioPin and ioCnt initialized in the step (1-3);

the IO pin configuration interface process is as follows: configuring a CPU pin in a cycle from 0 to ioCnt, wherein the configuration content comprises a configuration pin clock, a configuration corresponding pin register and a configuration pin port register; the read-write IO driving interface finds the corresponding port according to the gpioPort and then calls the read-write register to perform corresponding functional operation.

10. The computer program product of claim 8, wherein the generic functional instruction driven design comprises:

(2-1) defining a functional instruction structure, wherein the functional instruction structure is used for defining a structure variable based on C language, and encapsulating a parameter related to a functional instruction in a structure, and the structure is named as tFunc;

(2-2) instantiating a function type instruction structure variable and defining the number of members of the instantiated variable, and instantiating a structure pointer variable named pFanc according to the function type instruction structure defined in the step (2-1); defining a variable of loading quantity for the pointer variable, wherein the variable is an unsigned 8-bit integer variable and is named as cntFunc;

(2-3) initializing variables for loading the quantity of the variables of the structure pointer, and the variables of the structure pointer, initializing the variables cntFunc for loading the quantity of the variables of the structure pointer defined in the step (2-2) according to the quantity of the variables of the functional instructions called in the user programming; according to the value of the cntFunc and the memory size of the structure tFunc, distributing space for the structure pointer variable pFanc through malloc keywords; finally, initializing member variables of the structural body pFanc according to the configuration condition of functional instruction parameters called in user programming; if the functional instruction structure body has parameters related to the hardware port information, calling related configuration data to initialize the member variables related to the hardware configuration of the pFanc;

(2-4) designing and realizing a functional instruction initialization interface and a driving interface, and designing the functional instruction initialization interface and the driving interface according to the pFanc and the cntFunc initialized in the step (2-3); initializing corresponding function registers according to different types of CPU pins used by different functions; the driving interface is called when a user configures the driving interface;

the general interrupt function design comprises:

(3-1) an interrupt function macro definition, which is to define an interrupt macro first when an interrupt interface is called by a user; the interrupt macro means that the macro definition represents a certain interrupt;

(3-2) defining an interrupt service function, when a user calls an interrupt interface, defining an interrupt service function, converting an interrupt program written by the user in the ladder diagram programming from the ladder diagram language to the C language to generate a C language interrupt program, and packaging the C language interrupt program in the interrupt service function;

(3-3) pre-declaring an interrupt service function, and pre-declaring the interrupt service function by adopting a conditional compiling method according to the interrupt macro in the step (3-1);

and (3-4) preprocessing the basic functions of the interrupt service, wherein each interrupt function needs to be processed by some basic functions in advance to cushion the interrupt service functions of the user, and in order to realize the basic functions, preprocessing is performed by combining the interrupt macro in the step (3-1) in a conditional compiling mode.

Images