CN115241664A - Repair circuit of electric connection structure and control method thereof - Google Patents

Repair circuit of electric connection structure and control method thereof Download PDF

Info

Publication number
CN115241664A
CN115241664A CN202210784714.0A CN202210784714A CN115241664A CN 115241664 A CN115241664 A CN 115241664A CN 202210784714 A CN202210784714 A CN 202210784714A CN 115241664 A CN115241664 A CN 115241664A
Authority
CN
China
Prior art keywords
data
gate
control
connection structure
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210784714.0A
Other languages
Chinese (zh)
Inventor
张家瑞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN202210784714.0A priority Critical patent/CN115241664A/en
Publication of CN115241664A publication Critical patent/CN115241664A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R9/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, e.g. terminal strips or terminal blocks; Terminals or binding posts mounted upon a base or in a case; Bases therefor
    • H01R9/22—Bases, e.g. strip, block, panel
    • H01R9/28—Terminal boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/66—Structural association with built-in electrical component
    • H01R13/665—Structural association with built-in electrical component with built-in electronic circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/66—Structural association with built-in electrical component
    • H01R13/70—Structural association with built-in electrical component with built-in switch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R29/00—Coupling parts for selective co-operation with a counterpart in different ways to establish different circuits, e.g. for voltage selection, for series-parallel selection, programmable connectors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electronic Switches (AREA)

Abstract

The repair circuit of the electric connection structure comprises an electric connection module, M first data ends, M second data ends, a first control circuit module and a second control circuit module, wherein each first data end is correspondingly connected with the first ends of at least two electric connection structures one by one through at least two first switch units, and at least one electric connection structure is connected with at least two first data ends; each second data end is correspondingly connected with the second ends of the at least two electric connection structures through the at least two second switch units, and the at least one electric connection structure is connected with the at least two second data ends. Therefore, at least two electric connection structures are arranged between each first data end and the corresponding second data end to carry out data transmission, mutual standby between the electric connection structures is realized, and the reliability of data transmission is ensured.

Description

Repair circuit of electric connection structure and control method thereof
Technical Field
The present disclosure relates to, but is not limited to, a repair circuit of an electrical connection structure and a control method thereof.
Background
With the continuous development of integrated circuits, when semiconductor process devices are advanced to the nanometer level, it is more difficult to further improve the integration level by reducing the feature size, and the three-dimensional stacked memory device becomes another possible form for improving the integration level. In the stacked memory device, electrical connection between semiconductor chips of each layer is usually realized Through Silicon Vias (TSVs), the TSVs are prone to failure in the manufacturing and binding processes, the TSV failure will inevitably affect communication connection between the chips, and in order to ensure normal communication between the semiconductor chips, a spare Through Silicon Via is usually provided to prevent signal transmission Through the spare Through Silicon Via when some Through Silicon vias are damaged.
The semiconductor chips of the stacked memory device are difficult to transmit data in a bidirectional mode through the through silicon vias, the performance of the stacked memory device is limited, the standby through silicon vias are prone to failure due to the fact that short circuits occur, in addition, design redundancy is caused due to the fact that the number of the standby through silicon vias is too large, and the structural compactness of the semiconductor chips is affected.
Disclosure of Invention
The following is a summary of subject matter that is described in detail in this disclosure. This summary is not intended to limit the scope of the claims.
The present disclosure provides a repair circuit of an electrical connection structure and a control method thereof.
According to a first aspect of embodiments of the present disclosure, there is provided a repair circuit of an electrical connection structure, including:
the electric connection module comprises 1 st, 2 nd, 8230th and N electric connection structures, wherein N is a positive integer greater than or equal to 3;
the M first data ends are positioned on the first side of the electric connection module, each first data end is correspondingly connected with the first ends of at least two electric connection structures one by one through at least two first switch units, and at least one electric connection structure is connected with at least two first data ends;
the M second data ends are positioned on the second side of the electric connection module, correspond to the M first data ends one by one, are connected with the second ends of the at least two electric connection structures one by one through at least two second switch units and correspond to the connection relation between the M first data ends and the electric connection structures, and at least one electric connection structure is connected with the at least two second data ends, wherein M is a positive integer which is more than or equal to 2 and less than N;
the first control circuit is used for respectively controlling the on-off of each first switch unit according to the voltage change of the first end of each electric connection structure, and when one first switch unit connected with the same first data end is on, controlling the off of other first switch units connected with the first data end;
and the second control circuit is used for respectively controlling the second switch units to be switched on or switched off according to the voltage change of the second ends of the electric connection structures, and when one second switch unit connected with the same second data end is switched on, the second control circuit controls the other second switch units connected with the second data end to be switched off.
In some embodiments of the present disclosure, two adjacent first data terminals are respectively connected to at least one same electrical connection structure through the first switch unit;
two adjacent second data terminals are respectively connected to at least one same electrical connection structure through the second switch unit.
In some embodiments of the present disclosure, the 1 st first data terminal is connected to the 1 st, 8230through R first switch units, respectively, and the first terminals of the R electrical connection structures are connected to the first data terminal through R first switch units;
the ith first data terminal is respectively connected with the first terminals of the (i + R-1) th electric connection structures through R first switch units;
the 1 st second data terminal is respectively connected with the 1 st, 8230and R second terminals of the electric connection structures through R second switch units;
the jth second data end is connected with the second ends of the jth electrical connection structures of (j + R-1) th electrical connection structures of (j), (8230) th and (j + R-1) th through R second switch units respectively;
wherein i is a positive integer greater than or equal to 2, j is a positive integer greater than or equal to 2, and R is a positive integer greater than or equal to 2.
In some embodiments of the present disclosure, the first control circuit is configured to control on or off of each of the first switch units connected to each of the first data terminals;
for each first data end, the first control circuit is used for controlling the conduction of a first switch unit corresponding to an electric connection structure which is connected with the first control circuit and is in a normal working state and has a front serial number in the unoccupied electric connection structure;
the second control circuit is configured to control the second switch unit connected to each of the second data terminals to be turned on or off;
for each second data terminal, the second control circuit is used for controlling the conduction of a second switch unit corresponding to an electric connection structure which is connected with the second control circuit and has a front serial number and is in a normal working state in an unoccupied electric connection structure.
In some embodiments of the present disclosure, the first control circuit includes N discharge circuits and N first detection circuits, first ends of the N first detection circuits and the N discharge circuits are respectively connected to first ends of the N electrical connection structures in a one-to-one correspondence manner, and a second end of each first detection circuit is connected to each first switch unit of the corresponding electrical connection structure;
the second control circuit comprises N discharge circuits and N second detection circuits, the first ends of the N second detection circuits and the N discharge circuits are respectively connected with the second ends of the N electric connection structures in a one-to-one correspondence manner, and the second end of each second detection circuit is connected with each second switch unit of the corresponding electric connection structure;
wherein the charging circuit is configured to charge the corresponding electrical connection structure to a first voltage level, and the discharging circuit is configured to discharge the corresponding electrical connection structure to a second voltage level;
the first detection circuit is used for generating a first control signal according to the voltage level change of the first end of the connected electric connection structure, the first control signal is output by the second end of the first detection circuit, and the first control signal is used for controlling the conduction or the closing of each first switch unit corresponding to the electric connection structure;
the second detection circuit is configured to generate a second control signal according to a voltage level change of a second end of the electrically connected structure, where the second control signal is output by the second end of the second detection circuit and is used to control on or off of each second switch unit corresponding to the electrically connected structure.
In some embodiments of the present disclosure, the first control circuit includes a plurality of first sub-control units connected to the first switch units in a one-to-one correspondence, where the first sub-control units are configured to control on and off of the first switch units connected thereto;
each first data terminal corresponds to R first branch control units,
as for the 1 st first data terminal,
the 1 st first control unit corresponding to the 1 st first data end is used for controlling the conduction or the closing of the 1 st first switch unit connected with the 1 st first control unit according to a first control signal of the 1 st first detection circuit;
mth corresponding to 1 st first data terminal 1 A first control unit for controlling the first switch according to the m 1 A first control signal of the first detection circuit and (m) th control signal corresponding to the first control signal 1 -1) output signals of first sub-control units controlling the on or off of the first switching units connected thereto;
for the m-th 2 A first data terminal for receiving the first data signal,
m th 2 A 1 st first control unit corresponding to the first data terminal for controlling the first data terminal according to the m 2 A first control signal of the first detection circuit and an (m) th control signal of the first detection circuit 2 -1) the output signal of the 1 st first control unit corresponding to the 1 first data terminal controls the on or off of the 1 st first switch unit connected with it;
m th 2 M-th data terminal corresponding to the first data terminal 1 A first control unit for controlling the first switch according to the (m) th 2 +m 1 -1) first control signal of said first detection circuit, the (m) th corresponding thereto 1 -1) the output signal of the first control unit and 2 -1) first data pair pairs(m) th of reaction 1 -1) output signals of first sub-control units controlling the on or off of the first switching units connected thereto;
the second control circuit comprises a plurality of second sub-control units which are connected with the second switch units in a one-to-one correspondence mode, and the second sub-control units are used for controlling the on and off of the second switch units connected with the second control units;
each second data terminal corresponds to R second branch control units,
for the 1 st second data terminal,
the 1 st second branch control unit corresponding to the 1 st second data end is used for controlling the conduction or the closing of the second switch unit connected with the 1 st second branch control unit according to a second control signal of the 1 st second detection circuit;
mth corresponding to the 1 st second data terminal 1 A second sub-control unit for controlling the sub-control unit according to the m 1 A second control signal of the second detection circuit and an (m) th signal 1 -1) output signals of second sub-control units controlling the on or off of the second switching units connected thereto;
for the m-th 2 A second data terminal for receiving the second data signal,
m th 2 A 1 st second branch control unit corresponding to the second data terminal and used for controlling the first data terminal according to the m 2 A second control signal of the second detection circuit and an (m) th signal 2 -1) an output signal of a 1 st second sub-control unit corresponding to each second data terminal controls the second switch unit connected with the output signal to be switched on or off;
m th 2 M-th corresponding to the second data terminal 1 A second sub-control unit for controlling the second sub-control unit according to the (m) th 2 +m 1 -1) second control signal of said second detection circuit, the (m) th 1 -1) the output signal of the second sub-control unit and (m) th 2 -1) the (m) th of the second data terminal 1 -1) output signals of second sub-control units controlling the on or off of the second switching units connected thereto;
wherein m is 1 Is a positive integer greater than or equal to 2 and less than or equal to R, m 2 Is a positive integer greater than or equal to 2 and less than or equal to M.
In some embodiments of the present disclosure, for the 1 st first data terminal,
the 1 st first sub-control unit corresponding to the 1 st first data end comprises a first node, the input end of the first node is connected with the output end of the 1 st detection circuit, and the output end of the first node is used as the control end of the corresponding first switch unit;
when m is 1 When the value is less than R, the mth corresponding to the 1 st first data end 1 The first branch control units comprise a first AND gate and a first OR gate, wherein the input end of the first AND gate is respectively connected with the inverted signal of the output end of the first node and the mth gate 1 The output end of the first AND gate is connected with the control end of the corresponding first switch unit, the input end of the first OR gate is respectively connected with the output end of the first node and the output end of the first AND gate, and the output end of the first OR gate is used as the mth 1 The output end of each first branch control unit;
the Rth first sub-control unit corresponding to the 1 st first data end comprises a second AND gate and a second OR gate, the input end of the second AND gate is respectively connected with the reverse signal of the output end of the first OR gate, the output end of the Rth first detection circuit is connected with the control end corresponding to the first switch unit, the input end of the second OR gate is respectively connected with the output end of the first OR gate and the output end of the second AND gate, the output end of the second OR gate is used as the output end of the Rth first sub-control unit corresponding to the 1 st first data end and is connected with the Rth first sub-control unit corresponding to the 2 nd first data end;
when m is 2 Less than M, for the M-th 2 A first data terminal for receiving the first data signal,
m th 2 The 1 st first sub-control unit corresponding to the first data end comprises a third AND gate, and the input ends of the third AND gate are respectively connected with the mth 2 An output terminal of the first detection circuit and an (m) th signal 2 -1) first data pair pairsThe output end of the corresponding 1 st first control unit and the output end of the third AND gate are used as the m < th > unit 2 The output end of the 1 st first sub-control unit corresponding to each first data end is respectively connected with the control end of the corresponding first switch unit and the corresponding 2 nd first sub-control unit;
when m is 1 When less than R, m 2 M-th corresponding to the first data terminal 1 The first branch control units comprise a fourth AND gate and a third OR gate, and the input ends of the fourth AND gate are respectively connected with the (m) th gate 2 +m 1 -1) the output of said first detection circuit, the corresponding (m) th 1 -1) the inverted signal at the output of the first control unit and (m) th 2 -1) mth data terminal corresponding to first data terminal 1 The output ends of the fourth and gates are respectively connected with the control ends of the corresponding first switch units and the third or gates, and the input ends of the third or gates are respectively connected with the corresponding (m) th or gate 1 -1) the output of the first control unit and the output of the fourth and-gate, the output of the third or-gate being the m-th 2 M-th data terminal corresponding to the first data terminal 1 The output end of each first branch control unit is connected with the corresponding mth 1 +1 first slave control units;
m th 2 The Rth first branch control unit corresponding to the first data end comprises a fifth AND gate and a fourth OR gate, and the input ends of the fifth AND gate are respectively connected with the (R + m) th gate 1 -1) the inverted signal of the output of the first detection circuit, the corresponding output of the R-1 th first control unit and the (m) th 2 -1) an output terminal of an R-th first sub-control unit of the first data terminals, an output terminal of the fifth and-gate being connected to a control terminal of the corresponding first switch unit and a fourth or-gate, respectively, an input terminal of the fourth or-gate being connected to an output terminal of the corresponding R-1-th first sub-control unit and an output terminal of the fifth and-gate, an output terminal of the fourth or-gate being used as an m-th output terminal 2 The output end of the Rth first branch control unit corresponding to the first data end is connected with the mth 2 The R-th first branch control unit of +1 first data ends;
as for the mth first data terminal,
the 1 st first sub-control unit corresponding to the mth first data end comprises a sixth AND gate, the input end of the sixth AND gate is respectively connected with the output end of the mth first detection circuit and the 1 st first sub-control unit corresponding to the (M-1) th first data end, the output end of the sixth AND gate is used as the output end of the 1 st first sub-control unit corresponding to the mth first data end, and is respectively connected with the control end of the corresponding first switch unit and the corresponding 2 nd first sub-control unit;
when m is 1 When the current value is less than R, the M-th corresponding to the Mth first data terminal 1 The first branch control units comprise a seventh AND gate and a fifth OR gate, and the input ends of the seventh AND gate are respectively connected with the (M + M) th 1 -1) the output of said first detection circuit, the corresponding (m) th 1 -1) an inverted signal at the output of the first control unit and the mth signal corresponding to the (M-1) th first data terminal 1 The output end of the seventh AND gate is respectively connected with the control end of the corresponding first switch unit and the fifth OR gate, the input ends of the fifth or gates are respectively connected with the corresponding (m) th 1 -1) the output of the first control unit and the output of the seventh and gate, the output of the fifth or gate being the mth corresponding to the mth first data terminal 1 The output end of each first branch control unit is connected with the corresponding mth 1 +1 first branch control units;
the Rth first sub-control unit corresponding to the Mth first data end comprises an eighth AND gate, the input end of the eighth AND gate is respectively connected with the output end of the (R + M-1) th first detection circuit, the reverse signal of the output end of the corresponding R-1 th sub-control unit and the output end of the Rth first sub-control unit of the M-1 first data end, and the output end of the eighth AND gate is connected with the control end of the corresponding first switch unit;
for each second data end, the structures of the R second sub-control units corresponding to the second data end and the R first sub-control units corresponding to the first data end corresponding to the second data end are the same.
In some embodiments of the present disclosure, when the mth first data terminal is conducted with the mth second data terminal through the nth ' electrical connection structure, if N ' is less than N, the first switch unit and the second switch unit, which are respectively connected, are respectively turned off through the first sub-control units and the second sub-control units corresponding to the nth ' +1 to nth electrical connection structures.
In some embodiments of the present disclosure, the first detection circuit includes a first flip-flop and a first inverter, an input end of the first inverter is used as a first end of the first detection circuit and is connected to a first end of the corresponding electrical connection structure, an output end of the first inverter is connected to a clock input end of the first flip-flop, and an output end of the first flip-flop is used as a second end of the first detection circuit and is connected to each first switch unit and each first sub-control unit;
the second detection circuit comprises a second trigger and a second phase inverter, the input end of the second phase inverter is used as the first end of the second detection circuit and is connected with the second end of the corresponding electric connection structure, the output end of the second phase inverter is connected with the clock input end of the second trigger, and the output end of the second trigger is used as the second end of the second detection circuit and is connected with each second switch unit and each second sub-control unit.
In some embodiments of the present disclosure, the first flip-flop is a rising edge flip-flop and outputs a high level signal in response to a rising edge signal;
the second flip-flop is a rising edge flip-flop and outputs a high level signal in response to a rising edge signal.
In some embodiments of the present disclosure, the first switch unit is turned on in response to a high level signal output by the corresponding first branch control unit;
the second switch unit is turned on in response to the high level signal output by the corresponding first branch control unit.
In some embodiments of the present disclosure, the first detection circuit further includes a first transistor, a first electrode of the first transistor is connected to the input end of the first inverter, a second electrode of the first transistor is grounded, and a gate of the first transistor is connected to an inverted signal of the electrical signal;
the second detection circuit further comprises a second transistor, a first pole of the second transistor is connected with the input end of the second inverter, a second pole of the second transistor is grounded, and a grid electrode of the second transistor is connected with an inverted signal of an electric signal.
In some embodiments of the present disclosure, the reset terminal of the first flip-flop is connected to an electrical signal, and the first flip-flop is configured to reset the output terminal thereof when the reset terminal thereof does not receive the power-on signal;
the reset end of the second trigger is connected with an upper electric signal, and the second trigger is used for resetting the output end of the second trigger when the reset end of the second trigger does not receive the power-on signal.
In some embodiments of the present disclosure, the electrical connection structure is a through silicon via structure, the M first data terminals and the first control circuit are disposed in a first semiconductor chip, and the M second data terminals and the second control circuit are disposed in a second semiconductor chip.
A second aspect of the present disclosure provides a control method for a repair circuit of an electrical connection structure, where the repair circuit of the electrical connection structure includes an electrical connection module, the electrical connection module includes N electrical connection structures, a first side of the electrical connection module is provided with M first data terminals, a second side of the electrical connection module is provided with M second data terminals, each of the first data terminals is connected to first terminals of at least two of the electrical connection structures, each of the second data terminals is connected to second terminals of at least two of the electrical connection structures, where N is a positive integer greater than or equal to 3, and M is a positive integer greater than or equal to 2 and less than N, the control method includes:
detecting a voltage change at the first end and the second end of each of the electrical connection structures;
controlling the electric connection structure to be connected with or disconnected from the corresponding first data end according to the voltage change of the first end of each electric connection structure, and controlling the electric connection structure to be connected with or disconnected from the corresponding second data end according to the voltage change of the second end of each electric connection structure, so that the electric connection structure is selectively connected with or disconnected from the first data end, and the electric connection structure is selectively connected with or disconnected from the second data end;
when two ends of the electric connection structure are respectively communicated with a first data end and a second data end, the data signal is controlled to be transmitted from the communicated first data end to the second data end, or the data signal is controlled to be transmitted from the communicated second data end to the first data end.
In some embodiments of the present disclosure, the detecting a voltage variation at the first end and the second end of each of the electrical connection structures includes:
setting, by a charging circuit, a first end and a second end of an electrical connection structure to a first voltage level;
setting, by the discharge circuit, the first and second ends of the electrical connection structure to a second voltage level;
the method for controlling the electric connection structure to be connected with or disconnected from the corresponding first data end according to the voltage change of the first end of each electric connection structure, and controlling the electric connection structure to be connected with or disconnected from the corresponding second data end according to the voltage change of the second end of each electric connection structure comprises the following steps:
responding to the voltage of the first end of the electric connection structure changing from the first voltage level to the second voltage level, and controlling the electric connection structure to be alternatively conducted with the first data end through a first detection circuit;
and responding to the voltage of the second end of the electric connection structure changed from the first voltage level to the second voltage level, and controlling the electric connection structure to be alternatively conducted with the second data end through a second detection circuit.
In some embodiments of the present disclosure, the first data end, the electrical connection structure, and the second data end are connected through a control circuit to form a data transmission path, and the control circuit sequentially controls to connect each data transmission path according to a sequence number of the electrical connection structure corresponding to the data transmission path.
In the repair circuit of the electrical connection structure provided by the embodiment of the disclosure, the first data terminal and the second data terminal are both connected with the electrical connection structure in the electrical connection module through the switch unit, and when the voltage changes at the two ends of the electrical connection structure meet the requirements (i.e., the electrical connection structure is normal), the first control circuit and the second control circuit control the switch units at the two ends of the electrical connection structure to be turned on, so as to achieve the conduction of the first data terminal and the second data terminal. In addition, because the two ends of the electric connection structure are provided with the switch units, when some electric connection structures are short-circuited, the first switch units and the second switch units on the two sides of the electric connection structure can not be switched on, so that the current can not influence other electric connection structures, and the data transmission performance is ensured.
In M first data ends and M second data ends, each first data end is connected with the first ends of at least two electric connection structures through at least two first switch units, and each second data end is connected with the second ends of at least two electric connection structures through at least two second switch units, so that at least two electric connection structures are arranged between each first data end and the corresponding second data end for data transmission, backup among the electric connection structures is realized, and reliability of data transmission is guaranteed. At least one electric connection structure is connected with at least two first data ends simultaneously, at least one electric connection structure is connected with at least two second data ends simultaneously, so that the same electric connection structure can be applied to data transmission between different first data ends and second data ends, when one first switch unit connected with the first data ends is conducted, other first switch units connected with the first data ends are controlled to be closed, when one second switch unit connected with the same second data ends is conducted, other second switch units connected with the second data ends are controlled to be closed, mutual standby of the electric connection structures between different data ends is achieved, design redundancy of the connection structures is reduced, compactness of a semiconductor structure of a repair circuit adopting the electric connection structure is improved, and independence between data transmission paths can be guaranteed.
Other aspects will be apparent upon reading and understanding the attached figures and detailed description.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to indicate like elements. The drawings in the following description are directed to some, but not all embodiments of the disclosure. To a person skilled in the art, without inventive effort, other figures can be derived from these figures.
Fig. 1 is a schematic diagram showing a circuit configuration in the related art;
FIG. 2 illustrates a schematic diagram of a repair circuit electrically connected to a structure shown in an exemplary embodiment of the present disclosure;
FIG. 3 illustrates a circuit diagram of a repair circuit of an electrical connection configuration shown in an exemplary embodiment of the present disclosure;
FIG. 4 illustrates a circuit diagram of a repair circuit of an electrical connection configuration shown in another exemplary embodiment of the present disclosure;
fig. 5 is a schematic diagram illustrating a structure of a control circuit, an electrical connection structure, and a switch unit in a repair circuit of an electrical connection structure according to an exemplary embodiment of the present disclosure;
FIG. 6 illustrates a timing diagram of the operation of a repair circuit of the electrical connection configuration shown in an exemplary embodiment of the present disclosure;
fig. 7 is a flowchart illustrating a method for controlling a repair circuit of an electrical connection structure according to an exemplary embodiment of the present disclosure.
In the figure: 10', an electrical connection module; 11', an electrical connection structure; 20', a first control circuit; 30', a second control circuit; 40', a first switching unit; 50', a second switching unit;
10. electrically connecting the modules; 11. an electrical connection structure; 20. a first control circuit; 21. a discharge circuit; 211. a third transistor; 22. a first detection circuit; 221. a first flip-flop; 222. a first inverter; 223. a first transistor; 224. a third inverter; 30. a second control circuit; 31. a charging circuit; 311. a fourth transistor; 32. a second detection circuit; 321. a second flip-flop; 322. a second inverter; 323. a second transistor; 324. a fourth inverter; 40. a first switch unit; 41. an nMOS tube; 42. a pMOS tube; 50. a second switching unit; 60. a first data terminal; 70. a second data terminal; 80. a first branch control unit; 90. and a second branch control unit.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure. It should be noted that, in the present disclosure, the embodiments and the features of the embodiments may be arbitrarily combined with each other without conflict.
The stacked semiconductor device is mainly taken as an example to be introduced, and the repair circuit of the electrical connection structure and the control method thereof provided by the embodiment of the disclosure are understood to be suitable for other devices with the same problems.
The stacked semiconductor device includes a plurality of semiconductor chips stacked one on another, and the semiconductor chips are electrically connected to each other through an electrical connection structure such as a through-silicon via. Since the through silicon via needs to ensure physical connection, after the stacked semiconductor device is powered on, the through silicon via needs to be tested to ensure that the through silicon via can perform normal signal transmission. However, in order to implement the test, a one-way gating device such as an inverter is usually disposed on the test circuit of the through silicon via, so that it is difficult to implement the two-way transmission of data between chips through the through silicon via, thereby affecting the performance of the stacked semiconductor device.
For this, a circuit structure is proposed in the related art, which includes an electrical connection module 10', a first control circuit 20', and a second control circuit 30', as shown in fig. 1. The electrical connection module 10' includes two electrical connection structures 11', and a first switch unit 40' and a second switch unit 50' are respectively disposed at two ends of each electrical connection structure 11 '. The first control circuit 20 'is used for controlling the first switch unit 40' to be turned on or off according to the voltage variation of the first end of the electrical connection structure 11 '(e.g., the left end of the electrical connection structure 11'), and the second control circuit 30 'is used for controlling the second switch unit 50' to be turned on or off according to the voltage variation of the second end of the electrical connection structure 11 '(e.g., the right end of the electrical connection structure 11').
In the above circuit configuration, when the first switching unit 40 'and the second switching unit 50' are simultaneously in the on state, data can be transmitted from the first switching unit 40 'to the second switching unit 50' and also from the second switching unit 50 'to the first switching unit 40', thereby realizing bidirectional data transmission. In addition, since the first ends of the electrical connection structures 11' are isolated by the respective first switch units 40', and the second ends of the electrical connection structures 11' are isolated by the respective second switch units 50', it is avoided that the other electrical connection structures are affected after a fault, such as a short circuit, occurs in one of the electrical connection structures 11', and the reliability of the circuit structure is ensured.
However, in the above circuit structure, a spare electrical connection structure 11 is correspondingly arranged for each electrical connection structure 11', and although the detection of the electrical connection structure and the modification of the faulty electrical connection result can be realized, the number of electrical connection structures needs to be increased by one or several times, which causes the excessive number of electrical connection structures, causes design redundancy, and affects the structural compactness of the semiconductor chip.
Based on this, an exemplary embodiment of the present disclosure provides a repair circuit of an electrical connection structure, in which at least two first data terminals in the repair circuit of the electrical connection structure are respectively connected to a same electrical connection structure through corresponding first switch units, and at least two second data terminals are respectively connected to a same electrical connection structure through corresponding second switch units, so that the same electrical connection structure can be applied to data transmission between different first data terminals and second data terminals, and when one first switch unit connected to the same first data terminal is turned on, other first switch units connected to the first data terminal are controlled to be turned off, an electrical connection structure connected to other first switch units can serve as a backup for other first data terminals, and when one second switch unit connected to the same second data terminal is turned on, other second switch units connected to the second data terminal are controlled to be turned off, and an electrical connection structure connected to other second switch units can serve as a backup for other second data terminals, which reduces design redundancy of the connection structure, improves compactness of the repair circuit of the electrical connection structure, and can ensure independent data transmission paths between semiconductor structures.
As shown in fig. 2, an exemplary embodiment of the present disclosure provides a repair circuit of an electrical connection structure including an electrical connection module 10, M first data terminals 60, M second data terminals 70, a first control circuit 20, and a second control circuit 30. The electrical connection module 10 includes the first and second electrical connection structures 1 and 2, N is a positive integer greater than or equal to 3, taking fig. 3 as an example, the electrical connection module 10 includes 4 electrical connection structures 11, which are TSV1, TSV2, TSV3 and TSV4, respectively, taking fig. 4 as an example, and the electrical connection module 10 includes 6 electrical connection structures 11, which are TSV1, TSV2, TSV3, TSV4, TSV5 and TSV6, respectively.
The M first data terminals 60 are located on a first side of the electrical connection module 10 (for example, on a left side of the electrical connection module 10), and the M second data terminals 70 are located on a second side of the electrical connection module 10 (for example, on a right side of the electrical connection module 10), for example, the electrical connection module 10 is used to implement connection between chips, for example, connection between the chip Die0 and the chip Die1, then the first data terminals 60 and the first control circuits 20 are disposed on the chip Die0, and the second data terminals 70 and the second control circuits 20 are disposed on the chip Die1.
As shown in fig. 2, each first data terminal 60 is connected to the first terminals of the at least two electrical connection structures 11 through the at least two first switch units 40 in a one-to-one correspondence manner, that is, the first data terminal 60 is connected to the first terminals of the at least two electrical connection structures 11, and a first switch unit 40 is disposed between the first data terminal 60 and each electrical connection structure 11, where M is a positive integer greater than or equal to 2 and less than N. Continuing with fig. 3 as an example, in the embodiment shown in fig. 3, the repair circuit of the electrical connection structure includes two first data terminals 60 of IO1 and IO2, and the two first data terminals 60 of IO1 and IO2 are respectively connected to the first ends of the 3 electrical connection structures 11 through the 3 first electrical switch units 40 in a one-to-one correspondence manner, where the first data terminal IO1 is connected to the first ends of the three electrical connection structures 11 through the three first switch units 40, that is, the first data terminal IO1 is connected to the first end of the TSV1 through the first switch unit S41, is connected to the first end of the TSV2 through the first switch unit S42, and is connected to the first end of the TSV3 through the first switch unit S43. The first data terminal IO2 is connected to the first terminals of the three electrical connection structures 11 through the three first switch units 40, that is, IO2 is connected to the first terminal of TSV2 through the first switch unit S44, connected to the first terminal of TSV3 through the first switch unit S45, and connected to the first terminal of TSV4 through the first switch unit S46.
At least one electrical connection structure 11 connects at least two first data terminals 60, i.e. there is at least one electrical connection structure 11 connecting at least two first data terminals 60 simultaneously. For example, as shown in fig. 3, the first data terminal IO1 and the first data terminal IO2 are respectively connected to the TSV2 through different first switch units 40, and the first data terminal IO1 and the first data terminal IO2 are respectively connected to the TSV3 through different first switch units 40.
As shown in fig. 2, the M second data terminals 70 are located at the second side of the electrical connection module 10 and are in one-to-one correspondence with the M first data terminals 70, that is, each second data terminal 70 corresponds to one first data terminal 60, so as to form a data transmission path between the corresponding first data terminal 60 and second data terminal 70. In the embodiment shown in fig. 3, the repair circuit of the electrical connection structure includes two second data terminals 70, i.e. IO1 'and IO2', where the second data terminal IO1 'corresponds to the first data terminal IO1, and the second data terminal IO2' corresponds to the first data terminal IO 2.
Each of the second data terminals 70 is connected to the second terminals of the at least two electrical connection structures 11 through the at least two second switch units 50 in a one-to-one correspondence manner, and is connected to the connection relationship between the M first data terminals 60 and the electrical connection structures 11 in a one-to-one correspondence manner, for example, as shown in fig. 3, the second data terminal IO1' is connected to the second terminal of the TSV1 through the second switch unit S51, connected to the second terminal of the TSV2 through the second switch unit S52, and connected to the second terminal of the TSV3 through the second switch unit S53. The second data terminal IO2 'is connected to the second terminals of the three electrical connection structures 11 through the three second switch units 50, that is, the second data terminal IO2' is connected to the second terminal of the TSV2 through the second switch unit S54, connected to the second terminal of the TSV3 through the second switch unit S55, and connected to the second terminal of the TSV4 through the second switch unit S56.
At least one electrical connection structure 11 connects at least two second data terminals 70, i.e. there is at least one electrical connection structure 11 connecting at least two second data terminals 70 simultaneously. For example, as shown in fig. 3, the second data terminal IO1 'and the second data terminal IO2' are respectively connected to the TSV2 through the second switch unit 50, and the second data terminal IO1 'and the second data terminal IO2' are respectively connected to the TSV3 through the second switch unit 50.
The first control circuit 20 is configured to respectively control each first switch unit 40 to turn on or turn off according to a voltage variation at the first end of each electrical connection structure 11, and when one first switch unit 40 connected to the same first data end 60 is turned on, control other first switch units 40 connected to the first data end 60 to turn off, and continuing to take fig. 3 as an example, if the first control circuit 20 controls the first switch unit S42 corresponding to the first data end IO1 in the TSV2 to turn on, control the first switch unit S41 and the first switch unit S43 connected to the first data end IO1 to turn off. If the first control circuit 20 controls the first switch unit S45 corresponding to the first data terminal IO2 in the TSV3 to be turned on, the first switch unit S44 and the first switch unit S46 connected to the first data terminal IO2 are controlled to be turned off.
The second control circuit 30 is configured to respectively control each second switch unit 50 to turn on or off according to a voltage variation of the second end of each electrical connection structure 11, and when one second switch unit 50 connected to the same second data end 70 is turned on, control the other second switch units 50 connected to the second data end 70 to turn off. Referring to fig. 3, if the second control circuit 30 controls the second switch unit S52 corresponding to the second data terminal IO1 'in the TSV2 to be turned on, the second switch unit S51 and the second switch unit S52 connected to the second data terminal IO1' are controlled to be turned off. If the second control circuit 30 controls the second switch unit S55 corresponding to the second data terminal IO2 'in the TSV3 to be turned on, the second switch unit S54 and the second switch unit S56 connected to the second data terminal IO2' are controlled to be turned off.
In this embodiment, the first data terminal 60 and the second data terminal 70 are both connected to the electrical connection structure 11 in the electrical connection module 10 through a switch unit, and the switch unit is a bidirectional conductive switch device, when the voltage variation at two ends of the electrical connection structure 11 meets the requirement (i.e. the electrical connection structure is normal), the first control circuit 20 and the second control circuit 30 will control the switch units at two ends of the electrical connection structure 11 to be turned on, so as to implement the bidirectional conduction of the first data terminal 60 and the second data terminal 70, therefore, after the conduction, the data signal can be transmitted from the first data terminal 60 to the second data terminal 70, and can be transmitted from the second data terminal 70 to the first data terminal 60, thereby implementing the bidirectional transmission of data, and improving the performance of the electrical device, such as a semiconductor device, of the repair circuit using the electrical connection structure. In addition, because the switch units are disposed at both ends of the electrical connection structure 11, when some of the electrical connection structures 11 are short-circuited, the voltages at both ends of the electrical connection structure 11 do not change (that is, the voltages at both ends of the electrical connection structure 11 do not meet the change requirement), and under the control of the first control circuit 20 and the second control circuit 30, the first switch unit 40 and the second switch unit 50 at both sides of the electrical connection structure 11 cannot be turned on, so that the current does not affect the other electrical connection structures 11, thereby ensuring the data transmission performance.
In the M first data terminals 60 and the M second data terminals 70, each first data terminal 60 is connected to the first terminals of the at least two electrical connection structures 11 through the at least two first switch units 40, and each second data terminal 70 is connected to the second terminals of the at least two electrical connection structures 11 through the at least two second switch units 50, so that it is ensured that at least two electrical connection structures 11 are provided between each first data terminal 60 and the corresponding second data terminal 70 to enable data transmission, thereby implementing backup between the electrical connection structures 11 and ensuring reliability of data transmission. At least one electric connection structure 11 is connected with at least two first data terminals 60, at least one electric connection structure 11 is connected with at least two second data terminals 70, so that the same electric connection structure 11 can be applied to data transmission between different first data terminals 60 and second data terminals 70, and when one first switch unit 40 connected with the same first data terminal 60 is turned on, other first switch units 40 connected with the first data terminals 60 are controlled to be turned off, and when one second switch unit 50 connected with the same second data terminal 70 is turned on, other second switch units 50 connected with the second data terminal 70 are controlled to be turned off, so that sequential standby between the electric connection structures 11 is realized, design redundancy of the electric connection structure 11 is reduced, compactness of a semiconductor structure of a repair circuit adopting the electric connection structure is improved, and independence between data transmission paths can be ensured.
Illustratively, the electrical connection structure 11 includes through-silicon vias for implementing electrical connection between two adjacent semiconductor chips, i.e., a first semiconductor chip and a second semiconductor chip, M first data terminals 60 and the first control circuit 20 are disposed in the first semiconductor chip, and M second data terminals 70 and the second control circuit 30 are disposed in the second semiconductor chip. For example, in the stacked semiconductor device, through-silicon vias are used to realize electrical connection between a base semiconductor chip and a core semiconductor chip, or to realize electrical connection between core semiconductor chips.
In the M first data terminals 60, any two or any plurality of first data terminals 60 may be connected to the same electrical connection structure 11, and in order to facilitate layout of circuit patterns and ensure compactness of a repair circuit of the electrical connection structure, the adjacent first data terminals 60 are designed to be connected to the same electrical connection structure. In an exemplary embodiment, two adjacent first data terminals 60 are connected to at least one same electrical connection structure 11 through the first switching unit 40, respectively. In some embodiments, as shown in fig. 2, in adjacent first data terminals 60, one first switch unit 40 of one first data terminal 60 and one first switch unit 40 of another first data terminal 60 are connected to the same electrical connection structure 11, that is, the two first data terminals 60 share one electrical connection structure 11 through different first switch units. In other embodiments, in the adjacent first data terminals 60, the plurality of first switch units 40 connected to one first data terminal 60 and the plurality of first switch units 40 of another first data terminal 60 are connected to the same electrical connection structures 11, and it can be understood that the first data terminals 60 and one electrical connection structure 11 are connected in a one-to-one correspondence manner only through one first switch unit 40, when the plurality of first switch units 40 corresponding to one first data terminal 60 and the plurality of first switch units 40 corresponding to another first data terminal 60 are connected to the same electrical connection structures 11, it means that the two first data terminals 60 share the plurality of electrical connection structures 11, and for each electrical connection structure 11, the two first data terminals 60 are connected through the two first switch units 40 respectively. For example, as shown in fig. 3, the first data terminal IO1 and the first data terminal IO2 are connected to the first terminal of the TSV2 through the corresponding first switch units S42 and S44, respectively, and the first data terminal IO1 and the first data terminal IO2 are further connected to the first terminal of the TSV3 through the corresponding first switch units S43 and S45, respectively, so that the first data terminal IO1 and the first data terminal IO2 share the TSVs 2 and the TSV3.
Similarly, in the M second data terminals 70, any two or any plurality of second data terminals 70 may be connected to the same electrical connection structure 11, and in order to facilitate the layout of the circuit pattern and ensure the compactness of the repair circuit of the electrical connection structure, the adjacent second data terminals 70 are designed to be connected to the same electrical connection structure 11. In an exemplary embodiment, two adjacent second data terminals 70 are connected to at least one same electrical connection structure 11 through the second switching unit 50, respectively. In some embodiments, as shown in fig. 2, in adjacent second data terminals 70, one second switch unit 50 of one second data terminal 70 and one second switch unit 50 of another second data terminal 70 are connected to the same electrical connection structure 11, that is, two second data terminals 70 share one electrical connection structure 11. In other embodiments, in the adjacent second data terminals 70, the plurality of second switch units 50 of one second data terminal 70 and the plurality of second switch units 50 of another second data terminal 70 are connected to a plurality of same electrical connection structures 11, and it can be understood that the second data terminals 70 and one electrical connection structure 11 are connected in one-to-one correspondence only through one second switch unit 50, and when the plurality of second switch units 50 of one second data terminal 70 and the plurality of second switch units 50 of another second data terminal 70 are connected to a plurality of same electrical connection structures 11, it means that two second data terminals 70 share a plurality of electrical connection structures 11, and for each electrical connection structure 11, two second data terminals 70 are connected through two second switch units 50 respectively. For example, as shown in fig. 3, the second data terminal IO1 'and the second data terminal IO2' are connected to the second terminal of the TSV2 through the corresponding second switch units S52 and S54, respectively, and the second data terminal IO1 'and the second data terminal IO2' are further connected to the second terminal of the TSV3 through the corresponding second switch units S53 and S55, respectively, so that the second data terminal IO1 'and the second data terminal IO2' share the TSVs 2 and TSV3.
It is understood that, in this embodiment, as shown in fig. 3, two first data terminals 60 may share one or more electrical connection structures 11, and two second data terminals 70 may share one or more electrical connection structures 11, and in other embodiments, a plurality of first data terminals 60 may share one or more electrical connection structures 11, and a plurality of second data terminals 70 may share one or more electrical connection structures 11.
In an exemplary embodiment of the present disclosure, the 1 st first data terminal 60 is connected to the 1 st, 8230: R first ends of the electrical connection structures 11 through R first switch units 40, respectively; the ith first data terminal 60 is connected to the first terminals of the (i + R-1) th electrical connection structures 11 through R first switch units 40; the 1 st second data terminal 70 is connected with the 1 st, 8230the R electrical connection structures 11 through the R second switch units 50; the jth second data terminal 70 is connected to the second terminals of the jth, \ 8230; (j + R-1) electrical connection structures 11 through R second switch units 50, respectively; wherein i is a positive integer greater than or equal to 2, j is a positive integer greater than or equal to 2, and R is a positive integer greater than or equal to 2. Exemplarily, as shown in fig. 4, the 1 st first data terminal 60 is connected to the first terminals of the 1 st, 2 nd, and 3 rd electrical connection structures 11 through three first switch units 40, respectively. The ith first data terminal 60 is connected to the first terminals of the ith, (i + 1) and (i + 2) th electrical connection structures 11 through three first switch units 40, respectively. The 1 st second data terminal 70 is connected to the second terminals of the 1 st, 2 nd and 3 rd electrical connection structures 11 through three second switch units 50, respectively; the jth second data terminal 70 is connected to the second terminals of the jth, (j + 1), (j + 2) electrical connection structures 11 through the three second switch units 50, respectively. As such, the 2 nd electrical connection structure 11 and the 3 rd electrical connection structure 11 may serve as a backup for the 1 st electrical connection structure 11, that is, when the 1 st electrical connection structure 11 fails, the 2 nd or the 3 rd electrical connection structure 11 may be used for signal transmission, the (i + 1) th electrical connection structure 11 and the (i + 2) th electrical connection structure 11 may serve as a backup for the ith electrical connection structure 11, and when the ith electrical connection structure 11 fails, the (i + 1) th electrical connection structure 11 or the (i + 2) th electrical connection structure 11 may be used for signal transmission.
Exemplarily, as shown in fig. 4, the repair circuit of the electrical connection structure includes four first data terminals 60, which are first data terminals IO1, IO2, IO3, and IO4, respectively, and 6 electrical connection structures 11, which are TSV1, TSV2, TSV3, TSV4, TSV5, and TSV6, respectively, where the first data terminal IO1 is connected to first ends of TSV1, TSV2, and TSV3 through three first switch units 40, the first data terminal IO2 is connected to first ends of TSV2, TSV3, and TSV4 through three first switch units 40, the first data terminal IO3 is connected to first ends of TSV3, TSV4, and TSV5 through three first switch units 40, and the first data terminal IO4 is connected to first ends of TSV4, TSV5, and TSV6 through three first switch units 40. The repair circuit of the electrical connection structure further includes four second data terminals 70, which are second data terminals IO1', IO2', IO3 'and IO4', respectively, where the second data terminal IO1 'is connected to the second terminals of the TSVs 1, TSV2, and TSV3 through three second switch units 50, respectively, the second data terminal IO2' is connected to the second terminals of the TSVs 2, TSV3, and TSV4 through three second switch units 50, respectively, the second data terminal IO3 'is connected to the second terminals of the TSVs 3, TSV4, and TSV5 through three second switch units 50, respectively, and the second data terminal IO4' is connected to the second terminals of the TSVs 4, TSV5, and TSV6 through three second switch units 50, respectively.
In this embodiment, when TSVs 1, TSV2, TSV3, and TSV4 are all normal, the first data end IO1 may implement signal transmission through TSV1 and second data end IO1', the first data end IO2 may implement signal transmission through TSV2 and second data end IO2', the first data end IO3 may implement signal transmission through TSV3 and second data end IO3', and the first data end IO4 may implement signal transmission through TSV4 and second data end IO 4'. When the TSV2 fails, the first data end IO1 may implement signal transmission through the TSV1 and the second data end IO1', the first data end IO2 may implement signal transmission through the TSV3 and the second data end IO2', the first data end IO3 may implement signal transmission through the TSV4 and the second data end IO3', and the first data end IO4 may implement signal transmission through the TSV5 and the second data end IO 4'. When both the TSV2 and the TSV3 fail, the first data end IO1 can realize signal transmission through the TSV1 and the second data end IO1', the first data end IO2 can realize signal transmission through the TSV4 and the second data end IO2', the first data end IO3 can realize signal transmission through the TSV5 and the second data end IO3', and the first data end IO4 can realize signal transmission through the TSV6 and the second data end IO 4'.
For convenience of control, the first control circuit 20 may set the first switch unit 40 and the second switch unit 50 with the on priority, and the higher the on priority, the higher the priority, the more priority the conduction is. In one embodiment, the first control circuit 20 is configured to control the on or off of each first switch unit 40 connected to each first data terminal 60; for each first data terminal 60, the first control circuit 20 is configured to control the conduction of the first switch unit 40 corresponding to the electrical connection structure 11 with the first serial number and in the normal operating state, in the unoccupied electrical connection structure 11 connected thereto. For example, as shown in fig. 4, the first data port IO1 is connected to the TSVs 1, TSV2 and TSV3 through the first switch unit S41, the first switch unit S42 and the first switch unit S43, respectively, and if the first data port IO1 is already conducted with the TSV1, that is, the first switch unit S41 is conducted, the first switch unit S42 and the first switch unit S43 connected to the TSVs 2 and TSV3 are controlled to be turned off.
Similarly, the second control circuit 30 is configured to control the on or off of each second switch unit 50 connected to each second data terminal 70; for each second data terminal 70, the second control circuit 30 is configured to control the second switch unit 50 corresponding to the electrical connection structure 11 with the first serial number and in the normal working state, in the unoccupied electrical connection structure 11 connected to the second control circuit, to be turned on. For example, as shown in fig. 4, the second data terminal IO1 'is connected to the TSVs 1, TSV2 and TSV3 through the second switching unit S51, the second switching unit S52 and the second switching unit S53, respectively, and if the second data terminal IO1' is already conducted with the TSV1, that is, the second switching unit S51 is conducted, the second switching unit S52 and the second switching unit S53 connected to the TSVs 2 and TSV3 are controlled to be turned off.
Illustratively, the specific switch control and conducting data terminals of the repair circuit of the electrical connection structure shown in fig. 4 are as follows:
when TSVs 1 to TSV4 are all normal (TSV 5 and TSV6 may be normal and may fail), the data end conduction condition is:
IO1-TSV1-IO1’、IO2-TSV2-IO2’、IO3-TSV3-IO3’、IO4-TSV4-IO4’；
TSV1 breaks down, and when other TSVs are normal, the data end conduction condition is as follows:
IO1-TSV2-IO1’、IO2-TSV3-IO2’、IO3-TSV4-IO3’、IO4-TSV5-IO4’；
TSV2 is failed, and when other TSVs are normal, the conduction condition of the data end is as follows:
IO1-TSV1-IO1’、IO2-TSV3-IO2’、IO3-TSV4-IO3’、IO4-TSV5-IO4’；
when TSV3 fails and other TSVs are normal, the data end conduction condition is:
IO1-TSV1-IO1’、IO2-TSV2-IO2’、IO3-TSV4-IO3’、IO4-TSV5-IO4’；
TSV4 is failed, and when other TSVs are normal, the conduction condition of the data end is as follows:
IO1-TSV1-IO1’、IO2-TSV2-IO2’、IO3-TSV3-IO3’、IO4-TSV5-IO4’；
when TSV1-2 fails and other TSVs are normal, the data end conduction condition is as follows:
IO1-TSV3-IO1’、IO2-TSV4-IO2’、IO3-TSV5-IO3’、IO4-TSV6-IO4’；
TSV1 and TSV3 are in fault, and when other TSVs are normal, the data end conduction condition is as follows:
IO1-TSV2-IO1’、IO2-TSV4-IO2’、IO3-TSV5-IO3’、IO4-TSV6-IO4’；
when TSVs 1 and 4 have faults and other TSVs are normal, the data end conduction condition is as follows:
IO1-TSV2-IO1’、IO2-TSV3-IO2’、IO3-TSV5-IO3’、IO4-TSV6-IO4’；
TSV1 and TSV5 are in fault, and when other TSVs are normal, the data end conduction condition is as follows:
IO1-TSV2-IO1’、IO2-TSV3-IO2’、IO3-TSV4-IO3’、IO4-TSV6-IO4’；
when TSVs 1 and 6 have faults and other TSVs are normal, the data end conduction condition is as follows:
IO1-TSV2-IO1’、IO2-TSV3-IO2’、IO3-TSV4-IO3’、IO4-TSV5-IO4’；
when TSV2 and TSV3 fail and other TSVs are normal, the data end conduction condition is:
IO1-TSV1-IO1’、IO2-TSV4-IO2’、IO3-TSV5-IO3’、IO4-TSV6-IO4’；
TSV2 and TSV4 are in fault, and when other TSVs are normal, the data end conduction condition is as follows:
IO1-TSV1-IO1’、IO2-TSV3-IO2’、IO3-TSV5-IO3’、IO4-TSV6-IO4’；
TSV2 and TSV5 are in fault, and when other TSVs are normal, the data end conduction condition is as follows:
IO1-TSV1-IO1’、IO2-TSV3-IO2’、IO3-TSV4-IO3’、IO4-TSV6-IO4’；
TSV2 and TSV6 are in fault, and when other TSVs are normal, the data end conduction condition is as follows:
IO1-TSV1-IO1’、IO2-TSV3-IO2’、IO3-TSV4-IO3’、IO4-TSV5-IO4’；
TSV3 and TSV4 are in fault, and when other TSVs are normal, the data end conduction condition is as follows:
IO1-TSV1-IO1’、IO2-TSV2-IO2’、IO3-TSV5-IO3’、IO4-TSV6-IO4’；
TSV3 and TSV5 are in fault, and when other TSVs are normal, the data end conduction condition is as follows:
IO1-TSV1-IO1’、IO2-TSV2-IO2’、IO3-TSV4-IO3’、IO4-TSV6-IO4’；
TSV3 and TSV6 are in fault, and when other TSVs are normal, the data end conduction condition is as follows:
IO1-TSV1-IO1’、IO2-TSV2-IO2’、IO3-TSV4-IO3’、IO4-TSV5-IO4’；
when TSV4 and TSV5 fail and other TSVs are normal, the data end conduction condition is:
IO1-TSV1-IO1’、IO2-TSV2-IO2’、IO3-TSV3-IO3’、IO4-TSV6-IO4’；
when TSV4 and TSV6 fail and other TSVs are normal, the data end conduction condition is as follows:
IO1-TSV1-IO1’、IO2-TSV2-IO2’、IO3-TSV3-IO3’、IO4-TSV5-IO4’。
through the circuit design, only two electrical connection structures 11 are added, so that each electrical connection structure 11 can correspond to two spare electrical connection structures 11 (each electrical connection structure 11 is in turn spare), so that each pair of data ends (the first data end and the corresponding second data end) has 3 available electrical connection structures 11 to realize data transmission, thereby further ensuring the reliability of signal transmission, and no excessive electrical connection structures 11 are additionally added, so that the simplicity of a repair circuit of the electrical connection structure is ensured.
In an exemplary embodiment of the present disclosure, as shown in fig. 3, the first control circuit 20 includes N discharge circuits 21 and N first detection circuits 22, first ends of the N first detection circuits 22 and the N discharge circuits 21 are respectively connected to first ends of the N electrical connection structures 11 in a one-to-one correspondence manner, and a second end of each first detection circuit 22 is connected to each first switch unit 40 of the corresponding electrical connection structure 11. With continued reference to fig. 3, the second control circuit 30 includes N charging circuits 31 and N second detection circuits 32, first ends of the N second detection circuits 32 and the N charging circuits 31 are respectively connected to second ends of the N electrical connection structures 11, and a second end of each second detection circuit 32 is connected to a corresponding second switch unit 50 of the electrical connection structure 11.
Wherein the discharging circuit 21 is used for discharging the electrical connection structure 11, and the charging circuit 31 is used for charging the electrical connection structure 11. The first detection circuit 22 is configured to generate a first control signal according to a voltage level change at a first end of the connected electrical connection structure 11, where the first control signal is output from a second end of the first detection circuit 22 and is used to control on or off of each first switch unit 40 of the corresponding electrical connection structure 11. That is, after the discharge circuit 21 and the charge circuit 31 complete charging and discharging of the electrical connection structure 11, if the voltage on the left side of the electrical connection structure 11 changes, it indicates that the electrical connection structure 11 is normal, and if the voltage on the left side of the electrical connection structure 11 does not change, it indicates that the electrical connection structure 11 has a fault, such as a short circuit or an open circuit.
The second detection circuit 32 is configured to generate a second control signal according to a voltage level change of the second end of the connected electrical connection structure 11, where the second control signal is output by the second end of the second detection circuit 32 and is used to control the on/off of each second switch unit 50 of the corresponding electrical connection structure 11. That is, after the discharge circuit 21 and the charge circuit 31 complete charging and discharging of the electrical connection structure 11, if the voltage on the right side of the electrical connection structure 11 changes, it indicates that the electrical connection structure 11 is normal, and if the voltage on the right side of the electrical connection structure 11 does not change, it indicates that the electrical connection structure 11 has a fault, such as a short circuit or an open circuit.
In an exemplary embodiment of the present disclosure, the first control circuit 20 further includes a first sub-control unit 80 connected to each first switch unit 40 in a one-to-one correspondence, and the first sub-control unit 80 is configured to control on and off of the first switch unit 40 connected thereto. The second control circuit 30 further includes second sub-control units 90 connected to the second switch units 50 in a one-to-one correspondence manner, and the second sub-control units 90 are configured to control on and off of the second switch units 40 connected thereto.
Illustratively, a plurality of electrical connection structures 11 are disposed between two semiconductor chips, each electrical connection structure 11 is correspondingly provided with one discharge circuit 21 and one first detection circuit 22 in one of the semiconductor chips, and is correspondingly provided with one charge circuit 31 and one second detection circuit 32 in the other semiconductor chip, the corresponding electrical connection structure 11 is charged and discharged through the discharge circuit 21 and the charge circuit 31, and each first detection circuit 22 and each second detection circuit 32 respectively detect voltage changes at two ends of the corresponding electrical connection structure 11 and control each first sub-control unit 80 and each second sub-control unit 90 to further control on and off of each first switch unit 40 and each second switch unit 50.
Wherein, each first data terminal 60 corresponds to R first control units 80.
For the 1 st first data end, the corresponding first control units 80 are set as follows:
the 1 st first sub-control unit 80 corresponding to the 1 st first data terminal 60 is configured to control the 1 st first switch unit 40 connected thereto to be turned on or off according to the first control signal of the 1 st first detection circuit 22. For example, as shown in fig. 3, the 1 st first control unit 80 corresponding to the first data terminal IO1 is a first node a, the first node a is connected to the output terminal of the first detection circuit 22 and the control terminal of the first switch unit S41, and the first node a may also be replaced by a buffer circuit, an and gate, and the like, which is not limited herein.
Mth corresponding to 1 st first data terminal 1 A first control unit 80 for controlling the first control unit according to the m 1 A first control signal of the first detection circuit 22 and the (m) th control signal corresponding thereto 1 -1) output signals of the first control units 80 controlling the on or off of the first switching units 40 connected thereto. Illustratively, as shown in fig. 3, the 2 nd first control unit 80 corresponding to the first data terminal IO1 is a first control unit C1, an input terminal of the first control unit C1 is connected to the first node a and the first detection circuit 22 of the current stage (connected to the TSV 2), and an output terminal of the first control unit C1 is connected to the control terminal of the first switching unit S42.
For the m-th 2 Each first data terminal, corresponding to each first control unit 80, is configured as follows:
m th 2 A 1 st first control unit 80 corresponding to the first data terminal 60 and used for controlling the first data terminal according to the m 2 A first control signal of the first detection circuit 22 and an (m) th control signal 2 -1) the output signal of the 1 st first control unit 80 corresponding to the first data terminal 60 controls the 1 st first switch unit 40 connected thereto to be turned on or off. For example, as shown in fig. 3, the 1 st first control unit 80 corresponding to the first data terminal IO2 is a first control unit C2, an input terminal of the first control unit C2 is connected to the first detection circuit 22 of the current stage (connected to the TSV 2) and the first node a, and an output terminal of the first control unit C2 is connected to the first switch unit S44.
M th 2 M-th data terminal 60 1 A first control unit 80 for controlling the first control unit according to the (m) th 2 +m 1 -1) first control signal of first detection circuit 22, (m) th control signal corresponding thereto 1 -1) the output signal of the first control unit 80 and 2 -1) th (m) corresponding to the first data terminal 60 1 -1) the output signal of the first control unit 80, controlling the switching on or off of the first switching unit 40 connected thereto. For example, as shown in fig. 3, the 2 nd first control unit 80 corresponding to the first data terminal IO2 is a first control unit C4, an input terminal of the first control unit C4 is connected to the first detection circuit 22, the first control unit C2 and the first control unit C1 of the current stage (connected to the TSV 3), and an output terminal of the first control unit C4 is connected to the first switch unit S45.
Similarly, each second data terminal 70 corresponds to R second sub-control units 90.
For the 1 st second data terminal, each corresponding second sub-control unit 90 is set as follows:
the 1 st second sub-control unit 90 corresponding to the 1 st second data terminal 70 is configured to control the second switch unit 50 connected thereto to be turned on or off according to the second control signal of the 1 st second detection circuit 32. For example, as shown in fig. 3, the 1 st second sub-control unit 90 corresponding to the second data terminal IO1' is a second node B, the second node B is connected to the output terminal of the second detection circuit 32 and the control terminal of the second switch unit S51, and the second node B may also be replaced by a buffer circuit, an and gate, and the like, which is not limited herein.
Mth data terminal corresponding to the 1 st second data terminal 70 1 A second sub-control unit 90 for controlling the sub-control unit according to the m 1 A second control signal of the second detection circuit 32 and an (m) th signal 1 -1) output signals of the second sub-control units 90, controlling the second switching units 50 connected thereto to be turned on or off. Illustratively, as shown in fig. 3, the 2 nd second control unit 90 corresponding to the second data terminal IO1 'is a second control unit C1', an input terminal of the second control unit C1 'is connected to the second node B and the second detection circuit 32 of the current stage (connected to the TSV 2), and an output terminal of the second control unit C1' is connected to the control terminal of the second switch unit S52.
For the m-th 2 Each second data terminal, corresponding to each second sub-control unit 90, is configured as follows:
m th 2 A 1 st second sub-control unit 90 corresponding to the second data terminal 70 and used for controlling the first data terminal according to the m 2 A second control signal of the second detection circuit 32 and an (m) th signal 2 -1) the output signal of the 1 st second sub-control unit 90 corresponding to the second data terminal 70, controlling the second switch unit 50 connected thereto to be turned on or off. For example, as shown in fig. 3, the 1 st second control unit 90 corresponding to the second data terminal IO2 'is a second control unit C2', the input terminal of the second control unit C2 'is connected to the second detection circuit 32 and the second node B of the current stage (connected to the TSV 2), and the output terminal of the second control unit C2' is connected to the second switch unit S54.
M th 2 M-th data terminal 70 1 A second sub-control unit 90 for controlling the second sub-control unit according to the (m) th 2 +m 1 -1) second control signal of second detection circuit 32, (m) th 1 -1) the output signal of the second partial control unit 90 and the (m) th 2 -1) th (m) of second data terminal 70 1 -1) output signals of the second sub-control units 90, controlling the second switching units 50 connected thereto to be turned on or off. Wherein，m 1 Is greater than or equal to 2 and less than or equal to n 1 Positive integer of (1), m 2 A positive integer greater than or equal to 2 and less than or equal to M. For example, as shown in fig. 3, the 2 nd second control unit 80 corresponding to the second data terminal IO2 'is a second control unit C4', an input terminal of the second control unit C4 'is connected to the second detection circuit 32 of the current stage (connected to the TSV 3), the second control unit C2', and the second control unit C1', and an output terminal of the second control unit C4' is connected to the second switch unit S55.
The first and second sub-control units 80 and 90 may use logic circuits such as and gates or gates to control the first and second switch units 40 and 50. Illustratively, for the 1 st first data terminal, the 1 st first control unit 80 corresponding to the 1 st first data terminal includes a first node, an input end of the first node is connected to an output end of the 1 st first detection circuit 22, and an output end of the first node serves as a control end of the corresponding first switch unit 40. For example, as shown in fig. 3, the 1 st first control unit 80 includes a first node a.
When m is 1 When the value is less than R, the mth data terminal corresponding to the 1 st first data terminal 60 1 The first control units 80 comprise a first and gate and a first or gate, wherein the input end of the first and gate is respectively connected with the inverted signal of the output end of the first node and the mth 1 The output terminal of the first detection circuit 22, the output terminal of the first and gate are connected to the control terminal of the corresponding first switch unit 40, the input terminal of the first or gate is connected to the output terminal of the first node and the output terminal of the first and gate, respectively, and the output terminal of the first or gate is used as the mth node 1 An output of the first control unit 80. Exemplarily, as shown in fig. 3, the mth data terminal IO1 corresponds to the 1 st first data terminal IO1 1 The first control unit 80 includes a first control unit C1. As shown in fig. 4, the mth data terminal corresponding to the 1 st first data terminal IO1 1 The first control unit 80 includes a first control unit C6.
The R-th first sub-control unit 80 corresponding to the 1 st first data end 60 includes a second and gate and a second or gate, an input end of the second and gate is connected to the inverted signal of the output end of the first or gate and the output end of the R-th first detection circuit 22, an output end of the second and gate is connected to the control end of the corresponding first switch unit 40, an input end of the second or gate is connected to the output end of the first or gate and the output end of the second and gate, an output end of the second or gate is used as the output end of the R-th first sub-control unit 80 corresponding to the 1 st first data end 60, and is connected to the R-th first sub-control unit 80 corresponding to the 2 nd first data end 60. As shown in fig. 3, the R-th first sub-control unit 80 corresponding to the 1 st first data terminal 60 includes a first sub-control unit C3, and as shown in fig. 4, the R-th first sub-control unit 80 corresponding to the 1 st first data terminal 60 includes a first sub-control unit C8.
When m is 2 Less than M, for the M-th 2 A first data terminal 60, m 2 The 1 st first control unit 80 corresponding to the first data terminal 60 includes a third and gate, and the input terminals of the third and gate are respectively connected to the mth gate 2 An output terminal of the first detection circuit 22 and (m) th 2 -1) the output of the 1 st first control unit 80 corresponding to the first data terminal 60, the output of the third and gate being the mth 2 The output end of the 1 st first sub-control unit 80 corresponding to each first data end 60 is respectively connected to the control end of the corresponding first switch unit 40 and the corresponding 2 nd first sub-control unit 80. As shown in FIG. 4, m 2 The 1 st first sub-control unit 80 corresponding to the first data terminal 60 includes first sub-control units C7 and C10.
When m is 1 When less than R, m 2 M-th data terminal 60 1 The first control unit 80 comprises a fourth AND gate and a third OR gate, and the input ends of the fourth AND gate are respectively connected with the (m) th 2 +m 1 -1) output of the first detection circuit 22, the corresponding (m) th 1 -1) the inverted signal at the output of the first control unit 80 and the (m) th signal 2 -1) mth corresponding to first data terminal 60 1 The output end of the first control unit 80 and the output end of the fourth and gate are respectively connected with the control end of the corresponding first switch unit 40 and the third or gate, the input ends of the third OR gates are respectively connected with the corresponding (m) th 1 -1) the output of the first control unit 80, and the output of the fourth and-gate, the output of the third or-gate being the m-th 2 M-th data terminal 60 1 The output end of the first sub-control unit 80 is connected with the corresponding m-th 1 +1 first branch control units 80. As shown in FIG. 4, m 2 M-th data terminal 60 1 Each first controlling unit 80 comprises a first controlling unit C9 and a first controlling unit C12.
M th 2 The R-th first control unit 80 corresponding to the first data terminal 60 includes a fifth and gate and a fourth or gate, and the input terminals of the fifth and gate are respectively connected to the (R + m) -th gate 1 -1) the inverted signal of the output of the first detection circuit 22, the corresponding output of the R-1 th first control unit 80, and the (m) th 2 -1) the output of the R-th first sub-control unit 80 of the first data terminals 60, the output of the fifth AND-gate being connected to the control terminal of the corresponding first switching unit 40 and the fourth OR-gate, respectively, the input of the fourth OR-gate being connected to the output of the R-1-th first sub-control unit 80 and the output of the fifth AND-gate, the output of the fourth OR-gate being taken as the m-th 2 The output terminal of the Rth first control unit 80 corresponding to the first data terminal 60 is connected to the mth control unit 2 The R-th first demultiplexing unit 80 of the +1 first data terminal 60. As shown in FIG. 4, m 2 The R-th first sub-control unit 80 corresponding to the first data terminal 60 includes a first sub-control unit C11 and a first sub-control unit C14.
For the mth first data end 60, the 1 st first sub-control unit 80 corresponding to the mth first data end 60 includes a sixth and gate, an input end of the sixth and gate is respectively connected to an output end of the mth first detection circuit 22 and the 1 st first sub-control unit 80 corresponding to the (M-1) th first data end 60, and an output end of the sixth and gate is used as an output end of the 1 st first sub-control unit 80 corresponding to the mth first data end 60 and is respectively connected to a control end of the corresponding first switch unit 40 and the corresponding 2 nd first sub-control unit 80. As shown in fig. 3, the 1 st first sub-control unit 80 corresponding to the mth first data port 60 includes a first sub-control unit C2. As shown in fig. 4, the 1 st first sub-control unit 80 corresponding to the mth first data terminal 60 includes a first sub-control unit C13.
When m is 1 When the value is smaller than R, the Mth first data terminal 60 corresponds toM th 1 The first control units 80 comprise a seventh AND gate and a fifth OR gate, and the input ends of the seventh AND gate are respectively connected with the (M + M) th 1 -1) output of the first detection circuit 22, the corresponding (m) th 1 -1) inverted signal at the output of the first control unit 80 and the mth signal corresponding to the (M-1) th first data terminal 60 1 The output ends of the first branch control unit 80 and the seventh and gate are respectively connected with the control end of the corresponding first switch unit 40 and the fifth or gate, the input end of the fifth or gate is respectively connected with the corresponding (m) th 1 -1) the output of the first control unit 80, and the output of the seventh and gate, the output of the fifth or gate being the mth gate corresponding to the mth first data terminal 60 1 The output end of the first sub-control unit 80 is connected with the corresponding m-th 1 +1 first control units 80. As shown in FIG. 3, the mth first data terminal 60 corresponds to the mth 1 The first sub-control units 80 include a first sub-control unit C4, as shown in FIG. 4, the mth first data terminal 60 corresponds to the mth 1 The first control unit 80 includes a first control unit C15.
The R-th first sub-control unit 80 corresponding to the M-th first data terminal 60 includes an eighth and gate, an input end of the eighth and gate is connected to an output end of the (R + M-1) -th first detection circuit 22, an inverted signal of an output end of the corresponding R-1-th first sub-control unit 80, and an output end of the R-th first sub-control unit 80 of the M-1-th first data terminal 60, respectively, and an output end of the eighth and gate is connected to a control terminal of the corresponding first switch unit 40. As shown in fig. 3, the R-th first sub-control unit 80 corresponding to the M-th first data terminal 60 includes a first sub-control unit C5, and as shown in fig. 4, the R-th first sub-control unit 80 corresponding to the M-th first data terminal 60 includes a first sub-control unit C16.
For each second data terminal 70, R second sub-control units 90 corresponding to the second data terminal 70 have the same structure as R first sub-control units 80 corresponding to the first data terminal 60 corresponding to the second data terminal 70, and are not described herein again.
In an exemplary embodiment of the present disclosure, when the mth first data terminal 60 is conducted with the mth second data terminal 70 through the nth ' electrical connection structure 11, if N ' is less than N, the first switch unit 40 and the second switch unit 50 connected to each other are respectively turned off through the respective first sub-control units 80 and the respective second sub-control units 90 corresponding to the nth ' +1 to nth electrical connection structure 11. That is, when the number of the normal electrical connection structures 11 exceeds the number of the first data terminals 60 and the second data terminals 70 that need to perform data transmission, the first sub-control unit may close the first switch unit 40 corresponding to the electrical connection structure 11 that is normal and does not need to be used, and the second sub-control unit may close the second switch unit 50 corresponding to the electrical connection structure 11 that is normal and does not need to be used, so as to release the extra normal electrical connection structures 11 for transmission of other signals. For example, as shown in fig. 4, if 4 first data terminals IO1/IO2/IO3/IO4 are respectively conducted with 4 second data terminals IO1'/IO2'/IO3'/IO4' through the first 4 electrical connection structures TSV1/TSV2/TSV3/TSV4, the first switch units 40 connected to each of the first control units corresponding to the 5 th and 6 th electrical connection structures TSV5 and TSV6 are turned off, and the second switch units 50 connected to each of the second control units corresponding to the 5 th and 6 th electrical connection structures TSV5 and TSV6 are turned off.
The specific structure of the first sub-control unit 80 and the second sub-control unit 90 will be described in detail with reference to fig. 3 and 4. As shown in fig. 3, for the TSV2, the first control unit C1 corresponding to the first data terminal IO1 includes an and gate andsg 1 and an or gate ORG1, an input terminal of the and gate andsg 1 is connected to an inverse direction of an output terminal of the first detection circuit 22 corresponding to the TSV1, and an output terminal of the first detection circuit 22 corresponding to the TSV2 is connected to a control terminal of the first switch unit 40. The input terminal of the or gate ORG1 is connected to the output terminal of the first detection circuit 22 corresponding to the TSV1 and the output terminal of the and gate andsg 1. The first sub-control unit C2 corresponding to the first data end IO2 includes an and gate andsg 2, an input end of the and gate andsg 2 is connected to an output end of the first detection circuit 22 corresponding to the TSV1, and an output end of the first detection circuit 22 corresponding to the TSV 2. The structures of the second sub-control unit C1 'corresponding to the second data end IO1' and the second sub-control unit C2 'corresponding to the second data end IO2' are similar to the first sub-control units C1 and C2, respectively, and are not described herein again.
With continued reference to fig. 3, for the TSV3, the first control unit C3 corresponding to the first data terminal IO1 includes an and gate ang 3 and an or gate ORG2, wherein an input of the and gate ang 3 is connected to an inverse of an output of the or gate ORG1, and an output of the first detection circuit 22 corresponding to the TSV3, an output of the and gate ang 3 is connected to a control terminal of the first switching unit 40, an input of the or gate ORG2 is connected to an output of the or gate ORG1 and an output of the and gate ang 3, the first control unit C4 corresponding to the first data terminal IO2 includes an and gate ang 4 and an or gate ORG3, wherein an input of the and gate ang 4 is connected to an output of the or gate ORG1, an inverse of an output of the and gate ang 2 and an output of the first detection circuit 22 corresponding to the and gate 3, an output of the and gate ang 4 is connected to a control terminal of the first switching unit 40, or an input of the gate ORG3 is connected to an output of the and gate ang 4 and an output of the and gate ORG 2. The structures of the second sub-control unit C3 'corresponding to the second data end IO1' and the second sub-control unit C4 'corresponding to the second data end IO2' are similar to the first sub-control units C3 and C4, respectively, and are not described herein again.
For the TSV4, the first sub-control unit C5 corresponding to the first data port IO2 includes an and gate andsg 5, an input of the and gate andsg 5 is connected to an output of the or gate ORG2, an inverse of an output of the or gate ORG3 and an output of the first detection circuit 22 corresponding to the TSV4, and an output of the and gate andsg 5 is connected to a control port of the first switch unit 40. The structures of the second sub-control unit C5 'corresponding to the second data terminal IO2' are similar to those of the first sub-control unit C5, and are not described herein again.
In another embodiment, as shown in fig. 4, for the TSV2, the first sub-control unit C6 corresponding to the first data port IO1 includes an and gate andsg 6 and an or gate ORG4, an input of the and gate andsg 6 is connected to an inverse direction of an output terminal of the first detection circuit 22 corresponding to the TSV1 and an output terminal of the first detection circuit corresponding to the TSV2, an output of the and gate andsg 6 is connected to a control terminal of the first switch unit 40, and an input of the or gate ORG4 is connected to an output terminal of the and gate andsg 6 and an output terminal of the first detection circuit 22 corresponding to the TSV 1. The first sub-control unit C7 corresponding to the first data end IO2 includes an and gate andsg 7, an input of the and gate andsg 7 is connected to an output end of the first detection circuit 22 corresponding to the TSV1 and an output end of the first detection circuit 22 corresponding to the TSV2, and an output of the and gate andsg 7 is connected to a control end of the first switch unit 40. The structures of the second sub-control unit C6 'corresponding to the second data end IO1' and the second sub-control unit C7 'corresponding to the second data end IO2' are similar to the first sub-control units C6 and C7, respectively, and are not described herein again.
For the TSV3, the first branch control unit C8 corresponding to the first data terminal IO1 includes an and gate andsg 8 and an or gate ORG5, an input of the and gate andsg 8 is connected to an inverse direction of an output of the or gate ORG4, and an output of the first detection circuit 22 corresponding to the TSV3, and an output of the and gate andsg 8 is connected to a control terminal of the first switch unit 40. The input of or gate ORG5 is connected to the output of and gate andsg 8 and to the output of or gate ORG 4. The first sub-control unit C9 corresponding to the first data terminal IO2 includes an and gate andsg 9 and an or gate ORG6, an input of the and gate andsg 9 is connected to an output terminal of the or gate ORG4, an inverse of an output terminal of the and gate andsg 7 and an output terminal of the first detection circuit 22 corresponding to the TSV3, an output terminal of the and gate andsg 9 is connected to a control terminal of the first switch unit 40, and an input of the or gate ORG6 is connected to an output terminal of the and gate andsg 9 and an output terminal of the and gate andsg 7. The first sub-control unit C10 corresponding to the first data end IO3 includes an and gate andsg 10, an input of the and gate andsg 10 is connected to an output end of the and gate andsg 7 and an output end of the first detection circuit 22 corresponding to the TSV3, and an output of the and gate andsg 10 is connected to a control end of the first switch unit 40. The structures of the second sub-control unit C8 'corresponding to the second data end IO1', the second sub-control unit C9 'corresponding to the second data end IO2', and the second sub-control unit C10 'corresponding to the second data end IO3' are similar to the first sub-control units C8, 9, and 10, respectively, and are not described herein again.
For the TSV4, the first branch control unit C11 corresponding to the first data terminal IO2 includes an and gate andsg 11 and an or gate ORG7, an input of the and gate andsg 11 is connected to an output of the or gate ORG5, an inverse of an output of the or gate ORG6, and an output of the first detection circuit 22 corresponding to the TSV4, and an output of the and gate andsg 11 is connected to a control terminal of the first switch unit 40. The input of the or gate ORG7 is connected to the output of the and gate andsg 11 and to the output of the or gate ORG 6. The first sub-control unit C12 corresponding to the first data terminal IO3 includes an and gate andsg 12 and an or gate ORG8, an input of the and gate andsg 12 is connected to an output of the or gate ORG6, an inverse of an output of the and gate andsg 10 and an output of the first detection circuit 22 corresponding to the TSV4, and an output of the and gate andsg 12 is connected to a control terminal of the first switch unit 40. The input of the or gate ORG8 is connected to the output of the and gate andsg 12 and to the output of the and gate andsg 10. The first branch control unit C13 corresponding to the first data terminal IO4 includes an and gate andsg 13, an input of the and gate andsg 13 is connected to an output terminal of the and gate andsg 10 and an output terminal of the first detection circuit 22 corresponding to the TSV4, and an output of the and gate andsg 13 is connected to a control terminal of the first switch unit 40. The structures of the second sub-control unit C11 'corresponding to the second data end IO2', the second sub-control unit C12 'corresponding to the second data end IO3', and the second sub-control unit C13 'corresponding to the second data end IO4' are similar to the first sub-control units C11, C12, and C13, respectively, and are not described again here.
For the TSV5, the first branch control unit C14 corresponding to the first data terminal IO3 includes an and gate andsg 14 and an or gate ORG9, an input of the and gate andsg 14 is connected to an output terminal of the or gate ORG7, an inverse of an output terminal of the or gate ORG8, and an output terminal of the first detection circuit corresponding to the TSV5, and an output of the and gate andsg 14 is connected to a control terminal of the first switch unit 40. The input of or gate ORG9 is connected to the output of and gate andsg 14 and to the output of or gate ORG 8. The first branch control unit C15 corresponding to the first data terminal IO4 includes an and gate andsg 15 and an or gate ORG10, an input of the and gate andsg 15 is connected to an output terminal of the or gate ORG8, an inverse of an output terminal of the and gate andsg 13 and an output terminal of the first detection circuit 22 corresponding to the TSV5, an output of the and gate andsg 15 is connected to a control terminal of the first switch unit 40, and an input of the or gate ORG10 is connected to an output terminal of the and gate andsg 15 and an output terminal of the and gate andsg 13. The structures of the second sub-control unit C14 'corresponding to the second data end IO3' and the second sub-control unit C15 'corresponding to the second data end IO4' are similar to the first sub-control units C14 and C15, respectively, and are not described herein again.
For the TSV6, the first control unit C16 corresponding to the first data terminal IO4 includes an and gate andsg 16, an input of the and gate andsg 16 is connected to an output terminal of the or gate ORG9, an inverse of an output terminal of the or gate ORG10 and an output terminal of the first detection circuit 22 corresponding to the TSV6, and an output of the and gate andsg 16 is connected to a control terminal of the first switch unit 40.
Illustratively, the first switch unit 40 is configured to be turned on in response to a high level signal output by the corresponding first control unit 80 and turned off when a low level signal is received, for example, the first switch unit 40 is a CMOS transmission gate, and if a low level is output to the first switch unit 40, the first switch unit 40 is turned off, and if a high level is output to the first switch unit 40, the first switch unit 40 is turned on. In other embodiments, the first switch unit 40 may also be configured to be turned on when the control terminal receives a low level and turned off when the control terminal receives a high level, which is not limited by the present disclosure. The second switching unit 50 is provided similarly to the first switching unit 40, and is not described in detail herein.
In some embodiments, as shown in fig. 5, the first flip-flop 221 may be used to output the first control signal, for example, the first flip-flop 221 is a rising edge flip-flop, and when the voltage of the first side of the electrical connection structure 11 changes during charging and discharging, a rising edge signal is generated at a clock end of the first flip-flop 221, so that the first flip-flop 221 outputs the first control signal with a high level. Illustratively, as shown in fig. 5, the first detection circuit 22 includes a first flip-flop 221 and a first inverter 222, an input end D of the first flip-flop 221 is connected to the power supply VDD, an input end of the first inverter 222 serves as a first end of the first detection circuit 22 and is connected to a first end of the corresponding electrical connection structure 11, an output end of the first inverter 222 is connected to a clock input end Clk of the first flip-flop 221, and an output end of the first flip-flop 221 serves as a second end of the first detection circuit 22 and is connected to each first switch unit 40. In the 1 st electrical connection structure, the output terminal Q of the first flip-flop 221 is connected to the control terminal of the first switching unit 40 at the n-th 1 In the electrical connection structure, the output terminal of the first flip-flop 221 is connected to each of the first branch control units 80. When the electrical connection structure 11 is charged, the first terminal thereof is at a high level, and a low level is formed at the clock input terminal Clk of the first flip-flop 221 after passing through the first inverter 222. And when the electrical connection structure 11 is discharged, the first terminal thereof is changed from a high level to a low level,after passing through the first inverter 222, a high level is formed at the clock input Clk of the first flip-flop 221, so that a rising edge signal is detected at the clock input Clk of the first flip-flop 221 and the output Q of the first flip-flop 221 outputs a high level. Of course, in other embodiments, the first flip-flop 221 may also be other types of flip-flops such as a falling edge flip-flop, which is not limited by the present disclosure.
Similarly, as shown in fig. 5, the second detection circuit 32 includes a second flip-flop 321 and a second inverter 322, an input terminal of the second inverter 322 is connected to the second terminal of the corresponding electrical connection structure 11 as a first terminal of the second detection circuit 32, an output terminal of the second inverter 322 is connected to a clock input terminal of the second flip-flop 321, an output terminal of the second flip-flop 321 is connected to each second switch unit 50 and each second sub-control unit 90 as a second terminal of the second detection circuit 32, and in the 1 st electrical connection structure, the output terminal of the second flip-flop is connected to a control terminal of the second switch unit 50, and in the nth electrical connection structure, the output terminal of the second flip-flop is connected to a control terminal of the second switch unit 50 2 In the electrical connection structure, the output terminal of the second flip-flop 321 is connected to each second sub-control unit. The working process of the second flip-flop 321 is similar to that of the first flip-flop 221, and specific reference is made to the foregoing description on the first flip-flop 221, which is not repeated herein.
In an exemplary embodiment of the present disclosure, as shown in fig. 5, the first detection circuit 22 includes a first transistor 223, an input terminal of the first inverter 222 is connected to a first pole of the first transistor 223, a second pole of the first transistor 223 is grounded, and a gate of the first transistor 223 is connected to an inverted signal of the electrical signal. The first transistor 223 is configured to turn on its first pole and second pole when its gate receives a high level, and to turn off its first pole and second pole when its gate receives a low level. Because the gate of the first transistor 223 is connected with the inverse signal of the electrical signal, when the power is not turned on, the gate of the first transistor 223 inputs a high level, so that the first pole and the second pole of the first transistor 223 are turned on, thus, the input end of the first inverter 222 is grounded, the clock input end Clk output by the first inverter 222 to the first flip-flop 221 is a high level, that is, the clock input end Clk of the first flip-flop 221 is set to "1", thereby ensuring that before the power is turned on, the clock input end Clk of the first flip-flop 221 does not generate a rising edge, that is, a high level is not output, and further ensuring the reliability of the repair circuit of the electrical connection structure.
In one embodiment, as shown in fig. 5, the first detection circuit 22 further includes a third inverter 224 connected end to end with the first transistor 223, that is, an input terminal of the third inverter 224 is connected to an output terminal of the first inverter 222, and an output terminal of the third inverter 224 is connected to an input terminal of the first inverter 222, which both form a latch to ensure the reliability of the signal inputted to the clock input Clk of the first flip-flop 221.
Similarly, as shown in fig. 5, the second detection circuit 32 includes a second transistor 323, an input terminal of the second inverter 322 is connected to a first pole of the second transistor 323, a second pole of the second transistor 323 is grounded, and a gate of the second transistor 323 is connected to an inverted signal of the electrical signal. The second transistor 323 and the first transistor 223 function similarly, and it is understood that the second detection circuit 32 may also include a fourth inverter 324 connected end to end with the second transistor 323, which is specifically referred to the foregoing description about the first transistor 223 and is not described again here.
In an exemplary embodiment of the present disclosure, as shown in fig. 5, the reset terminal RN of the first flip-flop 221 is connected to a reverse signal of the electrical signal, and the first flip-flop 221 is configured to reset the output terminal Q when the reset terminal RN does not receive the power-on signal. When the first detection circuit 22 determines that the electrical connection structure 11 is normal, a high level is output, and when power is off, the reset terminal of the first flip-flop 221 does not receive a power-on signal any more, at this time, the output terminal Q of the first flip-flop 221 is reset, that is, the output terminal Q of the first flip-flop 221 outputs a low level, so as to control each corresponding first switch unit 40 to be turned off, thereby ensuring validity in next power-on detection.
Similarly, as shown in fig. 5, the reset terminal of the second flip-flop 321 is connected to the inverse signal of the upper electrical signal, and the second flip-flop 321 is configured to reset the output terminal thereof when the reset terminal thereof does not receive the upper electrical signal, so as to control each corresponding second switch unit 50 to be turned off. The operation of the reset terminal of the second flip-flop 321 is similar to that of the reset terminal of the first flip-flop 221, and specific reference is made to the foregoing description, which is not repeated herein.
In an exemplary embodiment of the present disclosure, as shown in fig. 5, the charging circuit 31 includes a pull-up driver for pulling up the electrical connection structure 11 to the first voltage level according to the charging driving signal PDRV. Illustratively, the pull-up driver includes a fourth transistor 311, a gate of the fourth transistor 311 is connected to the charge driving signal PDRV, a first pole of the fourth transistor 311 is connected to the power supply, and a second pole of the fourth transistor 211 is connected to the second end of the electrical connection structure 11. The fourth transistor 311 is configured such that the first and second poles thereof are turned off when the gate thereof is inputted with a high level and the first and second poles thereof are turned on when the gate thereof is inputted with a low level.
As shown in fig. 5, the discharge circuit 21 includes a pull-down driver for pulling down the electrical connection structure 11 to the second voltage level according to the discharge driving signal NDRV. Illustratively, the pull-down driver includes a third transistor 211, a gate of the third transistor 211 is connected to the discharge driving signal NDRV, a first pole of the third transistor 211 is grounded, and a second pole of the third transistor 211 is connected to the first end of the electrical connection structure 1. The third transistor 211 is configured such that the first and second electrodes thereof are turned on when the gate thereof is inputted with a high level and are turned off when the gate thereof is inputted with a low level.
The specific operation of the first detection circuit 22 will be described with reference to the timing chart shown in fig. 6, as shown in fig. 6, before the point a (Power-up), the Power-up signal Power on is at a low level, the reset terminal RN of the first flip-flop 221 is at a high level, and the output of the first flip-flop 221 is "0". While the reverse of the power-up signal
Figure BDA0003731485020000191
At a high level, therefore, the first transistor 223 is turned on, so that the input terminal of the first inverter 222 is grounded, and the first inverter 222 outputs a high level to the clock input terminal Clk of the first flip-flop 221, so that the clock input terminal Clk is set to "1". After Power-up (after point a), the Power-up signal Power on is high, the reset terminal RN of the first flip-flop 221 is low, and the first transistor 223 is turned off.When the charge driving signal PDRV outputs a low level (i.e., point B), the fourth transistor 311 is turned on to charge the electrical connection structure 11, and at the same time, the input terminal of the first inverter 222 is at a high level, and the first inverter 222 outputs a low level to the clock input terminal Clk of the first flip-flop 221, so that the clock input terminal Clk is set to "0". At point C, the charge driving signal PDRV output changes from a low level to a high level, so that the fourth transistor 311 is turned off. When the discharging driving signal NDRV outputs a high level (i.e., point D), the third transistor 211 is turned on to discharge the electrical connection structure 11, the input terminal of the first inverter 222 changes to a low level, the output of the first inverter 22 to the clock input Clk of the first flip-flop 221 changes from the low level to the high level, so that a rising edge is generated at the clock input Clk, and the first flip-flop 221 outputs a high level (TSV on). The operation of the second detection circuit 32 is similar to that of the first detection circuit 22, and is not described in detail herein.
An exemplary embodiment of the present disclosure also provides a control method of a repair circuit of an electrical connection structure, which is applicable to control of the repair circuit of the electrical connection structure, as shown in fig. 7, the control method includes:
s100, detecting voltage changes of a first end and a second end of each electric connection structure;
and S200, controlling the electric connection structures to be connected with or disconnected from the corresponding first data ends according to the voltage change of the first ends of the electric connection structures, controlling the electric connection structures to be connected with or disconnected from the corresponding second data ends according to the voltage change of the second ends of the electric connection structures, so that the electric connection structures are alternatively connected with or disconnected from the first data ends, and the electric connection structures are alternatively connected with or disconnected from the second data ends.
When two ends of the electric connection structure are respectively conducted with a first data end and a second data end, the data signal is controlled to be transmitted from the conducted first data end to the second data end, or the data signal is controlled to be transmitted from the conducted second data end to the first data end.
In this embodiment, the electrical connection structure can be controlled to be connected or disconnected with the first data terminal and the second data terminal respectively according to voltage changes at two ends of the electrical connection structure, so that after the electrical connection structure is connected, a data signal can be transmitted from the first data terminal to the second data terminal and from the second data terminal to the first data terminal, thereby realizing bidirectional data transmission, improving the performance of an electrical device, such as a semiconductor device, of a repair circuit adopting the electrical connection structure. In addition, the electric connection structure is alternatively conducted with the first data end and alternatively conducted with the second data end, so that mutual standby among the electric connection structures is realized, and the independence among data transmission paths is ensured.
In one embodiment, detecting a voltage change at the first end and the second end of each of the electrical connection structures comprises:
setting, by a charging circuit, a first end and a second end of an electrical connection structure to a first voltage level;
the first and second terminals of the electrical connection structure are set to a second voltage level by the discharge circuit.
The method for controlling the electric connection structure to be connected or disconnected with the corresponding first data end according to the voltage change of the first end of each electric connection structure, and controlling the electric connection structure to be connected or disconnected with the corresponding second data end according to the voltage change of the second end of each electric connection structure comprises the following steps:
responding to the voltage of the first end of the electric connection structure changing from a first voltage level to a second voltage level, and controlling the electric connection structure to be alternatively conducted with the first data end through the first detection circuit;
and responding to the voltage of the second end of the electric connection structure changing from the first voltage level to the second voltage level, and controlling the electric connection structure to be alternatively conducted with the second data end through the second detection circuit.
In this embodiment, the process of charging and discharging the electrical connection structure through the charging circuit and the discharging circuit, and controlling the electrical connection structure to be alternatively conducted with the first data terminal through the first detection circuit, and controlling the electrical connection structure to be alternatively conducted with the second data terminal through the second detection circuit refer to the related descriptions in the repair circuit of the electrical connection structure, and are not described herein again.
The first data end, the electric connection structure and the second data end are conducted through the control circuit to form a data transmission path, the control circuit sequentially controls the conduction of the data transmission paths according to the sequence of the electric connection structures corresponding to the data transmission paths and transmits data signals in the data transmission paths, so that the data transmission paths of the data signals can be conveniently selected, and the reliability of data signal transmission is ensured. For example, the repair circuit of the electrical connection structure has first data terminals IO1 to IO4, electrical connection structures TSV1 to TSV5, and second data terminals IO1 'to IO4', if the 1 st, 2 nd, 3 nd 5 electrical connection structures are normal, and the 4 th electrical connection structure is failed, the first data terminal IO1, the electrical connection structure TSV1, and the second data terminal IO1 'are conducted through a control circuit to form a data transmission path 1, the first data terminal IO2, the electrical connection structure TSV2, and the second data terminal IO2' are conducted through a control circuit to form a data transmission path IO2, the first data terminal IO3, the electrical connection structure TSV3, and the second data terminal IO3 'are conducted through a control circuit to form a data transmission path IO3, the first data terminal IO4, the electrical connection structure TSV5, and the second data terminal IO4' are conducted through a control circuit to form a data transmission path IO4, the control circuit sequentially controls and conducts the data transmission paths according to sequence numbers of the electrical connection structures corresponding to the data transmission paths, that the data transmission paths 1, the data transmission path TSV2, the data transmission path TSV3, and the data transmission path 4 are conducted sequentially, so that data transmission paths are conducted in sequence of the data transmission paths, and the data transmission paths are transmitted in sequence of the data transmission path.
The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (devices) and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In the present disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrases "comprising 8230; \8230;" 8230; "does not exclude the presence of additional like elements in an article or device comprising the element.
While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the present disclosure.
It will be apparent to those skilled in the art that various changes and modifications may be made to the present disclosure without departing from the spirit and scope of the disclosure. Thus, it is intended that the present disclosure cover the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.

Claims (17)

1. A repair circuit for an electrical connection structure, comprising:
the electric connection module comprises 1 st, 2 nd, 8230th and N electric connection structures, wherein N is a positive integer greater than or equal to 3;
the M first data ends are positioned on the first side of the electric connection module, each first data end is correspondingly connected with the first ends of at least two electric connection structures one by one through at least two first switch units, and at least one electric connection structure is connected with at least two first data ends;
the M second data terminals are positioned on the second side of the electric connection module, correspond to the M first data terminals one by one, are connected with the second terminals of the at least two electric connection structures one by one through the at least two second switch units, correspond to the connection relationship between the M first data terminals and the electric connection structures, and are connected with the at least two second data terminals through the at least one electric connection structure, wherein M is a positive integer greater than or equal to 2 and less than N;
the first control circuit is used for respectively controlling the on-off of each first switch unit according to the voltage change of the first end of each electric connection structure, and when one first switch unit connected with the same first data end is on, controlling the off of other first switch units connected with the first data end;
and the second control circuit is used for respectively controlling the second switch units to be switched on or switched off according to the voltage change of the second ends of the electric connection structures, and when one second switch unit connected with the same second data end is switched on, the second control circuit controls the other second switch units connected with the second data end to be switched off.
2. The repair circuit of an electrical connection structure according to claim 1, wherein two adjacent first data terminals are respectively connected to at least one same electrical connection structure through the first switch unit;
two adjacent second data terminals are respectively connected to at least one same electrical connection structure through the second switch unit.
3. The repair circuit of an electrical connection structure according to claim 2,
the 1 st first data terminal is respectively connected with the 1 st, 8230and R first ends of the electric connection structures through R first switch units;
the ith first data terminal is respectively connected with the first terminals of the (i + R-1) th electric connection structures through R first switch units;
the 1 st second data terminal is respectively connected with the 1 st, 8230and R second terminals of the electric connection structures through R second switch units;
the jth second data end is connected with the second ends of the jth electrical connection structures of (j + R-1) th electrical connection structures of (j), (8230) th and (j + R-1) th through R second switch units respectively;
wherein i is a positive integer greater than or equal to 2, j is a positive integer greater than or equal to 2, and R is a positive integer greater than or equal to 2.
4. The repair circuit of an electrical connection structure according to claim 2 or 3, wherein the first control circuit is configured to control the turning on or off of each of the first switch units connected to each of the first data terminals;
for each first data end, the first control circuit is used for controlling the conduction of a first switch unit corresponding to an electric connection structure which is connected with the first control circuit and is in a normal working state, wherein the first switch unit is in front of the serial number of the first control circuit and is in an unoccupied electric connection structure;
the second control circuit is configured to control the second switch unit connected to each of the second data terminals to be turned on or off;
for each second data terminal, the second control circuit is used for controlling the conduction of a second switch unit corresponding to an electric connection structure which is connected with the second control circuit and has a front serial number and is in a normal working state in the unoccupied electric connection structure.
5. The repair circuit of an electrical connection structure according to claim 3, wherein the first control circuit includes N discharge circuits and N first detection circuits, first terminals of the N first detection circuits and the N discharge circuits are respectively connected to the first terminals of the N electrical connection structures in a one-to-one correspondence, and a second terminal of each first detection circuit is connected to each first switch unit of the corresponding electrical connection structure;
the second control circuit comprises N discharge circuits and N second detection circuits, the first ends of the N second detection circuits and the N discharge circuits are respectively connected with the second ends of the N electric connection structures in a one-to-one correspondence manner, and the second end of each second detection circuit is connected with each second switch unit of the corresponding electric connection structure;
wherein the charging circuit is configured to charge the corresponding electrical connection structure to a first voltage level, and the discharging circuit is configured to discharge the corresponding electrical connection structure to a second voltage level;
the first detection circuit is used for generating a first control signal according to the voltage level change of the first end of the connected electric connection structure, the first control signal is output by the second end of the first detection circuit, and the first control signal is used for controlling the conduction or the closing of each first switch unit corresponding to the electric connection structure;
the second detection circuit is configured to generate a second control signal according to a voltage level change of a second end of the electrically connected structure, where the second control signal is output by the second end of the second detection circuit and is used to control on or off of each second switch unit corresponding to the electrically connected structure.
6. The repair circuit of an electrical connection structure according to claim 5, wherein the first control circuit includes a plurality of first sub-control units connected to the first switch units in a one-to-one correspondence, the first sub-control units being configured to control on and off of the first switch units connected thereto;
each first data terminal corresponds to R first branch control units,
for the 1 st first data terminal,
the 1 st first sub-control unit corresponding to the 1 st first data end is used for controlling the conduction or the closing of the 1 st first switch unit connected with the 1 st first sub-control unit according to a first control signal of the 1 st first detection circuit;
mth corresponding to the 1 st first data terminal 1 A first control unit for controlling the first switch according to the m 1 A first control signal of the first detection circuit and an (m) th control signal corresponding thereto 1 -1) output signals of first control units controlling the switching on or off of the first switching units connected thereto;
for the m-th 2 A first data terminal for receiving the first data signal,
m th 2 A 1 st first control unit corresponding to the first data terminal and used for controlling the first data terminal according to the m 2 A first control signal of the first detection circuit and (m) th 2 -1) the output signal of the 1 st first control unit corresponding to the 1 first data terminal controls the on or off of the 1 st first switch unit connected with it;
m th 2 M-th data terminal corresponding to the first data terminal 1 A first control unit for controlling the first switch according to the (m) th 2 +m 1 -1) first control signal of said first detection circuit, the (m) th corresponding thereto 1 -1) the output signal of the first control unit and 2 -1) the (m) th data terminal corresponding to the first data terminal 1 -1) output signals of first control units controlling the switching on or off of the first switching units connected thereto;
the second control circuit comprises a plurality of second sub-control units which are connected with the second switch units in a one-to-one correspondence mode, and the second sub-control units are used for controlling the on and off of the second switch units connected with the second control units;
each second data terminal corresponds to R second branch control units,
for the 1 st second data terminal,
the 1 st second branch control unit corresponding to the 1 st second data end is used for controlling the conduction or the closing of the second switch unit connected with the 1 st second branch control unit according to a second control signal of the 1 st second detection circuit;
mth corresponding to 1 st second data terminal 1 A second sub-control unit for controlling the sub-control unit according to the m 1 A second control signal of the second detection circuit and an (m) th signal 1 -1) output signals of second sub-control units controlling the on or off of the second switching units connected thereto;
for the m-th 2 A second data terminal for receiving the second data,
m th 2 A 1 st second sub-control unit corresponding to the second data terminal and used for controlling the first sub-control unit according to the m 2 A second control signal of the second detection circuit and an (m) th signal 2 -1) the output signal of the 1 st second sub-control unit corresponding to the second data terminal controls the second switch unit connected with the output signal to be switched on or off;
m th 2 M-th corresponding to the second data terminal 1 A second sub-control unit for controlling the second sub-control unit according to the (m) th 2 +m 1 -1) second control signal of said second detection circuit, the (m) th 1 -1) the output signal of the second sub-control unit and (m) th 2 -1) th (m) of second data terminals 1 -1) output signals of second sub-control units controlling the on or off of the second switching units connected thereto;
wherein m is 1 Is a positive integer greater than or equal to 2 and less than or equal to R, m 2 Is a positive integer greater than or equal to 2 and less than or equal to M.
7. The repair circuit of an electrical connection structure according to claim 6,
for the 1 st first data terminal,
the 1 st first sub-control unit corresponding to the 1 st first data end comprises a first node, the input end of the first node is connected with the output end of the 1 st first detection circuit, and the output end of the first node is used as the control end of the corresponding first switch unit;
when m is 1 When the value is less than R, the m-th corresponding to the 1 st first data end 1 The first branch control units comprise a first AND gate and a first OR gate, wherein the input end of the first AND gate is respectively connected with the inverted signal of the output end of the first node and the mth gate 1 The output end of the first AND gate is connected with the control end of the corresponding first switch unit, the input end of the first OR gate is respectively connected with the output end of the first node and the output end of the first AND gate, and the output end of the first OR gate is used as the mth 1 The output end of each first branch control unit;
the Rth first sub-control unit corresponding to the 1 st first data end comprises a second AND gate and a second OR gate, the input end of the second AND gate is respectively connected with the reverse signal of the output end of the first OR gate and the output end of the Rth first detection circuit, the output end of the second AND gate is connected with the control end corresponding to the first switch unit, the input end of the second OR gate is respectively connected with the output end of the first OR gate and the output end of the second AND gate, and the output end of the second OR gate is used as the output end of the Rth first sub-control unit corresponding to the 1 st first data end and is connected with the Rth first sub-control unit corresponding to the 2 nd first data end;
when m is 2 Less than M, for M 2 A first data terminal for receiving the first data signal,
m th 2 The 1 st first sub-control unit corresponding to the first data end comprises a third AND gate, and the input ends of the third AND gate are respectively connected with the mth 2 An output terminal of the first detection circuit and an (m) th signal 2 -1) the output terminal of the 1 st first control unit corresponding to the first data terminal, the output terminal of the third and gate being taken as the m-th output terminal 2 Corresponding to a first data terminalThe output end of the 1 st first sub-control unit is respectively connected with the control end of the corresponding first switch unit and the corresponding 2 nd first sub-control unit;
when m is 1 When less than R, m 2 M-th data terminal corresponding to the first data terminal 1 The first branch control units comprise a fourth AND gate and a third OR gate, and the input ends of the fourth AND gate are respectively connected with the (m) th gate 2 +m 1 -1) output of said first detection circuit, corresponding (m) th 1 -1) the inverted signal at the output of the first control unit and (m) th 2 -1) mth data terminal corresponding to first data terminal 1 The output ends of the fourth and gates are respectively connected with the control ends of the corresponding first switch units and the third or gates, and the input ends of the third or gates are respectively connected with the corresponding (m) th or gate 1 -1) the output of the first control unit and the output of the fourth and-gate, the output of the third or-gate being the m-th 2 M-th data terminal corresponding to the first data terminal 1 The output end of each first branch control unit is connected with the corresponding mth 1 +1 first branch control units;
m th 2 The Rth first branch control unit corresponding to the first data end comprises a fifth AND gate and a fourth OR gate, and the input ends of the fifth AND gate are respectively connected with the (R + m) th 1 -1) the inverted signal of the output of the first detection circuit, of the corresponding output of the R-1 st first control unit and of the (m) th 2 -1) an output terminal of an R-th first sub-control unit of the first data terminals, an output terminal of the fifth and-gate being connected to a control terminal of the corresponding first switch unit and a fourth or-gate, respectively, an input terminal of the fourth or-gate being connected to an output terminal of the corresponding R-1-th first sub-control unit and an output terminal of the fifth and-gate, an output terminal of the fourth or-gate being used as an m-th output terminal 2 The output end of the Rth first branch control unit corresponding to the first data end is connected with the mth 2 The R-th first control unit of +1 first data ends;
for the mth first data terminal,
the 1 st first sub-control unit corresponding to the mth first data end comprises a sixth AND gate, the input end of the sixth AND gate is respectively connected with the output end of the mth first detection circuit and the 1 st first sub-control unit corresponding to the (M-1) th first data end, the output end of the sixth AND gate is used as the output end of the 1 st first sub-control unit corresponding to the mth first data end, and is respectively connected with the control end of the corresponding first switch unit and the corresponding 2 nd first sub-control unit;
when m is 1 When the current value is less than R, the M-th corresponding to the Mth first data terminal 1 The first branch control units comprise a seventh AND gate and a fifth OR gate, and the input ends of the seventh AND gate are respectively connected with the (M + M) th 1 -1) output of said first detection circuit, corresponding (m) th 1 -1) an inverted signal at the output of the first control unit and the mth signal corresponding to the (M-1) th first data terminal 1 The output end of the seventh AND gate is respectively connected with the control end of the corresponding first switch unit and the fifth OR gate, the input ends of the fifth or gates are respectively connected with the corresponding (m) th 1 -1) the output of the first control unit and the output of the seventh and-gate, the output of the fifth or-gate being the M-th gate corresponding to the M-th first data terminal 1 The output end of each first branch control unit is connected with the corresponding mth 1 +1 first slave control units;
the Rth first sub-control unit corresponding to the Mth first data end comprises an eighth AND gate, the input end of the eighth AND gate is respectively connected with the output end of the (R + M-1) th first detection circuit, the reverse signal of the output end of the corresponding R-1 th first sub-control unit and the output end of the Rth first sub-control unit of the M-1 first data end, and the output end of the eighth AND gate is connected with the control end of the corresponding first switch unit;
for each second data end, the structures of the R second sub-control units corresponding to the second data end and the structures of the R first sub-control units corresponding to the first data end corresponding to the second data end are the same.
8. The repair circuit of claim 6, wherein when the mth first data terminal is connected to the mth second data terminal through the nth ' electrical connection structure, if N ' is less than N, the first switch unit and the second switch unit connected to each other are respectively turned off by the first control unit and the second control unit corresponding to the nth ' +1 to nth electrical connection structures.
9. The repair circuit of an electrical connection structure according to claim 6,
the first detection circuit comprises a first trigger and a first phase inverter, the input end of the first phase inverter is used as the first end of the first detection circuit and is connected with the first end of the corresponding electric connection structure, the output end of the first phase inverter is connected with the clock input end of the first trigger, and the output end of the first trigger is used as the second end of the first detection circuit and is connected with each first switch unit and each first sub-control unit;
the second detection circuit comprises a second trigger and a second phase inverter, the input end of the second phase inverter is used as the first end of the second detection circuit and is connected with the corresponding second end of the electric connection structure, the output end of the second phase inverter is connected with the clock input end of the second trigger, and the output end of the second trigger is used as the second end of the second detection circuit and is connected with each second switch unit and each second sub-control unit.
10. The repair circuit of an electrical connection structure according to claim 9,
the first trigger is a rising edge trigger and outputs a high level signal in response to a rising edge signal;
the second flip-flop is a rising edge flip-flop and outputs a high level signal in response to a rising edge signal.
11. The repair circuit of an electrical connection structure according to claim 9,
the first switch unit is switched on in response to the high-level signal output by the corresponding first branch control unit;
the second switch unit is turned on in response to the high level signal output by the corresponding first branch control unit.
12. The repair circuit of an electrical connection structure according to claim 9,
the first detection circuit further comprises a first transistor, a first pole of the first transistor is connected with the input end of the first inverter, a second pole of the first transistor is grounded, and a grid electrode of the first transistor is connected with an inverted signal of an electric signal;
the second detection circuit further comprises a second transistor, a first pole of the second transistor is connected with the input end of the second inverter, a second pole of the second transistor is grounded, and a grid electrode of the second transistor is connected with a reverse signal of an electric signal.
13. The repair circuit of an electrical connection structure according to claim 9,
the reset end of the first trigger is connected with an electrical signal, and the first trigger is used for resetting the output end of the first trigger when the reset end of the first trigger receives an electrifying signal;
the reset end of the second trigger is connected with an upper electric signal, and the second trigger is used for resetting the output end of the second trigger when the reset end of the second trigger receives a power-on signal.
14. The repair circuit of an electrical connection structure according to any one of claims 1 to 3, wherein the electrical connection structure is a through silicon via structure, the M first data terminals and the first control circuit are disposed in a first semiconductor chip, and the M second data terminals and the second control circuit are disposed in a second semiconductor chip.
15. The control method for the repair circuit of the electric connection structure is characterized in that the repair circuit of the electric connection structure comprises an electric connection module, the electric connection module comprises N electric connection structures, a first side of the electric connection module is provided with M first data ends, a second side of the electric connection module is provided with M second data ends, each first data end is connected with first ends of at least two electric connection structures, each second data end is connected with second ends of at least two electric connection structures, N is a positive integer larger than or equal to 3, M is a positive integer larger than or equal to 2 and smaller than N, and the control method comprises the following steps:
detecting a voltage change at the first end and the second end of each of the electrical connection structures;
controlling the electric connection structure to be connected with or disconnected from the corresponding first data end according to the voltage change of the first end of each electric connection structure, controlling the electric connection structure to be connected with or disconnected from the corresponding second data end according to the voltage change of the second end of each electric connection structure, so that the electric connection structure is alternatively connected with or disconnected from the first data end, and the electric connection structure is alternatively connected with or disconnected from the second data end;
when two ends of the electric connection structure are respectively communicated with a first data end and a second data end, the data signal is controlled to be transmitted from the communicated first data end to the second data end, or the data signal is controlled to be transmitted from the communicated second data end to the first data end.
16. The method of claim 15, wherein said detecting a change in voltage at the first and second ends of each of the electrical connection structures comprises:
setting, by a charging circuit, a first end and a second end of an electrical connection structure to a first voltage level;
setting, by the discharge circuit, the first and second ends of the electrical connection structure to a second voltage level;
the method for controlling the electric connection structure to be connected with or disconnected from the corresponding first data end according to the voltage change of the first end of each electric connection structure, and controlling the electric connection structure to be connected with or disconnected from the corresponding second data end according to the voltage change of the second end of each electric connection structure comprises the following steps:
responding to the voltage of the first end of the electric connection structure changing from the first voltage level to the second voltage level, and controlling the electric connection structure to be alternatively conducted with the first data end through a first detection circuit;
and responding to the voltage of the second end of the electric connection structure changed from the first voltage level to the second voltage level, and controlling the electric connection structure to be alternatively conducted with the second data end through a second detection circuit.
17. The control method of the repair circuit of an electrical connection structure according to claim 15,
the first data end, the electric connection structure and the second data end are conducted through a control circuit to form a data transmission path;
and the control circuit sequentially controls and conducts the data transmission paths according to the sequence numbers of the electric connection structures corresponding to the data transmission paths.
CN202210784714.0A 2022-07-05 2022-07-05 Repair circuit of electric connection structure and control method thereof Pending CN115241664A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210784714.0A CN115241664A (en) 2022-07-05 2022-07-05 Repair circuit of electric connection structure and control method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210784714.0A CN115241664A (en) 2022-07-05 2022-07-05 Repair circuit of electric connection structure and control method thereof

Publications (1)

Publication Number Publication Date
CN115241664A true CN115241664A (en) 2022-10-25

Family

ID=83671809

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210784714.0A Pending CN115241664A (en) 2022-07-05 2022-07-05 Repair circuit of electric connection structure and control method thereof

Country Status (1)

Country Link
CN (1) CN115241664A (en)

Similar Documents

Publication Publication Date Title
CN101248363B (en) Semiconductor device, semiconductor chip, method for testing wiring between chips and method for switching wiring between chips
US11004530B2 (en) Testing through-silicon-vias
US9177940B2 (en) Fault-tolerant unit and method for through-silicon via
US10591544B2 (en) Programmable integrated circuits with in-operation reconfiguration capability
KR101321480B1 (en) Semiconductor apparatus and stacked semiconductor apparatus
US8592813B2 (en) Semiconductor device and stacked semiconductor apparatus
TW201025543A (en) Systems and methods utilizing redundancy in semiconductor chip interconnects
US8193006B2 (en) Method of chip repair by stacking a plurality of bad dies
CN101241764A (en) Electric fuse circuit
KR20170090552A (en) Electrical short detecting circuit of stacked memory chips and method thereof
US8461904B2 (en) Switching device and semiconductor integrated circuit device including the same
CN104678240A (en) Circuit for testing power supply in multiple power modes
CN111198316A (en) Through silicon via detection circuit and method and integrated circuit
JP2004264057A (en) Boundary scan controller, semiconductor device, and method for identifying and controlling semiconductor circuit chip of semiconductor device
Chou et al. Yield enhancement by bad-die recycling and stacking with though-silicon vias
CN100407423C (en) Semiconductor device and semiconductor package
US9633928B2 (en) Through-silicon via access device for integrated circuits
TWI482165B (en) Technology of post-bond memory repair for three-dimensional integrated circuit
US20160154049A1 (en) Semiconductor device and method of testing semiconductor device
CN115241664A (en) Repair circuit of electric connection structure and control method thereof
Maity et al. Built-in self-repair for manufacturing and runtime TSV defects in 3D ICs
KR100746228B1 (en) Semiconductor Memory module and Semiconductor Memory Device
US6621294B2 (en) Pad system for an integrated circuit or device
TWI424530B (en) Fault-tolerant unit and method for through-silicon via
CN114421938A (en) Circuit structure and control method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination