CN114421938A

CN114421938A - Circuit structure and control method thereof

Info

Publication number: CN114421938A
Application number: CN202210041230.7A
Authority: CN
Inventors: 张家瑞
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-01-14
Filing date: 2022-01-14
Publication date: 2022-04-29

Abstract

The present disclosure provides a circuit structure and a control method thereof. The circuit structure includes: the electric connection module comprises N electric connection structures, and two ends of each electric connection structure are respectively connected with the first switch unit and the second switch unit; the first circuit module is used for controlling the on or off of the first switch unit according to the voltage change of the first side of the electric connection structure; the second circuit module is used for controlling the on or off of the second switch unit according to the voltage change of the second side of the electric connection structure; when the first switching unit and the second switching unit are simultaneously in the on state, data is transferred from the first switching unit to the second switching unit, or data is transferred from the second switching unit to the first switching unit. Therefore, the electric connection structure can realize bidirectional data transmission, and the performance of electric devices such as semiconductor devices adopting the circuit structure is improved.

Description

Circuit structure and control method thereof

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a circuit structure and a control method thereof.

Background

In the circuit structure, the device units are electrically connected Through an electrical connection structure, for example, in the stacked memory device, the semiconductor chips in each layer are electrically connected Through Silicon Vias (TSVs).

In the semiconductor chips electrically connected through the through-silicon vias, bidirectional data transmission through the through-silicon vias is difficult, and the performance of the stacked memory device is limited.

Disclosure of Invention

The following is a summary of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

The present disclosure provides a circuit structure and a control method thereof.

According to a first aspect of embodiments of the present disclosure, there is provided a circuit structure comprising:

the electric connection module comprises N electric connection structures, wherein two ends of each electric connection structure are respectively connected with the first switch unit and the second switch unit, and N is a positive integer greater than or equal to 1;

the first circuit module is used for controlling the first switch unit to be switched on or switched off according to the voltage change of the first side of the electric connection structure;

the second circuit module is used for controlling the second switch unit to be switched on or switched off according to the voltage change of the second side of the electric connection structure;

wherein data is transferred from the first switching unit to the second switching unit or data is transferred from the second switching unit to the first switching unit when the first switching unit and the second switching unit are simultaneously in a conductive state.

In some embodiments of the present disclosure, the first circuit module includes N charging circuits and N first detection circuits, a first end of each of the first detection circuits and the charging circuit are connected to a first side of the corresponding electrical connection structure, and a second end of each of the first detection circuits is connected to a control end of the first switch unit;

the second circuit module comprises N discharge circuits and N second detection circuits, a first end of each second detection circuit and the discharge circuit are connected with a second side of the corresponding electric connection structure, and a second end of each second detection circuit is connected with a control end of the second switch unit;

the charging circuit is used for charging the corresponding electric connection structure to a first voltage level, the discharging circuit is used for discharging the corresponding electric connection structure to a second voltage level, the first detection circuit is used for controlling the first switch unit to be switched on or switched off according to the voltage level change of the first side of the connected electric connection structure, and the second detection circuit is used for controlling the second switch unit to be switched on or switched off according to the voltage level change of the second side of the connected electric connection structure.

In some embodiments of the present disclosure, the first detection circuit includes a first flip-flop and a first inverter, an output terminal of the first flip-flop is connected to the control terminal of the first switch unit, a clock input terminal of the first flip-flop is connected to an output terminal of the first inverter, and an input terminal of the first inverter is connected to a first side of the corresponding electrical connection structure;

the second detection circuit comprises a second trigger and a second phase inverter, the output end of the second trigger is connected with the control end of the second switch unit, the clock input end of the second trigger is connected with the output end of the second phase inverter, and the input end of the second phase inverter is connected with the second side of the corresponding electric connection structure.

In some embodiments of the present disclosure, the first detection circuit includes a first transistor, an input terminal of the first inverter is connected to a first pole of the first transistor, a second pole of the first transistor is grounded, and a gate of the first transistor is connected to an inverted signal of the electrical signal;

the second detection circuit comprises a second transistor, the input end of the second inverter is connected with the first pole of the second transistor, the second pole of the second transistor is grounded, and the grid electrode of the second transistor is connected with the reverse signal of the electric signal.

In some embodiments of the present disclosure, a reset terminal of the first flip-flop is connected to an electrical signal, and the first flip-flop is configured to reset an output terminal thereof when the reset terminal thereof does not receive a power-on signal, so as to control the first switching unit to be turned off;

the reset end of the second trigger is connected with an upper electric signal, and the second trigger is used for resetting the output end of the second trigger when the reset end of the second trigger does not receive the power-on signal so as to control the second switch unit to be disconnected.

In some embodiments of the present disclosure, N is greater than or equal to 2,

in the N electric connection structures, the first side of each electric connection structure is connected to a first data terminal;

in the N electric connection structures, the second side of each electric connection structure is connected to a second data terminal;

and the data is transmitted from the first data terminal to the second data terminal, or the data is transmitted from the second data terminal to the first data segment.

In some embodiments of the present disclosure, the first circuit module and the second circuit module are configured to control the conduction of the first switch unit and the second switch unit at two ends of one of the N electrical connection structures.

In some embodiments of the present disclosure, the electrical connection structure is a through silicon via structure, the first circuit module is disposed in the first semiconductor unit, and the second circuit module is disposed in the second semiconductor unit.

A second aspect of the present disclosure provides a method for controlling a circuit structure, where the circuit structure includes an electrical connection module, the electrical connection module includes N electrical connection structures, N is a positive integer greater than or equal to 1, and two ends of each electrical connection structure are respectively connected to a first data terminal and a second data terminal, the method includes:

controlling a voltage change at a first side and a second side of the electrical connection structure;

controlling the electric connection structure to be connected or disconnected with the first data terminal according to the voltage change of the first side of the electric connection structure, and controlling the electric connection structure to be connected or disconnected with the second data terminal according to the voltage change of the second side of the electric connection structure;

when the electrical connection structure is conducted with the first data terminal and the second data terminal, control data is transmitted from the first data terminal to the second data terminal, or control data is transmitted from the second data terminal to the first data terminal.

In some embodiments of the present disclosure, the controlling the voltage variation of the first side and the second side of the electrical connection structure includes:

setting, by a charging circuit, a first side and a second side of an electrical connection structure to a first voltage level;

setting, by the discharge circuit, the first side and the second side of the electrical connection structure to a second voltage level;

the controlling the connection or disconnection between the electrical connection structure and the first data terminal according to the voltage variation of the first side of the electrical connection structure, and controlling the connection or disconnection between the electrical connection structure and the second data terminal according to the voltage variation of the second side of the electrical connection structure, includes:

controlling, by a first detection circuit, a first switching unit between the electrical connection structure and the first data terminal to be turned on in response to a voltage of a first side of the electrical connection structure changing from the first voltage level to the second voltage level;

and controlling a second switch unit between the electric connection structure and the second data terminal to be conducted through a second detection circuit in response to the voltage of the second side of the electric connection structure changing from the first voltage level to the second voltage level.

In some embodiments of the disclosure, the controlling, by the first detection circuit, the first switch unit between the electrical connection structure and the first data terminal to be turned on in response to the voltage of the first side of the electrical connection structure changing from the first voltage level to the second voltage level includes:

in response to the detection of a first rising edge signal by a clock input end of a first flip-flop of the first detection circuit, an output end of the first flip-flop outputs a first control signal to a control end of the first switch unit so as to control the first switch unit to conduct a path between the electrical connection structure and the first data end;

the controlling, by a second detection circuit, a second switch unit between the electrical connection structure and the second data terminal to be turned on in response to the voltage of the second side of the electrical connection structure changing from the first voltage level to the second voltage level includes:

in response to the clock input end of the second flip-flop of the second detection circuit detecting a second rising edge signal, the output end of the second flip-flop outputs a second control signal to the control end of the second switch unit to control the second switch unit to conduct the path between the electrical connection structure and the second data end.

In some embodiments of the present disclosure, the control method further comprises:

in response to the voltage on the first side of the electrical connection structure being charged to a first voltage level, the first inverter of the first detection circuit converts a first high level signal at its input into a first low level signal and inputs the first low level signal into the clock input of the first flip-flop;

in response to a voltage on the first side of the electrical connection structure changing from the first voltage level to the second voltage level, the first inverter converts a third low level signal at an input end thereof into a third high level signal at an output end thereof, and inputs the third high level signal into a clock input end of the first flip-flop so that the clock input end of the first flip-flop detects the first rising edge signal;

in response to the voltage on the second side of the electrical connection structure being charged to a second voltage level, the second inverter of the second detection circuit converts the second high level signal at its input terminal to the second low level signal at its output terminal and inputs the second low level signal to the clock input terminal of the second flip-flop;

in response to the voltage at the second side of the electrical connection structure changing from the second voltage level to the first voltage level, the second inverter converts a fourth low level signal at its input to a fourth high level signal at its output and inputs the fourth high level signal to the clock input of the second flip-flop so that the clock input of the second flip-flop detects the second rising edge signal.

in response to not receiving a power-on signal, inputting a fifth high level signal to a clock input terminal of the first flip-flop;

and in response to not receiving the power-on signal, inputting a sixth high-level signal to the clock input end of the second trigger.

In some embodiments of the present disclosure, the inputting a fifth high-level signal to the clock input terminal of the first flip-flop in response to not receiving the power-on signal includes:

in response to not receiving a power-up signal, grounding an input of the first inverter so that an output of the first inverter forms the fifth high level signal, and inputting the fifth high level signal to a clock input of the first flip-flop;

the inputting a sixth high level signal to the clock input terminal of the second flip-flop in response to not receiving the power-on signal includes:

in response to not receiving a power-up signal, grounding an input terminal of the second inverter so that an output terminal of the second inverter forms the sixth high level signal, and inputting the sixth high level signal to a clock input terminal of the second flip-flop.

in response to not receiving a power-on signal, controlling the first detection circuit to turn off the first switch unit;

and controlling the second detection circuit to disconnect the second switch unit in response to not receiving a power-on signal.

Wherein the controlling the first detection circuit to turn off the first switching unit in response to not receiving a power-on signal includes:

in response to that the reset terminal of the first flip-flop of the first detection circuit does not detect the power-on signal, the output terminal of the first flip-flop outputs a third control signal to the control terminal of the first switching unit so as to control the first switching unit to be switched off;

the controlling the second detection circuit to open the second switch unit in response to not receiving the power-on signal includes:

in response to that the reset terminal of the second flip-flop of the second detection circuit does not detect the power-on signal, the output terminal of the second flip-flop outputs a fourth control signal to the control terminal of the second switching unit to control the second switching unit to be switched off.

In the circuit structure and the control method thereof provided by the embodiment of the disclosure, a first switch unit and a second switch unit are arranged at two ends of an electric connection structure, the first circuit module controls the first switch unit to be turned on or off according to the voltage variation of the first side of the electrical connection structure, and the second circuit module controls the second switch unit to be turned on or off according to the voltage change of the second side of the electrical connection structure, namely, whether the electric connection structure is connected with the circuit or not is controlled by the first switch unit and the second switch unit, therefore, when the first switch unit and the second switch unit are simultaneously conducted, data can be transmitted to the second switch unit from the first switch unit through the electric connection structure and can also be transmitted to the first switch unit from the second switch unit through the electric connection structure, therefore, the electric connection structure can realize bidirectional data transmission, and the performance of electric devices such as semiconductor devices adopting the circuit structure is improved.

In the embodiment of the disclosure, when the circuit structure includes at least two electrical connection structures, two sides of the electrical connection structures are respectively connected with the first switch unit and the second switch unit, and because the electrical connection structures are arranged in parallel, when any electrical connection structure is short-circuited, the first switch unit and the second switch unit on two sides of the electrical connection structure cannot be turned on, so that the current does not affect other electrical connection structures, thereby ensuring the data transmission performance.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to indicate like elements. The drawings in the following description are directed to some, but not all embodiments of the disclosure. For a person skilled in the art, other figures can be derived from these figures without inventive effort.

FIG. 1 is a cross-sectional view of a semiconductor memory system according to the present invention;

fig. 2 is a perspective view of a semiconductor memory system according to the present invention;

FIG. 3 is a block diagram illustrating the components of a circuit configuration according to an exemplary embodiment;

FIG. 4 is a schematic diagram of a circuit configuration shown in accordance with an exemplary embodiment;

FIG. 5 is an enlarged view at A in FIG. 4;

FIG. 6 is an enlarged view at B in FIG. 4;

fig. 7 is a schematic structural diagram illustrating a first switching unit according to an exemplary embodiment;

FIG. 8 is a flow chart illustrating a method of controlling a circuit configuration according to an exemplary embodiment;

fig. 9 is a timing diagram illustrating a control method according to an exemplary embodiment.

In the figure:

100. a stacked semiconductor device; 110. a base semiconductor chip; 111. a port physical layer; 112. a data access layer; 120. a core semiconductor chip; 130. a through silicon via; 200. a controller; 300. an inserter; 400. a substrate;

10. an electrical connection module; 11. an electrical connection structure; 20. a first circuit module; 21. a charging circuit; 211. a third transistor; 22. a first detection circuit; 221. a first flip-flop; 222. a first inverter; 223. a first transistor; 224. a third inverter; 30. a second circuit module; 31. a discharge circuit; 311. a fourth transistor; 32. a second detection circuit; 321. a second flip-flop; 322. a second inverter; 323. a second transistor; 324. a fourth inverter; 40. a first switch unit; 41. an nMOS tube; 42. a pMOS tube; 50. a second switching unit; 60. a first data terminal; 70. a second data terminal; 80. and a diode.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure. It should be noted that, in the present disclosure, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.

The stacked semiconductor device is mainly used as an example for description, and the circuit structure and the control method thereof provided by the embodiment of the disclosure are understood to be suitable for other devices with the same problem.

First, a semiconductor memory system in which a stacked semiconductor device is located will be described as a whole. The semiconductor memory system may be implemented, for example, in the form of a system-in-package (SIP) module, a multi-chip package (MCP) module, or a system-on-chip (SoC) module, or in the form of a package-on-package (PoP) module including a plurality of packages. Referring to fig. 1, the semiconductor memory system includes a stacked semiconductor device 100, a controller 200, an interposer 300, and a substrate 400, the interposer 300 being formed on the substrate 400, the stacked semiconductor device 100 and the controller 200 being formed above the interposer 300, and illustratively, the stacked semiconductor device 100 and the controller 200 do not overlap each other in a vertical direction (i.e., a direction perpendicular to the substrate).

The stacked semiconductor device 100 has a port Physical layer (PHY) 111, and the port Physical layer 111 may be connected to the port Physical layer 111 of the controller 200 through an interposer 300, thereby enabling communication between the stacked semiconductor device 100 and the controller 200. The stacked semiconductor device 100 also has a Data Access (DA) layer 112, and the DA layer 112 may be used to receive data such as test data.

The stacked semiconductor device 100 may be, for example, a High Bandwidth Memory (HBM), which may include a plurality of stacked semiconductor chips electrically connected to each other through an electrical connection structure, such as a through silicon via 130. With continued reference to fig. 1, the multi-layer semiconductor chip includes a base semiconductor chip 110 and a multi-layer core semiconductor chip 120 stacked on the base semiconductor chip 110, with a port physical layer 111 and a data access layer 112 disposed on the base semiconductor chip 110. The electrical connection between the base semiconductor chip 110 and the core semiconductor chip 120, and between the core semiconductor chips 120 is achieved through the through-silicon vias 130. The number of the core semiconductor chips 120 is not limited, and may be three as shown in fig. 1, for example, and may be set according to the requirement. The number of the through-silicon vias 130 connected between the base semiconductor chip 110 and the core semiconductor chip 120 may be one or more, and similarly, the number of the through-silicon vias 130 connected between the core semiconductor chip 120 may be one or more.

Each core semiconductor chip 120 may include one or more channels. Illustratively, as shown in fig. 2, three core semiconductor chips 120 are included, and each core semiconductor chip 120 includes two channels, and thus, the stacked semiconductor device includes a first channel CH0 through a sixth channel CH 5. The plurality of through-silicon vias 130 passing through the plurality of core semiconductor chips 120 may be disposed to be applied to the first channel CH0 to the sixth channel CH5, respectively.

Since the through-silicon via 130 needs to ensure physical connection, after the stacked semiconductor device 100 is powered on, the through-silicon via 130 needs to be tested to ensure that the through-silicon via 130 can perform normal signal transmission. However, the applicant finds that in order to realize the test, an inverter and other devices are generally arranged on the test circuit of the through silicon via 130, so that it is difficult to realize bidirectional data transmission between chips through the through silicon via 130, and the performance of the stacked semiconductor device 100 is affected.

Based on this, a circuit structure is provided in exemplary embodiments of the present disclosure. As shown in fig. 3, fig. 3 illustrates a schematic diagram of a circuit structure provided according to an exemplary embodiment of the present disclosure, which includes an electrical connection module 10, a first circuit module 20, and a second circuit module 30. The electrical connection module 10 includes N electrical connection structures 11, and a first switch unit 40 and a second switch unit 50 are respectively disposed at two ends of each electrical connection structure 11. The first circuit module 20 is used for controlling the first switch unit 40 to be turned on or off according to a voltage variation of a first side of the electrical connection structure 11 (e.g., a left side of the electrical connection structure 11), and the second circuit module 30 is used for controlling the second switch unit 50 to be turned on or off according to a voltage variation of a second side of the electrical connection structure 11 (e.g., a right side of the electrical connection structure 11). When the first switching unit 40 and the second switching unit 50 are simultaneously in the on state, data is transferred from the first switching unit 40 to the second switching unit 50, or data is transferred from the second switching unit 50 to the first switching unit 40.

N may be 1, that is, the number of the electrical connection structures 11 is 1, then the first switch unit 40 is disposed at one end of the electrical connection structure 11, for example, as shown in fig. 4, one end of the electrical connection structure 11 is connected to the first data terminal 60 through the first switch unit 40, and the first circuit module 20 controls the first switch unit 40 to be turned on or off according to a voltage change of the first side of the electrical connection structure 11, that is, the first circuit module 20 may control the electrical connection structure 11 to be turned on or off from the first data terminal 60 according to a voltage change of the first side of the electrical connection structure 11, and it can be understood that the turning off described herein refers to forming an open circuit, for example, turning off the electrical connection structure 11 from the first data terminal 60. The other end of the electrical connection structure 11 is provided with a second switch unit 50, for example, the other end of the electrical connection structure 11 is connected to the second data terminal 70 via the second switch unit 50, and the second circuit module 30 controls the second switch unit 50 to turn on or off according to the voltage variation of the second side of the electrical connection structure 11, that is, the second circuit module 30 can control the electrical connection structure 11 to turn on or off with the second data terminal 70 according to the voltage variation of the second side of the electrical connection structure 11, and similarly, the turning off described herein refers to forming an open circuit, for example, disconnecting the electrical connection structure 11 from the second data terminal 70.

N may also be greater than 1, that is, there are a plurality of electrical connection structures 11, and each electrical connection structure 11 is provided with one first switch unit 40 and one second switch unit 50 correspondingly. For example, one end of each electrical connection structure 11 is connected to one first data terminal 60 through one first switch unit 40, and the first circuit module 20 can control the first switch unit 40 corresponding to each electrical connection structure 11 to be turned on or off according to the voltage variation of the first side of each electrical connection structure 11. The other end of each electrical connection structure 11 is connected to a second data terminal 70 through a second switch unit 50, and the second circuit module 30 can control the second switch unit 50 corresponding to each electrical connection structure 11 to be turned on or off according to the voltage variation of the second side of each electrical connection structure 11. When N is greater than 1, the first side of each electrical connection structure 11 is connected to one first data terminal 60, and the second side of each electrical connection structure 11 is connected to one second data terminal 70, that is, data transmission can be performed between the first data terminal 60 and the second data terminal 70 through any one or more of the plurality of electrical connection structures 11.

Illustratively, the electrical connection structure 11 includes a through silicon via for realizing electrical connection between two adjacent semiconductor units, i.e., the first semiconductor unit and the second semiconductor unit, for example, in a stacked semiconductor device, the through silicon via is used for realizing electrical connection between a base semiconductor chip and a core semiconductor chip, or for realizing electrical connection between the core semiconductor chips. To facilitate the formation of the circuit structure, in one embodiment, the first switching unit 40 and the first circuit module 20 are located in a first semiconductor unit, and the second switching unit 50 and the second circuit module 30 are located in a second semiconductor unit. In one embodiment, two diodes 80 with opposite directions are connected in parallel to each of the first data terminal 60 and the second data terminal 70, so that data in a specific direction can only be transmitted through the diodes 80 in the specific direction.

In the circuit structure provided in this embodiment, the first switch unit 40 and the second switch unit 50 are disposed at two ends of the electrical connection structure 11, the first circuit module 20 controls the first switch unit 40 to be turned on or off according to the voltage variation at the first side of the electrical connection structure 11, and the second circuit module 30 controls the second switch unit 50 to be turned on or off according to the voltage variation at the second side of the electrical connection structure 11, that is, whether the electrical connection structure 11 is connected to the circuit is controlled by the first switch unit 40 and the second switch unit 50, so that when the first switch unit 40 and the second switch unit 50 are simultaneously turned on, data can be transmitted from the first switch unit 40 to the second switch unit 50 through the electrical connection structure 11, and can also be transmitted from the second switch unit 50 to the first switch unit 40 through the electrical connection structure 11, so that the electrical connection structure 11 can implement bidirectional data transmission, the performance of an electric device such as a semiconductor device employing the circuit structure is improved.

Various embodiments of the circuit configuration will first be described, taking as an example one electrical connection structure 11. As shown in fig. 5, the first circuit module 20 includes a charging circuit 21 and a first detection circuit 22, a first end of the first detection circuit 22 and the charging circuit 21 are both connected to a first side of the electrical connection structure 11, and a second end of the first detection circuit 22 is connected to a control end of the first switch unit 40. As shown in fig. 6, the second circuit module 30 includes a discharge circuit 31 and a second detection circuit 32, a first end of the second detection circuit 32 and the discharge circuit 31 are both connected to the second side of the electrical connection structure 11, and a second end of the second detection circuit 32 is connected to the control end of the second switch unit 50.

The charging circuit 21 is configured to charge the electrical connection structure 11 to a first voltage level, the discharging circuit 31 is configured to discharge the electrical connection structure 11 to a second voltage level, the first detection circuit 22 is configured to control the first switch unit 40 to be turned on or off according to a voltage level change of a first side of the connected electrical connection structure 11, and the second detection circuit 32 is configured to control the second switch unit 50 to be turned on or off according to a voltage level change of a second side of the connected electrical connection structure 11. Illustratively, after the charging circuit 21 and the discharging circuit 31 sequentially complete the charging and discharging operations of the electrical connection structure 11, if the electrical connection structure 11 is normally connected, the voltages at two sides of the electrical connection structure 11 will change, i.e. from a high level after charging to a low level after discharging, and if the electrical connection structure 11 is open or short-circuited, the voltages at two sides of the electrical connection structure 11 will not change, so that, according to the voltage change at two sides of the electrical connection structure 11 during the charging and discharging processes, it can be determined whether the electrical connection structure 11 has a fault such as open circuit or short circuit, so that when the electrical connection structure 11 is determined to have a fault, the first switch unit 40 is turned off by the first detection circuit 22, and the second switch unit 50 is turned off by the second detection circuit 32, and when the electrical connection structure 11 is determined to be normal, the first switch unit 40 is turned on by the first detection circuit 22, and the second switching unit 50 is turned on by the second detection circuit 32.

Illustratively, the first switch unit 40 is configured to be turned on when the control terminal receives a high level and turned off when receiving a low level, for example, the first switch unit 40 is a CMOS transmission gate, which includes an nMOS transistor 41 and a pMOS transistor 42 connected in parallel as shown in fig. 7, gate voltages of the two transistors are set to complementary signals, and referring to fig. 7, when the control signal C is a high level, the two transistors are turned on and provide a low resistance current path between the nodes a and B, and when the control signal C is a low level, both the transistors are turned off and an open circuit is formed between the nodes a and B. In this way, when the first detection circuit 22 determines that the electrical connection structure 11 is faulty, a low level is output to the first switch unit 40, so that the first switch unit 40 is turned off, thereby disconnecting the electrical connection structure 11 from the first data terminal 60, and when the first detection circuit 22 determines that the electrical connection structure 11 is normal, a high level is output to the first switch unit 40, thereby turning on the electrical connection structure 11 and the first data terminal 60. In other embodiments, the first switch unit 40 may also be configured to be turned on when the control terminal receives a low level and turned off when the control terminal receives a high level, which is not limited by the present disclosure.

The second switching unit 50 is provided similarly to the first switching unit 40, and thus, will not be described in detail.

In some embodiments, the first flip-flop 221 may control the first switch unit 40, for example, the first flip-flop 221 is a rising edge flip-flop, and when the voltage on the first side of the electrical connection structure 11 changes during the charging and discharging process, a rising edge signal is generated at a clock end of the first flip-flop 221, so that the first flip-flop 221 outputs a high level to the first switch unit 40. Illustratively, as shown in fig. 5, the first detection circuit 22 includes a first flip-flop 221 and a first inverter 222, an output terminal Q of the first flip-flop 221 is connected to the control terminal of the first switching unit 40, an input terminal D of the first flip-flop 221 is connected to the power supply VDD, a clock input terminal Clk of the first flip-flop 221 is connected to an output terminal of the first inverter 222, and an input terminal of the first inverter 222 is connected to the first side of the electrical connection structure 11. Thus, when the electrical connection structure 11 is charged, the first side thereof is at a high level, and a low level is formed at the clock input Clk of the first flip-flop 221 after passing through the first inverter 222. When the electrical connection structure 11 is discharged, the first side thereof changes from high level to low level, and then forms high level at the clock input Clk of the first flip-flop 221 through the first inverter 222, so that the rising edge signal is detected at the clock input Clk of the first flip-flop 221, and the output Q of the first flip-flop 221 outputs high level to the control terminal of the first switch unit 40, so as to turn on the first switch unit 40. Of course, in other embodiments, the first flip-flop 221 may also be other types of flip-flops such as a falling edge flip-flop, which is not limited by the present disclosure.

Similarly, as shown in fig. 6, the second detection circuit 32 includes a second flip-flop 321 and a second inverter 322, an output terminal of the second flip-flop 321 is connected to the control terminal of the second switch unit 50, a clock input terminal of the second flip-flop 321 is connected to an output terminal of the second inverter 322, and an input terminal of the second inverter 322 is connected to the second side of the corresponding electrical connection structure 11. The working process of the second flip-flop 321 is similar to that of the first flip-flop 221, and specific reference is made to the foregoing description on the first flip-flop 221, which is not repeated herein.

In an exemplary embodiment of the present disclosure, as shown in fig. 5, the first detection circuit 22 includes a first transistor 223, an input terminal of the first inverter 222 is connected to a first pole of the first transistor 223, a second pole of the first transistor 223 is grounded, and a gate of the first transistor 223 is connected to an inverted signal of the electrical signal. The first transistor 223 is configured to turn on its first pole and second pole when its gate receives a high level, and to turn off its first pole and second pole when its gate receives a low level. Because the gate of the first transistor 223 is connected with the inverse signal of the electrical signal, when the circuit is not powered on, the gate of the first transistor 223 inputs a high level, so that the first pole and the second pole of the first transistor 223 are turned on, so that the input end of the first inverter 222 is grounded, and the clock input Clk output by the first inverter 222 to the first flip-flop 221 is a high level, that is, the clock input Clk of the first flip-flop 221 is set to "1", thereby ensuring that before the circuit is powered on, a rising edge is not generated at the clock input Clk of the first flip-flop 221, that is, the first switch unit 40 is not controlled to be turned on, and further ensuring the reliability of the circuit structure.

In one embodiment, as shown in fig. 5, the first detection circuit 22 further includes a third inverter 224 connected end to end with the first transistor 223, that is, an input terminal of the third inverter 224 is connected to an output terminal of the first inverter 222, and an output terminal of the third inverter 224 is connected to an input terminal of the first inverter 222, which both form a latch to ensure the reliability of the signal inputted to the clock input Clk of the first flip-flop 221.

Similarly, as shown in fig. 6, the second detection circuit 32 includes a second transistor 323, an input terminal of the second inverter 322 is connected to a first pole of the second transistor 323, a second pole of the second transistor 323 is grounded, and a gate of the second transistor 323 is connected to an inverted signal of the electrical signal. The second transistor 323 and the first transistor 223 function similarly, and it is understood that the second detection circuit 32 may also include a fourth inverter 324 connected end to end with the second transistor 323, which is specifically referred to the description of the first transistor 223 and will not be described again here.

In an exemplary embodiment of the present disclosure, as shown in fig. 5, the reset terminal RN of the first flip-flop 221 is connected to the up signal, and the first flip-flop 221 is configured to reset the output terminal Q thereof when the reset terminal RN thereof does not receive the power-on signal, so as to control the first switch unit 40 to be turned off. When the first detection circuit 22 determines that the electrical connection structure 11 is normal, a high level is output to control the first switch unit 40 to be turned on, and when the power is off, the reset terminal of the first flip-flop 221 does not receive the power-on signal any more, and at this time, the output terminal Q of the first flip-flop 221 is reset, that is, the output terminal Q of the first flip-flop 221 outputs a low level, so as to control the first switch unit 40 to be turned off, and to ensure the effectiveness of the next power-on detection.

Similarly, as shown in fig. 6, the reset terminal of the second flip-flop 321 is connected to the upper electrical signal, and the second flip-flop 321 is configured to reset the output terminal thereof when the reset terminal thereof does not receive the power-on signal, so as to control the second switching unit 50 to be turned off. The operation of the reset terminal of the second flip-flop 321 is similar to that of the reset terminal of the first flip-flop 221, and specific reference is made to the foregoing description, which is not repeated herein.

In an exemplary embodiment of the present disclosure, as shown in fig. 5, the charging circuit 21 includes a pull-up driver for pulling up the electrical connection structure 11 to the first voltage level according to the charging driving signal PDRV. Illustratively, the pull-up driver includes a third transistor 211, a gate of the third transistor 211 is connected to the charge driving signal PDRV, a first pole of the third transistor 211 is connected to the power source, and a second pole of the third transistor 211 is connected between the electrical connection structure 11 and the first switching unit 40. The third transistor 211 is configured such that the first and second electrodes thereof are turned off when a high level is inputted to the gate thereof, and the first and second electrodes thereof are turned on when a low level is inputted to the gate thereof.

As shown in fig. 6, the discharge circuit 31 includes a pull-down driver for pulling down the electrical connection structure 11 to the second voltage level according to the discharge driving signal NDRV. Illustratively, the pull-down driver includes a fourth transistor 311, a gate of the fourth transistor 311 is connected to the discharge driving signal NDRV, a first pole of the fourth transistor 311 is grounded, and a second pole of the fourth transistor 311 is connected between the electrical connection structure 11 and the second switching unit 50. The fourth transistor 311 is configured such that when its gate receives a high level, its first and second poles are turned on, and when its gate receives a low level, its first and second poles are turned off.

In the above embodiments, the specific structures of the first circuit module 20 and the second circuit module 30 are described, when there is one electrical connection structure 11, that is, when N is greater than or equal to 2, as shown in fig. 4, the first circuit module 20 includes N charging circuits 21 and N first detection circuits 22, that is, one charging circuit 21 and one first detection circuit 22 are separately disposed on the first side of each electrical connection structure 11, that is, the N charging circuits 21 correspond to the N electrical connection structures 11 one to one, the N first detection circuits 22 correspond to the N electrical connection structures 11 one to one, and each first detection circuit 22 controls the corresponding first switch unit 40 to be turned on or off according to the voltage change on the first side of the corresponding electrical connection structure 11. Similarly, the second circuit module 30 includes N discharge circuits 31 and N second detection circuits 32, that is, one discharge circuit 31 and one second detection circuit 32 are separately disposed on the second side of each electrical connection structure 11, that is, the N discharge circuits 31 correspond to the N electrical connection structures 11 one to one, the N second detection circuits 32 correspond to the N electrical connection structures 11 one to one, and each second detection circuit 32 controls the corresponding second switch unit 50 to be turned on or off according to the voltage variation on the second side of the electrical connection structure 11 corresponding to the second detection circuit 32.

In this embodiment, since the switch units are disposed at both ends of each electrical connection structure 11, only when the electrical connection structure 11 is detected to have no fault, the first switch unit 40 and the second switch unit 50 at both ends of the electrical connection structure 11 are turned on, before the semiconductor device is powered on, and when the electrical connection structure 11 has a fault, the first switch unit 40 and the second switch unit 50 at both ends of the electrical connection structure 11 are in an off state, that is, the first side of each electrical connection structure 11 is isolated by the respective first switch unit 40, each first switch unit 40 is controlled by the independent first detection circuit 22, the second side of each electrical connection structure 11 is isolated by the respective second switch unit 50, and each second switch unit 50 is controlled by the independent second detection circuit 32, so as to improve the influence on other electrical connection structures 11 caused by a fault of one electrical connection structure 11, such as a short circuit, further ensuring the reliability of the circuit structure.

In the embodiment that the electrical connection structure 11 is multiple, the specific structures of the first detection circuit 22, the charging circuit 21, the second detection circuit 32, and the discharging circuit 31 refer to the foregoing description, and are not repeated herein.

It should be noted that in the embodiment where there are a plurality of electrical connection structures 11, the detection for each electrical connection structure 11 may be performed simultaneously, or the detection may be performed for a plurality of electrical connection structures 11 sequentially in a predetermined order. In addition, when it is detected that more than 1 of the plurality of electrical connection structures 11 is normal, the normal electrical connection structures 11 may be all turned on, or the first circuit module 20 and the second circuit module 30 are used to control the first switch unit 40 and the second switch unit 50 at two ends of one electrical connection structure 11 of the N electrical connection structures 11 to be turned on, that is, when it is detected that one electrical connection structure 11 is normal, the first switch unit 40 and the second switch unit 50 of the electrical connection structure 11 are turned on, the electrical connection structure 11 is used to transmit data, and the other electrical connection structures 11 are used as a backup. Thus, the service life of the circuit structure can be further prolonged.

In the embodiment of the present disclosure, the electrical connection structures 11 are arranged in parallel, and the first switch unit 40 and the second switch unit 50 isolate the electrical connection structures 11, so that when a short circuit occurs in one of the electrical connection structures 11, the current does not affect the other electrical connection structures 11, thereby ensuring normal data transmission.

An exemplary embodiment of the present disclosure also provides a control method of a circuit configuration for controlling the circuit configuration, for example, as described above. The circuit structure includes an electrical connection module 10, the electrical connection module 10 includes N electrical connection structures 11, and two ends of each electrical connection structure 11 are respectively connected to a first data terminal 60 and a second data terminal 70, as shown in fig. 8, the control method includes the following steps:

and S100, controlling the voltage change of the first side and the second side of the electric connection structure.

Illustratively, the charging circuit 21 is controlled to charge the electrical connection structure 11, and then the discharging circuit 31 is controlled to discharge the electrical connection structure 11, thereby controlling the voltage variation of the first side and the second side of the electrical connection structure 11.

S200, controlling the electric connection structure to be connected with or disconnected from the first data end according to the voltage change of the first side of the electric connection structure, and controlling the electric connection structure to be connected with or disconnected from the second data end according to the voltage change of the second side of the electric connection structure.

In this step, whether the electrical connection structure 11 is normal is determined according to the voltage variation of the first side and the second side of the electrical connection structure 11, and when the electrical connection structure 11 is normal, the electrical connection structure 11 is conducted with the first data terminal 60 and the second data terminal 70, so that the subsequent data transmission is performed between the first data terminal 60 and the second data terminal 70 through the electrical connection structure 11 determined to be normal.

S300, when the electric connection structure is conducted with the first data end and the second data end, control data are transmitted from the first data end to the second data end, or control data are transmitted from the second data end to the first data end.

In the control method provided by the embodiment of the disclosure, whether the electrical connection structure 11 is normal is determined according to the voltage changes of the first side and the second side of the electrical connection structure 11, when the electrical connection structure 11 is normal, the electrical connection structure 11 is conducted with the first data terminal 60 and the second data terminal 70, and when the electrical connection structure 11 fails, the electrical connection structure 11 is disconnected with the first data terminal 60 and the second data terminal 70, so that when the electrical connection structure 11 is conducted with the first data terminal 60 and the second data terminal 70, data can be transmitted from the first data terminal 60 to the second data terminal 70 through the electrical connection structure 11, and can be transmitted from the second data terminal 70 to the first data terminal 60 through the electrical connection structure 11, so that the electrical connection structure 11 can implement bidirectional data transmission, and the performance of an electrical device such as a semiconductor device adopting the control method is improved.

In an exemplary embodiment, step S100 specifically includes the following steps:

s110, setting a first side and a second side of the electric connection structure to be a first voltage level through a charging circuit;

and S120, setting the first side and the second side of the electric connection structure to be at a second voltage level through a discharge circuit.

The first side and the second side of the electrical connection structure 11 are set to the first voltage level by the charging circuit 21, and the first side and the second side of the electrical connection structure 11 are set to the second voltage level by the discharging circuit 31, if the electrical connection structure 11 is normal, the voltage level changes at both the first side and the second side of the electrical connection structure 11, so that the electrical connection structure 11 can be controlled to be conducted with the first data terminal 60 and the second data terminal 70 according to the change.

Specifically, in this embodiment, the step S200 specifically includes the following steps:

s210, in response to the voltage on the first side of the electric connection structure changing from a first voltage level to a second voltage level, the first switch unit between the electric connection structure and the first data end is controlled to be conducted through the first detection circuit.

For example, the first switching unit 40 may be controlled to be turned on or off by the trigger outputting a control signal to the first switching unit 40 according to a voltage variation of the first side of the electrical connection structure 11. For example, if the first flip-flop 221 is a rising edge flip-flop, in response to the clock input terminal of the first flip-flop 221 of the first detection circuit 22 detecting the first rising edge signal, the output terminal of the first flip-flop 221 outputs a first control signal to the control terminal of the first switch unit 40 to control the first switch unit 40 to turn on the path of the electrical connection structure 11 and the first data terminal 60.

In this embodiment, when the first side voltage of the electrical connection structure 11 changes from the first voltage level to the second voltage level, the first rising edge signal can be detected at the clock input terminal of the first flip-flop 221, so that the output terminal of the first flip-flop 221 outputs a high level to control the first switch unit 40 to be turned on. As an example, in response to the voltage of the first side of the electrical connection structure 11 being charged to the first voltage level, the first inverter 222 of the first detection circuit 22 converts the first high level signal of its input terminal into the first low level signal and inputs the first low level signal to the clock input terminal of the first flip-flop 221.

In response to the voltage on the first side of the electrical connection structure 11 changing from the first voltage level to the second voltage level, the first inverter 222 converts the third low level signal at its input terminal into the third high level signal at its output terminal, and inputs the third high level signal to the clock input terminal of the first flip-flop 221, so that the clock input terminal of the first flip-flop 221 can detect the first rising edge signal, thereby outputting a high level to control the first switch unit 40 to be turned on.

And S220, in response to the voltage on the second side of the electric connection structure changing from the first voltage level to the second voltage level, controlling the second switch unit between the electric connection structure and the second data terminal to be conducted through the second detection circuit.

Similarly to step S210, in response to the clock input terminal of the second flip-flop 321 of the second detection circuit 32 detecting the second rising edge signal, the output terminal of the second flip-flop 321 outputs a second control signal to the control terminal of the second switch unit 50 to control the second switch unit 50 to turn on the path of the electrical connection structure 11 and the second data terminal 70.

Illustratively, in response to the voltage on the second side of the electrical connection structure 11 being charged to the second voltage level, the second inverter 322 of the second detection circuit 32 converts the second high level signal at its input terminal into the second low level signal at its output terminal, and inputs the second low level signal to the clock input terminal of the second flip-flop 321.

In response to the voltage on the second side of the electrical connection structure 11 changing from the second voltage level to the first voltage level, the second inverter 322 converts the fourth low level signal at its input terminal into the fourth high level signal at its output terminal, and inputs the fourth high level signal to the clock input terminal of the second flip-flop 321, so that the clock input terminal of the second flip-flop 321 can detect the second rising edge signal, thereby outputting a high level to control the second switch unit 50 to be turned on.

In an exemplary embodiment of the present disclosure, the control method further includes the steps of:

and S10, in response to the power-on signal not being received, inputting a fifth high level signal to the clock input end of the first trigger.

When the power-on signal is not received, i.e., in the power-off state, a fifth high level signal is input to the clock input terminal of the first flip-flop 221, i.e., the clock input terminal Clk of the first flip-flop 221 is set to "1", so as to ensure that no rising edge is generated at the clock input terminal Clk of the first flip-flop 221 before power-on, i.e., the first switch unit 40 is not controlled to be turned on, thereby ensuring the reliability of the circuit structure.

Illustratively, in particular, in response to not receiving the power-up signal, the input of the first inverter 222 is grounded such that the output of the first inverter 222 forms a fifth high level signal, and the fifth high level signal is input to the clock input of the first flip-flop 221.

And S20, in response to the power-on signal not being received, inputting a sixth high level signal to the clock input end of the second trigger.

When the power-on signal is not received, that is, in a power-off state, a sixth high level signal is input to the clock input terminal of the second flip-flop 321, that is, the clock input terminal Clk of the second flip-flop 321 is set to "1", so that it is ensured that before power-on, a rising edge is not generated at the clock input terminal Clk of the second flip-flop 321, that is, the second switch unit 50 is not controlled to be turned on, and thus the reliability of the circuit structure is ensured.

Illustratively, in particular, in response to not receiving the power-up signal, the input terminal of the second inverter 322 is grounded such that the output terminal of the second inverter 322 forms a sixth high level signal, and the sixth high level signal is input to the clock input terminal of the second flip-flop 321.

and S30, in response to not receiving the power-on signal, controlling the first detection circuit to open the first switch unit.

In this step, when the power-on signal is not received, i.e., in the power-off state, the first switch unit 40 is turned off, so as to ensure the effectiveness in the next power-on detection.

As an example, specifically, in response to the reset terminal of the first flip-flop 221 of the first detection circuit 22 not detecting the power-on signal, the output terminal of the first flip-flop 221 outputs a third control signal to the control terminal of the first switching unit 40 to control the first switching unit 40 to be turned off.

And S40, in response to not receiving the power-on signal, controlling the second detection circuit to open the second switch unit.

In this step, when the power-on signal is not received, i.e., in the power-off state, the second switch unit 50 is turned off, so as to ensure the effectiveness in the next power-on detection.

As an example, specifically, in response to the reset terminal of the second flip-flop 321 of the second detection circuit 32 not detecting the power-on signal, the output terminal of the second flip-flop 321 outputs a fourth control signal to the control terminal of the second switch unit 50 to control the second switch unit 50 to turn off.

The following describes a control method of the circuit structure provided in the embodiment of the present disclosure in detail with reference to a timing chart shown in fig. 9. Taking the control of the first detection circuit 22 and the first switch unit 40 as an example, before the point a, i.e. before the power is not powered, the power-on signal is at a low voltage, so that the reset terminal RN of the first flip-flop 221 is at a low voltage, the control terminal of the first switch unit 40 is at a low voltage, and the first switch unit 40 is turned off. The inverted signal of the power-up signal is a high voltage, so that the gate of the first transistor 223 is a high voltage, the first transistor 223 is turned on, the input terminal of the first inverter 222 is grounded, and the output terminal of the first inverter 222 outputs a high voltage, that is, the clock input terminal Clk of the first flip-flop 221 is set to "1".

After power-up at point a, the first transistor 223 is turned off, and the state of the first switching unit 40 is unchanged.

At point B, the charge driving signal PDRV outputs a low voltage, so that the first pole and the second pole of the third transistor 211 are turned on, the electric connection structure 11 is charged, the input terminal of the first inverter 222 is a high voltage, and the output terminal of the first inverter 222 outputs a low voltage to the clock input Clk of the first flip-flop 221, that is, the clock input Clk of the first flip-flop 221 is set to "0".

At the point C, the charge driving signal PDRV output is changed from a low voltage to a high voltage, so that the first and second poles of the third transistor 211 are turned off, and the state of the first switching unit 40 is not changed.

At the point D, the discharge driving signal NDRV outputs a high voltage, so that the first pole and the second pole of the fourth transistor 311 are turned on, the electric connection structure 11 is discharged, the input terminal of the first inverter 222 becomes a low voltage, the output terminal of the first inverter 222 outputs a high voltage to the clock input Clk of the first flip-flop 221, so that a rising edge is generated at the clock input Clk of the first flip-flop 221, and the output terminal of the first flip-flop 221 outputs a high voltage (TSV on) to the first switching unit 40, so as to turn on the first switching unit 40.

If the clock input Clk of the first flip-flop 221 does not detect a rising edge, it indicates that the electrical connection structure 11 is faulty, and the output of the first flip-flop 221 will not output a high voltage to turn on the first switch unit 40.

The control process of the second detection circuit 32 and the second switch unit 50 is similar to that of the first detection circuit 22 and the second switch unit 50, and is not described herein again.

The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (devices) and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In the present disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of additional like elements in the article or device comprising the element.

While preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the disclosure.

It will be apparent to those skilled in the art that various changes and modifications may be made to the disclosure without departing from the spirit and scope of the disclosure. Thus, it is intended that the present disclosure also cover the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.

Claims

1. A circuit structure, comprising:

2. The circuit structure of claim 1, wherein the first circuit module comprises N charging circuits and N first detection circuits, a first end of each of the first detection circuits and the charging circuit are connected to a first side of the corresponding electrical connection structure, and a second end of each of the first detection circuits is connected to a control end of the first switch unit;

3. The circuit structure of claim 2, wherein the first detection circuit comprises a first flip-flop and a first inverter, an output terminal of the first flip-flop is connected to the control terminal of the first switching unit, a clock input terminal of the first flip-flop is connected to an output terminal of the first inverter, and an input terminal of the first inverter is connected to the first side of the corresponding electrical connection structure;

4. The circuit structure of claim 3, wherein the first detection circuit comprises a first transistor, the input terminal of the first inverter is connected to the first pole of the first transistor, the second pole of the first transistor is connected to ground, and the gate of the first transistor is connected to the inverse of the electrical signal;

5. The circuit structure according to claim 3, wherein the reset terminal of the first flip-flop is connected with an upper electrical signal, and the first flip-flop is configured to reset the output terminal thereof to control the first switching unit to be turned off when the reset terminal thereof does not receive a power-on signal;

6. Circuit arrangement according to one of claims 2 to 5, characterized in that N is greater than or equal to 2,

7. The circuit structure according to any one of claims 1 to 5, wherein the first circuit module and the second circuit module are configured to control the conduction of the first switch unit and the second switch unit at two ends of one of the N electrical connection structures.

8. The circuit structure according to any one of claims 1 to 5, wherein the electrical connection structure is a through-silicon-via structure, the first circuit module is disposed in a first semiconductor unit, and the second circuit module is disposed in a second semiconductor unit.

9. A control method of a circuit structure is characterized in that the circuit structure comprises an electric connection module, the electric connection module comprises N electric connection structures, N is a positive integer greater than or equal to 1, two ends of each electric connection structure are respectively connected with a first data end and a second data end, and the control method comprises the following steps:

10. The method of claim 9, wherein said controlling the voltage change on the first and second sides of the electrical connection structure comprises:

11. The method of claim 10, wherein the controlling the first switching unit between the electrical connection structure and the first data terminal to conduct through the first detection circuit in response to the voltage on the first side of the electrical connection structure changing from the first voltage level to the second voltage level comprises:

12. The control method according to claim 11, characterized by further comprising:

13. The control method according to claim 12, characterized by further comprising:

14. The method of claim 13, wherein inputting a fifth high signal to the clock input of the first flip-flop in response to not receiving a power-up signal comprises:

15. The control method according to claim 10, characterized by further comprising:

in response to not receiving a power-on signal, controlling the second detection circuit to turn off the second switch unit;