CN115241293B - High-speed soft recovery high-voltage Schottky diode device and manufacturing method - Google Patents

High-speed soft recovery high-voltage Schottky diode device and manufacturing method Download PDF

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CN115241293B
CN115241293B CN202210677774.2A CN202210677774A CN115241293B CN 115241293 B CN115241293 B CN 115241293B CN 202210677774 A CN202210677774 A CN 202210677774A CN 115241293 B CN115241293 B CN 115241293B
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adopting
doped region
silicon dioxide
doping
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CN115241293A (en
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陈晓伦
朱涛
韩笑
崔鹏
李建立
朱瑞
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Jiangsu Xinshun Microelectronics Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66143—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

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Abstract

The invention discloses a high-speed soft recovery high-voltage Schottky diode device and a manufacturing method thereof. A high-speed soft-recovery high-voltage Schottky diode device includes a silicon substrate; the back of the silicon substrate is provided with a back electrode metal layer, and a first doping region and a second doping region which are alternately arranged are arranged above the back electrode metal layer; a third doped region is arranged above the first doped region and the second doped region; a fourth doped region is arranged on the upper side of the silicon substrate, and a fifth doped region is arranged in the fourth doped region; a metal silicide layer serving as a Schottky barrier is arranged above the silicon substrate between the fourth doped regions and the adjacent fourth doped regions; a sixth doped region is arranged on the right side of the fourth doped region; and a silicon dioxide layer is arranged above the right area of the fourth doped region. A front electrode metal layer is arranged above the metal silicide layer and the silicon dioxide layer; and a silicon nitride passivation layer is arranged above the front electrode metal layer and the silicon dioxide layer. The invention reduces reverse recovery time and improves switching speed.

Description

High-speed soft recovery high-voltage Schottky diode device and manufacturing method
Technical Field
The invention relates to the field of semiconductor devices, in particular to a diode and a manufacturing method thereof.
Background
Compared with a common PN junction diode, the Schottky diode rectifying device has lower forward voltage drop, is a multi-sub conductive device, has the advantages of short reverse recovery time and high switching speed, and is widely applied to an AC-DC power supply. However, schottky diodes have the limitation that they are multi-sub conductive, and do not have the large injection conductance modulation effect of the PN junction, so that when the reverse voltage requirement is high, the forward voltage drop is larger than that of the PN junction diode, and the trend of the reverse voltage is more obvious. In order to solve the problem, the structure design is optimized in the industry, a PN junction structure connected with the Schottky junction in parallel is introduced into the Schottky diode design, so that when the forward voltage of the Schottky junction reaches the PN junction opening voltage, the PN junction can be opened, the conductivity modulation of the substrate high-resistance layer is realized, and the forward voltage drop is reduced. However, the conductance modulation introduced by the PN junction also changes the Schottky diode from a multi-sub conductive unipolar device to a multi-sub and sub bipolar device which simultaneously participates in conduction, so that the problem of sub reverse recovery is brought along with the Schottky diode, the peak voltage of the sub hard recovery reverse recovery is high, and the switching speed is slow; the more the PN junction area is occupied, the deeper the conductivity modulation degree is, the lower the forward direction is, and the reverse recovery time is correspondingly increased, the higher the reverse recovery peak voltage is, and the slower the switching speed is; this is the highest reverse voltage of the mainstream products of the current schottky diode devices is generally within 300V, thus relatively achieving better balance performance of forward voltage drop and switching speed.
Disclosure of Invention
Aiming at the contradiction problems that the PN junction is more in duty ratio and the forward voltage drop is lower after the PN junction structure design connected with the Schottky junction in parallel is introduced to reduce the forward voltage drop in the prior art, but the switching speed is correspondingly slower and the reverse recovery peak voltage is higher, the invention provides a high-speed soft recovery high-voltage Schottky diode device, and also provides a manufacturing method of the high-speed soft recovery high-voltage Schottky diode device, which better balances the contradiction of the PN junction and the reverse voltage and improves the device performance.
The technical scheme of the invention is as follows: a high speed soft-recovery high voltage schottky diode device comprising a silicon substrate of a first conductivity type;
the back surface of the silicon substrate is provided with a back electrode metal layer, and a first doping region of a first conductivity type and a second doping region of a second conductivity type which are alternately arranged are arranged above the back electrode metal layer;
a third doped region of the first conductivity type is arranged above the first doped region and the second doped region, and the third doped region is positioned on the lower side of the silicon substrate;
a fourth doped region of the second conductivity type is arranged on the upper side of the silicon substrate, and a fifth doped region of the first conductivity type is arranged in the fourth doped region;
a metal silicide layer serving as a Schottky barrier is arranged above the silicon substrate between the fourth doped regions and the adjacent fourth doped regions;
a sixth doped region of the second conductivity type is arranged on the right side of the fourth doped region;
the right area of the fourth doping area is a terminal structure area, and silicon dioxide layers with different thicknesses are arranged above the terminal structure area;
a front electrode metal layer is arranged above the left side area of the metal silicide layer and the silicon dioxide layer;
and a silicon nitride passivation layer is covered on the right side area of the silicon dioxide layer and the upper side of the front electrode metal layer.
According to the invention, the fourth doped region and the fifth doped region with different introduced conductive types are in short circuit, namely the fourth doped region inherits the advantage of reducing forward direction by minority carrier injection conductivity modulation effect of PN junction, and meanwhile, the N-type and P-type short circuit structure has the advantages that the zero bias self-built electric field can quickly absorb injected minority carriers in the surrounding area, and the injected minority carrier can be converted into multi-carrier current to flow out of the heavily doped ohmic contact electrode; compared with the normal minority carrier recombination, the speed is greatly increased, the reverse recovery time is further reduced, and the switching speed is improved.
The right end of the metal silicide layer extends to the right side right above the fourth doped region. The left end of the silicon dioxide layer extends to right above the rightmost fourth doped region. The top of the silicon dioxide layer is higher than the top of the metal silicide layer.
The silicon dioxide layer comprises a first region and a third region, wherein the first region is positioned above the right side of the fourth doped region, the third region is positioned above the center of the sixth doped region, a second region is arranged between the first region and the third region, and the third region is clamped between the second region and the fourth region. The thickness of the first region is lower than that of the third region, the thickness of the third region is lower than that of the second region and that of the fourth region, and the thickness of the second region is matched with that of the fourth region.
The front electrode metal layer and the silicon nitride passivation layer are connected with the third region.
Further preferably, the fourth doped regions are arranged in an array.
Further preferably, the first doped region and the second doped region are adjacently arranged and arranged in an array.
Further preferably, the silicon substrate has a thickness of 20 μm to 250 μm and a resistivity of 2. Omega. Cm to 200. Omega. Cm.
Further preferably, the depth of the first doped region is 0.2-1.0 μm, and the average net doping concentration is 5E18-1E20;
the depth of the second doped region is 0.3-1.5 mu m, the average net doping concentration is 2E18-1E20, the width is 1-5 mu m, and the adjacent spacing is 2-50 mu m;
the depth of the third doped region is 0.5-2.0 mu m, and the average net doping concentration is 1E16-1E18;
the depth of the fourth doped region is 1.0-5.0 mu m, the average net doping concentration is 1E17-5E19, the width is 1 mu m-5 mu m, and the distance between the adjacent fourth doped regions is 5 mu m-50 mu m;
the depth of the fifth doped region is 0.5-4.0 mu m, and the average net doping concentration is 5E18-1E20;
the lateral distance between the sixth doped region and the fourth doped region is 2-15 μm.
Further preferably, the first conductivity type is N-type, and the second conductivity type is P-type;
alternatively, the first conductivity type is P-type and the second conductivity type is N-type.
The manufacturing method of the high-speed soft recovery high-voltage Schottky diode device is characterized by comprising the following steps of:
firstly, taking an N-type doped silicon substrate, and growing a silicon dioxide layer on the front surface of the silicon substrate by adopting a thermal oxidation process;
coating a first photoresist layer on the silicon dioxide layer grown in the step II, patterning the first photoresist layer by adopting a photoetching process, forming a process window on the silicon dioxide layer grown in the step II by wet etching or dry etching to expose the surface of the silicon substrate, and removing the first photoresist layer;
step three, doping the exposed process window by using the reserved silicon dioxide layer as a masking film and adopting a boron ion implantation process; then carrying out silicon dioxide thermal oxidation growth and impurity injection redistribution diffusion by adopting a furnace tube process, and finally forming a sixth doped region of the P type doping type; the thickness of the remained silicon dioxide layer is thickened, and a silicon dioxide layer is newly formed on the exposed process window;
coating a second photoresist layer, forming a photoresist pattern on the second photoresist layer by adopting a photoetching process, etching the silicon dioxide layer by adopting a dry etching process to form a bare silicon surface process window, and removing the second photoresist layer;
step five, doping the exposed process window by using the reserved silicon dioxide layer as a masking film and adopting a boron ion implantation process; then adopting a furnace tube to carry out impurity injection, redistributing and diffusing, synchronously newly growing a silicon dioxide thin layer on the exposed process window, and finally forming a fourth doping region of the P type doping type;
step six, using a thicker silicon dioxide layer adjacent to the silicon dioxide thin layer as a masking film, doping a process window at the silicon dioxide thin layer by adopting a phosphorus ion implantation process, and implanting ions to penetrate through the silicon dioxide thin layer; then adopting a furnace tube to carry out impurity injection, redistribution and diffusion, and slightly thickening the thickness of the synchronous silicon dioxide thin layer to finally form a fifth doping region of the N type doping type;
step seven, coating a third photoresist layer, forming a photoresist pattern on the third photoresist layer by adopting a photoetching process, forming a bare silicon surface process window on the silicon dioxide layer on the front surface of the silicon substrate by wet etching or dry etching, and removing the third photoresist layer;
depositing a metal layer serving as a Schottky contact barrier by adopting a PVD (physical vapor deposition) process, and then adopting a furnace tube heat treatment or a rapid annealing heat treatment process to enable the metal layer deposited on the surface of silicon of the exposed process window and silicon alloy to form metal silicide, wherein the metal layer on the silicon dioxide layer basically does not react with silicon dioxide; then removing the metal layer on the silicon dioxide layer by adopting a wet etching process, wherein the metal silicide formed by heat treatment basically does not react with etching liquid of wet etching and is reserved, the metal silicide forms Schottky rectifying contact with the front silicon of the silicon substrate, and the metal silicide forms ohmic contact with the fourth doped region and the fifth doped region;
step nine, adopting a PVD process to deposit a layer of front electrode metal layer, and then adopting a photoetching process wet etching process to form a required pattern;
step ten, depositing a silicon nitride passivation layer by adopting a CVD process, and then etching a bonding area window by adopting a photoetching process in a dry way;
step eleven, thinning the back surface of the silicon substrate to a required thickness by adopting a mechanical grinding mode, and then corroding and grinding the exposed silicon surface by adopting a wet silicon corrosion process to remove a mechanical damage layer and a stress layer;
step twelve, doping the back surface of the silicon substrate twice by adopting a phosphorus ion implantation process to form a third doping region of the doping type in the N type;
thirteenth, doping the back surface of the silicon substrate by adopting a phosphorus ion implantation process to form a first doping region of an N type doping type;
fourteen, coating a fourth photoresist layer on the back surface of the silicon substrate, forming a photoresist pattern on the fourth photoresist layer by adopting a photoetching process, masking by utilizing the photoresist pattern, doping the back surface twice by adopting a boron ion implantation process, and removing the photoresist to form a second doping region of a P type doping type;
fifteen, activating impurities injected into the first doped region, the second doped region and the third doped region by adopting a laser annealing activation technology on the back surface of the silicon substrate;
sixthly, a back electrode metal layer is deposited on the back of the silicon substrate by adopting a PVD process.
Further preferably, in the first step, the thickness of the silicon oxide layer is 0.5 μm to 1.0 μm.
Further preferably, in the step three, in the boron ion implantation process, the ion implantation energy is 40keV to 200keV, and the implantation dosage is 1E12 to 5E13;
the thickness of the newly grown silicon dioxide layer on the exposed process window is 1.0-2.0 mu m;
the process of impurity injection redistribution diffusion has constant temperature controlled in 1100-1250 deg.c and constant temperature time of 60-550 min.
Further preferably, in the fifth step, in the boron ion implantation process, the ion implantation energy is 40keV to 200keV, and the implantation dose is 2E14 to 1E16;
the process of impurity injection redistribution diffusion has the constant temperature control range of 1100-1250 ℃ and the constant temperature time of 60-500 min;
the thickness of the silica thin layer is 0.1 μm or less.
Further preferably, in the step six, in the phosphorus ion implantation process, the ion implantation energy is 70keV to 200keV, and the implantation dosage is 5E15 to 1.5E16;
the process of impurity implantation redistribution diffusion has constant temperature controlled in 1000-1200 deg.c and constant temperature time of 60-500 min.
Further preferably, the metal layer in the step eight may be a nickel-platinum alloy metal layer.
Further preferably, in the step twelve, in the two phosphorus ion implantation processes, the ion implantation energy of the first implantation process is 200keV-1000keV, and the implantation dosage is 5E13-2E15; the ion implantation energy of the second implantation process is 100keV-500keV, and the implantation dosage is 5E13-2E15.
Further preferably, in the step thirteenth, in the phosphorus ion energy implantation process, the ion implantation energy is 40keV to 70keV, and the implantation dose is 2E15 to 5E15.
Further preferably, in the fourteen steps, in the two boron ion implantation processes, the ion implantation energy of the first implantation process is 80keV to 200keV, and the implantation dosage is 5E14 to 5E15; the ion implantation energy of the second implantation process is 30keV-50keV, and the implantation dosage is 5E15-1E16.
On the basis of conforming to the common knowledge in the field, the above preferred conditions can be arbitrarily combined to obtain the preferred examples of the invention.
The invention has the positive progress effects that:
1) The introduced N-type and P-type short circuit structures, namely the fourth doped region inherits the advantage of reducing the forward direction by the minority carrier injection conductivity modulation effect of the PN junction, and meanwhile, the zero bias self-built electric field of the N-type and P-type short circuit structures can quickly absorb the injected minority carrier in the surrounding area, and is converted into multi-minority carrier current to flow out of the heavily doped ohmic contact electrode; compared with the normal minority carrier recombination, the speed is greatly increased, the reverse recovery time is further reduced, and the switching speed is improved.
2) The absorption speed and minority carrier distribution of injected minority carriers can be adjusted by adjusting and matching the distribution layout and density of the N-type and P-type short circuit structures, the concentration difference and junction depth difference of the N-type and P-type short circuit structures, so that the soft recovery characteristic is further optimized, and the reverse recovery peak voltage is reduced.
3) Compared with the prior art, the manufacturing method of the invention has the advantages that: the front N-type and P-type short circuit structure adopts a self-alignment process, the process flow is simple, no alignment requirement is required by etching, the N-type P-type junction depth difference realizes the horizontal and longitudinal omnibearing equidistant, and the minority carrier absorption effect is optimal. The structure of the primary cell of the sixth doping region and the fourth doping region of the terminal electric field expansion is designed separately, the electric field expansion function is achieved to improve the breakdown voltage during reverse bias, and the electric field is reduced and does not participate in forward conduction during forward conduction, so that minority carrier injection is not generated to influence the reverse recovery time. And for the N-type and P-type short circuit structures on the back surface, the third doped region of the P-type heavily doped region adopts a photoresist masking injection process, but does not need to be aligned with other patterns, and the difficulty is reduced.
Drawings
FIG. 1 is a schematic cross-sectional view of the present invention;
FIG. 2 is a cross-sectional view of the embodiment 1 of the present invention after step one;
FIG. 3 is a cross-sectional view of the second embodiment of the invention after step 1;
FIG. 4 is a cross-sectional view of the embodiment 1 of the present invention after step three;
FIG. 5 is a cross-sectional view of the embodiment 1 after step four;
FIG. 6 is a cross-sectional view of the embodiment of the invention after step five;
FIG. 7 is a cross-sectional view of the embodiment 1 after step six;
FIG. 8 is a cross-sectional view of the embodiment 1 of the present invention after step seven;
FIG. 9 is a cross-sectional view of the embodiment 1 of the present invention after step eight;
FIG. 10 is a cross-sectional view of embodiment 1 of the present invention after step nine;
FIG. 11 is a cross-sectional view of embodiment 1 of the present invention after step ten;
FIG. 12 is a cross-sectional view of the embodiment 1 of the present invention after step eleven;
FIG. 13 is a cross-sectional view of the embodiment 1 of the present invention after twelve and thirteen steps;
FIG. 14 is a cross-sectional view of the invention after fourteen steps in embodiment 1;
fig. 15 is a cross-sectional view of embodiment 1 of the present invention after sixteen steps.
Wherein: 1 is a silicon substrate, 2 is a silicon dioxide layer, 3 is a first process window, 4 is a sixth doped region, 5 is a second process window, 6 is a fourth doped region, 7 is a fifth doped region, 8 is a third process window, 9 is a metal silicide, 10 is a front electrode metal layer, 11 is a silicon nitride passivation layer, 12 is a third doped region, 13 is a first doped region, 14 is a second doped region, and 15 is a back electrode metal layer.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
Referring to fig. 1, in embodiment 1, a typical reverse operating voltage of 1200V is taken as an example of a diode product with a maximum forward conduction current of 10A;
a high-speed soft recovery high-voltage Schottky diode device comprises an N-type lightly doped silicon substrate 1, wherein a back electrode metal layer 15 is arranged on the back of the silicon substrate; the back surface of the silicon substrate is provided with first doped regions 13 of N type heavy doping type and second doped regions 14 of P type heavy doping type which are alternately arranged in an array; third doped regions 12 of the N type are arranged above the first doped regions and the second doped regions which are alternately arranged in an array;
the left side of the front surface of the silicon substrate 1 is provided with fourth doped regions 6 of P type heavy doping types which are arranged in an array; a fifth doped region 7 of an N type heavy doping type is arranged in the fourth doped region; a metal silicide layer 9 serving as a Schottky barrier is arranged above the fourth doped region and the silicon substrate between the adjacent fourth doped regions; a sixth doped region 4 of P type light doping type is arranged on the right side of the fourth doped region 6, the right region of the fourth doped region is a terminal structure region, and silicon dioxide layers 2 with different thicknesses are arranged above the terminal structure region; a front electrode metal layer 10 is arranged above the left side areas of the metal silicide layer 9 and the silicon dioxide layer 2; the right region of the silicon dioxide layer 2 and the top of the front electrode metal layer 10 are covered with a silicon nitride passivation layer 11.
The thickness of the silicon substrate is 110 μm-130 μm, and the resistivity is 40 Ω.cm-50Ω.cm.
The depth of the first doped region is 0.3-0.5 mu m, and the average net doping concentration is 1E19-3E19.
The depth of the second doped region is 0.4-1.0 mu m, the average net doping concentration is 5E18-5E19, the width is 3-5 mu m, and the adjacent spacing is 20-25 mu m.
The depth of the third doped region is 1.0-1.5 mu m, and the average net doping concentration is 1E16-1E17.
The depth of the fourth doped region is 3.0-4.0 mu m, the average net doping concentration is 5E17-5E18, the width is 5-7 mu m, and the adjacent interval is 20-25 mu m.
The depth of the fifth doped region is 1.0-3.0 mu m, and the average net doping concentration is 1E19-1E20.
The lateral distance between the sixth doped region and the fourth doped region is 10 μm-15 μm.
According to the invention, the advantages of forward direction reduction are inherited by the introduced N-type and P-type short circuit structures, namely the fourth doped region, such that the minority carrier injection conductivity modulation effect of the PN junction is reduced, and simultaneously, the N-type and P-type short circuit structures are designed on the front surface and the back surface, so that the zero bias self-built electric field can quickly absorb the minority carrier injection in the surrounding area, and the minority carrier injection current is converted into the majority carrier current to flow out of the heavily doped ohmic contact electrode; compared with the normal minority carrier recombination, the speed is greatly increased, the reverse recovery time is further reduced, and the switching speed is improved. On the other hand, the absorption speed and minority carrier distribution of injected minority carriers can be adjusted by adjusting and matching the distribution layout and density of the N-type and P-type short circuit structures, the concentration difference and junction depth difference of the N-type and P-type short circuit structures, soft recovery characteristics are realized by adjusting and optimizing, and reverse recovery peak voltage is reduced.
When the embodiment is applied to an actual circuit, the front electrode metal layer is the anode of the diode device, and the back electrode metal layer is the cathode of the diode device.
Referring to fig. 2-15, a typical reverse operating voltage of 1200V and a maximum forward conduction current of 10A is taken as an example of a diode product; a manufacturing method of a high-speed soft recovery high-voltage Schottky diode device is based on a 6-inch silicon wafer manufacturing process and comprises the following steps:
step one, an N-type lightly doped silicon substrate 1 is taken. The thickness of the silicon substrate is 110 μm-130 μm, and the resistivity is 40 Ω.cm-50Ω.cm. Growing a silicon dioxide layer 2 on the front surface by adopting a furnace tube thermal oxidation process; the furnace tube thermal oxidation adopts an oxyhydrogen synthesis oxidation process, and the process time is controlled to be 80-100 min for the oxyhydrogen synthesis oxidation stage; the temperature in the furnace tube is controlled between 1095 ℃ per minute and 1105 ℃ per minute, and oxygen (O) synthesized by oxyhydrogen 2 ) The gas flow is controlled to be 5.9L/min-6.1L/min, and hydrogen (H) synthesized by oxyhydrogen 2 ) The gas flow is controlled to be 10.3L/min-10.7L/min, and the hydrogen chloride (HCl) gas flow in the furnace tube is controlled to be 230ml/min-270ml/min; the thickness of the final silicon dioxide layer 2 is controlled to be 0.75-0.85 μm; see fig. 2;
step two, a positive first photoresist layer is coated on the silicon dioxide layer 2, and the thickness of the positive photoresist layer is controlled to be 1.0um-1.1 um; forming a pattern on the photoresist layer by adopting an exposure and development process, corroding the pattern window silicon dioxide layer by adopting hydrofluoric acid silicon dioxide corrosive liquid to form a first process window 3 of the bare silicon substrate, and finally removing the first photoresist layer; see fig. 3;
step three, using the silicon dioxide layer 2 as a masking film, doping the first process window 3 by adopting a boron ion implantation process, wherein the implantation process adopts zero-degree angle implantation, the implantation energy is 75keV-85keV, and the implantation dosage is 6E12-1E13; then carrying out silicon dioxide thermal oxidation growth and impurity injection redistribution diffusion by adopting a furnace tube process; the thermal oxidation adopts an oxyhydrogen synthesis oxidation process, and for the oxyhydrogen synthesis oxidation stage process, the temperature of a furnace tube is controlled at a constant temperature for 460-540 min; the temperature in the furnace tube is controlled between 1095 ℃ and 1105 ℃, and oxygen (O) synthesized by oxyhydrogen 2 ) The gas flow is controlled to be 5.9L/min-6.1L/min, and hydrogen (H) synthesized by oxyhydrogen 2 ) The gas flow is controlled to be 10.3L/min-10.7L/min, and the hydrogen chloride (HCl) gas flow in the furnace tube is controlled to be 230m1/min-270m1/min; the impurity redistribution furnace tube diffusion process is carried out, and at the moment, the constant temperature control time is 280-320 min; the temperature in the furnace tube is controlled between 1245 ℃ and 1255 ℃, and the nitrogen (N) in the furnace tube 2 ) The gas flow is controlled to be 9.5L/min-10.5L/min; finally forming a sixth doped region 4 of P type light doping type, wherein the thickness of the newly grown silicon dioxide layer on the exposed first process window 3 is 1.9-2.1 mu m; see fig. 4;
step four, a positive second photoresist layer is coated, and the thickness of the positive photoresist layer is controlled to be 1.4um-1.6 um; forming a pattern on the photoresist layer by adopting an exposure and development process, etching the silicon dioxide layer of the pattern window by adopting a plasma dry etching process to form a second process window 5 of the bare silicon substrate, and finally removing the second photoresist layer; see fig. 5;
fifthly, doping the second process window 5 by using the reserved silicon dioxide layer as a masking film and adopting a boron ion implantation process; the injection process adopts zero-degree injection, the injection energy is 75keV-85keV, and the injection dosage is 4E14-6E14; then adopting a furnace tube to carry out impurity injection redistribution diffusion process, wherein the temperature of the furnace tube is controlled at a constant temperature for 60-100 min; the temperature in the furnace tube is controlled to be 1145 ℃/min-1155 ℃, and the nitrogen (N) in the furnace tube 2 ) The gas flow is controlled to be 9.5L/min-10.5L/min, and oxygen (O) in the furnace tube 2 ) Controlling the gas flow rate at 75ml/min-85ml/min; finally forming a fourth doped region 6 of the P type heavy doping type, wherein the thickness of the newly grown silicon dioxide layer on the second process window 5 of the bare silicon substrate is 0.015-0.025 mu m; see fig. 6:
step six, using a thicker region in the silicon dioxide layer as a masking film, doping the second process window 5 by adopting a phosphorus ion implantation process, and enabling the implantation ions to penetrate through the silicon dioxide thin layer on the second process window 5; the injection process adopts zero-degree injection, the injection energy is 75keV-85keV, and the injection dosage is 6E15-7E15; then adopting a furnace tube to carry out impurity injection redistribution diffusion process, wherein the temperature of the furnace tube is controlled at constant temperature for 30-100 min; the temperature in the furnace tube is controlled between 1045 ℃ and 1055 ℃, and the nitrogen (N) in the furnace tube 2 ) The gas flow is controlled to be 9.5L/min-10.5L/min, and oxygen (O) in the furnace tube 2 ) Controlling the gas flow rate at 75ml/min-85ml/min; finally forming a fifth doped region 7 of an N type heavy doping type, wherein the thickness of the silicon dioxide layer on the second process window 5 is 0.015-0.03 mu m; see fig. 7;
step seven, a positive third photoresist layer is coated, and the thickness of the positive photoresist layer is controlled to be 1.4-umn-1.6 mu m; forming a pattern on the photoresist layer by adopting an exposure and development process, corroding the pattern window silicon dioxide layer by adopting hydrofluoric acid silicon dioxide corrosive liquid to form a third process window 8 of the bare silicon substrate, and finally removing the third photoresist layer; see fig. 8;
depositing a nickel-platinum alloy metal layer serving as a Schottky contact barrier by adopting a PVD (physical vapor deposition) process, wherein the thickness of the nickel-platinum alloy metal layer is 0.04-0.06 mu m; then carrying out alloy by adopting a furnace tube heat treatment process, wherein the furnace tube constant temperature time is 55-65 min; the temperature in the furnace tube is controlled to be 480-500 ℃ at constant temperature, and nitrogen (N) in the furnace tube 2 ) The gas flow is controlled to be 9.5L/min-10.5L/min; the alloying process is heat treated such that the metal layer deposited on the silicon surface of the third process window 8 forms a metal silicide with the silicon alloy, while the metal layer on the silicon dioxide layer does not substantially react with the silicon dioxide; then the aqua regia corrosive liquid is adopted to corrode and remove the metal layer on the silicon dioxide layer, and the formed metal is siliconizedThe metal silicide and the N-type lightly doped silicon substrate 1 form Schottky rectifying contact, and ohmic contact is formed between the metal silicide and the heavily doped fourth doped region and the heavily doped fifth doped region; see fig. 9;
step nine, adopting PVD technology to deposit a front electrode metal layer 10, preferably an aluminum layer, with the thickness of 4.5 μm-5.5 μm; then adopting a photoetching process wet etching process to form a required pattern; see fig. 10;
step ten, depositing a silicon nitride passivation layer 11 with the thickness of 0.6-0.8 mu m by adopting a CVD process; etching a bonding area window by adopting a photoetching process in a dry way; see fig. 11;
eleventh, thinning the back of the silicon substrate by adopting a mechanical grinding mode, controlling the final thickness to be 110-130 mu m, and then corroding and grinding the exposed silicon surface by adopting a wet silicon corrosion process to form a thickness of 2-3 mu m, and removing the mechanical damage layer and the stress layer; see fig. 12;
step twelve, doping the back surface of the silicon substrate twice by adopting a phosphorus ion high-energy implantation process; a first injection process, wherein zero-degree angle injection is performed, the injection energy is 250keV-300keV, and the injection dosage is 1E14-2E14; a second injection process, wherein zero-degree angle injection is performed, the injection energy is 150keV-180keV, and the injection dosage is 1E14-2E14; forming a third doped region 12 of the type doped in the N-type; see fig. 13;
thirteenth, doping the back surface of the silicon substrate by adopting a phosphorus ion implantation process; the injection process adopts 7-degree angle injection, the injection energy is 40keV-45keV, and the injection dosage is 3E15-4E15; forming a first doped region 13 of an N-type heavily doped type; see fig. 13;
fourteen, coating a positive fourth photoresist layer on the back surface of the silicon substrate, wherein the thickness of the positive photoresist layer is controlled to be 1.4um-1.6 um; forming a pattern on the photoresist layer by adopting an exposure and development process, masking by using the photoresist pattern, and doping the back surface by adopting a boron ion implantation process for two times; a first injection process, wherein zero-degree angle injection is performed, the injection energy is 90keV-100keV, and the injection dosage is 1E15-2E15; a second injection process, 7-degree angle injection, injection energy of 30keV-40keV and injection dosage of 6E15-8E15; removing the photoresist to form a second doped region 14 of the P type heavily doped type; see fig. 14;
fifteen, activating impurities injected into the first doped region, the second doped region and the third doped region by adopting a laser annealing activation technology on the back surface of the silicon substrate;
sixthly, a back electrode metal layer 15 is deposited on the back side of the silicon substrate by a PVD process. The metal layer is formed by combining three layers of titanium nickel silver. See fig. 15.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.

Claims (9)

1. A high speed soft-recovery high voltage schottky diode device comprising a silicon substrate of a first conductivity type;
the back surface of the silicon substrate is provided with a back electrode metal layer, and a first doping region of a first conductivity type and a second doping region of a second conductivity type which are alternately arranged are arranged above the back electrode metal layer;
a third doped region of the first conductivity type is arranged above the first doped region and the second doped region, and the third doped region is positioned on the lower side of the silicon substrate;
a fourth doped region of the second conductivity type is arranged on the upper side of the silicon substrate, and a fifth doped region of the first conductivity type is arranged in the fourth doped region; the depth of the fourth doped region is 1.0-5.0 mu m, the average net doping concentration is 1E17-5E19, the width is 1 mu m-5 mu m, and the distance between the adjacent fourth doped regions is 5 mu m-50 mu m; the depth of the fifth doped region is 0.5-4.0 mu m, and the average net doping concentration is 5E18-1E20;
a metal silicide layer serving as a Schottky barrier is arranged above the silicon substrate between the adjacent fourth doped regions;
a sixth doped region of the second conductivity type is arranged on the right side of the fourth doped region;
the right area of the fourth doping area is a terminal structure area, and silicon dioxide layers with different thicknesses are arranged above the terminal structure area;
a front electrode metal layer is arranged above the left side area of the metal silicide layer and the silicon dioxide layer;
a silicon nitride passivation layer is covered on the right side area of the silicon dioxide layer and the upper side of the front electrode metal layer,
the preparation method of the high-speed soft recovery high-voltage Schottky diode device comprises the following steps:
firstly, taking an N-type doped silicon substrate, and growing a silicon dioxide layer on the front surface of the silicon substrate by adopting a thermal oxidation process;
coating a first photoresist layer on the silicon dioxide layer grown in the step II, forming a pattern on the first photoresist layer by adopting a photoetching process, forming a process window on the silicon dioxide layer grown in the step II by adopting wet etching or dry etching, exposing the surface of the silicon substrate, and removing the first photoresist layer;
step three, doping the exposed process window by using the reserved silicon dioxide layer as a masking film and adopting a boron ion implantation process; then carrying out silicon dioxide thermal oxidation growth and impurity injection redistribution diffusion by adopting a furnace tube process, and finally forming a sixth doped region of the P type doping type; the thickness of the remained silicon dioxide layer is thickened, and a silicon dioxide layer is newly formed on the exposed process window;
coating a second photoresist layer, forming a photoresist pattern on the second photoresist layer by adopting a photoetching process, etching the silicon dioxide layer by adopting a dry etching process to form a bare silicon surface process window, and removing the second photoresist layer;
step five, doping the exposed process window by using the reserved silicon dioxide layer as a masking film and adopting a boron ion implantation process; then adopting a furnace tube to carry out impurity injection, redistributing and diffusing, synchronously newly growing a silicon dioxide thin layer on the exposed process window, and finally forming a fourth doping region of the P type doping type;
step six, using a thicker silicon dioxide layer adjacent to the silicon dioxide thin layer as a masking film, doping a process window at the silicon dioxide thin layer by adopting a phosphorus ion implantation process, and implanting ions to penetrate through the silicon dioxide thin layer; then adopting a furnace tube to carry out impurity injection, redistribution and diffusion, and slightly thickening the thickness of the synchronous silicon dioxide thin layer to finally form a fifth doping region of the N type doping type;
step seven, coating a third photoresist layer, forming a photoresist pattern on the third photoresist layer by adopting a photoetching process, forming a bare silicon surface process window on the silicon dioxide layer on the front surface of the silicon substrate by adopting wet etching or dry etching, and removing the third photoresist layer;
depositing a metal layer serving as a Schottky contact barrier by adopting a PVD (physical vapor deposition) process, and then adopting a furnace tube heat treatment or a rapid annealing heat treatment process to enable the metal layer deposited on the surface of silicon of the exposed process window and silicon alloy to form metal silicide, wherein the metal layer on the silicon dioxide layer basically does not react with silicon dioxide; then removing the metal layer on the silicon dioxide layer by adopting a wet etching process, wherein the metal silicide formed by heat treatment basically does not react with etching liquid of wet etching and is reserved, the metal silicide forms Schottky rectifying contact with the front silicon of the silicon substrate, and the metal silicide forms ohmic contact with the fourth doped region and the fifth doped region;
step nine, adopting a PVD process to deposit a layer of front electrode metal layer, and then adopting a photoetching process wet etching process to form a required pattern;
step ten, depositing a silicon nitride passivation layer by adopting a CVD process, and then etching a bonding area window by adopting a photoetching process in a dry way;
step eleven, thinning the back surface of the silicon substrate to a required thickness by adopting a mechanical grinding mode, and then corroding and grinding the exposed silicon surface by adopting a wet silicon corrosion process to remove a mechanical damage layer and a stress layer;
step twelve, doping the back surface of the silicon substrate twice by adopting a phosphorus ion implantation process to form a third doping region of the doping type in the N type;
thirteenth, doping the back surface of the silicon substrate by adopting a phosphorus ion implantation process to form a first doping region of an N type doping type;
fourteen, coating a fourth photoresist layer on the back surface of the silicon substrate, forming a photoresist pattern on the fourth photoresist layer by adopting a photoetching process, masking by utilizing the photoresist pattern, doping the back surface twice by adopting a boron ion implantation process, and removing the photoresist to form a second doping region of a P type doping type;
fifteen, activating impurities injected into the first doped region, the second doped region and the third doped region by adopting a laser annealing activation technology on the back surface of the silicon substrate;
sixthly, a back electrode metal layer is deposited on the back of the silicon substrate by adopting a PVD process.
2. A high speed soft recovery high voltage schottky diode device according to claim 1, wherein: the thickness of the silicon substrate is 20-250 mu m, and the resistivity is 2-200 omega cm.
3. A high speed soft recovery high voltage schottky diode device according to claim 1, wherein: the depth of the first doping region is 0.2-1.0 mu m, and the average net doping concentration is 5E18-1E20;
the depth of the second doped region is 0.3-1.5 mu m, the average net doping concentration is 2E18-1E20, the width is 1-5 mu m, and the adjacent spacing is 2-50 mu m;
the depth of the third doped region is 0.5-2.0 mu m, and the average net doping concentration is 1E16-1E18;
the lateral distance between the sixth doped region and the fourth doped region is 2-15 μm.
4. A high speed soft recovery high voltage schottky diode device according to claim 1, wherein: the first conductivity type is N type, and the second conductivity type is P type;
alternatively, the first conductivity type is P-type and the second conductivity type is N-type.
5. A high speed soft recovery high voltage schottky diode device according to claim 1, wherein: in the first step, the thickness of the silicon dioxide layer is 0.5-1.0 μm.
6. A high speed soft recovery high voltage schottky diode device according to claim 1, wherein: in the third step, in the boron ion implantation process, the ion implantation energy is 40keV-200keV, and the implantation dosage is 1E12-5E13;
the thickness of the newly grown silicon dioxide layer on the exposed process window is 1.0-2.0 mu m;
the process of impurity injection redistribution diffusion has constant temperature controlled in 1100-1250 deg.c and time of 60-500 min.
7. A high speed soft recovery high voltage schottky diode device according to claim 1, wherein: in the fifth step, in the boron ion implantation process, the ion implantation energy is 40keV-200keV, and the implantation dosage is 2E14-1E16;
the process of impurity injection redistribution diffusion has the constant temperature control range of 1100-1250 ℃ and the constant temperature time of 60-500 min;
the thickness of the silica thin layer is 0.1 μm or less.
8. A high speed soft recovery high voltage schottky diode device according to claim 1, wherein: in the sixth step, in the phosphorus ion implantation process, the ion implantation energy is 70keV-200keV, and the implantation dosage is 5E15-1.5E16;
the process of impurity implantation redistribution diffusion has constant temperature controlled in 1000-1200 deg.c and constant temperature time of 60-550 min.
9. A high speed soft recovery high voltage schottky diode device according to claim 1, wherein: in the twelfth step, in the two times of phosphorus ion implantation processes, the ion implantation energy of the first implantation process is 200keV-1000keV, and the implantation dosage is 5E13-2E15; the ion implantation energy of the second implantation process is 100keV-500keV, and the implantation dosage is 5E13-2E15;
in the thirteenth step, in the phosphorus ion energy implantation process, the ion implantation energy is 40keV-70keV, and the implantation dosage is 2E15-5E15;
in the fourteen steps, in the two boron ion implantation processes, the ion implantation energy of the first implantation process is 80keV-200keV, and the implantation dosage is 5E14-5E15; the ion implantation energy of the second implantation process is 30keV-50keV, and the implantation dosage is 5E15-1E16.
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US5162876A (en) * 1990-09-28 1992-11-10 Kabushiki Kaisha Toshiba Semiconductor device having high breakdown voltage
JPH09307098A (en) * 1996-05-13 1997-11-28 Sankosha Corp Method for setting breakover current or holding current for surge protection device
CN101587912A (en) * 2008-05-23 2009-11-25 三菱电机株式会社 Semiconductor device
CN104637942A (en) * 2013-11-08 2015-05-20 胜普电子股份有限公司 Fast recovery rectifier
CN110416319A (en) * 2019-08-21 2019-11-05 江苏中科君芯科技有限公司 The fast recovery diode device and preparation method of two-sided Schottky control

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5162876A (en) * 1990-09-28 1992-11-10 Kabushiki Kaisha Toshiba Semiconductor device having high breakdown voltage
JPH09307098A (en) * 1996-05-13 1997-11-28 Sankosha Corp Method for setting breakover current or holding current for surge protection device
CN101587912A (en) * 2008-05-23 2009-11-25 三菱电机株式会社 Semiconductor device
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CN110416319A (en) * 2019-08-21 2019-11-05 江苏中科君芯科技有限公司 The fast recovery diode device and preparation method of two-sided Schottky control

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