CN115241150A - Circuit board, preparation method thereof and semiconductor packaging piece - Google Patents

Circuit board, preparation method thereof and semiconductor packaging piece Download PDF

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Publication number
CN115241150A
CN115241150A CN202110440620.7A CN202110440620A CN115241150A CN 115241150 A CN115241150 A CN 115241150A CN 202110440620 A CN202110440620 A CN 202110440620A CN 115241150 A CN115241150 A CN 115241150A
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CN
China
Prior art keywords
layer
conductive
circuit board
copper
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110440620.7A
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Chinese (zh)
Inventor
何四红
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avary Holding Shenzhen Co Ltd
Qing Ding Precision Electronics Huaian Co Ltd
Original Assignee
Avary Holding Shenzhen Co Ltd
Qing Ding Precision Electronics Huaian Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Avary Holding Shenzhen Co Ltd, Qing Ding Precision Electronics Huaian Co Ltd filed Critical Avary Holding Shenzhen Co Ltd
Priority to CN202110440620.7A priority Critical patent/CN115241150A/en
Publication of CN115241150A publication Critical patent/CN115241150A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

The application provides a circuit board, including the substrate layer, set up in conducting circuit layer, a plurality of conducting posts and cover film on at least one surface of substrate layer, a plurality of conducting posts interval set up in on the conducting circuit layer, the cover film covers conducting circuit layer and the cladding is partly of leading electrical pillar every, every lead electrical pillar part expose in outside the cover film. The application also provides a semiconductor package comprising the circuit board and a preparation method of the circuit board.

Description

Circuit board, preparation method thereof and semiconductor packaging piece
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a circuit board, a semiconductor package including the circuit board, and a method for manufacturing the circuit board.
Background
The semiconductor package includes a package substrate, a chip, and a circuit board. The chip is carried on the packaging substrate and is electrically connected with the packaging substrate; and the packaging substrate is electrically connected with the outside or controls signal transmission through the circuit board. The bonding pads on the package substrate and the bonding pads on the circuit board are generally connected by means of solder ball bonding. However, the diameter of the solder ball is about 0.1-0.8 mm, and the minimum ball pitch is 0.35mm; if the ball pitch continues to decrease, a problem may occur that may cause bridging shorts. Therefore, the minimum pitch between pads on the package substrate using solder ball bonding is 0.35mm, which cannot meet the requirement of high integration.
Disclosure of Invention
In view of the above, it is desirable to provide a circuit board, a semiconductor package including the circuit board, and a method for manufacturing the circuit board, which solve the above problems.
An embodiment of the application provides a circuit board, including the substrate layer, set up in conducting circuit layer, a plurality of conducting pillar and cover film on at least one surface of substrate layer, a plurality of conducting pillar intervals set up in on the conducting circuit layer, the cover film covers conducting circuit layer and every conducting pillar's of cladding partly, every conducting pillar part expose in cover film is outer.
Another embodiment of the present application further provides a semiconductor package structure, which includes the circuit board and a package substrate, where the package substrate is disposed on the conductive pillars and electrically connected to the conductive pillars.
Another embodiment of the present application further provides a method for manufacturing the circuit board, which includes the following steps:
providing a copper-clad plate, wherein the copper-clad plate comprises a base material layer and a copper layer arranged on at least one surface of the base material layer;
forming a plurality of conductive pillars on the copper layer;
manufacturing a conductive circuit layer on the copper layer;
and arranging a covering film on the surface of the conductive circuit layer departing from the base material layer.
The circuit board provided by the embodiment of the application realizes the electrical connection with the plurality of welding pads of the packaging substrate through the plurality of conductive columns, the distance between the conductive columns can change along with the change of the distance between the welding pads, and the minimum value of the distance is far smaller than the minimum distance (0.35 mm) between the solder balls, so that the requirement of high integration level is met.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor package structure according to an embodiment of the present disclosure.
Fig. 2 is a schematic cross-sectional view of a copper-clad plate provided in an embodiment of the present application.
Fig. 3 is a schematic diagram after blind holes are formed on the copper-clad plate shown in fig. 2.
Fig. 4 is a schematic view of the blind via shown in fig. 3 after metallization of the via wall.
Fig. 5 is a schematic diagram of the copper-clad plate shown in fig. 4 after first dry films are arranged on two sides of the copper-clad plate.
Fig. 6 is a schematic view illustrating exposure of the first dry film shown in fig. 5.
Fig. 7 is a schematic view of developing the first dry film shown in fig. 6.
Fig. 8 is a schematic diagram of the structure shown in fig. 7 after electroplating.
Fig. 9 is a schematic view of the first dry film shown in fig. 8 after being removed.
Fig. 10 is a schematic view of the structure shown in fig. 9 after second dry films are disposed on both sides of the structure.
Fig. 11 is a schematic view of the second dry film shown in fig. 10 after exposure.
Fig. 12 is a schematic view of the second dry film of fig. 11 after removal.
Fig. 13 is a schematic view of the structure shown in fig. 12 after cover films are disposed on both sides.
Fig. 14 is a schematic view of the structure shown in fig. 13 after surface treatment.
Fig. 15 is a schematic view of the structure of fig. 14 after solder paste is applied.
Fig. 16 is a schematic cross-sectional view of a package substrate according to an embodiment of the present disclosure.
Fig. 17 is a schematic diagram of the packaged chip shown in fig. 16.
Description of the main elements
Semiconductor package structure 100
Circuit board 10
Package substrate 20
Chip 30
Encapsulation layer 40
Base material layer 11
Conductive line layer 12
Conductive post 14
Cover film 15
Connecting pad 121
Coating 17
Solder paste 18
Bonding pad 21
Dielectric layer 22
Conductive hole 23
Copper-clad plate 200
Copper layer 201
Blind hole 203
Metal layer 205
The first dry film 300
Second dry film 400
The following detailed description will further illustrate the present application in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any inventive step are within the scope of protection of the present application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Referring to fig. 1, an embodiment of the present invention provides a semiconductor package structure 100 including a circuit board 10, a package substrate 20, a chip 30 and a package layer 40.
The circuit board 10 includes a substrate layer 11, a conductive circuit layer 12, a plurality of conductive pillars 14, and a cover film 15. The conductive circuit layer 12 is disposed on at least one surface of the substrate layer 11. The conductive posts 14 are disposed on one conductive circuit layer 12 at intervals. The conductive post 14 is disposed on the conductive trace layer 12 in a protruding manner, and the conductive post 14 is a column. The cover film 15 covers the conductive circuit layer 12 and covers a part of the conductive post 14. A part of the conductive post 14 is exposed outside the cover film 15. In this embodiment, the conductive circuit layers 12 are disposed on two surfaces of the base material layer 11 opposite to each other.
The conductive trace layer 12 includes a plurality of connection pads 121 disposed at intervals. The conductive pillars 14 are respectively disposed on the connection pads 121. The spacing between two adjacent connection pads 121 is smaller than the spacing between two corresponding conductive pillars 14.
In some embodiments, the circuit board 10 further includes a conductive structure 16 penetrating through the substrate layer 11, and the conductive structure 16 is electrically connected to the conductive trace layers 12 on two opposite surfaces of the substrate layer 11. The conductive structures 16 may be conductive vias, conductive pillars, etc.
The substrate layer 11 is made of a flexible material. In some embodiments, the material of the substrate layer 11 includes one or more of liquid crystal high polymer, polytetrafluoroethylene, polyetheretherketone, polyphenylene oxide, polyimide, polyethylene terephthalate, polyethylene naphthalate, and polyethylene.
The conductive circuit layer 12 and the conductive pillars 14 are made of metal. In this embodiment, the conductive trace layer 12 and the conductive pillars 14 are made of copper.
The cover film 15 includes an adhesive layer and a cover layer which are stacked. The adhesive layer covers the conductive circuit layer 12, covers a part of the conductive posts 14, and fills gaps between conductive circuits on the conductive circuit layer 12. The cover layer covers the side of the adhesive layer facing away from the conductive circuit layer 12. In some embodiments, the material of the adhesive layer is a common adhesive, and the material of the cover layer is polyethylene terephthalate (PET).
In some embodiments, the surface of the conductive post 14 exposed outside the cover film 15 is covered with a plating layer 17. The plating layer 17 is formed on the surface of the conductive post 14 through a surface treatment process, so as to ensure that the conductive post 14 has good solderable or electrical properties. The material of the plating layer 17 may be gold, tin, or the like.
In some embodiments, the circuit board 10 further includes a plurality of solder pastes 18. The plurality of solder pastes 18 are respectively disposed on the plurality of conductive pillars 14. Along the thickness direction H of the circuit board 10, the height of the solder paste 18 is not greater than the height of the portion of the conductive pillar 14 exposed outside the cover film 15.
The package substrate 20 is disposed on the plurality of solder pastes 18 and electrically connected to the circuit board 10. The package substrate 20 includes a plurality of pads 21. The positions of the pads 21 correspond to the positions of the conductive pillars 14 one by one, and each pad 21 is soldered to the conductive pillar 14 through a corresponding solder paste 18. The difference between the pitch between two adjacent pads 21 and the pitch between two corresponding conductive pillars 14 is controlled to be within one third of the width (in the width direction W) of the pad 21.
The package substrate 20 further includes a dielectric layer 22, metal wiring layers (not shown) located on two opposite surfaces of the dielectric layer 22, and a conductive via 23, where the conductive via 23 is electrically connected to the metal wiring layers located on two opposite surfaces of the dielectric layer 22. The plurality of pads 21 are disposed on a metal wiring layer facing the circuit board 10. The dielectric layer is made of one or a combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass.
The chip 30 is disposed on a metal wiring layer away from the circuit board 10 and electrically connected to the package substrate 20. In the present embodiment, the chip 30 is connected to the package substrate 20 by flip chip technology.
The package layer 40 is disposed on a side of the package substrate 20 away from the circuit board 10 and covers the chip 30. The material of the encapsulation layer 40 includes one or more of polyimide, silicone, and epoxy.
An embodiment of the present application further provides a method for manufacturing the semiconductor package structure 100, which includes the following steps.
Step S1: referring to fig. 2, a copper-clad plate 200 is provided. The copper-clad plate 200 comprises a substrate layer 11 and a copper layer 201 arranged on at least one surface of the substrate layer 11. In the present embodiment, the copper layer 201 is provided on both surfaces of the base material layer 11 facing each other.
Step S2: referring to fig. 9, a plurality of conductive pillars 14 are formed on one copper layer 201, and a conductive structure 16 electrically connecting two copper layers 201 is formed.
In some embodiments, the plurality of conductive pillars 14 are formed sequentially using a photolithography process and an electroplating process, and the conductive structure 16 is formed sequentially using a drilling process, a metallization process, a photolithography process, and an electroplating process. The photolithography process for forming the conductive pillars 14 and the photolithography process for forming the conductive structure 16 are performed simultaneously, and the electroplating process for forming the conductive pillars 14 and the electroplating process for forming the conductive structure 16 are performed simultaneously.
Specifically, the step S2 includes the steps of:
step S21: referring to fig. 3, the copper-clad plate 200 is drilled to form a blind hole 203 penetrating through the substrate layer 11 and a copper layer 201. In this embodiment, the drilling is performed by a mechanical drilling or laser drilling process.
Step S22: referring to fig. 4, the walls of the blind vias 203 are metalized to form a metal layer 205 on the walls of the blind vias 203.
Step S23: referring to fig. 5, a first dry film 300 is disposed on a surface of the copper layer 201 away from the substrate layer 11. The first dry film 300 covers the surface of the copper layer 201 away from the substrate layer 11.
Step S24: referring to fig. 6 and 7, the first dry film 300 is exposed and developed to expose a portion of the copper layer 201 and the blind via 203.
Step S25: referring to fig. 8, a metal layer is plated on the exposed surface of the copper layer 201 to form the conductive pillars 14 and the conductive structure 16.
Step S26: referring to fig. 9, the first dry film 300 is removed.
And step S3: referring to fig. 12, a conductive circuit layer 12 is formed on the copper layer 201.
In some embodiments, the conductive circuit layer 12 is formed on the copper layer 201 by a photolithography process.
Specifically, step S3 includes the following steps:
in step S31, referring to fig. 10, a second dry film 400 is disposed on a surface of the copper layer 201 away from the substrate layer 11, and the second dry film 400 covers the plurality of conductive pillars 14 and the conductive structure 16.
In step S32, referring to fig. 11 and 12, the second dry film 400 is exposed and developed to expose a portion of the copper layer 201, and the exposed copper layer 201 is removed by etching to obtain the conductive circuit layer 12. It is understood that the second dry film 400 is removed after the conductive line layer 12 is etched.
In step S4, referring to fig. 13, a cover film 15 is disposed on a surface of the conductive circuit layer 12 away from the substrate layer 11. The cover film 15 is disposed on the conductive circuit layer 12 through bonding, pressing, and curing processes. The cover film 15 covers the conductive trace layer 12 and the conductive structure 16, fills gaps between conductive traces, and covers portions of the conductive posts 14. Part of the conductive post 14 is exposed outside the cover film 15.
In step S5, referring to fig. 14, the exposed conductive pillar 14 is subjected to a surface treatment to form a plating layer 17. The surface treatment process comprises gold plating, nickel plating and the like.
In step S6, referring to fig. 15, a solder paste 18 is formed on the exposed conductive pillars 14. The solder paste 18 can be formed on the conductive posts 14 by printing, coating, etc. Along the thickness direction H of the circuit board 10, the height of the solder paste 18 is not greater than the height of the portion of the conductive post 14 exposed outside the cover film 15.
In step S7, please refer to fig. 16, a package substrate 20 is provided. The package substrate 20 includes a dielectric layer 22, metal wiring layers (not shown) on two opposite surfaces of the dielectric layer 22, and a conductive via 23, where the conductive via 23 is electrically connected to the metal wiring layers on two opposite surfaces of the dielectric layer 22. A plurality of bonding pads 21 are disposed on the metal wiring layer on one surface of the dielectric layer 22.
Step S8, referring to fig. 17, a packaging layer 40 is used to package the chip 30 on the surface of the packaging substrate 20 away from the plurality of bonding pads 21. The chip 30 is connected to the package substrate 20 by flip chip technology.
In step S9, referring to fig. 1, the package substrate 20 is soldered on the conductive pillars 14 of the circuit board 10.
The positions of the plurality of pads 21 on the package substrate 20 correspond to the positions of the plurality of conductive pillars 14 one by one, and each pad 21 is soldered to a corresponding solder paste 18 by a reflow soldering process, so as to be soldered to a corresponding conductive pillar 14. The difference between the pitch between two adjacent pads 21 and the pitch between the corresponding two conductive pillars 14 is controlled to be within one third of the width (in the width direction W) of the pad 21.
In the circuit board 10 provided in the embodiment of the present invention, the plurality of conductive pillars 14 are electrically connected to the plurality of pads 21 of the package substrate 20, the pitch between the conductive pillars 14 can change along with the change of the pitch between the pads 21, and the minimum value of the pitch is much smaller than the minimum pitch (0.35 mm) between the solder balls, so as to satisfy the requirement of high integration level.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention.

Claims (10)

1. The utility model provides a circuit board, includes the substrate layer with set up in at least one conducting wire layer on the surface of substrate layer, its characterized in that, the circuit board still includes a plurality of electrically conductive posts and cover film, a plurality of electrically conductive post intervals set up in on the conducting wire layer, the cover film covers conducting wire layer and every partially of leading electrical pillar of cladding, every lead electrical pillar partially expose in cover film is outside.
2. The circuit board of claim 1, further comprising a solder paste disposed on each conductive post, wherein a height of the solder paste is less than or equal to a height of a portion of the conductive post exposed outside the cover film.
3. The circuit board of claim 1, wherein the material of the substrate layer comprises one or more of liquid crystal high polymer, polytetrafluoroethylene, polyetheretherketone, polyphenylene ether, polyimide, polyethylene terephthalate, polyethylene naphthalate, and polyethylene.
4. The circuit board of claim 1, wherein the conductive trace layers are disposed on opposite surfaces of the substrate layer, the circuit board further comprising conductive structures extending through the substrate layer, the conductive structures electrically connecting the conductive trace layers on the opposite surfaces of the substrate layer.
5. A semiconductor package structure, comprising the circuit board according to any one of claims 1 to 4, and a package substrate disposed on and electrically connected to the conductive pillars.
6. The semiconductor package structure according to claim 5, wherein the package substrate comprises a plurality of pads, the pads are respectively connected to the conductive pillars, and a difference between a pitch between two adjacent pads and a pitch between two corresponding conductive pillars is controlled within one third of a width of the pad.
7. A method for producing a circuit board according to any one of claims 1 to 4, comprising the steps of:
providing a copper-clad plate, wherein the copper-clad plate comprises a substrate layer and a copper layer arranged on at least one surface of the substrate layer;
forming a plurality of conductive pillars on the copper layer;
manufacturing a conductive circuit layer on the copper layer;
and arranging a covering film on the surface of the conductive circuit layer departing from the base material layer.
8. The method according to claim 7, wherein the plurality of conductive pillars are formed on the copper layer by a photolithography process and an electroplating process in sequence, and a conductive circuit layer is formed on the copper layer by a photolithography process.
9. The method according to claim 7, wherein the step of providing a cover film on a surface of the conductive circuit layer facing away from the substrate layer further comprises: and carrying out surface treatment on the conductive columns exposed outside the covering film to form a plating layer.
10. The method according to claim 9, wherein the step of performing surface treatment on the conductive post exposed outside the cover film to form the plating layer further comprises: and forming solder paste on the conductive columns exposed outside the covering film.
CN202110440620.7A 2021-04-23 2021-04-23 Circuit board, preparation method thereof and semiconductor packaging piece Pending CN115241150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110440620.7A CN115241150A (en) 2021-04-23 2021-04-23 Circuit board, preparation method thereof and semiconductor packaging piece

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110440620.7A CN115241150A (en) 2021-04-23 2021-04-23 Circuit board, preparation method thereof and semiconductor packaging piece

Publications (1)

Publication Number Publication Date
CN115241150A true CN115241150A (en) 2022-10-25

Family

ID=83666507

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110440620.7A Pending CN115241150A (en) 2021-04-23 2021-04-23 Circuit board, preparation method thereof and semiconductor packaging piece

Country Status (1)

Country Link
CN (1) CN115241150A (en)

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