CN115238621B - Migration method, migration apparatus, electronic device, and storage medium - Google Patents
Migration method, migration apparatus, electronic device, and storage medium Download PDFInfo
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Abstract
The invention discloses a processor core transplanting method, a transplanting device, electronic equipment and a storage medium, wherein the transplanting method of the embodiment of the invention comprises the following steps: compiling a guide application program to generate a plurality of instruction tightly-coupled memory files, converting a user application program to generate a data bit stream file, compiling the instruction tightly-coupled memory files and a register conversion level file of a processor core together to generate a bit variable file required by the configuration of the FPGA chip, splicing the bit variable file and the data bit stream file to obtain a flash memory configuration file, and transplanting the flash memory configuration file to the FPGA chip. The invention can fast transplant the processor core to the FPGA chip, thereby enabling the FPGA chip to become an on-chip programmable system platform, and thus, the corresponding software and hardware cutting can be carried out when the system is realized, and the flexibility and the expansibility of the system are improved.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a method and an apparatus for migrating a processor core, an electronic device, and a storage medium.
Background
Field Programmable Gate Arrays (FPGAs) are increasingly used to implement fast design of high performance embedded systems as a flexible and cost-effective platform. However, processors tend to be large and slow when implemented on the coarse grain architecture of FPGAs.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. To this end, the invention provides a processor core migration method, a migration device, an electronic device and a non-volatile computer-readable storage medium.
The transplantation method of the embodiment of the invention comprises the following steps:
compiling a boot application to generate a plurality of instruction tightly coupled memory files;
converting the user application program to generate a data bit stream file;
compiling the instruction tightly coupled memory file and the register conversion level file of the processor core together to generate a bit variable file required by configuring an FPGA chip;
splicing the bit variable file and the data bit stream file to obtain a flash memory configuration file; and
and transplanting the flash memory configuration file to the FPGA chip.
In some embodiments, the compiling the boot application to generate a plurality of instruction close-coupled memory files comprises:
configuring macro definition of relevant codes in the guide application program file according to the initial storage address and the size of the data bit stream file;
and starting the configured boot application program file to generate the instruction tightly coupled memory file.
In some embodiments, the START storage address of the data bitstream file is 0x000C0000, the SIZE of the data bitstream file is equal to the actual SIZE, the code macro definition in the boot application file associated with the START storage address of the data bitstream file is configured as SPI _ FLASH _ START _ ADDR, and the code macro definition in the boot application file associated with the SIZE of the data bitstream file is configured as APP _ BIN _ SIZE.
In some embodiments, the converting the user application to generate the data bitstream file includes:
opening the user application through a software development system;
configuring an addressing space of instructions and data in the user application program as an addressing space of the processor core;
and compiling the modified user application program to obtain the data bit stream file.
In some embodiments, said compiling said instruction close-coupled memory file and said processor core register conversion level file together to generate a bit variable file required to configure said FPGA chip comprises;
storing the instruction close-coupled memory file into the register conversion stage file;
and compiling the register conversion level file by a development tool matched with the FPGA chip to generate the bit variable file.
In some embodiments, the splicing the bit variable file and the data bit stream file to obtain a flash configuration file includes:
and splicing the bit variable file and the data bit stream file through a configuration tool in the development tool to generate the flash memory configuration file.
In some embodiments, before migrating the flash configuration file to the FPGA chip, the migration method further includes:
converting the data bit stream file into an initialization file of a DDR particle simulation model through an executable script file;
inputting the initialization file into a simulation directory of the DDR particle simulation model;
running the DDR particle simulation model to validate the data bitstream file.
In certain embodiments, the method of grafting further comprises:
starting the FPGA chip;
collecting serial port printing information, indicator light information and interrupt response information of the FPGA chip;
and determining a transplantation result according to the serial port printing information, the indicator light information and the interrupt response information.
The transplanting device comprises a first compiling module, a second compiling module and a third compiling module, wherein the first compiling module is used for compiling a guide application program to generate a plurality of instruction tightly-coupled memory files;
the conversion module is used for carrying out conversion processing on the user application program to generate a data bit stream file;
the second compiling module is used for jointly compiling the instruction tightly-coupled memory file and the register conversion level file of the processor core to generate a bit variable file required by configuring the FPGA chip;
the second compiling module is also used for splicing the bit variable file and the data bit stream file to obtain a flash memory configuration file; and
and the transplanting module is used for transplanting the flash memory configuration file to the FPGA chip.
The electronic device of the embodiment of the invention comprises a processor and a memory, wherein the memory stores a computer program, and the computer program causes the processor to execute the migration method when being executed by the processor.
A non-transitory computer-readable storage medium of an embodiment of the present invention includes a computer program that, when executed by a processor, causes the processor to execute the migration method.
In the transplanting method, the transplanting device, the electronic equipment and the storage medium of the embodiment of the invention, a plurality of instruction tightly-coupled memory files are generated by compiling a guide application program, a user application program is converted to generate a data bit stream file, the instruction tightly-coupled memory files and a register conversion level file of a processor core are compiled together to generate a bit variable file required by the configuration of an FPGA chip, the bit variable file and the data bit stream file are spliced to obtain a flash memory configuration file, and the flash memory configuration file is transplanted to the FPGA chip. Therefore, the embedded processor core is quickly transplanted on the FPGA chip, the system on the programmable chip is constructed, and the flexibility and the expansibility of the system are greatly improved, so that the balance of performance, power consumption and cost is achieved.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic flow diagram of a grafting method in some embodiments of the invention.
Fig. 2 is a block schematic diagram of a grafting device according to certain embodiments of the invention.
Fig. 3 is a schematic flow diagram of a grafting method according to some embodiments of the invention.
Fig. 4 is a schematic flow diagram of a grafting method according to some embodiments of the invention.
Fig. 5 is a schematic flow diagram of a grafting method according to some embodiments of the invention.
Fig. 6 is a flow diagram illustrating a grafting method according to some embodiments of the invention.
Fig. 7 is a schematic flow diagram of a grafting method according to some embodiments of the invention.
Fig. 8 is a block schematic diagram of a grafting device according to certain embodiments of the invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature "on," "above" and "over" the second feature may include the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is at a higher level than the second feature. "beneath," "under" and "beneath" a first feature includes the first feature being directly beneath and obliquely beneath the second feature, or simply indicating that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.
An FPGA (Field Programmable Gate Array) is a product of further development based on Programmable devices such as PAL (Programmable Array logic) and GAL (general Array logic). The circuit is used as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of circuits of the original programmable device is limited, more and more rapid design is used for realizing a high-performance embedded system, in addition, the market urgent need is directed at a 32-bit processor framework system which is optimized by an FPGA and meets the standards of the industry, and when the circuit is realized on a coarse grain framework of the FPGA, the processor is often larger and has lower speed. Although there are some dedicated soft IP processor cores available on the market that can be implemented on FPGAs, they have limitations in terms of development tools, technical support resources, and designer experience.
In view of this, referring to fig. 1, an embodiment of the present invention provides a migration method of a processor core, where the migration method includes:
01, compiling a boot application to generate a plurality of instruction tightly coupled memory files;
02, converting the user application program to generate a data bit stream file;
03, compiling the instruction tightly coupled memory file and the register conversion level file of the processor core together to generate a bit variable file required by configuring the FPGA chip;
04, splicing the bit variable file and the data bit stream file to obtain a flash memory configuration file; and
and 05, transplanting the flash memory configuration file to the FPGA chip.
Referring to fig. 2, an embodiment of the present invention further provides a migration apparatus 100 for a processor core, which includes a first compiling module 110, a converting module 120, a second compiling module 130, and a migrating module 140. Wherein 01 may be implemented by the first compiling module 110, 02 may be implemented by the converting module 120, 03 may be implemented by the second compiling module 130, and 04 may be implemented by the migrating module 140.
Alternatively, the first compiling module 110 may be configured to compile a boot application to generate a plurality of instruction close-coupled memory files, and the converting module 120 may be configured to perform a conversion process on a user application to generate a data bitstream file; the second compiling module 130 may be configured to compile the instruction tight coupling memory file and the register conversion level file of the processor core together, generate a bit variable file required by configuring the FPGA chip, and perform a splicing process on the bit variable file and the data bit stream file to obtain a flash memory configuration file; the migration module 140 may be used to migrate the flash configuration file to the FPGA chip.
The embodiment of the invention also provides electronic equipment, which comprises a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor is enabled to execute the transplanting method, namely, the processor can be used for compiling a guide application program to generate a plurality of instruction tightly-coupled memory files, converting a user application program to generate a data bit stream file, compiling the instruction tightly-coupled memory files and a register conversion level file of a processor core together to generate a bit variable file required by the configuration of the FPGA chip, splicing the bit variable file and the data bit stream file to obtain a flash memory configuration file, and transplanting the flash memory configuration file to the FPGA chip.
The electronic device may be a Personal Computer (PC), and the processor core is stored in a memory of the electronic device.
In some embodiments, the grafting device 100 may be part of an electronic device. Alternatively, the electronic device includes the transplantation device 100.
In some embodiments, the transplantation device 100 can be a discrete component assembled in a manner to have the aforementioned functions, or a chip having the aforementioned functions in the form of an integrated circuit, or a computer software code segment that causes a computer to have the aforementioned functions when run on the computer.
In some embodiments, the migration apparatus 100 may be a stand-alone or add-on to the electronic device as additional peripheral components, as hardware. The transplantation device 100 may also be integrated into an electronic apparatus, for example, the detection device 10 may be integrated into a processor when the transplantation device 100 is part of an electronic apparatus.
It should be noted that the FPGA chip belongs to a semi-custom chip in an asic, and is a programmable logic array, which can effectively solve the problem of the small number of gate circuits of the original chip. The basic structure of the FPGA comprises a programmable input/output unit, a configurable logic block, a digital clock management module, an embedded block RAM, wiring resources, an embedded special hard core, a bottom layer embedded functional unit and the like. The FPGA chip has the characteristics of abundant wiring resources, high repeatable programming and integration level and low investment, and is widely applied to the field of digital circuit design.
The processor core may include, but is not limited to, an ARM Cortex-M1 SoC or a RISC-V processor core, for example, the present invention is described by taking the processor core as the Cortex-M1 SoC, that is, the present invention transplants the ARM Cortex-M1 SoC into the FPGA chip. As can be understood by those skilled in the art, the Cortex-M1 SoC is a processor core optimally designed for an FPGA chip, and the customized design greatly improves the performance and efficiency of the processor core and reduces the occupation amount of logic units.
A boot application (Bootloader) is a component in an operating system based on an ARM processor. When the processor core with the ICACHE and the DCACHE is used, an application program needs to be guided to load a data bit stream file generated by a user application program into a DDR (double data rate) particle (DDR memory) and realize address jump.
An instruction tightly coupled memory (itcm) file is a memory (usually SRAM) with a small capacity, which is configured to store instructions and is physically close to and dedicated to a processor core, and can achieve a small access delay (usually one clock cycle).
The instruction close-coupled memory file includes itcm0, itcm1, itcm2, itcm3 executable files. The instruction close-coupled memory file can load a data bit stream file generated by a user application program into DDR particles of an FPGA chip and realize address jumping.
The user application program (processing core _ demo.c) is an application program established by a user, and the user application program may be a C language source program and is used for indicating the operation state after the processor core is transplanted to the FPGA chip, for example, the user application program may generate serial port printing information, adjust an indicator light of the FPGA chip, interrupt response of a key/serial port, and the like according to the operation state of the processor core in the FPGA chip.
Bin is an executable binary file, compiled by a user application.
The Register Transfer Level (Register Transfer Level) is a way of describing the data flow of a circuit in a manner of describing the Register Level.
The bit variable file (processing core _ top.sbit) is used to implement the guiding and address jumping of the data bit stream file generated by the user application program, that is, in step 03, the purpose of generating the bit variable file by the register conversion level file of the instruction tightly coupled memory file and the processor core is to implement the guiding and address jumping of the data bit stream file in the FPGA chip.
The Flash configuration file (processing core _ top.sfc) can be transmitted to the FPGA chip through a data line (CABLE) and can be fixed to an SPI Flash chip in the FPGA chip. Specifically, the FPGA Chip can be connected with a 12V power supply and a data line, a serial port of the FPGA Chip is connected with the electronic device, a serial port assistant is opened, a matched COM port is selected, and the Flash memory configuration file is solidified into an SPI Flash Chip in the FPGA Chip through the data line, so that the transplantation of a processor core is realized, and a System on Programmable Chip (SoPC) related to the FPGA Chip is constructed.
In the migration method, the migration apparatus 100, the electronic device, and the storage medium according to the embodiments of the present invention, the boot application is compiled to generate a plurality of instruction close-coupled memory files, the user application is converted to generate a data bit stream file, the instruction close-coupled memory files and the register conversion level file of the processor core are compiled together to generate a bit variable file required for configuring the FPGA chip, the bit variable file and the data bit stream file are spliced to obtain a flash memory configuration file, and the flash memory configuration file is migrated to the FPGA chip. Therefore, the embedded processor core is quickly transplanted on the FPGA chip, the system on the programmable chip is constructed, and the flexibility and the expansibility of the system are greatly improved, so that the balance of performance, power consumption and cost is achieved.
Referring to fig. 3, in some embodiments, step 01 includes:
011, configuring macro definition of relevant codes in the guide application program file according to the initial storage address and the size of the data bit stream file;
012, starting the configured boot application file to generate a command tight coupling memory file.
In some embodiments, sub-steps 011 and 012 can be implemented by first compiling module 110, or first compiling module 110 is configured to configure a macro definition of relevant code in a bootstrap application file according to a starting memory address and a size of the data bitstream file, and start the configured bootstrap application file to generate an instruction tight coupling memory file.
In some embodiments, the processor is configured to configure a macro definition of the associated code in the bootstrap application file based on the starting memory address and size of the data bitstream file, and to launch the configured bootstrap application file to generate the instruction close-coupled memory file.
It should be noted that the starting storage address and the size of the data bit stream file refer to the starting storage address and the size of the data bit stream file in the FPGA chip. The starting storage address of the data bit stream file is 0x000C0000, and the code macro definition corresponding to the starting storage address of the data bit stream file in the boot application file is configured as SPI _ FLASH _ START _ ADDR.
The size of the data bit stream file in the FPGA chip is the same as the actual size of the data bit stream file, so that the start-up time for booting the application program can be optimized, and the size of the data bit stream file is set to 4096 × 64 (i.e. the size of the data bit stream file supported in the FPGA chip is 256 KB). The macro definition of the code in the boot application file related to the SIZE of the data bitstream file is configured as APP _ BIN _ SIZE.
Therefore, the data bit stream file generated by the user application program can be loaded into the DDR particles of the FPGA chip and address jump can be realized subsequently according to the instruction tightly coupled memory file generated by the guide application program file.
Referring to fig. 4, in some embodiments, step 02 includes:
021, opening a user application program through a software development system;
022, configuring an addressing space of instructions and data in a user application program as an addressing space of a processor core;
023, the modified user application is compiled to obtain a data bitstream file.
In some embodiments, the sub-steps 021-023 may be implemented by the converting module 120, or the converting module 120 may be configured to open the user application through the software development system, configure an addressing space of instructions and data in the user application as an addressing space of the processor core, and compile the modified user application into the data bitstream file.
In some embodiments, the processor may be configured to open a user application through the software development system, configure an addressing space of instructions and data in the user application as an addressing space of the processor core, and compile the modified user application into the data bitstream file.
The software development system may be a Keil, that is, in this embodiment, the user application program is opened by the Keil, the addressing space of the instruction and the data in the user application program is modified into the addressing space of the ICACHE instruction and the DCACHE data in the processor core, and then the modified user application program is compiled to generate the data bit stream file of the executable binary system.
The ICACHE instruction's starting address is configured to: 0x10000000, with DDR grain mapping range: 0x10000000-0x10FFFFFF (16 MB);
the DCACHE data starting address is configured as follows: 0x30000000 with DDR grain mapping range: 0x30000000-0x3FFFFFFF (256 MB), and this mapping range cannot be exceeded, otherwise an error occurs.
Referring to fig. 5, in some embodiments, step 03 includes;
031, store the instruction tight-coupled memory file in the register conversion stage file;
032 and compiling the register conversion level file to generate a bit variable file by a development tool matched with the FPGA chip.
In some embodiments, sub-steps 031 and 032 may be implemented by the second compiling module 130, or the second compiling module 130 may be configured to store the instruction tightly coupled memory file in the register conversion stage file, and compile the register conversion stage file into the bit variable file by using a development tool associated with the FPGA chip.
In some embodiments, the processor may be configured to store the instruction close-coupled memory file in a register conversion level file, and to compile the register conversion level file into a bit variable file via a development tool associated with the FPGA chip.
The development tool may be an integrated development environment tool (SDS), that is, after the instruction tight coupling memory file is stored in the register conversion stage file, the instruction tight coupling memory file and the register conversion stage file of the processor core are compiled in the SDS to generate a bit variable file.
In this way, the leading and address jumping of the data bit stream file can be subsequently realized by the bit variable file.
Referring further to fig. 5, in some embodiments, step 04 includes:
041, the bit variable file and the data bit stream file are spliced by a configuration tool in the development tool to generate a flash memory configuration file.
In some embodiments, sub-step 041 may be implemented by second compiling module 130, or second compiling module 130 may be further configured to generate a flash configuration file by performing a splicing process on the bit variable file and the data bit stream file through a configuration tool in the development tool.
In some embodiments, the processor may be further configured to generate a flash configuration file by performing a splicing process on the bit variable file and the data bit stream file through a configuration tool in the development tool.
In the present embodiment, the generated bit variable file and the data bit stream file are automatically merged by a Configuration (Configuration) tool of SDS, and a flash memory Configuration file (processing core _ top.sfc) that can be fixed to the FPGA chip is generated. Therefore, the flash memory configuration file can be transplanted to the FPGA chip subsequently, and the transplantation of the processor core is realized.
Referring to fig. 6, in some embodiments, before step 05, the transplanting method further comprises:
001, converting the data bit stream file into an initialization file of the DDR particle simulation model through the executable script file;
002, inputting the initialization file into a simulation directory of the DDR particle simulation model;
and 003, running a DDR particle simulation model to verify the data bit stream file.
Further referring to FIG. 2, in some embodiments, the migration device 100 may further include a simulation module 150, wherein steps 001-003 may be implemented by the simulation module 150, or the simulation module 150 may be configured to convert the data bitstream file into an initialization file of the DDR particle simulation model through the executable script file, input the initialization file into a simulation directory of the DDR particle simulation model, and execute the DDR particle simulation model to verify the data bitstream file.
In some embodiments, the processor may be configured to convert the data bitstream file into an initialization file for the DDR particle simulation model via the executable script file, enter the initialization file into a simulation directory of the DDR particle simulation model, and run the DDR particle simulation model to verify the data bitstream file.
It should be noted that, in this embodiment, a Boot-free simulation method is adopted, that is, a Boot process of loading an instruction from the SPI-FLASH to the DDR particle is skipped, a required instruction is directly initialized and assigned to a predetermined space of the DDR particle, and the instruction and data are loaded after the system initialization is completed.
Specifically, in the KEIL development environment, an executable script file is used to convert a data bit stream file into an initialization file required for initializing a DDR particle simulation model, where the initialization file includes a mem _ addr.dat, a mem _ data.dat and a mem _ used.dat file, then the three initialization files are placed into a simulation directory (simulation) of a processor core file, and finally, the simulation model can be run by clicking sim.bat to obtain a simulation result, so that whether the data bit stream file is normal can be verified according to the simulation result.
Referring to fig. 7, in some embodiments, the transplanting method further includes:
06, starting the FPGA chip;
07, collecting serial port printing information, indicator light information and interrupt response information of the FPGA chip;
08, determining a transplanting result according to the serial port printing information, the indicator light information and the interrupt response information.
Referring to fig. 8, in some embodiments, the transplantation device 100 may further include a starting module 160, an acquiring module 170, and a determining module 180, wherein step 06 may be implemented by the starting module 160, step 07 may be implemented by the acquiring module 170, step 08 may be implemented by the determining module 180, or the starting module 160 may be configured to start the FPGA chip; the acquisition module 170 may be configured to acquire serial port printing information, indicator light information, and interrupt response information of the FPGA chip, and the determination module 180 may be configured to determine a transplantation result according to the serial port printing information, the indicator light information, and the interrupt response information.
In some embodiments, the processor may be further configured to start the FPGA chip, collect serial port printing information, indicator light information, and interrupt response information of the FPGA chip, and determine the transplantation result according to the serial port printing information, the indicator light information, and the interrupt response information.
Specifically, after the processor core is transplanted to the FPGA chip, the FPGA chip is restarted, the FPGA chip can run the flash configuration file after being started, the function of the processor core is realized, and at the moment, whether the processor core runs successfully or not can be judged according to serial port printing information, indicator light phenomena and key/serial port interrupt responses.
In the description herein, references to the description of the terms "one embodiment," "certain embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims (10)
1. A method for migrating a processor core, the method comprising:
compiling a boot application to generate a plurality of instruction tightly coupled memory files;
converting the user application program to generate a data bit stream file;
compiling the instruction tightly-coupled memory file and the register conversion level file of the processor core together to generate a bit variable file required by configuring an FPGA chip;
splicing the bit variable file and the data bit stream file to obtain a flash memory configuration file; and
transplanting the flash memory configuration file to the FPGA chip;
the compiling a boot application to generate a plurality of instruction tightly coupled memory files, comprising:
configuring macro definition of relevant codes in the guide application program file according to the initial storage address and the size of the data bit stream file;
and starting the configured boot application program file to generate the instruction tightly coupled memory file.
2. The migration method according to claim 1, wherein the starting storage address of the data bitstream file is 0x000C0000, the SIZE of the data bitstream file is equal to the actual SIZE, the code macro definition in the guide application file related to the starting storage address of the data bitstream file is configured as SPI _ FLASH _ START _ ADDR, and the code macro definition in the guide application file related to the SIZE of the data bitstream file is configured as APP _ BIN _ SIZE.
3. The migration method according to claim 1, wherein said performing conversion processing on the user application to generate the data bit stream file comprises:
opening the user application through a software development system;
configuring an addressing space of instructions and data in the user application program as an addressing space of the processor core;
and compiling the modified user application program to obtain the data bit stream file.
4. The migration method according to claim 1, wherein said compiling said instruction tightly coupled memory file and said processor core register conversion level file together generates a bit variable file required for configuring said FPGA chip, including;
storing the instruction close-coupled memory file into the register conversion stage file;
and compiling the register conversion level file by a development tool matched with the FPGA chip to generate the bit variable file.
5. The migration method according to claim 4, wherein the splicing the bit variable file and the data bit stream file to obtain a flash configuration file comprises:
and splicing the bit variable file and the data bit stream file through a configuration tool in the development tool to generate the flash memory configuration file.
6. The migration method according to claim 1, wherein before migrating the flash configuration file to the FPGA chip, the migration method further comprises:
converting the data bit stream file into an initialization file of a DDR particle simulation model through an executable script file;
inputting the initialization file into a simulation directory of the DDR particle simulation model;
running the DDR particle simulation model to validate the data bitstream file.
7. The grafting method of claim 1, further comprising:
starting the FPGA chip;
collecting serial port printing information, indicator light information and interrupt response information of the FPGA chip;
and determining a transplantation result according to the serial port printing information, the indicator light information and the interrupt response information.
8. An apparatus for porting a processor core, comprising:
a first compiling module for compiling a boot application to generate a plurality of instruction close-coupled memory files;
the conversion module is used for carrying out conversion processing on the user application program to generate a data bit stream file;
the second compiling module is used for compiling the instruction tightly-coupled memory file and the register conversion level file of the processor core together to generate a bit variable file required by the configuration of the FPGA chip;
the second compiling module is also used for splicing the bit variable file and the data bit stream file to obtain a flash memory configuration file; and
the migration module is used for migrating the flash configuration file to the FPGA chip;
the first compiling module is further configured to:
configuring macro definition of relevant codes in the guide application program file according to the initial storage address and the size of the data bit stream file;
and starting the configured boot application program file to generate the instruction tightly coupled memory file.
9. An electronic device comprising a processor and a memory, the memory storing a computer program that, when executed by the processor, causes the processor to perform the migration method of any one of claims 1-7.
10. A non-transitory computer-readable storage medium including a computer program which, when executed by a processor, causes the processor to execute the migration method of any one of claims 1-7.
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