CN105760137B - A kind of application method of configurable microcontroller core - Google Patents

A kind of application method of configurable microcontroller core Download PDF

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CN105760137B
CN105760137B CN201610061345.7A CN201610061345A CN105760137B CN 105760137 B CN105760137 B CN 105760137B CN 201610061345 A CN201610061345 A CN 201610061345A CN 105760137 B CN105760137 B CN 105760137B
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module
gate array
programmable gate
microcontroller core
instruction
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CN105760137A (en
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景蔚亮
陈邦明
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Shanghai Xinchu Integrated Circuit Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Stored Programmes (AREA)

Abstract

The present invention proposes a kind of configurable microcontroller core, including an embedded programmable Gate Array module and a full custom hardware circuit realize module, and the flush door array module is for realizing at least decoding function of instruction set in microcontroller core；By the embedded programmable gate array, the Instruction decoding functional module in microcontroller core can be reconfigured；User according to actual needs, downloads the binary digit stream file of the decoding function module of corresponding some or all of instruction set into the programmable gate array module, to realize the configurable of microcontroller core instruction set.

Description

A kind of application method of configurable microcontroller core
Technical field
The present invention relates to microcontroller technical field more particularly to a kind of configurable microcontroller cores and its user Method.
Background technique
With the development of integrated circuit technique, system on chip (SOC, SystemonChip) and specific integrated circuit (ASIC, ApplicationSpecificIntergratedCircut) technology has been applied in the every aspect in life now.At present System on chip or specific integrated circuit be usually that microcontroller core, memory, bus and various peripheral hardwares be integrated in one On a chip, we illustrate by taking system on chip as an example here, and Figure 1A is the structure chart of system on chip, in the microcontroller in figure Core, major function are the processing and control of data, and the microcontroller in system on chip can be ARM kernel, MIPS kernel etc.；Always Line, major function are that microcontroller core, memory, peripheral hardware and input/output port link together, for the transmission of data, Such as AMBA bus；Memory, for the storage of data and the execution of program, can for Static RAM (SRAM), only Read memory (ROM) or nonvolatile memory；Peripheral hardware, for example, clock timer, real-time clock (RTC, RealTimeClock), intelligent card interface and various communication protocols (SPI, UART, I2C etc.)；Input/output port is mainly used for counting According to output and input.The basic structure of microcontroller core is as shown in Figure 1B, includes arithmetic logic list in microcontroller core Member (ALU), boolean processor, accumulator, floating point processing unit, timing control logic, command register, command decoder, Jie Matter access control module etc..
For microcontroller core, it is manufactured by process flows such as deposit, photoetching, etching and ion implantings Afterwards, all hardware circuits have all been fixed, and cannot be modified, and its instruction set for certain microcontroller core It is fixed, for example microcontroller is ARM kernel, then the instruction set of the microcontroller is just the instruction set of ARM, if micro- Controller is MIPS kernel, then the instruction set of the microcontroller is just the instruction set of MIPS.For each microcontroller For kernel, its instruction set be it is determining, the interpretation method and decoding circuit of instruction set be also it is determining, for different fingers It enables for collection, the corresponding interpretation method of instruction set and decoding circuit are also different, therefore the microcontroller with different instruction set The interpretation method and decoding circuit of device kernel are different, and can not mutually be shared.
For applying in the microcontroller core in Internet of Things and wearable device field, client is in order to meet low-power consumption With the requirement of area, generally can the instruction set based on the microcontroller core certain optimization is done to application program, in order to reach Best optimum results to the optimization of application program generally proximate to bottom, for example on the level of compilation do application program excellent Change rather than done on the level of high-level language and optimize (such as C language), that is to say, that the application program optimized is with microcontroller The instruction set of device kernel has very big connection.Such as be for certain application program developed based on ARM instruction set, and Certain optimization is done, for the client that some possesses MIPS microcontroller core, if it is desired to using the application program one As there are two types of method, a kind of method is to buy microcontroller core based on ARM instruction set to apply the application program, because should Application program is developed based on ARM instruction set, cannot be used directly in the microcontroller core based on MIPS instruction set, but this Sample will increase the hardware cost of client；Another method is that the application program is transplanted to the microcontroller based on MIPS instruction set In device kernel, but a large amount of time if doing so can be consumed, increase the Time To Market of product, and the cost of software development It will increase, so that the cost of system be made to increase.
The microcontroller core of microcontroller core production firm production is in order to meet the needs of all clients, therefore certain The decoding of all instructions of a instruction set is all realized in core within the microcontroller, although meeting the demand of all users in this way, The application scenario of microcontroller core is improved, but also brings some problems, such as portions of client, exploitation Instruction used in major applications program is a part of the microcontroller core instruction set, is not microcontroller core Instruction set in all instructions can all be used, this will result in the waste of microcontroller core area and power consumption, to make At the increase of chip cost, this does not obviously meet the smaller and smaller requirement with low-power consumption of current chip area.
Field programmable gate array (FPGA, FieldProgrammableGateArray) is in programmable logic array (PAL, ProgrammableArrayLogic), gate array logic (GAL, GateArrayLogic) and programming device (PLD, ProgrammableLogicDevice it is developed on the basis of).FPGA is programmable silicon chip, uses patrolling for built in advance Block and programmable interconnection resource are collected, user is not necessarily to through flow and uses circuit board, can configure these chips to realize oneself Want the function of realizing, its appearance solves the deficiency of custom circuit, it is limited to also overcome original programming device gate circuit number The problem of.The basic structure of FPGA is as shown in Figure 1 C, the microcontroller core in figure in 1B, can be directly used in by user entirely The processing and configuration of FPGA system on chip data, if user realizes microcontroller core institute with programmable gate array in FPGA The programmable resource to be used is bigger, and area is also bigger, so the micro-control for having been cured realization is added generally in FPGA Device kernel processed, programmable gate array in figure, mainly by programmable logic cells, connection unit, switch unit and programmable I/O list Member composition.The hardware of microcontroller core in FPGA it has been determined that and the instruction set of microcontroller core have also determined that, It that is is dedicated, if microcontroller core in the FPGA of client is and the client now based on ARM instruction set Application program to be applied is developed based on PowerPC instruction set, then a kind of selection is that purchase is based on for the customer The FPGA of PowerPC, but currently without this FPGA, another option is will be based on the application journey of PowerPC instruction set Sequence is transplanted in the microcontroller core based on ARM instruction set, but this will take some time, and finally a kind of method is to pass through Programmable gate array realizes the microcontroller core based on PowerPC instruction set, but client generally will not when using FPGA It goes to realize a microcontroller core using programmable gate array, if if doing so, in the microcontroller in FPGA Core will not be just used always, then will result in the waste of hardware resource.
For certain microcontroller core, if this microcontroller core is popular at present, it is used in various In the SOC/ASIC/FPGA of occasion, then will result in the anabolic of hardware, so-called hardware it is anabolic that is different productions The product core component (i.e. kernel) of manufacturer is substantially all equally, substantially without otherness, and based in this kind of microcontroller The product of core has been readily accepted by customers, then client when buying product, will directly select based on this kind of microcontroller core Product, then will result in the competitive of other products in this way reduces, and all products are all based on same instruction set Microcontroller core exploitation, the interest that can also make people develop new microcontroller core in this way reduces, and causes novelty Decline.
Summary of the invention
In view of the above technical problems, this application provides a kind of configurable microcontroller core, including one it is embedded can It programs Gate Array module and a full custom hardware circuit realizes module, the embedded programmable Gate Array module, which includes at least, to be used In the Instruction decoding functional module for carrying out decoding processing to instruction in the microcontroller core.
Preferably, the full custom hardware circuit realize module include arithmetic logic unit and/or boolean processor and/or Accumulator and/or floating point processor and/or timing control logic device and/or command register and/or media access control module.
The present invention also provides a kind of application methods of configurable microcontroller core, comprising steps of
S0: a kind of configurable microcontroller core, including an embedded programmable Gate Array module and a full custom it is hard Part circuit realize module, the embedded programmable Gate Array module include at least in the microcontroller core to finger Enable the Instruction decoding functional module for carrying out decoding processing；
S1: user selects the instruction oneself used in corresponding instruction set according to oneself system needs；
S2: the Instruction decoding functional module for configuring the embedded programmable Gate Array module is downloaded；
S3: the user utilizes the synthesizer of the embedded programmable Gate Array module in PC by the finger of downloading Enabling decoding function module converter is binary digit stream file；
S4: by may be programmed input/output port for the binary stream file download to the embedded programmable gate array In module；
S5: the application program based on the instruction set is burnt into code area；
S6: the microcontroller core executes command adapted thereto after system electrification, thereby executing the application program.
Preferably, the step S2 comprising steps of
S21: judge described instruction whether be instruction set a part, if it is so execute S22, otherwise execute S23；
S22: downloading instructs corresponding Instruction decoding described in the embedded programmable Gate Array module for configuring Functional module executes S3；
S23: whole Instruction decoding functional modules for configuring the embedded programmable Gate Array module are downloaded, are held Row S3.
In conclusion by adopting the above-described technical solution, present patent application describes a kind of configurable microcontroller Kernel and its application method, its advantages have: its hardware and instruction set are configurable, and pass through the embedded programmable door Array, command decoder can reconfigure；User according to actual needs, downloads the decoding function module of corresponding instruction set extremely In the programmable gate array module, so that the effect for possessing the microcontroller core of different instruction set is realized, such client There is no need to buy the microcontroller core with other instruction set again.
Detailed description of the invention
Figure 1A is the structural schematic diagram of system on chip in the prior art；
Figure 1B is the structural schematic diagram of microcontroller core in the prior art；
Fig. 1 C is the basic structure schematic diagram of FPGA in the prior art；
Fig. 2 is a kind of structural schematic diagram of configurable microcontroller core of the present invention；
Fig. 3 is a kind of usage state diagram of configurable microcontroller core of the present invention；
Fig. 4 is a kind of application method flow chart one of configurable microcontroller core of the present invention；
Fig. 5 is a kind of application method flowchart 2 of configurable microcontroller core of the present invention；
Fig. 6 is the structure chart of smart home system in the embodiment of the present invention three；
Fig. 7 is the structural schematic diagram of application development packet in the embodiment of the present invention three.
Specific embodiment
A specific embodiment of the invention is further described with reference to the accompanying drawing.
Embodiment one
The present invention provides a kind of configurable microcontroller cores, as shown in Fig. 2, the microcontroller core includes one Embedded programmable Gate Array module and a full custom hardware circuit realize module:
The embedded programmable Gate Array module, for realizing decoding function is at least instructed in the microcontroller core Module, to realize the functions such as the decoding of instruction set；
The full custom hardware circuit realizes that module is connected with the embedded programmable gate array, for realizing described micro- Other modules in controller kernel in addition to the module realized with the embedded programmable gate array.
Wherein, the microcontroller core further includes a programmable input/output port, may be programmed input/output port with it is described Embedded programmable Gate Array module is connected, for downloading corresponding two-stage system bit stream file to the embedded programmable gate array Column module.
The full custom hardware circuit realizes that module includes at least arithmetic logic unit, boolean processor, accumulator, floating-point The modules such as processing unit, timing control logic, command register and media access control module.
Current microcontroller core is realized by full custom hardware circuit, and proposed by the present invention configurable micro- Controller kernel realizes that module forms by programmable gate array module and full custom hardware circuit.Embedded programmable gate array The function of module is: real with embedded programmable gate array the advantages of being reprogramed using embedded programmable gate array At least the decoding function module of instruction set, such client can download accordingly according to their own needs in existing microcontroller core The decoding function module of instruction set possess the microcontroller core of different instruction set to realize, there is no need to again by such client Buy have other instruction set microcontroller core, and every time client download command adapted thereto collection decoding function module when It waits, without downloading all instructions of the instruction set, only uses obtained finger in oneself application program with downloading according to their own needs It enables.And full custom hardware circuit realizes that module is then other modules realized other than the module that microcontroller core is realized, than Such as arithmetic logic unit, boolean processor.
As shown in figure 3, have the synthesizer of an embedded programmable gate array corresponding with the microcontroller core in PC, Specific instruction set decoding function module converter is corresponding binary digit stream file by the synthesizer, by described programmable Input/output port downloads to the binary file in the embedded programmable Gate Array module, to realize microcontroller Instruction set is configurable in kernel.
The present invention provides a kind of configurable microcontroller cores, pass through the embedded programmable gate array, instruction Decoder can reconfigure.
Embodiment two
According to a kind of configurable microcontroller core that above-described embodiment proposes, the present embodiment is based on the microcontroller Kernel proposes a kind of working method of microcontroller core.
As shown in figure 4, the specific works method of the configurable microcontroller core are as follows:
S1: user selects the instruction oneself used in corresponding instruction set according to oneself system needs；
S2: the Instruction decoding functional module for configuring the embedded programmable Gate Array module is downloaded；
S3: client utilizes the synthesizer of the embedded programmable gate array in PC by the described instruction decoding function mould of downloading Block is converted into binary digit stream file；
S4: the binary file is downloaded to by the embedded programmable gate array by the programmable input/output port In column module 01；
S5: the application program based on the instruction set is burnt into code area；
S6: the microcontroller core executes command adapted thereto after system electrification, thereby executing the application program.
In conjunction with Fig. 5, wherein the step S2 comprising steps of
S21: judge described instruction whether be instruction set a part, if it is so execute S22, otherwise execute S23；
S22: downloading is executed for configuring the corresponding Instruction decoding functional module of the embedded programmable Gate Array module S3；
S23: whole Instruction decoding functional modules for configuring the embedded programmable Gate Array module are downloaded, are held Row S3.
It is worth noting that corresponding Instruction decoding functional module refers to corresponding to described instruction in step S22 Instruction decoding functional module.The corresponding Instruction decoding functional module of i.e. different instructions is different, is only when determined described instruction When a part of instruction set, then not needing the whole Instruction decoding functional module of downloading, and only need to download the instruction institute The Instruction decoding functional module needed.
By adding the embedded programmable Gate Array module 01 in traditional microcontroller core, using it is described can The advantages of programming Gate Array module can reprogram, the decoding function of instruction set at least in realization microcontroller core.User According to actual needs, the decoding function module of corresponding instruction set is downloaded into the programmable gate array module, to realize Possess the effect of the microcontroller core of different instruction set, there is no need to be bought again with the micro- of other instruction set such client Controller kernel.And when client downloads corresponding instruction set decoding function module, the whole for downloading the instruction set is not needed Instruction, it is only necessary to download the part instruction used in oneself application program, according to their own needs so as to avoid microcontroller Using the waste of area and power consumption brought by all instructions collection in kernel.
Embodiment three
According to above-described embodiment, the present embodiment refines above embodiment, proposes the present invention in practice Concrete application.
Fig. 6 is a kind of structure chart of smart home system, and the smart home system includes at least: a configurable micro-control Device kernel, a code area, a data field and a chip with other functions processed.The application and development of the smart home system is flat Platform beyond the clouds, i.e., application program needed for the described smart home system and runs the application program corresponding instruction set decoding function The binary digit stream file of energy module, is stored in cloud.
In conjunction with Fig. 7, the cloud shares application developmentpackage corresponding to N number of application program.Wherein, it is based on MIPS instruction set The application program of exploitation has an X, respectively application program M_1, application program M_2 ..., M_X, developed based on ARM instruction set Application program have a Y, respectively application program A_1, application program A_2 ..., A_Y, and corresponding MIPS instruction set The binary digit stream file of the Instruction decoding functional module of the binary digit stream file and ARM instruction set of Instruction decoding functional module It is stored in cloud.For Mr. Yu client, if what the client selected according to their own needs is based on MIPS instruction set The instruction number for the MIPS instruction set that application program M_3, application program M_3 are used is 30, then the client only needs to apply The binary digit stream file for 30 MIPS Instruction decoding functional modules that program M_3 and application program M_3 are used is downloaded from cloud Get off, the code area of application program M_3 storage in systems, 30 MIPS Instruction decoding function moulds that application program M_3 is used The binary digit stream file of block is downloaded in the embedded programmable Gate Array module 01 in configurable microcontroller core 1, System can directly executing application M_3 in this way.If client now according to oneself need selection referred to based on ARM Enable the application program A_1 of collection, the instruction number of the ARM instruction set that application program A_1 is used is 40, then the client only need by The binary digit stream file for 40 ARM instruction decoding function modules that application program A_1 and application program A_1 are used is under cloud Load is got off, the code area of application program A_1 storage in systems, 40 ARM instruction decoding function moulds that application program A_1 is used The binary digit stream file of block is downloaded in the embedded programmable Gate Array module in configurable microcontroller core 1, this Sample system can directly executing application A_1.
A kind of microcontroller core that the present embodiment proposes, if client needs to run the application journey based on certain instruction set Sequence, it is only necessary to download the corresponding instruction that corresponding application program and the application program are used from application development platform and concentrate accordingly Decoding function module binary digit stream file.The application based on fixed instruction collection can only be run in conventional microcontroller kernel Program cannot run the application program based on other instruction set, if it is desired to the application program of other instruction set is run, it is just necessary It buys corresponding hardware and needs to transplant the application program, and utilize controllable microcontroller core proposed by the present invention, section The expense for having saved hardware and software reduces the Time To Market of product.
The foregoing is merely preferred embodiments of the present invention, are not intended to limit embodiments of the present invention and protection model It encloses, to those skilled in the art, should can appreciate that and all be made with description of the invention and diagramatic content Equivalent replacement and obviously change obtained scheme, should all be included within the scope of the present invention.

Claims (2)

1. a kind of application method of configurable microcontroller core, which is characterized in that comprising steps of
S0: providing a kind of configurable microcontroller core, including an embedded programmable Gate Array module and a full custom it is hard Part circuit realize module, the embedded programmable Gate Array module include at least in the microcontroller core to finger Enable the Instruction decoding functional module for carrying out decoding processing；
S1: user selects the instruction oneself used in corresponding instruction set according to oneself system needs；
S2: the Instruction decoding functional module for configuring the embedded programmable Gate Array module is downloaded；
S3: the user is translated the described instruction of downloading using the synthesizer of the embedded programmable Gate Array module in PC Code functional module is converted into binary digit stream file；
S4: by may be programmed input/output port for the bit stream file download to the embedded programmable gate array mould In block；
S5: the application program based on the instruction set is burnt into code area；
S6: the microcontroller core executes command adapted thereto after system electrification, thereby executing the application program.
2. the application method of configurable microcontroller core according to claim 1, which is characterized in that the step S2 packet Include step:
S21: judge described instruction whether be instruction set a part, if it is so execute S22, otherwise execute S23；
S22: downloading instructs corresponding Instruction decoding function for configuring described in the embedded programmable Gate Array module Module executes S3；
S23: whole Instruction decoding functional modules for configuring the embedded programmable Gate Array module are downloaded, are executed S3。
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CN108108191A (en) * 2018-01-09 2018-06-01 湖南国科微电子股份有限公司 A kind of collocation method of SOC chip and SOC chip cpu instruction collection
CN111209037A (en) * 2018-11-22 2020-05-29 深圳市中兴微电子技术有限公司 RISC processor architecture and its realizing method
CN111460746A (en) * 2020-03-31 2020-07-28 上海安路信息科技有限公司 Method and device for realizing circuit design by FPGA IP soft core and FPGA chip
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CN102200905A (en) * 2010-03-26 2011-09-28 Mips技术公司 Microprocessor with compact instruction set architecture
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