CN115225592A - Direct memory access data transmission method and system - Google Patents
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- CN115225592A CN115225592A CN202210617295.1A CN202210617295A CN115225592A CN 115225592 A CN115225592 A CN 115225592A CN 202210617295 A CN202210617295 A CN 202210617295A CN 115225592 A CN115225592 A CN 115225592A
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 70
- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000004891 communication Methods 0.000 claims abstract description 39
- 230000002776 aggregation Effects 0.000 claims abstract description 26
- 238000004220 aggregation Methods 0.000 claims abstract description 26
- 238000012546 transfer Methods 0.000 claims description 15
- 238000012545 processing Methods 0.000 claims description 11
- 230000004931 aggregating effect Effects 0.000 claims description 6
- 230000001960 triggered effect Effects 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9057—Arrangements for supporting packet reassembly or resequencing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9036—Common buffer combined with individual queues
Abstract
The invention provides a direct memory access data transmission method and a system, which relate to the technical field of network communication and comprise the following steps: when an operating system of a computer system sends data outwards, network data packets sent each time are dispersed into a plurality of sending packets which are respectively stored in different memory addresses, and a linked list is correspondingly generated; the driver acquires and sequentially aggregates corresponding sending packets from each memory address to a data sending buffer area according to the sending sequence in the linked list, and in the aggregation process, adds a first separator between two adjacent sending packets and executes direct memory access when the data sending buffer area reaches a first transmission standard each time so as to move all the currently aggregated sending packets in the data sending buffer area to the communication hardware equipment; the communication hardware device identifies each transmitted packet for transmission based on each first delimiter. The method has the advantages of reducing the access times of the direct memory and effectively improving the transceiving performance of the network data packet, particularly the packet on the network.
Description
Technical Field
The present invention relates to the field of network communication technologies, and in particular, to a method and a system for transmitting dma data.
Background
When sending a network packet, a popular computer operating system, such as a windows operating system or a linux operating system, uses a scatter List structure/gather List structure to scatter a network packet to a plurality of discrete Memory addresses for storage, such as containing two or more MDLs (Memory Descriptor lists ) for storing data, where each MDL (Memory Descriptor List ) is a Memory block. When a DMA (Direct Memory Access) mode is used for transmitting network data packets, since a DMA burst is triggered for each Memory block by the current communication hardware devices on the market, several DMA bursts are required for transmitting each network data packet. If the data packets are small, such as game applications and real-time audio applications, each data packet is about 100Bytes, the DMA applies for a bus once, the amount of data transmitted is small, and the DMA performance is reduced at this time, so that the network transmission performance is reduced sharply. Similarly, there is a similar problem in data reception.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a direct memory access data transmission method, which comprises the steps of configuring a computer system in advance, wherein the computer system is loaded with communication hardware equipment and is correspondingly provided with a driving program of the communication hardware equipment, and the computer system is also provided with a data sending cache region;
the direct memory access data transfer method includes a data sending process, the data sending process including:
step S1, when an operating system of the computer system sends data outwards, dispersing network data packets sent each time into a plurality of sending packets, storing the sending packets in different memory addresses respectively, and correspondingly generating a linked list, wherein the linked list is configured with the sending sequence of each sending packet and the corresponding memory address;
step S2, the driver acquires the linked list, sequentially aggregates the corresponding sending packets to the data sending buffer area from each memory address according to the sending sequence in the linked list, adds a first separator between two adjacent sending packets in the aggregation process, and executes direct memory access when the data sending buffer area reaches a first transmission standard each time so as to move all the sending packets currently aggregated in the data sending buffer area to the communication hardware equipment;
and S3, the communication hardware equipment identifies each sending packet according to each first separator so as to correspondingly send each sending packet to the network.
Preferably, in the step S2, when the occupied space of the data sending buffer reaches a first space value or the aggregation time reaches a first time value, it indicates that the data sending buffer reaches the first transmission standard.
Preferably, if a data receiving buffer is configured in the communication hardware device, the direct memory access data transmission method further includes a data receiving process, where the data receiving process includes:
step A1, when receiving a plurality of received packets sent by the network, the communication hardware device sequentially aggregates the received packets to the data receiving buffer according to a receiving order, adds a second separator between two adjacent received packets, and performs a dma each time the data receiving buffer reaches a second transmission standard, so as to move all the currently aggregated received packets in the data receiving buffer to the driver;
step A2, the driver identifies each received packet according to each second delimiter, so as to correspondingly send each received packet to the operating system.
Preferably, in the step A1, when the occupied space of the data receiving buffer reaches a second space value or the aggregation time reaches a second time value, it indicates that the data receiving buffer reaches the second transmission standard.
The invention also provides a direct memory access data transmission system, which applies the direct memory access data transmission method and comprises the following steps:
a computer system having communications hardware devices loaded thereon, the computer system comprising:
the operating system is used for dispersing the network data packets sent each time into a plurality of sending packets to be stored in different memory addresses respectively when data are sent outwards, and correspondingly generating a linked list, wherein the linked list is configured with the sending sequence of each sending packet and the corresponding memory address;
the driver is connected with a data sending buffer, and comprises a first processing unit, a second processing unit and a communication hardware device, wherein the first processing unit is used for acquiring the linked list, sequentially aggregating the corresponding sending packets from each memory address to the data sending buffer according to the sending sequence in the linked list, adding a first separator between every two adjacent sending packets in the aggregation process, and executing direct memory access when the data sending buffer reaches a first transmission standard each time so as to move all the sending packets aggregated currently in the data sending buffer to the communication hardware device;
the communication hardware device comprises a first identification unit, which is used for identifying each sending packet according to each first separator so as to correspondingly send each sending packet to a network.
Preferably, when the occupied space of the data sending buffer reaches a first space value or the aggregation time reaches a first time value, it indicates that the data sending buffer reaches the first transmission standard.
Preferably, the communication hardware device further comprises:
the second processing unit is connected with a data receiving buffer area, and is used for sequentially aggregating each receiving packet to the data receiving buffer area according to a receiving sequence when receiving a plurality of receiving packets sent by the network, adding a second separator between two adjacent receiving packets, and executing one direct memory access when the data receiving buffer area reaches a second transmission standard each time so as to move all the currently aggregated receiving packets in the data receiving buffer area to the driving program;
the driver further includes a second identifying unit for identifying each of the received packets according to each of the second separators, so as to send each of the received packets to the operating system.
Preferably, when the occupied space of the data receiving buffer reaches a second space value or the aggregation time reaches a second time value, it indicates that the data receiving buffer reaches the second transmission standard.
The technical scheme has the following advantages or beneficial effects:
1) When a computer system sends a network data packet to a network, by aggregating sending packets scattered in different memory addresses together and similarly aggregating a plurality of receiving packets together when receiving the network data packet, a direct memory access operation is triggered only when the aggregation operation meets corresponding transmission standards, thereby effectively reducing the direct memory access times and further effectively improving the transceiving performance of the network data packet, particularly a small packet, on the network;
2) When the aggregation is carried out, the sending packets or the receiving packets are separated by adopting corresponding separators, so that the effective identification of the sending packets or the receiving packets after the data transportation is realized.
Drawings
FIG. 1 is a flow chart illustrating a data transmission process according to a preferred embodiment of the present invention;
FIG. 2 is a flow chart illustrating a data receiving process according to a preferred embodiment of the present invention;
FIG. 3 is a block diagram of a DMA data transfer system according to an embodiment of the present invention.
Detailed Description
The invention is described in detail below with reference to the figures and specific embodiments. The present invention is not limited to the embodiment, and other embodiments may be included in the scope of the present invention as long as the gist of the present invention is satisfied.
In a preferred embodiment of the present invention, based on the above problems in the prior art, a method for transmitting data accessed by a direct memory is provided, in which a computer system is configured in advance, a communication hardware device is loaded on the computer system, a driver of the communication hardware device is installed correspondingly, and a data transmission buffer is also configured in the computer system;
the direct memory access data transmission method includes a data transmission process, as shown in fig. 1, the data transmission process includes:
step S1, when an operating system of a computer system sends data outwards, dispersing network data packets sent each time into a plurality of sending packets, storing the sending packets in different memory addresses respectively, and correspondingly generating a linked list, wherein the linked list is configured with the sending sequence and the corresponding memory address of each sending packet;
s2, the driver acquires the linked list, sequentially aggregates corresponding sending packets to a data sending cache region from each memory address according to the sending sequence in the linked list, adds a first separator between two adjacent sending packets in the aggregation process, and executes direct memory access when the data sending cache region reaches a first transmission standard each time so as to move all the currently aggregated sending packets in the data sending cache region to the communication hardware equipment;
and S3, the communication hardware equipment identifies each sending packet according to each first separator so as to correspondingly send each sending packet to the network.
Specifically, in this embodiment, the communication hardware device includes, but is not limited to, a network card, a wifi device, and a bluetooth device. When the operating system sends data outwards, one or more network data packets sent each time can be generated, a linked list can be correspondingly generated for each data packet, or a plurality of network data packets sent each time can be correspondingly generated into a linked list, and the plurality of network data packets also have corresponding sending sequences in the linked list.
Taking a single network data packet as an example, the network data packet may include a plurality of transmission packets, and after the driver acquires the linked list, the driver sequentially copies each transmission packet to the data transmission buffer according to the transmission sequence of each transmission packet to perform aggregation, it may be understood that the storage space of the data transmission buffer is limited, and therefore, a corresponding first transmission standard needs to be set as a trigger condition for direct memory access.
Specifically, in this embodiment, on the premise that the storage space of the data sending buffer is limited, if the network data packet includes too many sending packets, for example, 10 sending packets, and the corresponding data sending buffer can only store 8 sending packets at most, after 8 sending packets in the first sending sequence are copied and the corresponding first separator is added, a dma is performed, and then the remaining 2 sending packets are also copied and aggregated, and so on. Because the aggregated data sending buffer area is a continuous memory, when the data is required to be sent according to the first transmission standard, the data in the data sending buffer area can be moved to the communication hardware equipment by using only one direct memory access. The netperf is used for testing the performance of the small packet to be sent, and the technical scheme can improve the performance of the small packet by 15%.
As a preferred embodiment, when executing the aggregation operation, the driver may process, according to the transmission order of the linked list, based on the storage space of the driver, the occupied memory of each transmission packet, and the first space value before aggregation to obtain which transmission packets can be aggregated to the data transmission buffer, and then sequentially copy each transmission packet according to the corresponding memory address, where a first separator is added before or after each copy of a transmission packet.
As another preferred embodiment, when executing the aggregation operation, the driver may, according to the sending order of the linked list, check the occupied space and the remaining space of the data sending buffer and the occupied memory of the sending packet before copying a sending packet each time, then determine whether the sending packet can be aggregated this time, and similarly, if the aggregation is possible, sequentially copy each sending packet according to the corresponding memory address, and add a first separator before or after copying a sending packet each time until the occupied space of the data sending buffer reaches the first space value.
It can be seen that, in the above embodiment, only whether the occupied space of the data sending buffer reaches the first space value is considered, and if the operating system sends more network data packets each time or the data amount of each network data packet is large, the occupied space of the data sending buffer can reach the first space value quickly, and the requirements for reducing the number of times of direct memory access and reducing the data transmission delay can be met only by considering whether the occupied space of the data sending buffer reaches the first space value. However, if the number of network data packets sent by the operating system each time is small, for example, only one network data packet is sent, and the data volume of the network data packet is small, that is, after all the sent packets of the network data packet are aggregated to the data sending buffer, the occupied space of the data sending buffer still cannot reach the first space value. At this moment, if the next network data packet is sent after a long time, long-time waiting can cause high delay, based on the fact that a timer can be configured at the same time, timing is triggered when aggregation operation is started, and when the aggregation time consumption reaches a first time value, even if the occupied space of the data sending cache region does not reach the first space value, direct memory access can be triggered and executed, so that the time of direct memory access is reduced, and the delay condition is comprehensively considered.
It is to be understood that the first transmission criterion may be configured to at least one of the occupied space of the data sending buffer region reaching a first space value and the aggregation time reaching a first time value according to the application scenario. In addition, the first transmission standard may also be configured such that the number of the transmission packets aggregated this time reaches a preset threshold.
In this embodiment, the first spatial value and the first time value may be unique values respectively, or may be multiple values respectively, and may be configured as required. Taking a plurality of first time values as an example, a shorter first time value can be configured correspondingly according to real-time requirements, such as higher real-time requirements in a game mode, and a longer first time value can be configured correspondingly, such as lower real-time requirements, in an actual application scene, a driver can recognize the real-time requirements through software configuration, and then dynamically adapt to the corresponding first time value. The first spatial value is analogized, and the description is omitted here.
In a preferred embodiment of the present invention, a data receiving buffer is configured in the communication hardware device, and the dma data transmission method further includes a data receiving process, as shown in fig. 2, the data receiving process includes:
a1, when receiving a plurality of receiving packets sent by a network, a communication hardware device sequentially aggregates the receiving packets to a data receiving buffer area according to a receiving sequence, adds a second separator between two adjacent receiving packets, and executes direct memory access when the data receiving buffer area reaches a second transmission standard each time so as to move all the currently aggregated receiving packets in the data receiving buffer area to a driver;
and step A2, the driver identifies each receiving packet according to each second delimiter so as to correspondingly send each receiving packet to the operating system.
Specifically, in this embodiment, the data receiving process is the reverse of the data transmission path in the data sending process, but the data aggregation operation and the identification operation are the same as the data receiving process, and the specific process is not described herein again.
In a preferred embodiment of the present invention, in step A1, when the occupied space of the data receiving buffer reaches a second space value or the aggregation time reaches a second time value, it indicates that the data receiving buffer reaches the second transmission standard.
Specifically, in this embodiment, the configuration principle of the second transmission standard is the same as that of the first transmission standard, and details are not described here. It is understood that the specific values of the first spatial value and the second spatial value may be the same or different, and the specific values of the first time value and the second time value may be the same or different. Wherein the first spatial value is preferably a maximum transmission unit.
The present invention further provides a dma data transfer system, which applies the above dma data transfer method, as shown in fig. 3, the dma data transfer system includes:
a computer system 1, wherein a communication hardware device 2 is loaded on the computer system 1, the computer system 1 comprises:
the operating system 11 is configured to, when data is sent to the outside, disperse a network data packet sent each time into a plurality of sending packets, store the sending packets in different memory addresses, and generate a linked list correspondingly, where the sending order and the corresponding memory address of each sending packet are configured in the linked list;
the driver 12 is connected to a data sending buffer 13, the driver 12 includes a first processing unit 121, configured to acquire a linked list, sequentially aggregate corresponding sending packets from each memory address to the data sending buffer according to a sending order in the linked list, add a first separator between two adjacent sending packets in the aggregation process, and perform a direct memory access when the data sending buffer reaches a first transmission standard each time, so as to move all currently aggregated sending packets in the data sending buffer to the communication hardware device;
the communication hardware device 2 comprises a first identification unit 21 for identifying each of the transmitted packets according to each of the first spacers, so as to transmit each of the transmitted packets into the network accordingly.
In a preferred embodiment of the present invention, when the occupied space of the data transmission buffer reaches a first space value or the aggregation time reaches a first time value, it indicates that the data transmission buffer reaches the first transmission standard.
In a preferred embodiment of the present invention, the communication hardware device 2 further comprises:
the second processing unit 22 is connected to a data receiving buffer 23, and the second processing unit 22 is configured to, when receiving multiple received packets sent by the network, sequentially aggregate the received packets to the data receiving buffer according to a receiving order, add a second delimiter between two adjacent received packets, and perform a dma each time the data receiving buffer reaches a second transmission standard, so as to move all currently aggregated received packets in the data receiving buffer to the driver;
the driver 12 further includes a second identifying unit 122 for identifying each received packet according to each second delimiter so as to send each received packet to the operating system accordingly.
In a preferred embodiment of the present invention, when the occupied space of the data receiving buffer reaches a second space value or the aggregation time reaches a second time value, it indicates that the data receiving buffer reaches the second transmission standard.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (8)
1. A direct memory access data transmission method is characterized in that a computer system is configured in advance, communication hardware equipment is loaded on the computer system, a driver of the communication hardware equipment is correspondingly installed on the computer system, and a data sending cache region is also configured in the computer system;
the direct memory access data transmission method includes a data transmission process, the data transmission process including:
step S1, when an operating system of the computer system sends data outwards, dispersing network data packets sent each time into a plurality of sending packets, storing the sending packets in different memory addresses respectively, and correspondingly generating a linked list, wherein the linked list is configured with the sending sequence of each sending packet and the corresponding memory address;
step S2, the driver acquires the linked list, sequentially aggregates the corresponding sending packets to the data sending buffer area from each memory address according to the sending sequence in the linked list, adds a first separator between two adjacent sending packets in the aggregation process, and executes direct memory access when the data sending buffer area reaches a first transmission standard each time so as to move all the sending packets currently aggregated in the data sending buffer area to the communication hardware equipment;
and S3, the communication hardware equipment identifies each sending packet according to each first separator so as to correspondingly send each sending packet to the network.
2. The dma data transmission method according to claim 1, wherein in step S2, when the occupied space of the data transmission buffer reaches a first space value or the aggregation time reaches a first time value, it indicates that the data transmission buffer reaches the first transmission standard.
3. The dma data transfer method of claim 1, wherein a data receiving buffer is configured in the communication hardware device, and the dma data transfer method further comprises a data receiving process, and the data receiving process comprises:
step A1, when receiving a plurality of received packets sent by the network, the communication hardware device sequentially aggregates the received packets to the data receiving buffer according to a receiving order, adds a second separator between two adjacent received packets, and performs a dma each time the data receiving buffer reaches a second transmission standard, so as to move all the currently aggregated received packets in the data receiving buffer to the driver;
step A2, the driver identifies each receiving packet according to each second delimiter, so as to correspondingly send each receiving packet to the operating system.
4. The dma data transmission method according to claim 3, wherein in step A1, when the occupied space of the data receiving buffer reaches a second space value or the aggregate time reaches a second time value, it indicates that the data receiving buffer reaches the second transmission standard.
5. A direct memory access data transfer system to which the direct memory access data transfer method according to any one of claims 1 to 4 is applied, the direct memory access data transfer system comprising:
a computer system having communications hardware devices loaded thereon, the computer system comprising:
the operating system is used for dispersing the network data packets sent each time into a plurality of sending packets to be stored in different memory addresses respectively when data are sent outwards, and correspondingly generating a linked list, wherein the linked list is configured with the sending sequence of each sending packet and the corresponding memory address;
the driver is connected with a data sending buffer, and comprises a first processing unit, a second processing unit and a communication hardware device, wherein the first processing unit is used for acquiring the linked list, sequentially aggregating the corresponding sending packets from each memory address to the data sending buffer according to the sending sequence in the linked list, adding a first separator between every two adjacent sending packets in the aggregation process, and executing direct memory access when the data sending buffer reaches a first transmission standard each time so as to move all the sending packets aggregated currently in the data sending buffer to the communication hardware device;
the communication hardware device comprises a first identification unit, which is used for identifying each sending packet according to each first separator, so as to send each sending packet to the network correspondingly.
6. The DMA data transfer system of claim 5, wherein the data send buffer meets the first transfer criteria when the occupancy of the data send buffer reaches a first space value or the aggregate elapsed time reaches a first time value.
7. The dma data transfer system of claim 5, wherein the communication hardware device further comprises:
the second processing unit is connected with a data receiving buffer area, and is used for sequentially aggregating each receiving packet to the data receiving buffer area according to a receiving sequence when receiving a plurality of receiving packets sent by the network, adding a second separator between two adjacent receiving packets, and executing one direct memory access when the data receiving buffer area reaches a second transmission standard each time so as to move all the currently aggregated receiving packets in the data receiving buffer area to the driving program;
the driver further includes a second identifying unit for identifying each of the received packets according to each of the second separators, so as to send each of the received packets to the operating system.
8. The DMA data transfer system of claim 7, wherein the data receiving buffer meets the second transfer criteria when the occupation space of the data receiving buffer reaches a second space value or the aggregate time reaches a second time value.
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