CN115224129A - Planar power MOS device and preparation method thereof - Google Patents

Planar power MOS device and preparation method thereof Download PDF

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Publication number
CN115224129A
CN115224129A CN202210713117.9A CN202210713117A CN115224129A CN 115224129 A CN115224129 A CN 115224129A CN 202210713117 A CN202210713117 A CN 202210713117A CN 115224129 A CN115224129 A CN 115224129A
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region
source
drain
gate
redundant
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黄汇钦
吴龙江
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Sirius Semiconductor Chengdu Co ltd
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Sirius Semiconductor Chengdu Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

The application belongs to the technical field of semiconductors and provides a planar power MOS device and a preparation method thereof, wherein the planar power MOS device comprises: the semiconductor device comprises a semiconductor substrate, an N-type well region, a P-type well region, a grid oxide layer, a grid metal layer, a source electrode region, a P-type doped region, an isolation region, a drain electrode region, at least one of a grid redundant region, a drain redundant region and a source redundant region. At least one of a grid redundant area, a drain redundant area and a source redundant area is arranged in the planar power MOS device; the breakdown effect of the edge region of the planar power MOS device is greatly reduced, the electric field and the stress of the planar power MOS device are reduced, and the gate redundant region, the drain redundant region and the source redundant region are only arranged at the edge region of the planar power MOS device, so that the performance of the middle region of the planar power MOS device is kept, the performance of the device is kept to the maximum extent, and the pressure resistance of the power MOS device is improved.

Description

Planar power MOS device and preparation method thereof
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a planar power MOS device and a preparation method thereof.
Background
The common MOSFET is only suitable for the condition that the breakdown voltage of a drain electrode and a source electrode is low, the voltage is limited to 10V-30V in practice, the limitation is mainly caused by the common MOSFET structure, firstly, the channel length required in the application of high drain-source voltage is very long, and the increase of the channel length can bring unacceptable channel resistance and further increase the area of a device; secondly, the higher the drain-source voltage, the higher the electric field strength at the gate oxide layer at the interface of the drain and the source, which requires a thicker gate oxide layer, thereby having a serious influence on the threshold voltage of the device.
However, under the trend of miniaturization of the existing power MOS device, the development of the power MOS device is limited only by increasing the distance between the drain and the source to improve the voltage resistance of the power MOS device.
Therefore, the conventional planar power MOS device has the problems of large volume and poor voltage withstanding performance.
Disclosure of Invention
In order to solve the above technical problem, embodiments of the present application provide a planar power MOS device and a method for manufacturing the same, which can solve the problems of a large volume and poor voltage endurance of the existing planar power MOS device.
A first aspect of an embodiment of the present application provides a planar power MOS device, including:
a semiconductor substrate;
the N-type well region and the P-type well region are in contact and are both positioned on the semiconductor substrate;
the grid oxide layer is positioned on the N-type well region and the P-type well region;
the grid metal layer is positioned on the grid oxide layer;
the source region and the P-type doped region are arranged on the P-type well region, the source region is in contact with the gate oxide layer, and the P-type doped region is in contact with the source region;
the isolation region and the drain region are arranged on the N-type well region, and the isolation region is arranged between the drain region and the gate oxide layer; and
at least one of a gate redundant region, a drain redundant region, and a source redundant region;
the grid redundant region is arranged on the grid oxide layer and positioned at two ends of the grid metal layer; wherein the material of the gate redundant region is different from the material of the gate metal layer;
the drain electrode redundant region is arranged on the N-type well region, positioned at two ends of the drain electrode region and respectively contacted with the drain electrode region and the isolation region; wherein the material of the drain redundant region is different from the material of the drain region;
the source redundant region is arranged on the P-type well region, positioned at two ends of the source region and respectively contacted with the source region and the P-type doped region; wherein the material of the source redundant region is different from the material of the source region.
In one embodiment, the planar power MOS device further includes:
the inversion layer is arranged between the N-type well region and the drain region and is in contact with the isolation region;
wherein a doping type of the inversion layer is different from a doping type of the drain region.
In one embodiment, the gate redundancy region includes: a first gate redundancy unit and a second gate redundancy unit; wherein, the first and the second end of the pipe are connected with each other,
the first grid redundancy unit is arranged at the first end of the grid metal layer, the second grid redundancy unit is arranged at the second end of the grid metal layer, and the first grid redundancy unit and the second grid redundancy unit are not in contact with each other.
In one embodiment, the drain redundancy region includes: a first drain redundancy unit and a second drain redundancy unit; wherein the content of the first and second substances,
the first drain electrode redundant unit is arranged at the first end of the drain electrode area, the second drain electrode redundant unit is arranged at the second end of the drain electrode area, and the first drain electrode redundant unit and the second drain electrode redundant unit are not contacted with each other.
In one embodiment, the source redundancy region includes: a first source redundancy cell and a second source redundancy cell; wherein the content of the first and second substances,
the first source redundancy unit is arranged at the first end of the source region, the second source redundancy unit is arranged at the second end of the source region, and the first source redundancy unit and the second source redundancy unit are not contacted with each other.
In one embodiment, the first gate redundancy unit and the second gate redundancy unit have the same width as the gate metal layer, and the first gate redundancy unit and the second gate redundancy unit have the same thickness as the gate metal layer.
In one embodiment, the lengths of the first gate redundancy unit and the second gate redundancy unit are both in the range of 10% -30% of the length of the gate oxide layer.
In one embodiment, the first gate redundancy unit and the second gate redundancy unit are symmetrically disposed.
In one embodiment, the sum of the lengths of the gate redundancy region and the gate metal layer is less than or equal to the length of the gate oxide layer.
A second aspect of the present application provides a method for manufacturing a planar power MOS device, including:
providing a semiconductor substrate;
sequentially forming an N-type well region and a P-type well region on the semiconductor substrate; wherein the N-type well region is in contact with the P-type well region;
forming a source region and a P-type doped region on the P-type well region; wherein the P-type doped region is in contact with the source region;
forming an isolation region and a drain region on the N-type well region; wherein the isolation region is in contact with the drain region;
forming a grid oxide layer on the N-type well region, the P-type well region, the source region and the isolation region, and forming a grid metal layer on the grid oxide layer; and
forming a grid redundant area on the grid oxide layer, wherein the grid redundant area is arranged at two ends of the grid metal layer; the material of the gate redundant region is different from that of the gate metal layer; or/and
forming a drain redundant region on the N-type well region, wherein the drain redundant region is arranged at two ends of the drain region and is respectively contacted with the drain region and the isolation region; the material of the drain redundant region is different from that of the drain region; or/and
forming source redundant regions on the P-type well region, wherein the source redundant regions are arranged at two ends of the source region and are respectively contacted with the source region and the P-type doped region; wherein the material of the source redundancy region is different from the material of the source region.
Compared with the prior art, the embodiment of the application has the advantages that: at least one of a grid redundant area, a drain redundant area and a source redundant area is arranged in the planar power MOS device; the breakdown effect of the edge area of the planar power MOS device is greatly reduced, the electric field and the stress of the planar power MOS device are reduced, and the grid redundant area, the drain redundant area and the source redundant area are only arranged in the edge area of the planar power MOS device, so that the performance of the middle area of the planar power MOS device is reserved, the performance of the device is reserved to the maximum extent, and the pressure resistance of the power MOS device is improved. In addition, at least one of a grid redundant area, a drain redundant area and a source redundant area is added, and the withstand voltage of the planar power MOS device is greatly improved on the basis of not adding any process step and photomask. The problems of large volume and poor pressure resistance of the existing planar power MOS device are solved.
Drawings
Fig. 1 is a schematic view of a vertical-plane structure of a planar power MOS device according to an embodiment of the present application;
fig. 2 is a schematic top view of a planar power MOS device according to an embodiment of the present application;
fig. 3 is a schematic top view of a planar power MOS device according to another embodiment of the present application;
fig. 4 is a schematic diagram illustrating an edge region structure of a planar power MOS device according to an embodiment of the present application;
fig. 5 is a schematic diagram illustrating an inversion layer structure of a planar power MOS device according to an embodiment of the present application;
fig. 6 is a schematic diagram illustrating a specific structure of a gate redundancy region of a planar power MOS device according to an embodiment of the present application;
fig. 7 is a schematic diagram illustrating steps of a method for fabricating a planar power MOS device according to an embodiment of the present application;
FIG. 8 illustrates an embodiment of the present invention after forming N-well and P-well regions;
fig. 9 is a schematic diagram illustrating a source region and a P-type doped region formed according to an embodiment of the present application;
FIG. 10 is a schematic diagram illustrating the formation of drain regions and isolation regions according to one embodiment of the present application;
FIG. 11 is a schematic diagram illustrating a gate oxide layer and a gate metal layer formed according to one embodiment of the present disclosure;
fig. 12 is a schematic diagram illustrating a gate redundant region, a drain redundant region, and a source redundant region formed according to an embodiment of the present application.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means one or more unless specifically limited otherwise.
As is well known, a common MOSFET is only suitable for a situation that the breakdown voltage of a drain and a source is low, and in practice, the voltage is limited to 10V-30V, which is mainly limited by the structure of the common MOSFET, firstly, the channel length required in the application of high drain-source voltage is very long, and the increase of the channel length brings unacceptable channel resistance, and further increases the area of a device; secondly, the higher the drain-source voltage, the stronger the electric field strength at the gate oxide layer at the drain and source interfaces, which requires a thicker gate oxide layer, thereby having a severe effect on the threshold voltage of the device.
However, under the trend of miniaturization of the existing power MOS device, the development of the power MOS device is limited only by increasing the distance between the drain and the source to improve the voltage resistance of the power MOS device.
Therefore, the conventional planar power MOS device has the problems of large volume and poor pressure resistance.
In order to solve the above technical problem, embodiments of the present invention provide a planar power MOS device, as shown in fig. 1, fig. 2, and fig. 3, wherein the planar power MOS device includes: the semiconductor device includes a semiconductor substrate 10, an N-type well region 20, a P-type well region 30, a gate oxide layer 40, a gate metal layer 50, a source region 60, a P-type doped region 70, an isolation region 80, a drain region 90, and at least one of a gate redundancy region 110, a drain redundancy region 120, and a source redundancy region 130.
Specifically, the N-type well region 20 and the P-type well region 30 are in contact and both located on the semiconductor substrate 10; the gate oxide layer 40 is located on the N-type well region 20 and the P-type well region 30; the gate metal layer 50 is positioned on the gate oxide layer 40; the source region 60 and the P-type doped region 70 are disposed on the P-type well region 30, the source region 60 is in contact with the gate oxide layer 40, and the P-type doped region 70 is in contact with the source region 60; the isolation region 80 and the drain region 90 are disposed on the N-well 20, and the isolation region 80 is disposed between the drain region 90 and the gate oxide layer 40; the gate redundancy region 110 is disposed on the gate oxide layer 40 and located at two ends of the gate metal layer 50; wherein, the material of the gate redundant region 110 is different from the material of the gate metal layer 50; the drain redundant region 120 is disposed on the N-well region 20 and located at two ends of the drain region 90, and is in contact with the drain region 90 and the isolation region 80, respectively; wherein, the material of the drain redundant region 120 is different from that of the drain region 90; the source redundancy region 130 is disposed on the P-well region 30 and located at two ends of the source region 60, and is in contact with the source region 60 and the P-doped region 70, respectively; wherein the material of the source redundant region 130 is different from the material of the source region 60.
In the present embodiment, when the planar power MOS device is used in different application scenarios, the required withstand voltage is different, and when the conventional planar power MOS device needs a high withstand voltage, the withstand voltage of the planar power MOS device is generally increased by increasing the distance between the source region 60 and the drain region 90. However, this operation greatly increases the volume of the planar power MOS device, which not only causes material loss, but also results in undesirable breakdown voltage. Simulation and experiment of TCAD (Technology Computer aid Design) shows that the electric field and stress are maximum at the edge of the device (10% -30% area, refer to area a and area B in fig. 4), and the breakdown effect occurs in the edge area first when the reverse bias is increased, which limits the breakdown voltage of the device. In the embodiment of the present application, a redundant device is disposed in a region of the planar power MOS device where a punch-through effect is likely to occur, that is, at least one of the gate redundant region 110, the drain redundant region 120, and the source redundant region 130 is disposed, so as to improve the withstand voltage capability of the planar power MOS device.
In this embodiment, referring to fig. 2 and 3, the planar power MOS device at least includes: at least one of the gate redundant region 110, the drain redundant region 120, and the source redundant region 130. It is understood that only one of the gate redundant region 110, the drain redundant region 120, and the source redundant region 130 may be included, and two or all of them may be included. Specifically, the gate redundancy region 110 is disposed on the gate oxide layer 40 and located at two ends of the gate metal layer 50; wherein, the material of the gate redundant region 110 is different from the material of the gate metal layer 50. It can be understood that the gate redundancy region 110 is disposed in a region where a breakdown effect is likely to occur at two ends of the gate metal layer 50, that is, in a region of 10% -30% of an edge of the gate metal layer 50, and by disposing the gate redundancy region 110 with a material different from that of the gate metal layer 50, the region where the gate redundancy region 110 is disposed cannot operate due to the absence of the gate metal layer 50, so that the breakdown effect of the edge region of the planar power MOS device is greatly reduced, and an electric field and stress of the planar power MOS device are reduced.
In the present embodiment, the source redundancy regions 130 are disposed on the P-well region 30 and located at two ends of the source region 60, and are respectively in contact with the source region 60 and the P-type doped region 70; wherein the material of the source redundancy region 130 is different from the material of the source region 60. It can be understood that the source redundancy regions 130 are disposed at two ends of the source region 60, where the breakdown effect is likely to occur, i.e. 10% -30% of the edge of the source region 60, and by disposing the source redundancy regions 130 with a different material from that of the source region 60, the region where the source redundancy regions 130 are disposed cannot work due to the absence of the source region 60, so that the breakdown effect at the edge region of the planar power MOS device is greatly reduced, the electric field and stress of the planar power MOS device are reduced, and since the source redundancy regions 130 are disposed at two ends of the source region 60 only, the performance of the middle region of the planar power MOS device is maintained at the same time, the performance of the device is maintained to the maximum, and the voltage endurance of the power MOS device is improved.
In the present embodiment, the drain redundancy region 120 is disposed on the N-well 20 and located at two ends of the drain region 90, and is respectively in contact with the drain region 90 and the isolation region 80; wherein, the material of the drain redundant region 120 is different from that of the drain region 90; it can be understood that the drain redundancy region 120 is disposed in a region where a punch-through effect is likely to occur at two ends of the drain region 90, that is, in a region 10% -30% of an edge of the drain region 90, by disposing the drain redundancy region 120 with a material different from that of the drain region 90, the region where the drain redundancy region 120 is disposed cannot operate due to the absence of the drain region 90, so that the punch-through effect of the edge region of the planar power MOS device is greatly reduced, and an electric field and stress of the planar power MOS device are reduced, and the drain redundancy region 120 is disposed only at two ends of the drain region 90, so that a performance of a middle region of the planar power MOS device is maintained at the same time, the performance of the device is maintained to the maximum, and a withstand voltage capability of the power MOS device is improved.
In the present embodiment, due to the relationship of the electric field distribution in the gate metal layer 50, the source region 60, and the drain region 90, it is known from TCAD simulation and experiment that any one of the gate redundant region 110, the drain redundant region 120, and the source redundant region 130 is sequentially disposed in the planar power MOS device, and it can be found that the effect of disposing the gate redundant region 110 at the two ends of the gate metal layer 50 on improving the voltage endurance capability of the planar power MOS device is greater than the effect of disposing the source redundant region 130 at the two ends of the source region 60, and the effect of disposing the source redundant region 130 at the two ends of the source region 60 on improving the voltage endurance capability of the planar power MOS device is greater than the effect of disposing the drain redundant region 120 at the two ends of the drain region 90. However, the provision of the drain redundancy regions 120 at both ends of the drain region 90 can also improve the voltage withstanding characteristics of the power MOS device, but the effect is not as good as that of the provision of the gate redundancy regions 110. Therefore, the present application preferably uses the gate redundancy regions 110 disposed at the two ends of the gate metal layer 50 to solve the problem that the conventional planar power MOS device is prone to punch-through in the edge region, which further affects the reliability of the planar power MOS device.
In the embodiment of the present application, by using the design of the redundant devices (e.g., the gate redundant region 110, the drain redundant region 120, and the source redundant region 130) in the regions (refer to the regions a and B in fig. 4) where the planar power MOS device is prone to the punch-through effect, although the design area of the planar power MOS device is sacrificed, the withstand voltage of the planar power MOS device can be greatly improved without adding any process steps and masks. The problems of large volume and poor pressure resistance of the existing planar power MOS device are solved.
In one embodiment, referring to fig. 5, the planar power MOS device further includes: an inversion layer 100.
Specifically, the inversion layer 100 is disposed between the N-type well region 20 and the drain region 90, and the inversion layer 100 is in contact with the isolation region 80; wherein the inversion layer 100 has a doping type different from that of the drain region 90.
In the embodiment, the inversion layer 100 is disposed between the N-type well region 20 and the drain region 90, and the inversion layer 100 is in contact with the isolation region 80, and the doping type of the inversion layer 100 is different from that of the drain region 90, so that the voltage endurance of the planar power device can be improved by disposing the inversion layer 100 at the lower edge of the drain region 90. Specifically, the drain region 90 is doped with N-type ions, and the inversion layer 100 is doped with P-type ions. In the embodiment, the inversion layer 100 is arranged at the position where the breakdown effect is likely to occur in the edge region of the drain region 90, because the doping type of the inversion layer 100 is different from that of the drain region 90, the breakdown effect can be greatly relieved, the electric field and the stress of the planar power device are reduced, and because the inversion layer 100 is only arranged at the edge part of the planar power device, the performance of the middle region of the planar power device is simultaneously maintained, the performance of the device is maximally maintained, and the withstand voltage capability of the power MOS device is improved.
In one embodiment, referring to fig. 2, the gate redundancy region 110 includes: a first gate redundancy unit 111 and a second gate redundancy unit 112.
Specifically, the first gate redundancy unit 111 is disposed at a first end of the gate metal layer 50, the second gate redundancy unit 112 is disposed at a second end of the gate metal layer 50, and the first gate redundancy unit 111 and the second gate redundancy unit 112 are not in contact with each other.
In the present embodiment, the first gate redundancy unit 111 and the second gate redundancy unit 112 are respectively disposed at two ends of the gate metal layer 50. That is, the first gate redundancy unit 111 and the second gate redundancy unit 112 are respectively located in the edge regions where the breakdown effect is likely to occur in the edge region of the planar power MOS device, that is, the gate redundancy region 110 is disposed in the region where the breakdown effect is likely to occur in the gate metal layer 50, so that the edge region of the planar power MOS device cannot normally operate in the edge region due to the absence of the gate metal layer 50, and further, the withstand voltage of the planar power MOS device is greatly improved. Because breakdown effect is easy to occur in the edge regions of both ends of the gate metal layer 50 to limit the withstand voltage of the device, the problem that the withstand voltage of the device is reduced due to the breakdown effect easily occurring at both ends of the gate metal layer 50 can be effectively solved by arranging the first gate redundancy unit 111 and the second gate redundancy unit 112 at both ends of the gate metal layer 50, so that the gate metal layer 50 cannot work due to the absence of the gate metal layer 50 in the regions where the first gate redundancy unit 111 and the second gate redundancy unit 112 are arranged, the breakdown effect is greatly relieved, and the electric field and the stress of the planar power device are reduced.
In one embodiment, referring to fig. 3, the drain redundancy region 120 includes: a first drain redundancy unit 121 and a second drain redundancy unit 122.
Specifically, the first drain redundancy unit 121 is disposed at a first end of the drain region 90, the second drain redundancy unit 122 is disposed at a second end of the drain region 90, and the first drain redundancy unit 121 and the second drain redundancy unit 122 are not in contact with each other. Wherein the first and second drain redundancy cells 121 and 122 are in contact with the drain region 90 and the isolation region 80, respectively.
In this embodiment, the first drain redundancy unit 121 and the second drain redundancy unit 122 are respectively located in an edge region of the planar power MOS device where a punch-through effect is likely to occur, that is, the drain redundancy region 120 is disposed in an edge region of the drain region 90 where a punch-through effect is likely to occur, so that the edge region of the planar power MOS device cannot normally operate in the edge region due to the absence of the drain region 90, and further, the withstand voltage of the planar power MOS device is greatly improved. Because breakdown effect is easy to occur in the edge regions at both ends of drain region 90 to limit the withstand voltage of the device, the problem of reduced withstand voltage of the device caused by breakdown effect at both ends of drain region 90 can be effectively solved by arranging first drain redundancy unit 121 and second drain redundancy unit 122, and the first drain redundancy unit 121 and second drain redundancy unit 122 are arranged at both ends of drain region 90, so that the region provided with first drain redundancy unit 121 and second drain redundancy unit 122 cannot work due to the absence of drain region 90, thereby greatly relieving the breakdown effect and reducing the electric field and stress of the planar power device.
In one embodiment, referring to fig. 3, the source redundancy region 130 includes: a first source redundancy cell 131 and a second source redundancy cell 132.
Specifically, the first source redundancy unit 131 is disposed at a first end of the source region 60, the second source redundancy unit 132 is disposed at a second end of the source region 60, and the first source redundancy unit 131 and the second source redundancy unit 132 are not in contact with each other. Wherein the first and second source redundancy cells 131 and 132 are in contact with the source region 60 and the P-type doped region 70, respectively.
In this embodiment, the first source redundancy unit 131 and the second source redundancy unit 132 are respectively located in the edge regions of the planar power MOS device where the punch-through effect is likely to occur, that is, the source redundancy region 130 is disposed in the region of the edge of the source region 60 where the punch-through effect is likely to occur, so that the edge region of the planar power MOS device cannot normally operate in the edge region due to the absence of the source region 60, and the withstand voltage of the planar power MOS device is greatly improved. Because breakdown effects are easy to occur in the edge regions at both ends of the source region 60 to limit the withstand voltage of the device, the problem of reduced withstand voltage of the device due to the breakdown effects easily occurring at both ends of the source region 60 can be effectively solved by arranging the first source redundancy unit 131 and the second source redundancy unit 132, and the first source redundancy unit 131 and the second source redundancy unit 132 are arranged at both ends of the source region 60, so that the region provided with the first source redundancy unit 131 and the second source redundancy unit 132 cannot work due to the absence of the source region 60, thereby greatly relieving the breakdown effects and reducing the electric field and the stress of the planar power device.
In one embodiment, referring to fig. 6, the width W1 of each of the first and second gate redundancy cells 111 and 112 is the same as the width W2 of the gate metal layer 50, and the thickness of each of the first and second gate redundancy cells 111 and 112 is the same as the thickness of the gate metal layer 50.
Specifically, the first gate redundancy unit 111 and the second gate redundancy unit 112 are arranged in the region where the breakdown effect is likely to occur in the edge region of the gate metal layer 50 of the planar power MOS device, so as to reduce the on-resistance of the power MOS device, and further improve the withstand voltage of the power MOS device, it can be understood that the first gate redundancy unit 111 and the second gate redundancy unit 112 just fill the region where the gate metal layer 50 is reduced, and the width W1 and the thickness of the first gate redundancy unit 111 and the second gate redundancy unit 112 are the same as the width W2 and the thickness of the gate metal layer 50. By using the first gate redundancy unit 111 and the second gate redundancy unit 112 in the region where the punch-through effect is likely to occur, although the design area is sacrificed, the withstand voltage of the device can be greatly improved without adding any process steps and masks.
In this embodiment, it can be understood that the width and thickness of the first and second source redundancy cells 131 and 132 are the same as those of the source region 60, and the width and thickness of the first and second drain redundancy cells 121 and 122 are the same as those of the drain region 90, and thus the description thereof is omitted.
In one embodiment, referring to fig. 6, the lengths L1 of the first gate redundancy cell 111 and the second gate redundancy cell 112 each range from 10% to 30% of the length L2 of the gate oxide layer 40.
Specifically, according to TCAD simulation and experiments, it is known that the electric field and the stress at the edge (10% to 30%) of the power MOS device are the largest, and when the reverse bias is increased, the edge area first generates a breakdown effect, which limits the withstand voltage of the power MOS device, so that only the length L1 of the first gate redundancy unit 111 and the second gate redundancy unit 112 needs to be kept within 10% to 30% of the length L2 of the gate oxide layer 40. The problem that the edge part of the power MOS device is easy to generate the breakdown effect can be solved. Meanwhile, the performance of the middle area power MOS device is kept, and the performance of the power device is kept to the maximum extent while the withstand voltage of the device is improved. Moreover, the voltage endurance capability of the power device is improved without increasing the distance between the source region 60 and the drain region 90, and the voltage endurance of the device is greatly improved without adding any process steps and masks. Therefore, the planar power device of the application is more miniaturized while the voltage endurance is improved.
In one embodiment, the lengths of the first source redundancy unit 131 and the second source redundancy unit 132 are both 10% -30% of the length of the P-well region 30; the lengths of the first drain redundancy unit 121 and the second drain redundancy unit 122 are both 10% -30% of the length of the N-type well region 20. The function of the first gate redundancy unit 111 is the same as that of the second gate redundancy unit 112, and the description thereof is omitted.
In one embodiment, as shown with reference to fig. 2, the first gate redundancy unit 111 and the second gate redundancy unit 112 are symmetrically disposed.
Specifically, the first gate redundancy unit 111 is disposed above an edge region of a first end of the gate oxide layer 40, the second gate redundancy unit 112 is disposed above an edge region of a second end of the gate oxide layer 40, and the first gate redundancy unit 111 and the second gate redundancy unit 112 are respectively disposed at two ends of the gate metal layer 50.
In one embodiment, the first source redundancy unit 131 and the second source redundancy unit 132 are symmetrically disposed, and the first drain redundancy unit 121 and the second drain redundancy unit 122 are symmetrically disposed. The roles of the first gate redundancy unit 111 and the second gate redundancy unit 112 are the same, and are not described again.
In one embodiment, the sum of the lengths of the gate redundancy region 110 and the gate metal layer 50 is less than or equal to the length of the gate oxide layer 40. It can be understood that, after the gate redundancy regions 110 are disposed at the two ends of the gate metal layer 50, the total length thereof does not exceed the total length of the gate oxide layer 40, that is, no part exceeding the length of the gate oxide layer 40 is exposed outside, so that the design of using the redundancy device (i.e., the gate redundancy region 110) in the region where the breakdown effect is likely to occur can greatly improve the withstand voltage of the device without adding any process step and mask, and at the same time, the material loss is reduced, and the consumables are saved.
In one embodiment, the sum of the lengths of the source redundancy region 130 and the source region 60 is less than or equal to the length of the P-well region 30, and the sum of the lengths of the drain redundancy region 120 and the drain region 90 is less than or equal to the length of the N-well region 20, which are the same as the gate redundancy region 110, and are not repeated herein.
The embodiment of the present application further provides a method for manufacturing a planar power MOS device, which is shown in fig. 7 and includes steps S10 to S60.
Step S10: a semiconductor substrate 10 is provided.
Step S20: referring to fig. 8, an N-type well region 20 and a P-type well region 30 are formed in this order on a semiconductor substrate 10; wherein N-type well region 20 and P-type well region 30 are in contact.
Step S30: referring to fig. 9, a source region 60 and a P-type doped region 70 are formed on the P-type well region 30; wherein the P-type doped region 70 contacts the source region 60.
Step S40: referring to fig. 10, isolation regions 80 and drain regions 90 are formed on the N-type well region 20; where isolation region 80 and drain region 90 are in contact.
Step S50: referring to fig. 11, a gate oxide layer 40 is formed on the N-type well region 20, the P-type well region 30, the source region 60, and the isolation region 80, and a gate metal layer 50 is formed on the gate of the gate oxide layer 40.
Step S60: referring to fig. 12, a gate redundancy region 110 is formed on the gate oxide layer 40, and the gate redundancy region 110 is disposed at two ends of the gate metal layer 50; the material of the gate redundancy region 110 is different from that of the gate metal layer 50; or/and forming a drain redundant region 120 on the N-type well region 20, wherein the drain redundant region 120 is disposed at two ends of the drain region 90 and is in contact with the drain region 90 and the isolation region 80, respectively; the material of the drain redundant region 120 is different from the material of the drain region 90; or/and forming a source redundancy region 130 on the P-type well region 30, wherein the source redundancy region 130 is disposed at two ends of the source region 60 and is in contact with the source region 60 and the P-type doped region 70, respectively; wherein the material of the source redundancy region 130 is different from the material of the source region 60.
In this embodiment, by using the design of the redundant devices (e.g., the gate redundant region 110, the drain redundant region 120, and the source redundant region 130) in the regions of the planar power MOS device where the punch-through effect is likely to occur, although the design area of the planar power MOS device is sacrificed, the withstand voltage of the planar power MOS device can be greatly improved without adding any process steps and masks. The problems of large volume and poor pressure resistance of the existing planar power MOS device are solved.
In this embodiment, the planar power MOS device includes at least: at least one of the gate redundant region 110, the drain redundant region 120, and the source redundant region 130. It can be understood that the gate redundancy region 110 is disposed in a region where a breakdown effect is likely to occur at two ends of the gate metal layer 50, that is, in a region of 10% -30% of an edge of the gate metal layer 50, and by disposing the gate redundancy region 110 with a material different from that of the gate metal layer 50, the region where the gate redundancy region 110 is disposed cannot operate due to the absence of the gate metal layer 50, so that the breakdown effect of the edge region of the planar power MOS device is greatly reduced, and an electric field and stress of the planar power MOS device are reduced.
In the present embodiment, the source redundancy regions 130 are disposed on the P-well region 30 and located at two ends of the source region 60, and are respectively in contact with the source region 60 and the P-type doped region 70; wherein the material of the source redundancy region 130 is different from the material of the source region 60. It can be understood that the source redundancy regions 130 are disposed at two ends of the source region 60, where the breakdown effect is likely to occur, i.e. 10% -30% of the edge of the source region 60, and by disposing the source redundancy regions 130 with a different material from that of the source region 60, the region where the source redundancy regions 130 are disposed cannot work due to the absence of the source region 60, so that the breakdown effect at the edge region of the planar power MOS device is greatly reduced, and the electric field and stress of the planar power MOS device are reduced, and further, because the source redundancy regions 130 are disposed at two ends of the source region 60 only, the performance at the middle region of the planar power MOS device is maintained at the same time, the performance of the device is maintained to the maximum, and the voltage endurance of the power MOS device is improved.
In the present embodiment, the drain redundancy region 120 is disposed on the N-well 20 and located at two ends of the drain region 90, and is in contact with the drain region 90 and the isolation region 80, respectively; wherein, the material of the drain redundant region 120 is different from that of the drain region 90; it can be understood that the drain redundancy region 120 is disposed in a region where a breakdown effect is likely to occur at both ends of the drain, i.e. a region of 10% -30% of the edge of the drain, and by disposing the drain redundancy region 120 with a material different from that of the drain region 90, the region where the drain redundancy region 120 is disposed cannot operate without the drain region 90, so that the breakdown effect at the edge region of the planar power MOS device is greatly reduced, and an electric field and stress of the planar power device are reduced, and since the drain redundancy region 120 is disposed only at both ends of the drain region 90, the performance at the middle region of the planar power MOS device is maintained at the same time, the performance of the device is maintained to the maximum, and the voltage endurance capability of the power MOS device is improved.
In the present embodiment, in step S60, a gate redundancy region 110 is formed on the gate oxide layer 40, or a drain redundancy region 120 is formed on the N-type well region 20, or a source redundancy region 130 is formed on the P-type well region 30. It can be understood that, it is not necessary to form the gate redundant region 110, the drain redundant region 120, and the source redundant region 130 on the power MOS device at the same time, and it is only necessary to form at least one of the gate redundant region 110, the drain redundant region 120, and the source redundant region 130 according to the actual application requirement, so as to solve the problem that the edge of the power MOS device is prone to punch through. Meanwhile, the performance of the power MOS device in the middle area is kept, and the performance of the power device is kept to the maximum extent while the withstand voltage of the device is improved.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
The units described as separate parts may or may not be physically separate, and the parts displaying data as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (10)

1. A planar power MOS device, comprising:
a semiconductor substrate;
the semiconductor device comprises an N-type well region and a P-type well region, wherein the N-type well region is in contact with the P-type well region and is positioned on the semiconductor substrate;
the grid oxide layer is positioned on the N-type well region and the P-type well region;
the grid metal layer is positioned on the grid oxide layer;
the source region and the P-type doped region are arranged on the P-type well region, the source region is in contact with the gate oxide layer, and the P-type doped region is in contact with the source region;
the isolation region and the drain region are arranged on the N-type well region, and the isolation region is arranged between the drain region and the grid oxide layer; and
at least one of a gate redundant region, a drain redundant region, and a source redundant region;
the grid redundant region is arranged on the grid oxide layer and positioned at two ends of the grid metal layer; wherein the material of the gate redundant region is different from the material of the gate metal layer;
the drain electrode redundant region is arranged on the N-type well region, positioned at two ends of the drain electrode region and respectively contacted with the drain electrode region and the isolation region; wherein the material of the drain redundant region is different from that of the drain region;
the source redundant region is arranged on the P-type well region, positioned at two ends of the source region and respectively contacted with the source region and the P-type doped region; wherein the material of the source redundancy region is different from the material of the source region.
2. The planar power MOS device of claim 1, wherein the planar power MOS device further comprises:
the inversion layer is arranged between the N-type well region and the drain region and is in contact with the isolation region;
wherein a doping type of the inversion layer is different from a doping type of the drain region.
3. The planar power MOS device of claim 1, wherein the gate redundancy region comprises: a first gate redundancy unit and a second gate redundancy unit; wherein the content of the first and second substances,
the first grid redundancy unit is arranged at the first end of the grid metal layer, the second grid redundancy unit is arranged at the second end of the grid metal layer, and the first grid redundancy unit and the second grid redundancy unit are not in contact with each other.
4. The planar power MOS device of claim 1, wherein the drain redundancy region comprises: a first drain redundancy unit and a second drain redundancy unit; wherein the content of the first and second substances,
the first drain electrode redundant unit is arranged at the first end of the drain electrode area, the second drain electrode redundant unit is arranged at the second end of the drain electrode area, and the first drain electrode redundant unit and the second drain electrode redundant unit are not contacted with each other.
5. The planar power MOS device of claim 1, wherein the source redundancy region comprises: a first source redundancy cell and a second source redundancy cell; wherein the content of the first and second substances,
the first source redundancy unit is arranged at the first end of the source region, the second source redundancy unit is arranged at the second end of the source region, and the first source redundancy unit and the second source redundancy unit are not contacted with each other.
6. The planar power MOS device of claim 3, wherein the first gate redundancy unit and the second gate redundancy unit each have a width identical to a width of the gate metal layer, and wherein the first gate redundancy unit and the second gate redundancy unit each have a thickness identical to a thickness of the gate metal layer.
7. The planar power MOS device of claim 3, wherein the first gate redundancy cell and the second gate redundancy cell each have a length in a range of 10% -30% of a length of the gate oxide layer.
8. The planar power MOS device of claim 3, wherein the first gate redundancy unit and the second gate redundancy unit are symmetrically disposed.
9. The planar power MOS device of claim 1, wherein a sum of lengths of the gate redundancy region and the gate metal layer is less than or equal to a length of the gate oxide layer.
10. A method for preparing a planar power MOS device is characterized by comprising the following steps:
providing a semiconductor substrate;
sequentially forming an N-type well region and a P-type well region on the semiconductor substrate; wherein the N-type well region and the P-type well region are in contact;
forming a source region and a P-type doped region on the P-type well region; wherein the P-type doped region is in contact with the source region;
forming an isolation region and a drain region on the N-type well region; wherein the isolation region is in contact with the drain region;
forming a grid oxide layer on the N-type well region, the P-type well region, the source region and the isolation region, and forming a grid metal layer on the grid oxide layer; and
forming a grid redundant area on the grid oxide layer, wherein the grid redundant area is arranged at two ends of the grid metal layer; the material of the gate redundant region is different from that of the gate metal layer; or/and
forming a drain redundant region on the N-type well region, wherein the drain redundant region is arranged at two ends of the drain region and is respectively contacted with the drain region and the isolation region; the material of the drain redundant region is different from that of the drain region; or/and
forming source redundant regions on the P-type well region, wherein the source redundant regions are arranged at two ends of the source region and are respectively contacted with the source region and the P-type doped region; wherein the material of the source redundant region is different from the material of the source region.
CN202210713117.9A 2022-06-22 2022-06-22 Planar power MOS device and preparation method thereof Pending CN115224129A (en)

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