CN115223927A - Method for forming semiconductor structure - Google Patents

Abstract

A method of forming a semiconductor structure, the method comprising: forming mask sidewall layers conformally covering the top of the target layer and the top and sidewalls of the core layer, wherein in the first region, the mask sidewall layers on opposite sidewalls of the core layer have a minimum spacing value in a direction perpendicular to an extending direction of the opening; forming a grinding stop layer for conformally covering the mask side wall layer, wherein the thickness of the grinding stop layer is greater than or equal to half of the minimum spacing value; forming a filling material layer covering the top of the grinding stop layer; planarizing the filling material layer, wherein the rest filling material layer is used as the filling layer, and the top of the filling layer is flush with the top of the grinding stop layer in the first area; and taking the top of the mask side wall layer as a stop position, etching and removing the grinding stop layer and the filling layer which are higher than the top of the mask side wall layer, wherein the tops of the rest grinding stop layer and the filling layer are flush with the top of the mask side wall layer. The probability of generating defects on the top and the side wall of the mask side wall layer is reduced.

Description

Method for forming semiconductor structure

Technical Field

The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.

Background

With the rapid growth of the semiconductor Integrated Circuit (IC) industry, semiconductor technology is driven by moore's law to move towards smaller process nodes, so that the integrated circuit is developed towards smaller size, higher circuit precision and higher circuit complexity.

In the development of integrated circuits, the functional density (i.e., the number of interconnect structures per chip) generally increases, while the geometric size (i.e., the minimum component size that can be produced by the process steps) decreases, which increases the difficulty and complexity of integrated circuit fabrication.

At present, under the condition that the technology nodes are continuously reduced, how to improve the matching degree between the graph formed on the wafer and the target graph becomes a challenge.

Disclosure of Invention

The embodiment of the invention provides a method for forming a semiconductor structure, which improves the performance of the semiconductor structure.

In order to solve the above problem, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate comprising a target layer for forming a target pattern, the substrate comprising a first region and a second region, a pitch adjacent to the target pattern formed in the first region being smaller than a pitch adjacent to the target pattern formed in the second region, a core layer formed on top of the target layer in the first region, the core layer having an opening formed therein through the core layer; forming mask sidewall layers conformally covering the top of the target layer and the top and sidewalls of the core layer, wherein in the first region, the mask sidewall layers on opposite sidewalls of the core layer have a minimum spacing value in a direction perpendicular to the extending direction of the opening; forming a polish stop layer conformally covering the mask sidewall layer, the polish stop layer having a thickness greater than or equal to half of the minimum spacing value; forming a filling material layer covering the top of the grinding stop layer; planarizing the filling material layer, wherein the rest of the filling material layer is used as a filling layer, and the top of the filling layer is flush with the top of the grinding stop layer in the first area; and after the filling layer is formed, etching and removing the grinding stop layer and the filling layer which are higher than the top of the mask side wall layer by taking the top of the mask side wall layer as a stop position, wherein the tops of the residual grinding stop layer and the residual filling layer are flush with the top of the mask side wall layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

the embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of forming mask side wall layers which cover the top of a target layer and the top and side walls of a core layer in a conformal manner, wherein in a first region, in the direction vertical to the extending direction of an opening, the minimum interval value is formed between the mask side wall layers on the opposite side walls of the core layer; forming a grinding stop layer for conformally covering the mask side wall layer, wherein the thickness of the grinding stop layer is greater than or equal to half of the minimum spacing value; forming a filling material layer covering the top of the grinding stop layer; planarizing the filling material layer, wherein the rest filling material layer is used as a filling layer, and the top of the filling layer is flush with the top of the grinding stop layer in the first area; and after the filling layer is formed, etching and removing the grinding stop layer and the filling layer which are higher than the top of the mask side wall layer by taking the top of the mask side wall layer as a stop position, wherein the tops of the rest grinding stop layer and the rest filling layer are flush with the top of the mask side wall layer. Compared with the prior art in which the top of the mask sidewall layer is directly used as a planarization process stop position after a filling material layer is formed on the top of the polish stop layer, the embodiment of the invention forms the polish stop layer conformally covering the mask sidewall layer, and the thickness of the polish stop layer is greater than or equal to half of the minimum spacing value, so that in the first region, the polish stop layer can be filled in at least the residual space of the partial opening where the mask sidewall layer is exposed, so that the top flatness of the polish stop layer in the first region is higher, a good flat surface is provided for the subsequent planarization process, then the filling material layer is formed on the top of the polish stop layer, then the top of the polish stop layer with higher top flatness in the first region is used as a planarization process stop position, part of the filling material layer is removed, so that the top of the filling layer is flush with the top of the polish stop layer in the first region, and finally the polish stop layer and the filling layer higher top of the mask sidewall layer are removed as a whole, so that the planarization process defects are reduced by combining the top of the polish stop layer and the top of the mask sidewall layer.

Drawings

Fig. 1 to fig. 3 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;

fig. 4 to 16 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

At present, the performance of semiconductor structures is still to be improved. There are still reasons for the performance of semiconductor structures to be improved when analyzed in conjunction with a method of forming the semiconductor structures. Fig. 1 to fig. 3 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.

Referring to fig. 1, providing a substrate including a target layer 10, the substrate including a first region 10A and a second region 10B, a core layer 13 formed on top of the target layer 10 of the first region 10A, the core layer 13 having an opening 20 formed therein through the core layer 13; a mask sidewall layer 14 is formed conformally covering the top of the target layer 10, and the top and sidewalls of the core layer 13.

Referring to fig. 2, an etching stop layer 15 is formed to cover the top and the sidewall of the mask sidewall layer 14, and after the etching stop layer 15 is formed, a filling layer 16 is formed to cover the top and the sidewall of the etching stop layer 15, and the filling layer also fills the remaining space of the opening 20.

Referring to fig. 3, the etching stop layer 15 and the filling layer 16 on the top of the mask sidewall layer 14 are planarized with the top of the mask sidewall layer 14 as a stop position.

The research finds that the removal rates of the etching stop layer 15 and the filling layer 16 on the top of the mask side wall layer 14 are different under the influence of the pattern density of the core layer 13 in different areas, so that in the process of flattening the etching stop layer 15 and the filling layer 16 on the top of the mask side wall layer 14, the flatness of the tops of the remaining etching stop layer 15 and the remaining filling layer 16 and the tops of the mask side wall layer 14 is poor, the situation that the mask side wall layer 14, the etching stop layer 15 and the filling layer 16 are simultaneously ground is easy to occur, the probability that defects are generated on the tops and the side walls of the mask side wall layer is increased, and the performance of a semiconductor structure is influenced.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising a target layer for forming a target pattern, the substrate comprising a first region and a second region, a pitch adjacent to the target pattern formed in the first region being smaller than a pitch adjacent to the target pattern formed in the second region, a core layer formed on top of the target layer in the first region, the core layer having an opening formed therein through the core layer; forming mask sidewall layers conformally covering the top of the target layer and the top and sidewalls of the core layer, wherein in the first region, the mask sidewall layers on opposite sidewalls of the core layer have a minimum spacing value in a direction perpendicular to the extending direction of the opening; forming a polish stop layer conformally covering the mask sidewall layer, the polish stop layer having a thickness greater than or equal to half of the minimum spacing value; forming a filling material layer covering the top of the grinding stop layer; planarizing the filling material layer, wherein the rest filling material layer is used as a filling layer, and the top of the filling layer is flush with the top of the grinding stop layer in the first area; and after the filling layer is formed, etching and removing the grinding stop layer and the filling layer which are higher than the top of the mask side wall layer by taking the top of the mask side wall layer as a stop position, wherein the tops of the residual grinding stop layer and the residual filling layer are flush with the top of the mask side wall layer.

In the scheme disclosed by the embodiment of the invention, mask side wall layers which cover the top of the target layer and the top and the side walls of the core layer in a conformal manner are formed, and in the first region, the minimum interval value is formed between the mask side wall layers positioned on the opposite side walls of the core layer in the direction vertical to the extending direction of the opening; forming a grinding stop layer for conformally covering the mask side wall layer, wherein the thickness of the grinding stop layer is greater than or equal to half of the minimum spacing value; forming a filling material layer covering the top of the grinding stop layer; planarizing the filling material layer, wherein the rest filling material layer is used as the filling layer, and the top of the filling layer is flush with the top of the grinding stop layer in the first area; and after the filling layer is formed, etching and removing the grinding stop layer and the filling layer which are higher than the top of the mask side wall layer by taking the top of the mask side wall layer as a stop position, wherein the tops of the rest grinding stop layer and the rest filling layer are flush with the top of the mask side wall layer. Compared with the conventional scheme that after a filling material layer is formed on the top of the grinding stop layer, the top of the mask side wall layer is directly used as a planarization process stop position, the embodiment of the invention forms the grinding stop layer which conformally covers the mask side wall layer, and the thickness of the grinding stop layer is more than or equal to half of the minimum spacing value, so that in the first area, the grinding stop layer can be filled in at least the residual space of the partial opening exposed by the mask side wall layer, so that the top flatness of the grinding stop layer in the first area is higher, a good flat surface is provided for the subsequent planarization process, then the filling material layer is formed on the top of the grinding stop layer, then the top of the grinding stop layer with higher top flatness in the first area is used as a planarization process stop position, part of the filling material layer is removed, the top of the filling layer is flush with the top of the grinding stop layer in the first area, and finally the grinding stop layer and the filling layer higher top of the mask side wall layer are removed integrally, so that the top of the filling layer and the top of the mask side wall layer are flush with the top of the grinding stop layer in the first area, and the top of the semiconductor side wall layer are etched, and the top of the semiconductor device is processed by the top of the semiconductor process, thereby reducing the defects of the top of the semiconductor device.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

FIGS. 4 to 16 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention

Referring to fig. 4, a substrate is provided, the substrate including a target layer 101 for forming a target pattern, the substrate including a first region 100A and a second region 100B, a pitch (pitch) of adjacent target patterns formed in the first region 100A being smaller than a pitch of adjacent target patterns formed in the second region 100B, a core layer 103 formed on top of the target layer 101 of the first region 100A, and an opening 160 formed in the core layer 103 to penetrate through the core layer 103.

The substrate is used for providing a process platform for subsequent process procedures.

In this embodiment, semiconductor devices such as transistors and capacitors may be formed in the substrate, and functional structures such as a resistor structure and a conductive structure may be formed in the substrate.

In this embodiment, the pitch of the adjacent target patterns formed in the first region 100A is smaller than the pitch of the adjacent target patterns formed in the second region 100B. Wherein the pitch adjacent to the target pattern refers to: the sum of the width (width) of the target pattern and the space (space) between adjacent target patterns.

Since the pitch of the target patterns adjacent to the first area 100A is smaller than the pitch of the target patterns adjacent to the second area 100B, the line width of the target patterns in the first area 100A is generally smaller, the density of the target patterns in the first area 100A is greater, and in order to meet the pattern precision of the target patterns in different areas, the first area 100A needs to use a Self-aligned Double imaging process (SADP), while the second area 100B does not need to use a Self-aligned Double imaging process.

The target layer 101 is used as a material layer to be patterned subsequently to form a target pattern.

In this embodiment, the target layer 101 is a hard mask material layer.

The hard mask material layer is used for forming a hard mask layer through a subsequent patterning process.

In this embodiment, the target layer 101 is made of silicon nitride. In other embodiments, the material of the target layer 101 may also be silicon oxide, silicon oxynitride, silicon carbide, titanium oxide, titanium nitride, tantalum oxide, tantalum nitride, boron nitride, copper nitride, aluminum nitride, or tungsten nitride.

Correspondingly, the target pattern is a mask opening formed in the hard mask layer, and the mask opening is used for defining the functional pattern in the substrate. The functional patterns may be a gate structure, an interconnect opening in a Back end of line (BEOL) process, a fin in a fin field effect transistor (FinFET), a channel stack in a Gate All Around (GAA) transistor or a fork gate transistor (forkheet), a Hard Mask (HM) layer, and the like.

In this embodiment, the substrate further includes a dielectric layer 100, and the target layer 101 is located on the dielectric layer 100.

The dielectric layer 100 is subsequently patterned to form a plurality of interconnect openings in the dielectric layer 100. The interconnect opening serves as a functional pattern

In this embodiment, the dielectric layer 100 is made of a low-k dielectric material (low-k dielectric material refers to a dielectric material having a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant less than 2.6), silicon oxide, silicon nitride, or silicon oxynitride. Specifically, the material of the dielectric layer 100 may be SiOCH.

It should be noted that, in this embodiment, other film layers or structures in the substrate below the dielectric layer 100 are not illustrated.

In this embodiment, the substrate further includes an etch stop layer 102, and the etch stop layer 102 is located above the target layer 101.

The etching stop layer 102 is used for defining an etching stop position in an etching process of subsequent pattern definition processing, so that the loss of the target layer 101 is reduced, the depth consistency of the etching process is improved, and the effect of the subsequent patterning process is improved.

In this embodiment, the material of the etch stop layer 102 is silicon oxide. In other embodiments, the material of the etch stop layer may also be silicon nitride, aluminum oxide, titanium nitride, tungsten nitride, aluminum nitride, or the like.

In this embodiment, the core layer 103 provides a process foundation for subsequently forming a mask sidewall layer covering the top and sidewalls of the core layer 103.

It should be noted that, before the subsequent step of etching the target layer 101 to form the target pattern, the core layer 103 needs to be removed first, and in order to remove the core layer 103, a material that is easy to remove is selected. In this embodiment, the material of the core layer 103 includes one or more of amorphous silicon, polysilicon, silicon oxide, silicon nitride, and silicon oxynitride. As an example, the material of the core layer 103 is amorphous silicon.

In this embodiment, the opening 160 provides a spatial location for a mask sidewall layer and a polishing stop layer to be formed in the opening 160, and is also used to define the shape and location of a subsequent target pattern.

Referring to fig. 5, mask sidewall layers 104 conformally covering the top of the target layer 101 and the top and sidewalls of the core layer 103 are formed, and the mask sidewall layers 104 on opposite sidewalls of the core layer 103 have a minimum spacing value S in a direction perpendicular to the extending direction of the opening 160 in the first region 100A.

The mask sidewall layer 104 provides a process foundation for the subsequent formation of a mask sidewall.

In this embodiment, the process of forming the mask sidewall layer 104 includes an atomic layer deposition process.

The ald process includes multiple ald cycles to improve the uniformity of the thickness of the mask sidewall layer 104 and to conformally cover the sidewalls and top of the core layer 103 and the bottom of the opening 160 with the mask sidewall layer 104. In other embodiments, the mask sidewall layer may be formed by a Chemical Vapor Deposition (CVD) process.

In this embodiment, in the step of forming the mask sidewall layer 104, the material of the mask sidewall layer 104 includes TiO, siN, and SiO ₂ One or more of (a).

By using TiO, siN or SiO ₂ In the semiconductor manufacturing process, under a mature atomic layer deposition process, the thickness uniformity of the mask sidewall layer 104 formed on the sidewall and the top of the core layer 103 and the bottom of the opening 160 is better, and the material of the core layer 103 (such as amorphous silicon) has a higher etching selectivity, which is beneficial to the subsequent removal of the core layer 103.

In this embodiment, in the first region 100A, the mask sidewall layers 104 on the opposite sidewalls of the core layer 103 have a minimum spacing value S in a direction perpendicular to the extending direction of the opening 160.

In the first region 100A, since there may be discrete nonuniformity of the core layer 103, that is, nonuniformity of the lateral dimension of the opening 160, the intervals between the mask sidewall layers on the opposite sidewalls of the core layer may be different. Wherein, when the first region 100A has a plurality of interval values, a minimum value of the plurality of interval values is a minimum interval value S.

Referring to fig. 6, a polish stop layer 105 is formed conformally covering the mask sidewall layer 104, the thickness of the polish stop layer 105 being greater than or equal to half of the minimum spacing value.

It should be noted that, by making the thickness of the polishing stop layer 105 greater than or equal to half of the minimum spacing value, the polishing stop layer 105 can fill at least the remaining space of the exposed portion of the opening 160 of the mask sidewall layer 104, so that the top surface of the polishing stop layer 105 in the first region 100A has a higher flatness, and provides a good flat surface for the subsequent planarization process.

Since the thickness of the polishing stop layer 105 is greater than or equal to half of the minimum spacing value, when the remaining space of the opening 160 exposed by the mask sidewall layer 104 is smaller, the polishing stop layers 105 on the opposite sidewalls of the mask sidewall layer 104 contact each other to fill the remaining space of the opening 160.

It should be noted that even if the remaining space of the opening 160 is not filled with the polishing stop layer 105, the remaining space of the opening 160 formed with the polishing stop layer 105 is smaller, which is advantageous to make the flatness of the top surface of the polishing stop layer 105 in the first region 100A higher.

In addition, since the core layer 103 in the first region 100A is not uniform in separation, that is, the opening 160 is not uniform in lateral dimension, in the first region 100A, the opening 160 having a larger lateral dimension is affected by the thickness of the polishing stop layer 105, and the polishing stop layer 105 does not fill the opening 160 having a larger lateral dimension completely.

In the step of forming the polishing stop layer 105 conformally covering the mask sidewall layer 104 according to the size of the remaining space of the opening 160 exposed by the mask sidewall layer 104, in the first region 100A, the polishing stop layer 105 is filled in the remaining space of each of the openings 160 exposed by the mask sidewall layer 104, or the polishing stop layer 105 is filled in the remaining space of a portion of the opening 160 exposed by the mask sidewall layer 104.

As an example, as shown in fig. 6, the polishing stop layer 105 fills the remaining space of the opening 160 exposed by the mask sidewall layer 104.

In this embodiment, the process of forming the polishing stop layer 105 includes an atomic layer deposition process.

The polishing stop layer 105 formed by the ald process has good thickness uniformity and good step coverage (step coverage) capability, so that the polishing stop layer 105 can conformally cover the mask sidewall layer 104 well, and in the first region 100A, for the opening 160 with a smaller lateral dimension, the polishing stop layer 105 on the opposite sidewalls of the mask sidewall layer 104 is in contact with each other, so as to fill the remaining space of the opening 160 exposed by the mask sidewall layer 104. In other embodiments, the mask sidewall layer may be formed by a Chemical Vapor Deposition (CVD) process.

In this embodiment, in the step of forming the polishing stop layer 105, the thickness of the polishing stop layer 105 is 10 nm to 30 nm.

The thickness of the polishing stopper layer 105 is not preferably too large or too small. If the thickness of the grinding stop layer 105 is too large, the process difficulty and the process cost are increased and the process efficiency is reduced in the subsequent process of etching and removing the grinding stop layer 105 higher than the top of the mask side wall layer 104; if the thickness of the polishing stop layer 105 is too small, in the first region 100A, the occupied space of the opening 160 by the polishing stop layer 105 is too small, which easily results in poor flatness of the top surface of the polishing stop layer 105 in the first region 100A, and further increases the probability of forming residues on the top surface of the polishing stop layer 105 in the subsequent process of planarizing the filling material layer, and simultaneously, reduces the flatness of the top surface of the polishing stop layer 105, and affects the subsequent process of forming the target pattern in the target layer 101, thereby affecting the performance of the semiconductor structure. For this reason, in the present embodiment, the thickness of the polishing stop layer 105 is 10 nm to 30 nm. For example, the polish stop layer 105 has a thickness of 15 nm, 20 nm, or 25 nm.

Referring to fig. 7, a layer of filler material 106 is formed overlying the top of the polish stop layer 105.

The layer of filler material 106 provides a process foundation for the subsequent formation of a filler layer.

In this embodiment, the process of forming the filling material layer 106 includes a chemical vapor deposition process.

The chemical vapor deposition process has the characteristics of simple operation, high process efficiency, good coverage and the like.

In this embodiment, the material of the filling material layer 106 includes one or more of silicon oxide, silicon oxynitride, silicon carbide, titanium oxide, titanium nitride, and silicon nitride.

The silicon oxide, the silicon oxynitride, the silicon carbide, the titanium oxide, the titanium nitride, and the silicon nitride have characteristics of high material hardness, and the like, so that the hardness of the shielding layer formed in the second region 100B subsequently is also high, and the shielding layer can be retained in the subsequent process of removing the core layer 103.

Referring to fig. 8, the filling material layer 106 is planarized, the remaining filling material layer 106 serves as a filling layer 107, and the top of the filling layer 107 is flush with the top of the polish stop layer 105 in the first region 100A.

As can be seen from the above description, since the flatness of the top surface of the polish stop layer 105 in the first region 100A is high, in the process of planarizing the filler material layer 106, the top of the filler layer 107 is flush with the top of the polish stop layer 105 in the first region 100A in a good flat environment on the top of the polish stop layer 105.

In this embodiment, the step of planarizing the filling material layer 106 includes: a portion of the filler material layer 106 is removed with the top of the polish stop layer 105 in the first region 100A as a stop for the planarization process.

The top surface of the polishing stop layer 105 has a high flatness, and the top of the polishing stop layer 105 in the first region 100A is used as a stop position for the planarization process, so that the filling layer 107 having a high top surface flatness is formed in the second region 100B, thereby preparing for forming a shielding layer in the second region 100B.

In this embodiment, the process of planarizing the filler material layer 106 includes a chemical mechanical polishing process.

The chemical mechanical polishing process has the characteristics of global planarization, low process cost, high operation efficiency and the like, and simultaneously, because the flatness of the top surface of the polishing stop layer 105 in the first region 100A is high, a good flat surface is provided for the planarization process, so that the flatness of the top surface of the filling layer 107 and the flatness of the top surface of the polishing stop layer 105 in the first region 100A are also high.

Referring to fig. 9, after the filling layer 107 is formed, the top of the mask sidewall layer 104 is used as a stop position, the polishing stop layer 105 and the filling layer 107 higher than the top of the mask sidewall layer 104 are etched and removed, and the tops of the remaining polishing stop layer 105 and the remaining filling layer 107 are flush with the top of the mask sidewall layer 104.

The top of the filling layer 107 is flush with the top of the grinding stop layer 105 in the first region 100A, and the grinding stop layer 105 and the filling layer 107 higher than the top of the mask side wall layer 104 are removed integrally, so that the flatness of the tops of the remaining grinding stop layer 105 and the filling layer 107 and the top of the mask side wall layer 104 is higher, and therefore, the probability of generating defects on the top and the side wall of the mask side wall layer 104 is reduced by combining a planarization process and an etching process, and the performance of a semiconductor device is improved.

In this embodiment, the process of removing the polishing stop layer 105 and the filling layer 107 higher than the top of the mask sidewall layer 104 by etching includes a plasma dry etching process.

In the process of removing the grinding stop layer 105 and the filling layer 107 higher than the top of the mask side wall layer 104 by using a plasma dry etching process, the removal rate of the grinding stop layer 105 and the filling layer 107 is far greater than that of the mask side wall layer 104.

Moreover, the plasma dry etching treatment process has the advantages of high etching rate, high etching selectivity, low cost and the like.

In this embodiment, the parameters of the plasma dry etching process include: the etching gas comprises CF ₆ And CHF ₃ One or more of (a); the chamber pressure is 3mTorr to 10mTorr; the radio frequency power is 50W to 1000W.

It should be noted that the chamber pressure should not be too high or too low. If the chamber pressure is too high, during the process of removing the polishing stop layer 105 and the filling layer 107 higher than the top of the mask sidewall layer 104, it is easy to cause a portion of the polishing stop layer 105 remaining on the top of the mask sidewall layer 104 to affect the subsequent process of forming the target pattern in the target layer 101, thereby affecting the performance of the semiconductor; if the chamber pressure is too low, during the process of removing the polishing stop layer 105 and the filling layer 107 above the top of the mask sidewall layer 104, portions of the polishing stop layer 105 and the filling layer 107 in the opening 160 are also removed, which may result in poor flatness of the top surface of the remaining polishing stop layer 105 and filling layer 107, thereby affecting the subsequent formation of the target pattern in the target layer 101. To this end, in this embodiment, the chamber pressure is 3mTorr to 10mTorr.

It should be noted that the radio frequency power should not be too large, nor too small. If the rf power is too high, during the process of removing the polishing stop layer 105 and the filling layer 107 higher than the top of the mask sidewall layer 104, the polishing stop layer 105 and the filling layer 107 in the opening 160 are also easily removed, which results in poor flatness of the top surface of the remaining polishing stop layer 105 and the filling layer 107, thereby affecting the subsequent formation of the target pattern in the target layer 101; if the rf power is too low, during the process of removing the polishing stop layer 105 and the filling layer 107 higher than the top of the mask sidewall layer 104, a residual portion of the polishing stop layer 105 is easily located on the top of the mask sidewall layer 104, which affects the subsequent process for forming the target pattern in the target layer 101, and thus affects the performance of the semiconductor. For this reason, in this embodiment, the rf power is 50W to 1000W.

In this embodiment, in the step of removing the polishing stop layer 105 and the filling layer 107 higher than the top of the mask sidewall layer 104 by etching, an etching selection ratio of the polishing stop layer 105 to the mask sidewall layer 104 is greater than 10:1.

it should be noted that the etching selectivity of the polish stop layer 105 to the mask sidewall layer 104 is not too small. If the etching selectivity of the polishing stop layer 105 to the mask sidewall layer 104 is too small, the mask sidewall layer 104 is easily removed by etching in the process of removing the polishing stop layer 105 higher than the top of the mask sidewall layer 104 by etching, and the subsequent process for forming the target pattern in the target layer 101 is affected, thereby affecting the performance of the semiconductor. For this reason, in this embodiment, in the step of removing the polishing stop layer 105 and the filling layer 107 higher than the top of the mask sidewall layer 104 by etching, an etching selection ratio of the polishing stop layer 105 to the mask sidewall layer 104 is greater than 10:1.

in this embodiment, the etching selection ratio of the filling layer 107 to the mask sidewall layer 104 is greater than 10:1.

it should be noted that the etching selectivity of the filling layer 107 to the mask sidewall layer 104 is not too small. If the etching selectivity of the filling layer 107 to the mask sidewall layer 104 is too small, the mask sidewall layer 104 is easily removed by etching in the process of removing the filling layer 107 higher than the top of the mask sidewall layer 104 by etching, and the subsequent process for forming the target pattern in the target layer 101 is affected, thereby affecting the performance of the semiconductor. For this reason, in this embodiment, the etching selection ratio of the filling layer 107 to the mask sidewall layer 104 is greater than 10:1.

referring to fig. 10 to 11, the remaining polish stop layer 105 and the filling layer 107 in the first region 100A and a portion of the filling layer 107 and the polish stop layer 105 in the second region 100B are removed, a discrete barrier layer 112 is formed on top of the mask sidewall layer 104 in the second region 100B, and first trenches 113 are formed between sidewalls of adjacent mask sidewall layers 104, between sidewalls of mask sidewall layers 104 and barrier layers 112, and between sidewalls of adjacent barrier layers 112.

The bottom of the first trench 113 exposes a portion of the top surface of the mask sidewall layer, which provides a process foundation for subsequently removing the mask sidewall layer 104 at the bottom of the first trench 113.

In this embodiment, the step of removing, by etching, the remaining polishing stop layer 105 and the filling layer 107 in the first region 100A and the part of the filling layer 107 in the second region 100B includes: as shown in fig. 10, a patterned mask layer 111 is formed on top of the mask sidewall layer 104 and on top of the filling layer 107, and the mask layer 111 in the first region 100A is located on top of the core layer 103, and the mask layer 111 in the second region 100B is located on top of the filling layer 107; as shown in fig. 11, with the mask layer 111 as a mask, the remaining polishing stop layer 105 and the filling layer 107 in the first region 100A and a portion of the filling layer 107 in the second region 100B are removed by etching.

In this embodiment, the process of removing the remaining polishing stop layer 105 and the filling layer 107 in the first region 100A and the part of the filling layer 107 and the polishing stop layer 105 in the second region 100B by etching includes a dry etching process.

It should be noted that the dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristic of anisotropic etching, the longitudinal etching rate of the anisotropic dry etching process is far greater than the transverse etching rate, and quite accurate pattern conversion can be obtained, so that the shapes of the mask side wall layer 104 and the shielding layer can be accurately controlled in the process of removing the residual grinding stop layer 105 and the filling layer 107 positioned in the first area 100A and the partial filling layer 107 and the grinding stop layer 105 positioned in the second area 100B.

In this embodiment, the mask layer 111 includes a planarization material layer 110, an anti-reflective coating 109 on the planarization material layer 110, and a photoresist layer 108 on the anti-reflective coating 109.

The planarization material layer 110 provides a flat surface for the formation of the photoresist layer 108, thereby improving the exposure effect during the formation of the photoresist layer 108. The material of the planarization material layer 110 includes an organic material. In this embodiment, the material of the planarization material layer 110 is Spin-on carbon (SOC). In other embodiments, the material of the planarization material layer may also be other organic materials, such as: one or more of an ODL (organic dielectric layer) material, a DUO (Deep UV Light Absorbing Oxide) material, and an APF (Advanced Patterning Film) material.

The material of the anti-reflective coating 109 includes a bottom anti-reflective coating (BARC) material. As an example, the BARC material is a Si-ARC (silicon-containing anti-reflective coating) material.

In this embodiment, before removing the remaining polishing stop layer 105 and the filling layer 107 in the first region 100A and the part of the filling layer 107 and the polishing stop layer 105 in the second region 100B, the method further includes: and sequentially etching the anti-reflection coating 109 and the planarization material layer 110 by taking the photoresist layer 108 as a mask.

It should be noted that, in other embodiments, the photoresist layer may be consumed during the etching of the anti-reflective coating and the organic material layer, and the mask layer may only include the organic material layer and the anti-reflective coating on the organic material layer.

Referring to fig. 12, after the shielding layer 112 and the first trench 113 are formed, the mask sidewall layer 104 on the top of the core layer 103 and at the bottom of the first trench 113 is removed, and a mask sidewall 115 on the sidewall of the core layer 103 is formed.

The mask sidewall 115 and the blocking layer 112 provide a process basis for subsequently etching the target layer 102 to form a target pattern in the target layer 102.

In this embodiment, the process of removing the mask sidewall layer 104 on the top of the core layer 103 and at the bottom of the first trench 113 includes a dry etching process.

Referring to fig. 13, after the mask sidewall spacers 115 are formed, the core layer 103 is removed to form a second trench 116.

The bottom of the second trench 116 exposes a portion of the top surface of the target layer 101 in preparation for subsequent formation of a target pattern in the target layer 101.

It should be noted that the process for removing the core layer 103 includes one or both of a wet etching process and an ashing process.

The wet etching process has isotropic characteristics. The core layer 103 can be removed while the mask sidewall 115 and the blocking layer 112 are maintained.

Note that the material of the core layer 103 is amorphous silicon. The material hardness of the amorphous silicon is less than the material hardness of the mask sidewall 115 and the blocking layer 112, so that the mask sidewall 115 and the blocking layer 112 can be retained during the process of removing the core layer 103.

It should be noted that the etching selectivity of the core layer 103 to the mask sidewall spacer 115 is not too small. If the etching selection ratio of the core layer 103 to the mask sidewall 115 is too small, a portion of the core layer 103 is likely to remain, which affects a subsequent process for forming a target pattern in the target layer 101, thereby affecting the performance of a semiconductor. For this reason, in this embodiment, in the step of removing the core layer 103, an etching selection ratio of the core layer 103 to the mask sidewall spacer 115 is greater than 10:1.

referring to fig. 14, the target layer 101 at the bottoms of the second trench 116 and the first trench 113 is etched by using the mask sidewall 115 and the blocking layer 112 as masks, and a target pattern 117 is formed in the target layer 101.

As can be seen from the above description, by combining the planarization process and the etching process, the probability of defects on the top and the sidewall of the mask sidewall layer is reduced, so that the flatness of the top of the shielding layer 112 and the top of the mask sidewall 115 is higher, which correspondingly improves the pattern precision and the pattern quality of the target pattern 117.

In this embodiment, the step of etching the target layer 101 at the bottoms of the second trench 116 and the first trench 113, and forming the target pattern 117 in the target layer 101 includes: a mask opening is formed in the target layer 101, the mask opening is used as a target pattern 117, and the remaining target layer 101 is used as a hard mask layer 180.

The hard mask layer 180 provides a process foundation for the subsequent etching of the dielectric layer 100 to form an interconnect opening in the dielectric layer 100.

In this embodiment, the forming the etch stop layer 102 on the target layer 101 further includes, with the mask sidewall 115 and the blocking layer 112 as masks, in a process of etching the target layer 101 to form a target pattern 117: the etch stop layer 102 is etched.

After the target pattern 117 is formed, the method further includes: and removing the mask side wall 115 and the blocking layer 112.

Referring to fig. 15, after the target pattern 117 is formed, the forming method further includes: and etching the dielectric layer 100 along the mask opening by taking the hard mask layer 180 as a mask to form an interconnection opening 118 in the dielectric layer 100.

The interconnect openings 118 provide spatial locations for subsequent formation of metal interconnect lines.

In this embodiment, the hard mask layer 180 is formed by transferring the pattern into the target layer 102, which is beneficial to improving the process stability and process effect of etching the dielectric layer 100 and improving the precision of transferring the target pattern.

It should be noted that, in the present embodiment, other layers or structures of the substrate below the dielectric layer 100 are not illustrated, and therefore, in an actual process, the bottom of the interconnect opening 118 exposes a corresponding conductive structure (e.g., a contact hole plug, etc.).

It should be further noted that, during the subsequent formation of the metal interconnection line in the interconnection opening 118, the remaining etching stop layer 102 and the hard mask layer 180 are removed, thereby exposing the top surface of the dielectric layer 100 in preparation for the subsequent process.

Referring to fig. 16, metal interconnect lines 120 are formed in the interconnect openings 118.

The metal interconnection lines 120 are used to electrically connect the semiconductor structure to an external circuit or other interconnection structure.

In this embodiment, the metal interconnection line 120 is made of copper. In other embodiments, the metal interconnection line may also be made of a conductive material such as aluminum.

In this embodiment, the metal interconnection line 120 is formed in the interconnection groove by an electroplating method.

Accordingly, the process of forming the metal interconnect line 120 includes a filling step of conductive material and a planarization step of the conductive material to remove the conductive material above the top of the dielectric layer.

In this embodiment, a chemical mechanical polishing process is used to planarize the conductive material.

The chemical mechanical polishing process makes the metal interconnection line 120 formed in the interconnection groove have a flat surface, which improves the electrical connection effect of the metal interconnection line 120.

The detailed description of the metal interconnection line 120 is omitted here.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (15)

1. A method of forming a semiconductor structure, comprising:

providing a substrate comprising a target layer for forming a target pattern, the substrate comprising a first region and a second region, a pitch adjacent to the target pattern formed in the first region being smaller than a pitch adjacent to the target pattern formed in the second region, a core layer formed on top of the target layer in the first region, the core layer having an opening formed therein through the core layer;

forming mask sidewall layers conformally covering the top of the target layer and the top and sidewalls of the core layer, wherein in the first region, the mask sidewall layers on opposite sidewalls of the core layer have a minimum spacing value in a direction perpendicular to the extending direction of the opening;

forming a polish stop layer conformally covering the mask sidewall layer, the polish stop layer having a thickness greater than or equal to half of the minimum spacing value;

forming a filling material layer covering the top of the grinding stop layer;

planarizing the filling material layer, wherein the rest filling material layer is used as a filling layer, and the top of the filling layer is flush with the top of the grinding stop layer in the first area;

and after the filling layer is formed, etching and removing the grinding stop layer and the filling layer which are higher than the top of the mask side wall layer by taking the top of the mask side wall layer as a stop position, wherein the tops of the residual grinding stop layer and the residual filling layer are flush with the top of the mask side wall layer.

2. The method of forming a semiconductor structure of claim 1, further comprising: after the grinding stop layer and the filling layer which are higher than the top of the mask side wall layer are removed through etching, the rest of the grinding stop layer and the filling layer which are positioned in the first area and the part of the filling layer which is positioned in the second area are removed, a discrete shielding layer is formed at the top of the mask side wall layer of the second area, and first grooves are formed among the side walls of the adjacent mask side wall layers, among the side walls of the mask side wall layers and the shielding layer and among the side walls of the adjacent shielding layers;

after the shielding layer and the first groove are formed, removing the mask side wall layers positioned at the top of the core layer and the bottom of the first groove to form mask side walls positioned on the side walls of the core layer;

after the mask side wall is formed, removing the core layer to form a second groove;

and etching the target layer at the bottoms of the second groove and the first groove by taking the mask side wall and the shielding layer as masks, and forming a target pattern in the target layer.

3. The method of claim 1, wherein planarizing the layer of fill material comprises a chemical mechanical polishing process.

4. The method of claim 1, wherein etching away the polish stop layer and the fill layer above the top of the mask sidewall layer comprises a plasma dry etch process.

5. The method of forming a semiconductor structure of claim 4, wherein the parameters of the plasma dry etch process comprise: the etching gas comprises CF ₆ And CHF ₃ One or two of them; the chamber pressure is 3mTorr to 10mTorr; the radio frequency power is 50W to 1000W.

6. The method of claim 1, wherein the process of forming the polish stop layer comprises an atomic layer deposition process.

7. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming a polish stop layer conformally covering the mask sidewall layer, the polish stop layer is filled in a remaining space of each of the openings exposed by the mask sidewall layer or a remaining space of a portion of the openings exposed by the mask sidewall layer in the first region.

8. The method of claim 1, wherein in the step of forming the polish stop layer, the polish stop layer has a thickness of 10 nm to 30 nm.

9. The method of claim 1, wherein in the step of removing the polish stop layer and the fill layer above the top of the mask sidewall layer, an etch selectivity ratio of the polish stop layer to the mask sidewall layer is greater than 10:1;

the etching selection ratio of the filling layer to the mask side wall layer is greater than 10:1.

10. the method of claim 1, wherein the process of forming the mask sidewall layer comprises an atomic layer deposition process.

11. As claimed in claim1, in the step of forming the mask side wall layer, the material of the mask side wall layer comprises TiO, siN and SiO ₂ One or more of (a).

12. The method of claim 1, wherein the process of forming the layer of filler material comprises a chemical vapor deposition process.

13. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the layer of filler material, the material of the layer of filler material comprises one or more of silicon oxide, silicon oxynitride, silicon carbide, titanium oxide, titanium nitride, and silicon nitride.

14. The method of claim 2, wherein the step of etching away the remaining polish stop layer and the fill layer in the first region and the portion of the fill layer in the second region comprises: forming graphical mask layers on the tops of the mask side wall layers and the top of the filling layer, wherein the mask layer in the first area is located on the top of the core layer, and the mask layer in the second area is located on the top of the filling layer; and etching and removing the residual grinding stop layer and the filling layer in the first area and part of the filling layer in the second area by taking the mask layer as a mask.

15. The method of forming a semiconductor structure of claim 2, wherein in the step of providing a substrate, the substrate further comprises a dielectric layer, the target layer being located on the dielectric layer;

etching the target layer at the bottoms of the second groove and the first groove, wherein the step of forming a target pattern in the target layer comprises the following steps: forming a mask opening in the target layer, wherein the mask opening is used as a target pattern, and the rest target layer is used as a hard mask layer;

after the target pattern is formed, the forming method further includes: taking the hard mask layer as a mask, etching the dielectric layer along the mask opening, and forming an interconnection opening in the dielectric layer; and forming a metal interconnection line in the interconnection opening.

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