CN115223864A - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

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Publication number
CN115223864A
CN115223864A CN202210843703.5A CN202210843703A CN115223864A CN 115223864 A CN115223864 A CN 115223864A CN 202210843703 A CN202210843703 A CN 202210843703A CN 115223864 A CN115223864 A CN 115223864A
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mask layer
initial
temperature
substrate
region
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盛薄辉
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3178—Coating or filling in grooves made in the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating

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Abstract

The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a substrate, wherein the substrate is provided with a first area and a second area which are adjacent; forming an initial first mask layer on the first area and the second area, wherein the initial temperature of the initial first mask layer for starting a cross-linking reaction is a first temperature; forming an initial second mask layer on one side, far away from the substrate, of the initial first mask layer, wherein the initial temperature of the initial second mask layer, at which a cross-linking reaction starts, is a second temperature, the second temperature is lower than the first temperature, and the cross-linking reaction temperature interval of the initial second mask layer is wider than that of the initial first mask layer; and heating the initial first mask layer and the initial second mask layer, wherein the duration of the initial first mask layer in a flowing state is longer than that of the initial second mask layer in the flowing state. The embodiment of the disclosure is at least beneficial to improving the thickness uniformity of the mask layer while simplifying the preparation process of the semiconductor structure.

Description

Semiconductor structure and preparation method thereof
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
Background
In a semiconductor process, in order to improve the accuracy of pattern transfer, a planarization process is performed on the surface of a semiconductor structure, and the conventional planarization process includes: chemical Mechanical Planarization (CMP).
However, since the pattern densities of different regions of the semiconductor structure are different, the thickness of the formed mask layer is not uniform, that is, the top surfaces of the mask layers located in different regions of the semiconductor structure are not flush, which affects the accuracy of the subsequent process steps. Thus, it is necessary to increase the height of the mask layer and to reduce the height difference between different regions of the semiconductor structure by alternately using the CMP process, thereby increasing the manufacturing cost of the semiconductor structure and complicating the manufacturing process of the semiconductor structure.
Disclosure of Invention
The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof, which are at least beneficial to improving the thickness uniformity of a mask layer while simplifying the preparation process of the semiconductor structure.
According to some embodiments of the present disclosure, in one aspect, the present disclosure provides a method for manufacturing a semiconductor structure, including: providing a substrate, wherein the substrate is provided with a first area and a second area which are adjacent, and the pattern density of the pattern in the first area is greater than that of the pattern in the second area; forming an initial first mask layer on the first area and the second area, wherein the initial temperature of the initial first mask layer for starting a crosslinking reaction is a first temperature; forming an initial second mask layer on one side, far away from the substrate, of the initial first mask layer, wherein the initial temperature of the initial second mask layer, at which a cross-linking reaction starts, is a second temperature, the second temperature is lower than the first temperature, and the cross-linking reaction temperature interval of the initial second mask layer is wider than the cross-linking reaction temperature interval of the initial first mask layer; and heating the initial first mask layer and the initial second mask layer to gradually solidify the initial first mask layer and the initial second mask layer to form the mask layers, wherein the duration of the initial second mask layer in the flowing state is longer than that of the initial first mask layer in the flowing state.
In some embodiments, the first temperature ranges from 220 ℃ to 230 ℃ and the second temperature ranges from 130 ℃ to 140 ℃.
In some embodiments, the temperature range for the crosslinking reaction of the initial first mask layer is 220 ℃ to 270 ℃, and the temperature range for the crosslinking reaction of the initial second mask layer is 130 ℃ to 220 ℃.
In some embodiments, the forming of the initial first mask layer on the first region and the second region is a first step, the forming of the initial second mask layer on a side of the initial first mask layer away from the substrate is a second step, and the heating of the initial first mask layer and the initial second mask layer is a third step, and the forming of the mask layer includes: and sequentially repeating the first step, the second step and the third step to form the mask layer, wherein the repeated times are positive integers more than or equal to 1.
In some embodiments, a top surface of the mask layer in the first region, which is away from the substrate, is a first top surface, a top surface of the mask layer in the second region, which is away from the substrate, is a second top surface, and a height difference between the first top surface and the second top surface is less than or equal to a first preset value.
In some embodiments, the first predetermined value ranges from 5nm to 10nm.
In some embodiments, the step of forming the initial first mask layer comprises: providing a first coating comprising a phenolic resin, a crosslinker, and a first solvent, wherein the crosslinker comprises a carboxybenzene, the first solvent comprises one of propylene glycol methyl ether acetate or propylene glycol methyl ether, and wherein the phenolic resin has a mass fraction ranging from 60wt.% to 85wt.%, the crosslinker has a mass fraction ranging from 1wt.% to 10wt.%, and the first solvent has a mass fraction ranging from 10wt.% to 90wt.%; coating the first coating on the first region and the second region to form the initial first mask layer.
In some embodiments, the step of forming the initial second mask layer comprises: providing a second coating comprising a self-crosslinking resin and a second solvent, wherein the self-crosslinking resin comprises a self-crosslinking phenolic resin, the second solvent comprises one of propylene glycol methyl ether acetate or propylene glycol methyl ether, and the mass fraction of the second solvent ranges from 50wt.% to 90wt.%; and coating the second coating on one side of the initial first mask layer far away from the substrate to form the initial second mask layer.
In some embodiments, the step of heating the initial first mask layer and the initial second mask layer comprises: and heating the initial first mask layer and the initial second mask layer to a third temperature, wherein the third temperature is higher than the upper limit value of a temperature interval of the initial first mask layer in the cross-linking reaction, and the third temperature is higher than the upper limit value of the temperature interval of the initial second mask layer in the cross-linking reaction.
In some embodiments, the step of heating the initial first mask layer and the initial second mask layer comprises: providing a hot plate that is heated in an environment maintained at the third temperature; and placing the substrate with the initial first mask layer and the initial second mask layer on the hot plate, wherein the hot plate continuously heats the initial first mask layer and the initial second mask layer for a preset time.
In some embodiments, the preset duration ranges from 60s to 90s.
In some embodiments, the method of making further comprises: and carrying out planarization treatment on the mask layer.
In some embodiments, the thickness of the mask layer after the planarization treatment is 100mm to 200nm in a direction along the substrate toward the mask layer
According to some embodiments of the present disclosure, in another aspect, there is provided a semiconductor structure prepared by the method as described in any one of the above methods, the semiconductor structure including: the pattern density of the patterns in the first area is greater than that of the patterns in the second area; and the mask layer is positioned on the first area and the second area, the top surface, far away from the substrate, of the mask layer positioned in the first area is a first top surface, the top surface, far away from the substrate, of the mask layer positioned in the second area is a second top surface, and the height difference between the first top surface and the second top surface is smaller than or equal to a second preset value.
In some embodiments, the second predetermined value ranges from 0nm to 10nm.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages:
the initial second mask layer cross-linking reaction temperature interval is wider than the initial first mask layer cross-linking reaction temperature interval, so that the duration time of the initial second mask layer in a flowing state is longer, and thus, the good flowing property of the initial second mask layer is beneficial to make up the deficiency of the flowing property of the initial first mask layer, so that the overall flowing property of the initial mask layer consisting of the initial first mask layer and the initial second mask layer is improved, and in the process of heating the initial mask layer, the time that part of the initial mask layer is in the flowing state is longer, namely, the initial mask layer has longer time to flow from a high-height area to a low-height area on the substrate, for example, the initial mask layer flows from the first area to the second area, so that the height difference between the initial mask layer in the first area and the initial mask layer in the second area is reduced, the thickness uniformity between the initial mask layers in different areas of the substrate is improved, and the thickness uniformity between the mask layers in different areas of the substrate is improved. Moreover, the thickness uniformity of the mask layer can be improved without increasing the height of the mask layer and alternatively using a CMP process, thereby being beneficial to reducing the preparation cost of the mask layer and simplifying the preparation process of the mask layer.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified; in order to more clearly illustrate the embodiments of the present disclosure or technical solutions in the conventional art, the drawings required to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without inventive efforts.
FIG. 1 is a schematic, partial cross-sectional view of a semiconductor structure;
fig. 2 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 3 to fig. 5 are schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;
fig. 6 is a graphical representation of the relationship between the degree of cross-linking reaction and the temperature of the initial first mask layer and the initial second mask layer in one embodiment of the present disclosure.
Detailed Description
As known from the background art, in the process of manufacturing a semiconductor structure, the process of manufacturing a mask layer needs to be simplified, and the thickness uniformity of the formed mask layer needs to be improved.
It is analyzed and found that referring to fig. 1, fig. 1 is a partial cross-sectional view of a semiconductor structure, wherein a substrate 10 has a first region 11 and a second region 12 adjacent to each other, and a pattern density of a pattern 14 in the first region 11 is greater than a pattern density of the pattern 14 in the second region 12. It will be understood that the base 10 includes a substrate 13 and a pattern 14 formed on the substrate 13.
The pattern density of the pattern 14 in the first area 11 is greater than the pattern density of the pattern 14 in the second area 12, and then the interval between adjacent patterns 14 in the first area 11 is smaller than the interval between adjacent patterns 14 in the second area 12, so that the filling degree of the mask layer 15 to the interval between adjacent patterns in different areas on the substrate 13 is different, which may cause uneven thickness of the mask layer 15 located in the second area 12, for example, the mask layer 15 located in the second area 12 has a groove, and in a subsequent etching process, an area with a lower thickness in the mask layer 15 is easily completely etched through, thereby damaging the surface of the substrate 10 below the area, and in some embodiments, the substrate 10 is a wafer, which may easily cause wafer defects in the subsequent etching process, and the yield of products formed based on the wafer is low. Therefore, the height difference between the mask layer 15 in the first region 11 and the mask layer 15 in the second region 12 can be effectively and simply reduced, so that other subsequent process steps can be performed in order.
Therefore, a new preparation process needs to be designed at present to improve the thickness uniformity of the formed mask layer and simplify the preparation process steps of the mask layer.
The disclosed implementation provides a semiconductor structure and a preparation method thereof, in the preparation method, an initial second mask layer cross-linking reaction temperature interval is wider than an initial first mask layer cross-linking reaction temperature interval, so that the duration of the initial second mask layer in a flowing state is longer, thus being beneficial to making up the deficiency of the fluidity of the initial first mask layer by utilizing the good fluidity of the initial second mask layer, improving the overall fluidity of the initial mask layer formed by the initial first mask layer and the initial second mask layer, and the time of partial area of the initial mask layer in the flowing state is more durable, thereby being beneficial to utilizing the good fluidity and the durable flowing time of the initial mask layer, reducing the height difference between the initial mask layer positioned in a first area and the initial mask layer positioned in a second area, and improving the thickness uniformity between the initial mask layers positioned on different areas of a substrate, namely improving the thickness uniformity between the mask layers positioned on different areas of the substrate. Moreover, the preparation process of the mask layer is facilitated to be simplified, and the preparation cost for forming the mask layer is reduced.
Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the embodiments of the disclosure, numerous technical details are set forth in order to provide a better understanding of the embodiments of the disclosure. However, the claimed embodiments of the present disclosure may be practiced without these specific details or with various changes and modifications based on the following embodiments.
An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which will be described in detail below with reference to the accompanying drawings. Fig. 2 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; fig. 3 to fig. 5 are schematic structural diagrams corresponding to steps in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure; fig. 6 is a schematic diagram illustrating a relationship between a degree of a cross-linking reaction of an initial first mask layer and an initial second mask layer and a temperature in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.
Referring to fig. 2 to 5, a method of fabricating a semiconductor structure includes:
s101: referring to fig. 3, a substrate 100 is provided, the substrate 100 having a first region 110 and a second region 120 adjacent to each other, the pattern density of the pattern 140 in the first region 110 is greater than the pattern density of the pattern 140 in the second region 120.
In some embodiments, the base 100 includes a substrate 130 and a pattern 140 on the substrate 130, wherein the substrate 130 may be a silicon substrate, a germanium substrate, a silicon carbide substrate, a silicon on insulator substrate, or the like.
It is noted that, in some embodiments, the first region 110 may be a memory cell array region in a semiconductor structure, and the second region 120 may be a peripheral logic circuit region in the semiconductor structure. In some embodiments, the pattern 140 in the substrate 100 may be used as a mask layer for patterning the substrate 100.
S102: with continued reference to fig. 3, an initial first mask layer 101 is formed over the first region 110 and the second region 120, and the initial temperature at which the initial first mask layer 101 begins to undergo a cross-linking reaction is a first temperature.
It is understood that the pattern density of the patterns 140 in the first region 110 is greater than the pattern density of the patterns 140 in the second region 120, the distance between the adjacent patterns 140 in the first region 110 is a first distance, and the distance between the adjacent patterns 140 in the second region 120 is a second distance, and the first distance is smaller than the second distance, so that the initial first mask layer 101 fills the first region 110 to a different extent than the second region 120, which may result in the top surface of the initial first mask layer 101 in the first region 110 away from the substrate 100 being higher than the top surface of the initial first mask layer 101 in the second region 120 away from the substrate 100.
In some embodiments, the thickness of the initial first mask layer 101 may be 90nm to 110nm in a direction Y of the substrate 100 pointing toward the initial first mask layer 101.
S103: referring to fig. 4, an initial second mask layer 102 is formed on a side of the initial first mask layer 101 away from the substrate 100, where an initial temperature at which the initial second mask layer 102 starts to perform a cross-linking reaction is a second temperature, and the second temperature is lower than the first temperature; the cross-linking reaction temperature interval of the initial second mask layer 102 is wider than the cross-linking reaction temperature interval of the initial first mask layer 101.
It is understood that the top surface of the initial first mask layer 101 in the first region 110, which is far from the substrate 100, is higher than the top surface of the initial first mask layer 101 in the second region 120, which is far from the substrate 100, and the initial second mask layer 102 covers the side of the initial first mask layer 101, which is far from the substrate 100, so that the top surface of the initial second mask layer 102 in the first region 110, which is far from the substrate 100, is higher than the top surface of the initial second mask layer 102 in the second region 120, which is far from the substrate 100.
In addition, the initial first mask layer 101 has a high crosslinking reaction temperature, so that the crosslinking reaction is rapidly carried out, and the fluidity is poor; the initial second mask layer 102 has a low cross-linking reaction temperature, a wider cross-linking reaction interval in a low temperature region, and a long fluidity retention time.
Therefore, the second temperature is lower than the first temperature, the time when the initial first mask layer 101 starts to undergo the cross-linking reaction is the first time, the time when the initial second mask layer 102 starts to undergo the cross-linking reaction is the second time, and subsequently, in the process that the initial first mask layer 101 and the initial second mask layer 102 are heated, the temperature of the initial first mask layer 101 itself and the temperature of the initial second mask layer 102 themselves are gradually increased, the second time is earlier than the first time, the components in the initial second mask layer 102 start to undergo the cross-linking reaction first, and the cross-linking reaction temperature interval of the initial second mask layer 102 is wider than the cross-linking reaction temperature interval of the initial first mask layer 101, so that the duration of the initial second mask layer 102 in the flowing state is longer.
In some embodiments, the thickness of the initial second mask layer 102 may be 90nm to 110nm along the direction Y.
S104: with combined reference to fig. 4 and 5, the initial first mask layer 101 and the initial second mask layer 102 are heated to gradually solidify the initial first mask layer 101 and the initial second mask layer 102 to form the mask layer 103, and a duration of the initial second mask layer 102 in a flowing state is greater than a duration of the initial first mask layer 101 in a flowing state.
The general flow direction of the initial second mask layer 102 is illustrated by the arrow X in fig. 5. It will be appreciated that during the heating of the initial first mask layer 101 and the initial second mask layer 102, the initial first mask layer 101 is also in a flowing state for a period of time, and the flowing tendency of the initial first mask layer 101 is consistent with the flowing tendency of the initial second mask layer 102, except that the flowing degree of the initial first mask layer 101 is less pronounced than the flowing degree of the initial second mask layer 102. As the crosslinking reaction temperature interval of the initial second mask layer 102 is wider than the crosslinking reaction temperature interval of the initial first mask layer 101, the duration of the flowing state of the initial second mask layer 102 is longer, so that the initial second mask layer 102 with strong fluidity spontaneously flows from the first region 110 with high height to the second region 120 with low height, and the flowing time of the initial second mask layer 102 is longer, which is beneficial to make up for the deficiency of the fluidity 101 of the initial first mask layer 101 by utilizing the good fluidity of the initial second mask layer 102, so as to improve the overall fluidity of the initial mask layer composed of the initial first mask layer 101 and the initial second mask layer 102, as shown in fig. 5, the height difference between the initial second mask layer 102 located in the first region 110 and the initial second mask layer 102 located in the second region 120 is beneficial to reduce, thereby integrally improving the thickness uniformity between the initial mask layers located in different regions of the substrate 100.
In addition, as the heating process continues to perform the curing molding on the initial first mask layer 101 and the initial second mask layer 102 to form the mask layer 103, it can be understood that, for the initial first mask layer 101, the curing molding of the initial first mask layer 101 is that the degree of the cross-linking reaction of the components in the initial first mask layer 101 reaches 100%; for the initial second mask layer 102, the curing and forming of the initial second mask layer 102 means that the cross-linking reaction degree of the components in the initial second mask layer 102 reaches 100%. Since the height difference between the initial second mask layer 102 in the first region 110 and the initial second mask layer 102 in the second region 120 is gradually decreased during the heating process, the height difference between the mask layer 103 in the first region 110 and the mask layer 103 in the second region 120 is also lower for the mask layer 103 that is solidified and molded based on the heated initial first mask layer 101 and the initial second mask layer 102, i.e., the purpose of improving the thickness uniformity between the mask layers 103 in different regions of the substrate 100 is achieved.
It should be noted that, in fig. 5, a difference between the heights of the finally formed mask layer 103 on the first region 110 and the second region 120 is taken as an example, and it is understood that the difference is smaller than the difference between the heights of the mask layer on the first region and the second region in the prior art, and the difference between the heights of the mask layer 103 on the first region 110 and the second region 120 in an embodiment of the present disclosure will be described in detail later.
In some embodiments, for the initial second mask layer 102, the temperature at which the initial second mask layer 102 starts to undergo the cross-linking reaction is a second temperature, which may range from 130 ℃ to 140 ℃, and the temperature at which the initial second mask layer 102 undergoes the cross-linking reaction is in a range from 130 ℃ to 220 ℃; for the initial first mask layer 101, the temperature at which the initial first mask layer 101 starts to undergo the cross-linking reaction is a first temperature, which may range from 220 ℃ to 230 ℃, and the temperature range at which the initial first mask layer 101 undergoes the cross-linking reaction is 220 ℃ to 270 ℃. As can be seen, not only the second temperature is lower than the first temperature, but also the temperature interval of the component crosslinking reaction in the initial second mask layer 102 is wider than the temperature interval of the component crosslinking reaction in the initial first mask layer 101, and since the initial first mask layer 101 and the initial second mask layer 102 are heated together, the time-dependent change process of the temperature of the initial first mask layer 101 itself is substantially the same as the time-dependent change process of the temperature of the initial second mask layer 102 itself, and the duration of the initial second mask layer 102 in the flowing state is longer than the duration of the initial first mask layer 101 in the flowing state.
In one example, referring to fig. 6, for the initial first mask layer 101, the temperature at which the initial second mask layer 102 starts to undergo a cross-linking reaction is 130 ℃, and the temperature at which the initial second mask layer 102 undergoes a cross-linking reaction to a 100% degree is 220 ℃; for the initial first mask layer 101, the temperature at which the initial first mask layer 101 starts to undergo a cross-linking reaction is 230 ℃, and the temperature at which the initial first mask layer 101 undergoes a cross-linking reaction to an extent of 100% is 270 ℃.
It should be noted that the method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure includes at least the following embodiments.
In some embodiments, the initial first mask layer 101 is formed once on the first region 110 and the second region 120, the initial second mask layer 102 is formed once on a side of the initial first mask layer 101 away from the substrate 100, and the mask layer 103 meeting actual requirements can be formed after a heating process is performed on the initial first mask layer 101 and the initial second mask layer 102.
In one example, the mask layer 103 meeting the actual requirement refers to: the difference in height between the mask layer 103 on the first region 110 and the second region 120 is less than or equal to a first preset value.
The top surface of the mask layer 103 located in the first region 110, which is far away from the substrate 100, is a first top surface a, the top surface of the mask layer 103 located in the second region 120, which is far away from the substrate 100, is a second top surface b, a height difference of the mask layer 103 on the first region 110 and the second region 120 refers to a height difference between the first top surface a and the second top surface b, and the first preset value may range from 5nm to 10nm.
In other embodiments, the forming of the initial first mask layer 101 on the first region 110 and the second region 120 is a first step S102, the forming of the initial second mask layer 102 on a side of the initial first mask layer 101 away from the substrate 100 is a second step S103, and the heating of the initial first mask layer 101 and the initial second mask layer 102 is a third step S104, where the forming of the mask layer 103 includes: the first step S101, the second step S102, and the third step S103 are sequentially repeated for a positive integer of 1 or more to form the mask layer 103.
It is understood that, due to the influence of the layout area of the first region 110 and the layout area of the second region 120, the limitation of the process equipment for forming the initial first mask layer 101 or the initial second mask layer 102 on the substrate 100, or the influence of the height of the pattern 140 in the substrate 100, etc., when the first step S102, the second step S103, and the third step S104 are performed only once, the height difference of the solidified initial second mask layer 102 on the first region 110 and the second region 120 as a whole is greater than the first preset value. Therefore, the first step S102, the second step S103, and the third step S104 need to be sequentially repeated, that is, the good flowability of the initial second mask layer 102 and the lasting flowing time of the initial second mask layer 102 in the second step S103 are utilized again, so as to further reduce the height difference between the initial second mask layer 102 located in the first region 110 and the initial second mask layer 102 located in the second region 120, that is, further improve the thickness uniformity of the initial first mask layer 101 and the initial second mask layer 102 as a whole, so that the finally formed overall thickness of the mask layer 103 meets the preset thickness, and the height difference between the mask layer 103 on the first region 110 and the mask layer 103 on the second region 120 is less than or equal to the first preset value.
The top surface of the mask layer 103 in the first region 110, which is far away from the substrate 100, is a first top surface a, the top surface of the mask layer 103 in the second region 120, which is far away from the substrate 100, is a second top surface b, the height difference of the mask layer 103 in the first region 110 and the second region 120 refers to the height difference between the first top surface a and the second top surface b, and the first preset value may be in a range of 5nm to 10nm.
In some embodiments, the material of the initial first mask layer 101 and the material of the initial second mask layer 102 may both be Spin On Carbon (SOC) hard masks.
In some embodiments, the step of forming the initial first mask layer 101 may include: providing a first coating, wherein the first coating comprises a phenolic resin, a cross-linking agent and a first solvent, the cross-linking agent comprises carboxyl benzene, the first solvent comprises one of propylene glycol methyl ether acetate or propylene glycol methyl ether, the mass fraction of the phenolic resin ranges from 60wt.% to 85wt.%, the mass fraction of the cross-linking agent ranges from 1wt.% to 10wt.%, and the mass fraction of the first solvent ranges from 10wt.% to 90wt.%; a first coating is applied on the first region 110 and the second region 120 to form an initial first mask layer 101.
In some embodiments, the initial temperature at which the resin, the crosslinking agent, and the solvent in the initial first mask layer 101 begin to undergo a crosslinking reaction is 230 ℃ or higher.
In some embodiments, the step of forming the initial second mask layer 102 may include: providing a second coating comprising a self-crosslinking resin and a second solvent, wherein the self-crosslinking resin comprises a self-crosslinking phenolic resin, the second solvent comprises one of propylene glycol methyl ether acetate or propylene glycol methyl ether, and the mass fraction of the second solvent ranges from 50wt.% to 90wt.%; a second coating is applied to the side of the initial first mask layer 101 remote from the substrate 100 to form an initial second mask layer 102.
It is to be understood that in some embodiments, the components of the initial second mask layer 102 can undergo a cross-linking reaction by self-cross-linking, i.e., without the aid of a cross-linking agent to assist the components of the initial second mask layer 102 in the cross-linking reaction.
In some embodiments, the weight average molecular mass of the phenolic resin in the initial first mask layer 101 is higher than the weight average molecular mass of the self-crosslinking resin in the initial second mask layer 102.
In some embodiments, the optical properties of the initial second mask layer 102 are better than the optical properties of the initial first mask layer 101. The refractive index of the initial second mask layer 102 is greater than the refractive index of the initial first mask layer 101, and the extinction coefficient of the initial second mask layer 102 is greater than the extinction coefficient of the initial first mask layer 101. For example, the refractive index of the initial second mask layer 102 may be 1.49, the refractive index of the initial first mask layer 101 may be 1.40, the extinction coefficient of the initial second mask layer 102 may be 0.65, and the extinction coefficient of the initial first mask layer 101 may be 0.30.
In some embodiments, the carbon content of the initial first mask layer 101 is lower than the carbon content of the initial second mask layer 102. For example, the carbon content of the initial first mask layer 101 may be 78%, and the carbon content of the initial second mask layer 102 may be 85%.
In some embodiments, the step of heating the initial first mask layer 101 and the initial second mask layer 102 may comprise: the initial first mask layer 101 and the initial second mask layer 102 are heated to a third temperature, and the third temperature is higher than the upper limit of the temperature interval of the crosslinking reaction of the initial first mask layer 101, and the third temperature is higher than the upper limit of the temperature interval of the crosslinking reaction of the initial second mask layer 102. Wherein the third temperature may be 400 ℃. Therefore, the formation of the mask layer 103 by curing the initial first mask layer 101 and the initial second mask layer 102 at a high temperature is facilitated, the thickness uniformity of the formed mask layer 103 is improved, and meanwhile, the good structural strength of the mask layer 103 is ensured, so that the subsequent other process steps can be performed orderly.
In some embodiments, the step of heating the initial first mask layer 101 and the initial second mask layer 102 may comprise: providing a hot plate to heat the hot plate in an environment maintained at a third temperature; the substrate 100 formed with the initial first mask layer 101 and the initial second mask layer 102 is placed on a hot plate, which continuously heats the initial first mask layer 101 and the initial second mask layer 102 for a preset time period.
In some embodiments, the preset duration may range from 60s to 90s.
It will be appreciated that the initial first mask layer 101 and the initial second mask layer 102 are indirectly heated by a hot plate. The heating temperature to the hot plate is maintained at the third temperature and then the hot plate transfers heat to the initial first mask layer 101 and the initial second mask layer 102 on the hot plate by thermal conduction, so that the temperature of the initial first mask layer 101 and the initial second mask layer 102 themselves is raised.
In one example, after the substrate 100 formed with the initial first mask layer 101 and the initial second mask layer 102 is placed on a hot plate, the temperature of the hot plate itself is decreased and then increased, so that the temperatures of the initial first mask layer 101 and the initial second mask layer 102 are gradually increased, and the duration of the entire heating process is about 60s to 90s.
It should be noted that, in the above embodiments, the finally formed mask layer 103 may meet at least one of the following requirements:
in some embodiments, the top surface of the mask layer 103 in the first region 110 away from the substrate 100 is a first top surface a, the top surface of the mask layer 103 in the second region 120 away from the substrate 100 is a second top surface b, and a height difference between the first top surface a and the second top surface b is less than or equal to a first preset value. Wherein the first preset value can be 5 nm-10 nm
In some embodiments, the method of making can further comprise: the mask layer 103 is subjected to planarization processing. It is understood that there may be a certain difference in the heights of the mask layer 103 formed by the above embodiments on the first region 110 and the second region 120, and the strength of the mask layer 103 can support the planarization process, so as to further improve the thickness uniformity of the mask layer 103, and facilitate the subsequent other process steps. The thickness of the mask layer 103 after the planarization treatment may be in the range of 100nm to 200nm in the direction Y. In practical applications, the height difference between the finally formed mask layer 103 on the first region 110 and the second region 120 may be 0 or infinitely close to 0.
To sum up, the crosslinking reaction temperature interval of the initial second mask layer 102 is wider than the crosslinking reaction temperature interval of the initial first mask layer 101, so that the duration of the initial second mask layer 102 in the flowing state is longer, which is beneficial to make up for the deficiency of the fluidity of the initial first mask layer 101 by utilizing the good fluidity of the initial second mask layer 102, so as to improve the overall fluidity of the initial mask layer composed of the initial first mask layer 101 and the initial second mask layer 102, and the time of the initial mask layer partial region in the flowing state is more durable, so as to be beneficial to utilize the good fluidity and the durable flowing time of the initial mask layer, so as to reduce the height difference between the initial mask layer located in the first region 110 and the initial mask layer located in the second region 120, thereby improving the thickness uniformity between the initial mask layers located in different regions of the substrate 100, i.e. improving the thickness uniformity between the mask layers 103 located in different regions of the substrate 100. Moreover, it is advantageous to simplify the process for preparing the mask layer 103 and to reduce the manufacturing cost for forming the mask layer 103.
Another embodiment of the present disclosure further provides a semiconductor structure formed by the manufacturing method provided in the above embodiment. A semiconductor structure provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the foregoing embodiments are not described herein again.
Referring to fig. 5, a semiconductor structure includes: a substrate 100, the substrate 100 having a first region 110 and a second region 120 adjacent to each other, the pattern density of the pattern in the first region 110 being greater than the pattern density of the pattern in the second region 120; and the mask layer 103 is positioned on the first region 110 and the second region 120, the top surface of the mask layer 103 positioned in the first region 110, which is far away from the substrate 100, is a first top surface a, the top surface of the mask layer 103 positioned in the second region 120, which is far away from the substrate 100, is a second top surface b, and the height difference between the first top surface a and the second top surface b is less than or equal to a second preset value. Thus, it is advantageous to ensure that the difference between the thickness of the mask layer 103 on the first region 110 and the thickness of the second region 120 is small, so as to facilitate the subsequent processing steps.
In some embodiments, the second preset value may range from 0nm to 10nm.
It is understood that, in some embodiments, the mask layer 103 in the semiconductor structure provided in another embodiment of the present disclosure may be a combination of the initial first mask layer 101 and the initial second mask layer 102 that are solidified and molded after the heating process in an embodiment of the present disclosure, a height difference between the first region 110 and the second region 120 of the combination of the initial first mask layer 101 and the initial second mask layer 102 may be 0 or infinitely close to 0, and the height difference may also be in a first preset value, where the first preset value may range from 5nm to 10nm; in other embodiments, the mask layer 103 in the semiconductor structure provided by another embodiment of the present disclosure may be a combination of the initial first mask layer 101 and the initial second mask layer 102 after the heating process and the planarization process in an embodiment of the present disclosure, and a height difference between the combination of the initial first mask layer 101 and the initial second mask layer 102 on the first region 110 and the second region 120 is 0 or infinitely close to 0.
In some embodiments, the thickness of the mask layer 103 after the planarization process may range from 100nm to 200nm along the direction Y of the substrate 100 pointing to the mask layer 103.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the present disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the embodiments of the present disclosure in practice. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the embodiments of the disclosure, and it is intended that the scope of the embodiments of the disclosure be limited only by the terms of the appended claims.

Claims (15)

1. A method for fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a first area and a second area which are adjacent, and the pattern density of the pattern in the first area is greater than that of the pattern in the second area;
forming an initial first mask layer on the first area and the second area, wherein the initial temperature of the initial first mask layer for starting a crosslinking reaction is a first temperature;
forming an initial second mask layer on one side, far away from the substrate, of the initial first mask layer, wherein the initial temperature of the initial second mask layer, at which a cross-linking reaction starts, is a second temperature, the second temperature is lower than the first temperature, and the cross-linking reaction temperature interval of the initial second mask layer is wider than the cross-linking reaction temperature interval of the initial first mask layer;
and heating the initial first mask layer and the initial second mask layer to gradually solidify the initial first mask layer and the initial second mask layer to form the mask layers, wherein the duration of the initial second mask layer in the flowing state is longer than that of the initial first mask layer in the flowing state.
2. The method of claim 1, wherein the first temperature is in a range of 220 ℃ to 230 ℃ and the second temperature is in a range of 130 ℃ to 140 ℃.
3. The method of claim 1, wherein the temperature range at which the initial first mask layer undergoes the cross-linking reaction is 220 ℃ to 270 ℃, and the temperature range at which the initial second mask layer undergoes the cross-linking reaction is 130 ℃ to 220 ℃.
4. The method according to any of claims 1 to 3, wherein the forming of the initial first mask layer on the first region and the second region is a first step, the forming of the initial second mask layer on a side of the initial first mask layer remote from the substrate is a second step, and the heating of the initial first mask layer and the initial second mask layer is a third step, and the forming of the mask layer includes:
and sequentially repeating the first step, the second step and the third step to form the mask layer, wherein the repeated times are positive integers more than or equal to 1.
5. The method according to claim 1, wherein a top surface of the mask layer in the first region, which is away from the substrate, is a first top surface, a top surface of the mask layer in the second region, which is away from the substrate, is a second top surface, and a height difference between the first top surface and the second top surface is less than or equal to a first preset value.
6. The method of claim 5, wherein the first predetermined value is in a range of 5nm to 10nm.
7. The method of any of claims 1 to 3, wherein the step of forming the initial first mask layer comprises:
providing a first coating comprising a phenolic resin, a crosslinker, and a first solvent, wherein the crosslinker comprises a carboxybenzene, the first solvent comprises one of propylene glycol methyl ether acetate or propylene glycol methyl ether, and wherein the phenolic resin has a mass fraction ranging from 60wt.% to 85wt.%, the crosslinker has a mass fraction ranging from 1wt.% to 10wt.%, and the first solvent has a mass fraction ranging from 10wt.% to 90wt.%;
coating the first coating on the first region and the second region to form the initial first mask layer.
8. The method of any of claims 1 through 3, wherein the step of forming the initial second mask layer comprises:
providing a second coating comprising a self-crosslinking resin and a second solvent, wherein the self-crosslinking resin comprises a self-crosslinking phenolic resin, the second solvent comprises one of propylene glycol methyl ether acetate or propylene glycol methyl ether, and the mass fraction of the second solvent ranges from 50wt.% to 90wt.%;
and coating the second coating on one side of the initial first mask layer far away from the substrate to form the initial second mask layer.
9. The method of any of claims 1 to 3, wherein the step of heating the initial first mask layer and the initial second mask layer comprises:
and heating the initial first mask layer and the initial second mask layer to a third temperature, wherein the third temperature is higher than the upper limit value of a temperature interval of the initial first mask layer in the cross-linking reaction, and the third temperature is higher than the upper limit value of the temperature interval of the initial second mask layer in the cross-linking reaction.
10. The method of claim 9, wherein heating the initial first mask layer and the initial second mask layer comprises:
providing a hot plate that is heated in an environment maintained at the third temperature;
and placing the substrate with the initial first mask layer and the initial second mask layer on the hot plate, wherein the hot plate continuously heats the initial first mask layer and the initial second mask layer for a preset time.
11. The method of claim 10, wherein the predetermined period of time is in a range of 60s to 90s.
12. The production method according to any one of claims 1 to 3, further comprising: and carrying out planarization treatment on the mask layer.
13. The method according to claim 12, wherein the thickness of the mask layer after the planarization process is 100nm to 200nm in a direction along the substrate toward the mask layer.
14. A semiconductor structure prepared by the method of any one of claims 1-13, comprising:
the pattern density of the patterns in the first area is greater than that of the patterns in the second area;
and the mask layer is positioned on the first area and the second area, the top surface, far away from the substrate, of the mask layer positioned in the first area is a first top surface, the top surface, far away from the substrate, of the mask layer positioned in the second area is a second top surface, and the height difference between the first top surface and the second top surface is smaller than or equal to a second preset value.
15. The semiconductor structure of claim 14, wherein the second predetermined value ranges from 0nm to 10nm.
CN202210843703.5A 2022-07-18 2022-07-18 Semiconductor structure and preparation method thereof Pending CN115223864A (en)

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