CN115223646A

CN115223646A - Memory device, memory system including the same, and test operation of the memory device

Info

Publication number: CN115223646A
Application number: CN202210100271.9A
Authority: CN
Inventors: 李俊赫; 俞登觉; 郑栋在; 李珉圭
Original assignee: SK Hynix Inc
Current assignee: SK Hynix Inc
Priority date: 2021-04-20
Filing date: 2022-01-27
Publication date: 2022-10-21
Also published as: US20220336040A1; KR20220144657A

Abstract

The technology includes a memory device, a memory system including the memory device, and a test operation of the memory device. The memory device includes: a memory block connected to a word line and a select line; bit lines connected to the memory blocks; a voltage generator configured to generate a test voltage to be applied to a selected line of the word line and the selection line; a page buffer configured to sense a voltage of a bit line to store and output test data; and a control logic circuit configured to determine whether a first defect exists in the memory block according to the test data.

Description

Memory device, memory system including the same, and test operation of the memory device

Cross Reference to Related Applications

This application claims priority from korean patent application No. 10-2021-0051250, filed on korean intellectual property office at 20.4.2021, the entire disclosure of which is incorporated herein by reference.

Technical Field

The present disclosure relates to a memory device, a memory system including the memory device, and a test operation of the memory device, and more particularly, to a memory device configured to test defects of a memory device included in a memory system, a memory system including the memory device, and a test operation of the memory device.

Background

The memory system may include a memory device configured to store data and a controller configured to control the memory device.

The memory device may include a memory block in which data is stored and peripheral circuitry configured to perform a program operation, a read operation, or an erase operation. The memory block may include a plurality of strings connected between the bit lines and the source lines, and the plurality of strings may include memory cells capable of storing data. A plurality of memory cells may be programmed, read, or erased according to voltages applied to the word lines and bit lines.

As the storage capacity of the memory system increases and the integration degree increases, the size and distance of memory cells included in the memory device decrease. As the size and distance of the memory cell are reduced, the size of a line connected to the memory cell is reduced, and thus a short defect or an open defect may occur in a manufacturing step of the memory device. The short defect refers to a defect in which elements required to be electrically separated from each other are connected to each other, and the open defect refers to a defect in which elements required to be electrically connected to each other are separated from each other.

Disclosure of Invention

According to one embodiment of the present disclosure, a memory device may include: a memory block connected to a word line and a select line; bit lines connected to the memory blocks; a voltage generator configured to generate a test voltage to be applied to a selected line of the word line and the selection line; a page buffer configured to sense a voltage of a bit line to store and output test data; and a control logic circuit configured to determine whether a first defect exists in the memory block according to the test data. The page buffer includes: a sense latch configured to store test data determined according to a voltage of a sense node during a test operation for detecting a first defect of a memory block; a sense discharge circuit configured to discharge a sense node; and a bit line selection circuit configured to block a connection between the sense node and the bit line when the test data is determined according to a voltage of the sense node. When a test operation starts and there is no first defect in the memory block, the test data is held as reset data in the sense latch, and when there is a first defect in the memory block, the test data is changed.

According to one embodiment of the present disclosure, a memory system may include: a memory device including a page buffer connected to a memory block through a bit line; and a controller configured to transmit a test command to the memory device and determine whether there is a defect based on test data output from the memory device during a test operation for detecting a defect of the memory block. The memory device is configured to: storing initial data in a sense latch of a page buffer in response to a test command; discharging a sense node connected between the bit line and the sense latch; storing test data in the sense latch according to a voltage of the sense node changed by the test operation; and outputting the test data to the controller. The controller is configured to determine that a first defect occurs in the memory block when the test data is different from the initial data.

According to one embodiment of the present disclosure, a method of performing a test operation on a memory device may be provided. The method can comprise the following steps: resetting the sense latch; discharging a sense node connected between a sense latch and a bit line; applying a test voltage to a selected line of word lines and select lines in a memory block connected to bit lines; transmitting a voltage of the bit line to a sensing node; and storing the test voltage in the sense latch according to the voltage of the sense node.

Drawings

FIG. 1 is a diagram illustrating a memory system according to one embodiment of the present disclosure.

Fig. 2 is a diagram illustrating a memory device.

Fig. 3 is a diagram illustrating a memory cell array.

Fig. 4 is a diagram illustrating a memory block.

Fig. 5 is a diagram illustrating a defect occurring in a memory block.

Fig. 6 is a diagram illustrating a connection configuration between a page buffer group and a memory block.

Fig. 7A and 7B are diagrams illustrating the principle of a test operation according to one embodiment of the present disclosure.

Fig. 8 is a circuit diagram illustrating a page buffer according to one embodiment of the present disclosure.

Fig. 9 is a timing diagram illustrating a test operation of the memory device according to the first embodiment of the present disclosure.

Fig. 10 is a timing diagram illustrating a test operation of a memory device according to a second embodiment of the present disclosure.

Fig. 11 is a timing diagram illustrating a test operation of a memory device according to a third embodiment of the present disclosure.

Fig. 12 is a diagram illustrating a controller according to one embodiment of the present disclosure.

Fig. 13 is a diagram illustrating a memory system including the memory device of the present disclosure.

Fig. 14 is a diagram illustrating another memory system including the memory device of the present disclosure.

Detailed Description

Specific structural and functional descriptions of embodiments in accordance with the concepts disclosed in this specification or application are intended only to describe embodiments in accordance with the concepts of the present disclosure. Embodiments in accordance with the concepts of the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth in this specification or application.

One embodiment of the present disclosure provides a memory device capable of detecting a short defect among defects occurring in the memory device, a memory system including the memory device, and a test operation of the memory device.

According to the present technique, a short defect among defects that may occur in a memory device can be detected.

Referring to fig. 1, a memory system 1000 may be configured to store, erase, or output data in response to a request of a host. For example, the memory system 1000 may include a memory device 1100 capable of storing data, and a controller 1200 capable of communicating between a host and the memory device 1100. Although a memory system 1000 including one memory device 1100 is shown in fig. 1, two or more memory devices may be included in the memory system 1000.

When a request is received from a host, the controller 1200 may generate a command for controlling the memory device 1100 according to the received request. The controller 1200 may be configured to manage logical addresses used in the host and physical addresses used in the memory device 1100. For example, during a programming operation, the controller 1200 may map logical addresses used in the host and physical addresses used in the memory device 1100 to each other. During a read operation, the controller 1200 may search for a physical address mapped to a logical address requested by the host and output data read according to the physical address to the host.

The controller 1200 according to the present embodiment may be configured to: during a test operation of the memory device 1100, a test command CMD _ T is transmitted to the memory device 1100, and whether a short defect exists is determined based on test DATA _ T output from the memory device 1100.

The controller 1200 may perform a test operation when a test request is received from a host, but may perform a test operation when a background operation is performed even if there is no request of the host.

Fig. 2 is a diagram illustrating a memory device.

Referring to fig. 2, the memory device 1100 may include: a memory cell array 110 in which data is stored, and peripheral circuits 120 to 170 capable of performing a program operation, a read operation, or an erase operation.

The memory cell array 110 may include a plurality of memory blocks in which data is stored. Each of the memory blocks includes a plurality of memory cells, and the plurality of memory cells may be implemented in a two-dimensional structure in which the memory cells are arranged in parallel on the substrate or a three-dimensional structure in which the memory cells are stacked on the substrate in a vertical direction.

The peripheral circuits 120 to 170 may include a row decoder 120, a voltage generator 130, a page buffer group 140, a column decoder 150, an input/output circuit 160, and a control logic circuit 170.

The row decoder 120 may select one memory block from among the memory blocks included in the memory cell array 110 according to a row address RADD and transmit the operating voltage Vop to the selected memory block.

The voltage generator 130 may generate and output an operation voltage Vop required for various operations in response to the operation code OPCD. For example, the voltage generator 130 may generate a test voltage, a program voltage, a read voltage, an erase voltage, a pass voltage, a verify voltage, a negative voltage, etc. in response to the operation code OPCD and selectively output the generated voltages.

The page buffer group 140 may be connected to the memory cell array 110 through a bit line. For example, the page buffer group 140 may include a page buffer connected to each of the bit lines. The page buffers may be simultaneously operated in response to the page buffer control signal PBSIG, and may temporarily store data during a program operation or a read operation. During a read operation or a verify operation, the page buffer may sense a voltage of the bit line, which varies according to a threshold voltage of the memory cell. That is, whether the threshold voltage of the memory cell is lower or higher than the read voltage or the verify voltage may be determined according to the result of the sensing operation performed in the page buffer. In one embodiment of the present disclosure, the page buffer may sense a voltage of the bit line and maintain data stored in the latch as initial data or change data stored in the latch according to the sensed voltage. The terms "simultaneous" and "simultaneously" with respect to a process as used herein mean that the process occurs over overlapping time intervals. For example, if a first process occurs over a first time interval and a second process occurs simultaneously over a second time interval, the first time interval and the second time interval at least partially overlap each other such that there is a time when both the first process and the second process are occurring.

The column decoder 150 may transfer data through the data lines DL connecting the input/output circuit 160 and the page buffer group 140 according to a column address CADD.

The input/output circuit 160 may be connected to the controller 1200 of fig. 1 through an input/output line IO. The input/output circuit 160 may input/output a command CMD, an address ADD, and data through an input/output line IO. For example, the input/output circuit 160 may transmit a command CMD and an address ADD received from the controller 1200 through the input/output line IO to the control logic circuit 170, and transmit data received from the controller 1200 through the input/output line IO to the page buffer group 140. The input/output circuit 160 may output data received from the page buffer group 140 to the controller 1200 through an input/output line IO. According to the present embodiment, test data output from the page buffer group 140 during a test operation may be output to the controller 1200 through the input/output circuit 160.

The control logic circuit 170 may output an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to a command CMD and an address ADD. For example, the control logic circuit 170 may include software that executes an algorithm in response to the command CMD, and hardware configured to output various signals according to the address ADD and the algorithm. The control logic circuit 170 may control the row decoder 120, the voltage generator 130, the page buffer group 140, and the column decoder 150 to perform a test operation according to a test command. During a test operation, the control logic circuit 170 may determine whether a selected memory block is defective according to test data read from the memory cell array 110.

Fig. 3 is a diagram illustrating a memory cell array.

Referring to fig. 3, the memory cell array 110 may be configured as a single plane or a multi-plane. A single plane refers to a configuration including only one plane in the memory cell array 110, and a multi-plane refers to a configuration including a plurality of planes in the memory cell array 110. Fig. 3 shows memory cell array 110 configured as a multi-plane. For example, the first to fourth planes P1 to P4 may be included in the memory cell array 110. The first to fourth planes P1 to P4 may be defined as memory areas in which different row decoders and different page buffer groups are connected. Each of the first to fourth planes P1 to P4 may include first to ith memory blocks BLK1 to BLKi (i is a positive integer). The first to ith memory blocks BLK1 to BLKi included in different planes may be connected to different row decoders and different page buffer groups, and the first to ith memory blocks BLK1 to BLKi included in the same plane may be connected to the same row decoder and the same page buffer group. The first to ith memory blocks BLK1 to BLKi may be configured in the same structure.

Fig. 4 is a diagram illustrating a memory block.

Referring to fig. 4, any one of the plurality of memory blocks BLK1 to BLKi shown in fig. 3 is shown as an embodiment.

The memory block BLKi may include a plurality of strings ST connected between the first to mth bit lines BL1 to BLm and the source lines SL. Each of the strings ST may include a source selection transistor SST, first to nth memory cells C1 to Cn, and a drain selection transistor DST connected in series between a source line SL and first to mth bit lines BL1 to BLm (m is a positive integer).

Since the memory block BLKi shown in fig. 4 is a diagram illustrating the configuration of the memory block, the numbers of the source selection transistor SST, the first to nth memory cells C1 to Cn, and the drain selection transistor DST are not limited to the numbers shown in fig. 4.

The gates of the source selection transistors SST connected to the different strings ST may be connected to a source selection line SSL, the gates of each of the first to nth memory cells C1 to Cn may be connected to first to nth word lines WL1 to WLn, and the gates of the drain selection transistors DST may be connected to a drain selection line DSL.

Groups of memory cells connected to the same word line and included in different strings ST may constitute one page PG. The program operation and the read operation may be performed in units of a page PG. In the test operation according to the present embodiment, the pages PG may be selected one by one, or a plurality of pages PG may be simultaneously selected.

The memory cells included in the memory block BLKi may be programmed differently according to a programming method. For example, the program operation may be performed in a Single Level Cell (SLC) method, a multi-level cell (MLC) method, a Three Level Cell (TLC) method, or a four level cell (QLC) method. The SLC method is a method in which one bit of data is stored in one memory cell. The MLC method is a method in which two bits of data are stored in one memory cell. The TLC method is a method in which three bits of data are stored in one memory cell. The QLC method is a method in which four bits of data are stored in one memory cell. Additionally, five or more bits of data may be stored in one memory cell.

Fig. 5 is a diagram illustrating a defect occurring in a memory block.

Referring to fig. 5, a portion of a string ST is schematically shown. The string ST may include a plurality of memory cells, and the memory cells may be connected to different word lines WLn 2, WLn 1 and WLn.

When a defect occurs inside the string ST, a short defect DE _ SH or an open defect DE _ OP may occur. The short defect DE _ SH may be a defect in which the word line and the channel CH are electrically connected to each other, and the open defect DE _ OP may be a defect in which an area where the electrical connection is disconnected occurs in the channel CH. That is, the short defect DE _ SH is a defect that elements that need to be electrically disconnected from each other are connected to each other, and the open defect DE _ OP is a defect that elements that need to be electrically connected to each other are disconnected from each other.

Assuming that there is no open defect DE _ OP in the string ST but a short defect DE _ SH occurs in the memory cells connected to the (n-2) th word line WLn-2, the voltage applied to the (n-2) th word line WLn-2 may be directly transferred to the channel CH during a program operation, a read operation, or an erase operation. In this case, since the voltage or current of the bit line BL is changed, the reliability of the program operation, the read operation, or the erase operation may be lowered.

Assuming that there is no short defect DE _ SH in the string ST but an open defect DE _ OP occurs in the channel CH between the nth word line WLn and the (n-1) th word line WLn-1, the voltage or current of the bit line BL may be continuously maintained as an initial value regardless of the voltage applied to the word line during a program operation, a read operation, or an erase operation. In this case, since the state of the memory cell may not be sensed, the reliability of the program operation, the read operation, or the erase operation may be reduced.

In the present embodiment, a method of detecting a short defect DE _ SH is described.

Referring to fig. 6, the page buffer group 140 may include first to mth page buffers PB1 to PBm connected to the first to mth bit lines BL1 to BLm. Since the first to mth page buffers PB1 to PBm sense voltages of the first to mth bit lines BL1 to BLm, respectively, the number of bit lines in which a short defect occurs may be counted during the test operation according to the present embodiment. That is, the number and position of columns in which a short defect occurs can be detected from the result of the test operation.

Fig. 7A and 7B are diagrams illustrating the principle of a test operation according to one embodiment of the present disclosure, and a portion where the string ST is connected to the first page buffer PB1 is shown as an example.

Fig. 7A is a diagram illustrating a case where there is no defect or an open defect DE _ OP occurs in the string ST, and fig. 7B is a diagram illustrating a case where a short defect DE _ SH occurs in the string ST.

Referring to fig. 7A, the first page buffer PB1 may include a precharge circuit PRE, a bit line selection circuit BSEL, a discharge circuit DIS, and a sense latch Ls connected around a sense node SO. The precharge circuit PRE, the bit line selection circuit BSEL, the discharge circuit DIS, and the sense latch Ls may be used during a test operation. The precharge circuit PRE may be configured to precharge the first bit line BL1. The bit line selection circuit BSEL may be configured to connect or disconnect the first bit line BL1 and the first page buffer PB1 to or from each other. The discharge circuit DIS may be configured to discharge the sensing node SO. For example, the voltage of the discharged sensing node SO may be 0V. The sense latch Ls may be configured to store test data determined from the voltage of the sense node SO during a test operation.

During the test operation according to the present embodiment, the sensing node SO may be discharged and initialized to have 0V, and the first bit line BL1 and the sensing node SO may be connected to each other through the bit line selection circuit BSEL. Accordingly, the first bit line BL1 may also be discharged and initialized to have 0V. The "1" data as the initial data may be stored in the sense latch Ls. In the present embodiment, the initial data is set to "1", but the initial data may be set to "0" according to the memory device. In one embodiment, resetting the sense latch Ls may include storing initial data in the sense latch.

As shown in fig. 7A, in the case where there is an open defect DE _ OP or no defect in the channel CH, when a test voltage Vtest having a positive voltage is applied to the selected word line Sel _ WL, the test data of the sense latch Ls may be held as "1" data as initial data. A positive voltage is a voltage greater than zero. More specifically, even if the test voltage Vtest having a positive voltage is applied to the selected word line Sel _ WL, the voltage of the first bit line BL1 is not increased since the test voltage Vtest is not transferred to the first bit line BL1. That is, since the voltage of the first bit line BL1 is maintained at 0V, the voltage of the sensing node SO may also be maintained at 0V, and thus the data stored in the sensing latch Ls may not be changed.

When the test data "1" stored in the sensing latch Ls is output to the controller 1200 of fig. 1, the controller 1200 may determine that there is no defect in the string ST or an open defect DE _ OP even if there is a defect in the string ST according to the "1" data.

Referring to fig. 7B, in the case where a short defect DE _ SH exists in the string ST, when a test voltage Vtest having a positive voltage is applied to a selected word line Sel _ WL, initial data "1" stored in the sense latch Ls may be changed to "0" data. Alternatively, when the initial data is set to "0", the initial data "0" stored in the sense latch Ls may be changed to "1" data. More specifically, when the test voltage Vtest having a positive voltage is applied to the selected word line Sel _ WL, the voltage of the first bit line BL1 may be increased because the selected word line Sel _ WL and the channel CH are electrically connected to each other due to the short defect DE _ SH. That is, since the voltage of the first bit line BL1 increases to a positive voltage, the voltage of the sense node SO may also increase to a positive voltage, and thus the data stored in the sense latch Ls is changed.

When the test data "0" stored in the sensing latch Ls is output to the controller 1200 of fig. 1, the controller 1200 may determine that the short defect DE _ SH exists in the string ST according to the "0" data.

Since the plurality of page buffers are configured identically to each other, a first page buffer PB1 among the plurality of page buffers is shown in fig. 8.

Referring to fig. 8, the first page buffer PB1 may include a bit line precharge circuit PRE, a bit line discharge circuit BDIS, a bit line selection circuit BSEL, a selection precharge circuit SEL _ PC, a sense discharge circuit DIS, a sense latch Ls, a SET circuit SET, and a latch group LG. The bit line precharge circuit PRE, the bit line discharge circuit BDIS, the bit line selection circuit BSEL, the selection precharge circuit SEL _ PC, the sense discharge circuit DIS, the sense latch Ls, the SET circuit SET, and the latch group LG may operate in response to the page buffer control signal PBSIG of fig. 2. That is, the page buffer control signal PBSIG may be a signal for turning on or off the switches included in all the page buffers including the first page buffer PB1.

The bit line precharge circuit PRE may be configured to precharge the first bit line BL1 during a program operation, a read operation, or an erase operation. In the test operation according to the present embodiment, the bit line precharge circuit PRE is deactivated. The bit line precharge circuit PRE may include a first switch S1, the first switch S1 being configured to supply the power supply voltage VCC to the first bit line BL1 in response to a bit line precharge signal BL _ PRE. The first switch S1 may be implemented with an NMOS transistor. In the test operation according to the present embodiment, since the bitline precharge circuit PRE is deactivated, the bitline precharge signal BL _ PRE can be maintained at a low level.

The bit line discharge circuit BDIS may be configured to discharge the first bit line BL1. The bit line discharge circuit BDIS may include a second switch S2, the second switch S2 connecting or disconnecting the first bit line BL1 and the ground terminal GND to or from each other in response to the bit line discharge signal BL _ DIS. The second switch S2 may be implemented with an NMOS transistor that operates in response to the bit line discharge signal BL _ DIS.

The bit line selection circuit BSEL may include a third switch S3, and the third switch S3 is configured to connect or disconnect the first bit line BL1 and the current sensing node CSO in response to the page sensing signal PBSENSE. The third switch S3 may be implemented with an NMOS transistor that connects or disconnects the first bit line BL1 and the current sensing node CSO from each other in response to the page sensing signal PBSENSE.

The select precharge circuit SEL _ PC may be connected between a first node N1 to which the power supply voltage VCC is supplied and a current sensing node CSO. The select precharge circuit SEL _ PC may be configured: to connect or disconnect the current sensing node CSO and the sensing node SO to each other, the current sensing node CSO or the sensing node SO is precharged. The selection precharge circuit SEL _ PC may include fourth to ninth switches S4 to S9 connected between the first node N1 and the current sensing node CSO. For example, the fourth switch S4 and the fifth switch S5 may be connected in parallel with each other between the first node N1 and the second node N2, and the sixth switch S6 may be connected between the second node N2 and the current sensing node CSO. The fourth switch S4 may be implemented with a PMOS transistor that is turned on or off in response to the inverted sensing precharge signal SA _ PRE _ N, and the fifth switch S5 may be implemented with a PMOS transistor that is turned on or off according to data stored in the sensing latch node QS. The sixth switch S6 may be implemented with an NMOS transistor that is turned on or off in response to the current sensing signal SA _ CSOC. The seventh to ninth switches S7 to S9 may be connected in series between the first node N1 and the current sensing node CSO, and may be connected in parallel to the fourth to sixth switches S4 to S6. The seventh switch S7 may be implemented with a PMOS transistor that is turned on or off according to data stored in the sense latch node QS. Eighth switch S8 can be implemented with a PMOS transistor that is turned on or off in response to inverted sense precharge signal SA _ PRE _ N. The ninth switch S9 may be implemented with an NMOS transistor that is turned on or off in response to the sensing signal SA _ SENSE. The sensing node SO may be connected between the eighth switch S8 and the ninth switch S9.

The sense discharge circuit DIS may be configured to discharge the sense node SO. The sensing discharge circuit DIS may include tenth and eleventh switches S10 and S11 connected in series between the sensing node SO and the ground terminal GND. The tenth switch S10 may be implemented with an NMOS transistor that is turned on or off in response to the sensing discharge signal SA _ DIS. The eleventh switch S11 may be implemented with an NMOS transistor that is turned on or off according to data stored in the sense latch node QS. When the sense discharge signal SA _ DIS is logic high and "1" data is stored in the sense latch node QS, the sense node SO may be discharged.

In the present embodiment, "1" data refers to a state in which the voltage of the sense latch node QS is high, and "0" data refers to a state in which the voltage of the sense latch node QS is 0V or a negative voltage. Discharging refers to lowering the voltage of the node to 0V or a negative voltage, and precharging refers to increasing the voltage of the node to a positive voltage.

The sense latch Ls may include first and second inverters I1 and I2 connected between a sense latch node QS and an inverting sense latch node QS _ N. For example, an input terminal of the first inverter I1 may be connected to a sense latch node QS, and an output terminal may be connected to an inverting sense latch node QS _ N. An input terminal of the second inverter I2 may be connected to an inverting sense latch node QS _ N, and an output terminal may be connected to a sense latch node QS. The sense latch Ls may store sensed data during a sensing operation of a selected memory cell. For example, when the voltage of the first bit line BL1 is determined by the selected memory cell and the first bit line BL1 and the sensing node SO are connected to each other, the voltage of the sensing node SO may be determined. When the voltage of the sense node SO is determined, the data of the sense latch node QS may be determined by the operation of the SET circuit SET. During a test operation, test data may be stored in the sense latch node QS.

The setting circuit SET may be configured to reset the sensing latch Ls or change data stored in the sensing latch Ls according to the voltage of the sensing node SO. For example, the setting circuit SET may include: a twelfth switch S12 and a thirteenth switch S13 connected in series between the sense latch node QS and the ground terminal GND, and a fourteenth switch S14 and a fifteenth switch S15 connected in series between the inverse sense latch node QS _ N and the ground terminal GND. The twelfth switch S12 may be implemented with an NMOS transistor that is turned on or off in response to the latch reset signal LRST. The thirteenth switch S13 may be implemented with an NMOS transistor that is turned on or off in response to the page buffer reset signal PBRST. The fourteenth switch S14 may be implemented with an NMOS transistor that is turned on or off in response to the latch set signal LSET. The fifteenth switch S15 may be implemented with an NMOS transistor that is turned on or off according to the voltage of the sensing node SO. The common node COM may be connected between the twelfth switch S12 and the thirteenth switch S13 and between the fourteenth switch S14 and the fifteenth switch S15. The SET circuit SET may transmit data stored in the sense latch Ls to the latch group LG through the common node COM.

The latch group LG may include first to kth latches L1 to Lk. The first to kth latches L1 to Lk may temporarily store data used during a program operation or a read operation and output data received from the SET circuit SET during the read operation or the test operation to the first data line DL1. The first to kth latches L1 to Lk may exchange data with the sensing node SO. Assuming that the first latch L1 is connected to the SET circuit SET and the kth latch Lk is connected to the first data line DL1, the test data stored in the sense latch Ls during the test operation may be transferred to the first latch L1. The test data transferred to the first latch L1 may be transferred to the kth latch Lk, and the test data transferred to the kth latch Lk may be output to the input/output circuit 160 of fig. 2 through the first data line D1.

Referring to fig. 8 and 9, a test operation may be performed after an erase operation on a memory cell. The test operation may include a setting step (S91), a discharging step (S92), a testing step (S93), an evaluating step (S94), and a sensing step (S95) that are sequentially performed.

The setting step S91 is a step of initializing the sense latch Ls. For example, in the setting step S91, "1" data as initial data may be stored in the sense latch node QS of the sense latch Ls. For example, in a state where the page buffer reset signal PBRST transitions to logic high H and the thirteenth switch S13 is turned on, the latch set signal LSET may transition to logic high H for a predetermined time. When both the page buffer reset signal PBRST and the latch set signal LSET have a logic high H value, the thirteenth switch S13 and the fourteenth switch S14 may be turned on, and thus a current path may be formed between the inverted sense latch node QS _ N and the ground terminal GND. Accordingly, "0" data may be stored in the inverting sense latch node QS _ N, and "1" data may be stored in the sense latch node QS. When "1" data is stored in the sense latch node QS, the latch set signal LSET transitions to logic low L, and the page buffer reset signal PBRST also transitions to logic low L. The term "predetermined" (such as a predetermined time) as used herein with respect to a parameter means that the value of the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

When the discharging step S92 starts, the sensing discharge signal SA _ DIS, the bit line discharge signal BL _ DIS, the sensing signal SA _ SENSE, and the page sensing signal PBSENSE may transition to logic high to discharge the sensing node SO, and thus the tenth switch S10, the second switch S2, the ninth switch S9, and the third switch S3 may be turned on. Accordingly, the sensing node SO and the first bit line BL1 may be connected to the ground terminal GND to be discharged. For example, the voltages of the sensing node SO and the first bit line BL1 may be 0V. In the discharging step S92, the turn-on voltage Von may be applied to the drain select line DSL and the source select line SSL of fig. 4. At this time, a voltage of 0V may be applied to the source lines SL of fig. 4. In the discharging step S92, all the word lines may be floated or discharged.

When the test step S93 starts, the test voltage Vtest having a positive voltage may be applied to the selected word line Sel _ WL. In the test step S93, even if the test voltage Vtest is applied to the selected word line Sel _ WL, since the sensing discharge signal SA _ DIS and the bit line discharge signal BL _ DIS are maintained at the high H, the voltage of the sensing node SO may be maintained at a discharge level (e.g., 0V), or the voltage of the sensing node SO may be slightly increased at a low level even if the voltage of the sensing node SO is increased to a positive voltage.

When the evaluation step S94 begins, the sense discharge signal SA _ DIS and the bit line discharge signal BL _ DIS may transition to logic low L. The on voltage Von may be continuously supplied to the drain select line DSL and the source select line SSL, or 0V, which is an off voltage, may be applied.

When the sensing discharge signal SA _ DIS and the bit line discharge signal BL _ DIS transition to logic low L, since the tenth switch S10 and the second switch S2 are turned off, a current path between the sensing node SO, the first bit line BL1, and the ground terminal GND may be blocked.

When there is no short defect between the selected word line Sel _ WL, the selected memory cell connected to the selected word line Sel _ WL, and the channel formed in the selected memory cell, the voltage of the sensing node SO may be maintained at a discharge level (e.g., 0V). When there is a short defect between the selected word line Sel _ WL, the selected memory cell connected to the selected word line Sel _ WL, and the channel formed in the selected memory cell, the precharge voltage Vpre may be applied to the sense node SO. Here, the precharge voltage Vpre may be a voltage of the test voltage Vtest applied to the selected word line Sel _ WL. For example, when there is a short defect in a selected word line Sel _ WL region, the test voltage Vtest applied to the selected word line Sel _ WL may be supplied to the first bit line BL1 through the channel of the string. When the voltage of the first bit line BL1 increases by the test voltage Vtest, the voltage of the sensing node SO connected to the first bit line BL1 may also increase. Accordingly, the precharge voltage Vpre applied to the sensing node SO may have a positive voltage level lower than the test voltage Vtest by the threshold voltage of the switch.

At this time, in order to increase a difference between the level of the test voltage Vtest applied to the sensing node SO and the discharge level (e.g., 0V), the current sensing signal SA _ CSOC having the compensation voltage Vcom may be applied to the sixth switch S6. In other words, the current sensing signal SA _ CSOC for weakly turning on the sixth switch S6 may be applied to the gate of the sixth switch S6. When the sixth switch S6 is fully turned on, since the power supply voltage VCC applied to the second node N2 can be supplied to the current sensing node CSO even if it is not a short defect, the current sensing signal SA _ CSOC may have the compensation voltage Vcom lower than the power supply voltage VCC, so that the compensation voltage Vcom lower than the power supply voltage VCC is transmitted. Since the ninth switch S9 is turned on, when the compensation voltage Vcom is applied to the current sensing node CSO, the precharge voltage may also be applied to the sensing node SO. Since the fifteenth switch S15 is turned on or off by the voltage applied to the sensing node SO, the positive voltage may be set to a level at which the fifteenth switch S15 may maintain an off state. The current sensing signal SA _ CSOC having the compensation voltage Vcom may be activated only during a predetermined time in the evaluation step S94 and may be deactivated before the evaluation step S94 ends.

When the sensing step S95 starts, the selected word line Sel _ WL may be discharged. When the on-voltage Von is applied to the drain selection line DSL until the sensing step S95 starts, the drain selection line DSL may also be discharged. The SENSE signal SA _ SENSE and the page SENSE signal PBSENSE may transition to logic low L.

Subsequently, when the latch reset signal LRST transitions to the logic high H, the twelfth switch S12 may be turned on, and thus the sensing latch node QS and the sensing node SO may be connected to each other. When the voltage of the sensing node SO is 0V or the compensation voltage Vcom, the fifteenth switch S15 is turned off. Accordingly, even if the twelfth switch S12 is turned on, the data of the sense latch node QS may be maintained as "1". That is, when the test data stored in the sense latch node QS is "1", the controller 1200 of fig. 1 may determine that there is no short defect between the selected word line Sel _ WL and the channel. When the voltage of the sensing node SO is the precharge voltage Vpre, the fifteenth switch S15 is turned on, and thus the data of the sensing latch node QS may be changed from "1" to "0". That is, when the test data stored in the sense latch node QS becomes "0", the controller 1200 of fig. 1 may determine that there is a short defect between the selected word line Sel _ WL and the channel.

Referring to fig. 10, since the test operation according to the second embodiment of the present disclosure is performed similarly to the first embodiment described with reference to fig. 9, a description of the steps repeated with the first embodiment is omitted.

In the test operation according to the second embodiment, the test voltage Vtest may be simultaneously applied to all word lines WL connected to the selected memory block. For example, in the setting step S91 and the discharging step S92, all the word lines WL may be floated or discharged. When the test step S93 starts, the test voltage Vtest may be applied to all the word lines WL.

As in the second embodiment, when the test voltage Vtest is applied to all the word lines WL, the page position where the short defect occurs may not be accurately known, but whether the short defect occurs in the selected memory block may be quickly checked.

Referring to fig. 11, since the test operation according to the third embodiment of the present disclosure is performed similarly to the first embodiment described with reference to fig. 9, a description of the steps repeated with the first embodiment is omitted.

In the test operation according to the third embodiment, it may be checked whether there is a short defect in the region to which the drain select line DSL is connected. For example, when a test operation is performed, all word lines WL may be floated or discharged, and 0V corresponding to an off voltage may be applied to the source selection lines SSL. When the test step S93 starts, the test voltage Vtest or the turn-on voltage Von may be applied to the drain select line DSL, and when the sensing step S95 starts, the drain select line DSL may be discharged.

Additionally, it is also possible to check whether there is a short defect in a region to which the source selection line SSL is connected by applying the third embodiment by applying the test voltage Vtest or the turn-on voltage Von to the source selection line SSL.

As in the third embodiment, by applying the test voltage Vtest to the lines to check whether there is a short defect, even if the lines are not the word lines WL connected to the memory cells, it is possible to check whether there is a short defect for each line.

Fig. 12 is a diagram illustrating the controller 1200 shown in fig. 1.

Referring to fig. 12, the controller 1200 may include a flash translation layer 101, a central processing unit 102, an error correction circuit 103, a defect detector 104, and a system buffer 105. Additionally, the controller 1200 may also include devices that perform various functions.

The flash translation layer 101 may be configured to: logical addresses used in a host and physical addresses used in a memory device are mapped to each other, and the mapped addresses are managed.

The central processing unit 102 may be configured to control the flash translation layer 101, the error correction circuit 103, the defect detector 104, and the system buffer 105 included in the controller 1200. For example, the central processing unit 102 may generate a command for controlling the memory device according to a request of the host, and may perform various operations for managing the memory device. For example, the central processing unit 102 may be configured to output a test command CMD _ T to perform a test operation on the memory device.

The error correction circuit 103 may be configured to: errors in data read from a memory device are detected during a read operation, and the detected errors are corrected.

The defect detector 104 may be configured to: during a test operation of the memory device, test data read from the memory device is received, and it is determined whether the memory device is defective according to the received test data. For example, when "0" data is included in the test data read from the memory device, the defect detector 104 may determine that a short defect exists in the string corresponding to the "0" data.

The system buffer 105 may be configured to store various system data used in the controller 1200. For example, system buffer 105 can store an address mapping table generated by flash translation layer 101 and temporarily store data read from a memory device.

Fig. 13 is a diagram illustrating the memory system 1000 shown in fig. 1, the memory system 1000 including the memory device 1100 and the controller 1200 of the present disclosure. In one embodiment, the memory device 1100 and the controller 1200 may be the memory device 1100 and the controller 1200 discussed above with reference to fig. 1.

Referring to fig. 13, a memory system 1000 may include a memory device 1100 in which data is stored, and a controller 1200 that communicates between the memory device 1100 and a host 2000.

The memory device 1100 may be configured with the memory device 1100 shown in fig. 1.

The memory system 1000 may include a plurality of memory devices 1100, and the memory devices 1100 may be connected to the controller 1200 through at least one channel. For example, a plurality of memory devices 1100 may be connected to one channel, and even in the case where a plurality of channels are connected to the controller 1200, a plurality of memory devices 1100 may be connected to each channel.

The controller 1200 may communicate between the host 2000 and the memory device 1100. The controller 1200 may control the memory device 1100 according to a request of the host 2000, or the controller 1200 may perform a background operation to improve performance of the memory system 1000 even without a request from the host 2000. The host 2000 may generate requests for various operations and output the generated requests to the memory system 1000. For example, the request may include: a program request that may control a program operation, a read request that may control a read operation, an erase request that may control an erase operation, and so on.

The host 2000 may communicate with the memory system 1000 through various interfaces such as peripheral component interconnect express (PCIe), advanced Technology Attachment (ATA), serial ATA (SATA), parallel ATA (PATA), serial Attached SCSI (SAS), non-volatile memory express (NVMe), universal Serial Bus (USB), multi-media card (MMC), enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

Referring to fig. 14, the memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100, a controller 1200, and a card interface 7100.

In one embodiment, the memory device 1100 may be configured with the memory device 1100 shown in FIG. 1. In one embodiment, the controller 1200 may be configured with the controller 1200 shown in fig. 1.

The controller 1200 may control data exchange between the memory device 1100 and the card interface 7100. According to one embodiment, the card interface 7100 may be a Secure Digital (SD) card interface or a multimedia card (MMC) interface, but is not limited thereto.

The card interface 7100 may provide an interface for data exchange between the host 60000 and the controller 1200 according to the protocol of the host 60000. According to one embodiment, the card interface 7100 may support a Universal Serial Bus (USB) protocol and an inter-chip (IC) -USB protocol. Here, the card interface 7100 may refer to hardware, software installed in hardware, or a signal transmission method capable of supporting a protocol used by the host 60000.

When the memory system 70000 is connected to a host interface 6200 of a host 60000, the interface 6200 may perform data communication with the memory device 1100 through the card interface 7100 and the controller 1200 under the control of a microprocessor (μ P) 6100, the host 60000 such as a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone, console video game hardware, or a digital set-top box.

Claims

1. A memory device, comprising:

a memory block connected to a word line and a select line;

bit lines connected to the memory blocks;

a voltage generator configured to generate a test voltage to be applied to a selected line of the word line and the selection line;

a page buffer configured to sense a voltage of the bit line to store and output test data; and

a control logic circuit configured to determine whether a first defect exists in the memory block according to the test data,

wherein the page buffer includes:

a sense latch configured to store test data determined according to a voltage of a sense node during a test operation for detecting the first defect of the memory block;

a sense discharge circuit configured to discharge the sense node; and

a bit line selection circuit configured to block a connection between the sense node and the bit line when the test data is determined according to the voltage of the sense node, and

wherein the test data is held as reset data in the sense latch when the test operation begins and the first defect is not present in the memory block, and the test data is changed when the first defect is present in the memory block.

2. The memory device of claim 1, wherein the voltage generator is configured to generate the test voltage as a positive voltage.

3. The memory device of claim 1, wherein the sense latch is configured to be reset at a beginning of the test operation.

4. The memory device of claim 3, wherein the sense discharge circuit is configured to discharge the sense node when the sense latch is reset.

5. The memory device of claim 1, wherein the bit line selection circuit is configured to: connecting the bit line and the sense node to each other when the sense node is discharged and the test voltage is applied to the selected line, and disconnecting the connection between the bit line and the sense node before the test data is determined according to the voltage of the sense node.

6. The memory device of claim 1, further comprising:

a bit line discharge circuit configured to discharge the bit lines simultaneously when the sense node is discharged.

7. The memory device of claim 1, wherein the selected line is all of the word lines, some of the word lines, a word line selected from the word lines, all of the select lines, some of the select lines, or a select line selected from the select lines.

8. The memory device according to claim 1, wherein the first defect is a short defect in which the selected line and a memory cell or a selection transistor connected to the selected line are electrically connected to each other.

9. The memory device according to claim 8, wherein when the first defect is not present in the memory block is a case where there is no defect in the memory block or there is a second defect different from the first defect.

10. The memory device according to claim 9, wherein the second defect is an open defect in which a part of a channel of a string including the memory cell and the selection transistor is electrically disconnected.

11. A memory system, comprising:

a memory device including a page buffer connected to a memory block through a bit line; and

a controller configured to transmit a test command to the memory device and determine whether the defect exists based on test data output from the memory device during a test operation for detecting a defect of the memory block,

wherein the memory device is configured to: storing initial data in a sense latch of the page buffer in response to the test command; discharging a sense node connected between the bit line and the sense latch; storing the test data in the sense latch according to the voltage of the sense node changed by the test operation; and outputting the test data to the controller, and

the controller is configured to determine that a first defect occurs in the memory block when the test data is different from the initial data.

12. The memory system of claim 11, wherein the memory device is configured to: transmitting a voltage of the bit line changed by the test voltage to the sense node after applying the test voltage to a selected line of a word line and a select line connected to the memory block while the sense node is discharged, and storing the test data in the sense latch according to the voltage of the sense node.

13. The memory system of claim 12, wherein the controller comprises:

a central processing unit configured to generate the test command; and

a defect detector configured to detect the first defect according to the test data.

14. A method of performing a test operation on a memory device, the method comprising:

resetting the sense latch;

discharging a sense node connected between the sense latch and a bit line;

applying a test voltage to a selected line of word lines and select lines in a memory block connected to the bit lines;

transmitting a voltage of the bit line to the sense node; and

storing the test voltage in the sense latch according to the voltage of the sense node.

15. The method of claim 14, wherein resetting the sense latch comprises: storing initial data in the sense latch.

16. The method of claim 14, wherein discharging the sense node comprises: discharging the sense node and the bit line by forming a current path between the sense node and the bit line and a ground terminal.

17. The method of claim 14, wherein applying the test voltage comprises: setting the test voltage applied to the selected line to a positive voltage.

18. The method of claim 14, wherein transmitting the voltage of the bit line to the sense node comprises: increasing the voltage of the bit line when there is a short defect between the selected line and a memory cell or a select transistor connected to the selected line, and maintaining the bit line at a discharge level when there is no short defect between the selected line and the memory cell or the select transistor.

19. The method of claim 16, wherein transmitting the voltage of the bit line to the sense node comprises: blocking the current path.

20. The method of claim 14, wherein storing the test voltage in the sense latch according to the voltage of the sense node comprises: storing test data having the same value as initial data in the sense latch when the voltage of the sense node is maintained at a discharge level, and storing the test data having a value different from that of the initial data in the sense latch when the voltage of the sense node is increased to a positive voltage.