CN115223500A

CN115223500A - Display panel and display device

Info

Publication number: CN115223500A
Application number: CN202210876930.8A
Authority: CN
Inventors: 张蒙蒙; 李玥; 高娅娜; 周星耀
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2022-07-25
Filing date: 2022-07-25
Publication date: 2022-10-21

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel includes a scan line extending in a first direction and a longitudinal reset line extending in a second direction, the first direction and the second direction crossing each other; the display panel includes a display area in which adjacent longitudinal reset lines are disconnected from each other. The invention can improve the display unevenness and the display uniformity.

Description

Display panel and display device

Technical Field

The invention relates to the technical field of display, in particular to a display panel and a display device.

Background

The Organic Light-Emitting Diode (OLED) has the advantages of self-luminescence, fast response time, wide viewing angle, low cost, simple manufacturing process, good resolution, high brightness and the like, and can meet the new requirements of consumers on display products. The current OLED display product has the problem of uneven display, and the visual experience of a user is influenced.

Disclosure of Invention

The embodiment of the invention provides a display panel and a display device, which aim to solve the problem of uneven display in the prior art and improve the display effect.

In a first aspect, an embodiment of the present invention provides a display panel, where the display panel includes scan lines extending in a first direction and longitudinal reset lines extending in a second direction, where the first direction and the second direction cross each other; the display panel includes a display area in which adjacent longitudinal reset lines are disconnected from each other.

In a second aspect, based on the same inventive concept, embodiments of the present invention further provide a display device, including the display panel provided in any embodiment of the present invention.

The display panel and the display device provided by the embodiment of the invention have the following beneficial effects: longitudinal reset lines are provided in the display panel, an extending direction of the longitudinal reset lines and an extending direction of the scan lines cross each other, and adjacent longitudinal reset lines are disconnected from each other in the display area. When the display is driven line by line, in the same time period of driving a line of pixel circuit lines, partial pixel circuits in the line of pixel circuit lines connected with the line of pixel circuit lines are reset through the longitudinal reset line, the number of the pixel circuits reset by one longitudinal reset line is reduced, the voltage drop on the longitudinal reset line is obviously reduced, and the difference of the reset conditions of the pixel circuits connected with the same longitudinal reset line in the line of pixel circuit lines is smaller. And because the longitudinal reset wires are mutually disconnected in the display area, the pixel circuits respectively coupled with the adjacent longitudinal reset wires in one row of pixel circuit rows cannot be mutually influenced when reset is carried out, so that the difference of the reset conditions of the pixel circuits at different positions in the pixel circuit rows is smaller, the brightness difference of the light-emitting devices driven by the pixel circuits at different positions in the pixel circuit rows can be reduced, and the problem of uneven display is solved. In addition, the difference of the reset conditions of the pixel circuits connected with the same longitudinal reset wire in one row of pixel circuit rows is small, the occurrence of insufficient reset of the pixel circuits can be reduced, and dark-state luminescence is avoided.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without inventive labor.

FIG. 1 is a schematic diagram of a pixel circuit in the prior art;

fig. 2 is a schematic view of a display panel according to an embodiment of the invention;

FIG. 3 is a schematic diagram of a pixel circuit in another display panel according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a pixel circuit in another display panel according to an embodiment of the present invention;

FIG. 5 is a schematic view of a portion of another display panel according to an embodiment of the present invention;

FIG. 6 is a partial schematic view of another display panel according to an embodiment of the invention;

FIG. 7 is a partial schematic view of another display panel according to an embodiment of the invention;

FIG. 8 is a partial schematic view of another display panel according to an embodiment of the invention;

FIG. 9 is a partial schematic view of another display panel according to an embodiment of the invention;

FIG. 10 is a schematic view of another display panel according to an embodiment of the present invention;

FIG. 11 is a schematic view of another display panel according to an embodiment of the present invention;

FIG. 12 is a schematic view of another display panel according to an embodiment of the present invention;

FIG. 13 is a schematic view of another display panel according to an embodiment of the present invention;

FIG. 14 is a schematic view of another display panel according to an embodiment of the present invention;

FIG. 15 is a schematic view of another display panel according to an embodiment of the present invention;

FIG. 16 is a schematic view of another display panel according to an embodiment of the present invention;

FIG. 17 isbase:Sub>A schematic cross-sectional view taken at line A-A' of FIG. 10;

FIG. 18 is a schematic view of another display panel according to an embodiment of the present invention;

FIG. 19 is a schematic cross-sectional view taken at line B-B' of FIG. 18;

FIG. 20 is a schematic view of another display panel according to an embodiment of the present invention;

FIG. 21 is a schematic cross-sectional view taken at the location of line C-C' of FIG. 20;

FIG. 22 is a schematic view of another display panel according to an embodiment of the present invention;

FIG. 23 is a schematic view of another display panel according to an embodiment of the present invention;

FIG. 24 is a schematic view of another display panel according to an embodiment of the present invention;

fig. 25 is a schematic view of a display device according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

In the OLED display technology, the OLED device is driven by current, and a pixel circuit is disposed in the display panel to supply a driving current to the OLED. Fig. 1 is a schematic diagram of a pixel circuit in the prior art, and as shown in fig. 1, the pixel circuit at least includes a driving module 01, a data writing module 02, and a first resetting module 03. The working period of the pixel circuit at least comprises a reset phase, a data writing phase and a light-emitting phase. In the reset stage, the first reset module 03 starts to reset the driving module 01; in the data writing stage, the data writing module 02 starts to write data voltage into the driving module 01; in the light emitting stage, the driving module 01 generates a driving current and supplies the driving current to the light emitting device 04.

The inventor analyzes the reason that the display panel has uneven display based on the working process of the pixel circuit, and considers that the reset condition of the reset stage to the driving module 01 affects the magnitude of the driving current in the subsequent light-emitting stage, and further affects the brightness of the light-emitting device 04. When there is a difference in the reset condition of the pixel circuit in the display panel, a difference in luminance of the light emitting device 04 is caused, causing a problem of display unevenness.

In some display panels, the pixel circuit further includes a second reset module, the second reset module is coupled to the light emitting device 04, the second reset module is configured to reset the electrode of the light emitting device 04, and the resetting of the electrode of the light emitting device 04 may also affect the light emitting condition of the light emitting device 04. When there is a difference in the reset condition of the pixel circuit in the display panel, the brightness difference of the light emitting device 04 is also caused, which causes the problem of uneven display.

In addition, the pixel circuit may cause inaccurate light emission luminance of the pixel when reset is insufficient. Particularly, when a low gray level dark state is displayed, there may be a problem of dark state light emission, which not only causes uneven display but also causes a decrease in contrast.

The display panel is provided with a plurality of pixel circuit rows, a plurality of reset lines and a plurality of scanning lines, the extension directions of the reset lines and the scanning lines are the same, one reset line is coupled with the plurality of pixel circuits in one pixel circuit row, and one scanning line is coupled with the plurality of pixel circuits in one pixel circuit row. Wherein the reset line is used for providing a reset signal to the pixel circuit. In the prior art, a display panel displays by driving a row by row, and in the same time period for driving a row of pixel circuit rows to work, one reset line provides a reset signal to all the pixel circuits in the row of pixel circuit rows. Since the reset line needs to be connected to all the pixel circuits in a row of pixel circuit rows, the length of the reset line is long and the voltage drop is large. However, the reset signal on the reset line is usually transmitted from two ends of the line to the middle, or the reset signal is transmitted from one end of the reset line to the other end, and due to the existence of the voltage drop, the reset conditions of the pixel circuits at the positions of the near end and the far end of the pixel circuit row from the reset signal input end are different, so that the brightness difference exists between the pixels driven by the pixel circuits at different positions in the pixel circuit row, and the display is not uniform. In addition, the pixel circuit may have a problem of insufficient reset at a position far from the reset signal input terminal, resulting in dark state light emission.

For large-sized products, the length of the reset line is relatively longer, and the display unevenness caused by different reset conditions of the reset line on the pixel circuits at different positions in the pixel circuit row is more serious. In the case of high frequency display products, the row driving time is shortened due to high frequency display, and the reset time is shortened, which also aggravates display unevenness caused by different pixel circuit reset conditions at different positions in the pixel circuit row.

In order to solve the problems in the prior art, embodiments of the present invention provide a display panel, in which a wiring manner of reset lines in a display area is designed, reset lines originally extending in a transverse direction are changed to extend in a longitudinal direction, and the reset lines extending in the longitudinal direction are not connected in the display area. In the case of displaying by driving row by row, the pixel circuits connected thereto are reset by the vertical reset line, rather than all the pixel circuits in one row of pixel circuit row being reset by one reset line extending in the lateral direction, in the same period of driving one row of pixel circuit row. In the same period, the number of the pixel circuits reset by one longitudinal reset line is less, so that the voltage drop on the longitudinal reset line is obviously reduced, and the difference of the reset conditions of the pixel circuits connected with the same longitudinal reset line in one row of pixel circuit rows is smaller, so that the problem of uneven display can be solved.

Fig. 2 is a schematic view of a display panel according to an embodiment of the present invention, and as shown in fig. 2, the display panel includes a display area AA and a non-display area NA. The display panel comprises a plurality of pixel circuits 10, wherein the pixel circuits 10 are arranged in an array, the pixel circuits 10 are arranged in a pixel circuit row 10H along a first direction x, the pixel circuits 10 are arranged in a pixel circuit column 10L along a second direction y, and the first direction x and the second direction y are mutually crossed; the first direction x may be considered to be the transverse direction and the second direction y may be considered to be the longitudinal direction. The pixel circuit 10 is merely illustrated as a block diagram, and the structure of the pixel circuit 10 will be illustrated in the following specific embodiment.

The display area AA of the display panel further includes light emitting devices, and one pixel circuit 10 is coupled to at least one of the light emitting devices, and the pixel circuit 10 is used for driving the light emitting device to emit light. The light emitting device may be an organic light emitting device or an inorganic light emitting device.

The display panel includes scan lines 20 extending in a first direction x and longitudinal reset lines 30 extending in a second direction y. The longitudinal reset lines 30 and the scan lines 20 are insulatively crossed. A row of pixel circuit rows 10H connects the same scan line 20, that is, the scan line 20 drives a plurality of pixel circuits 10 in a row of pixel circuit rows 10H.

Adjacent longitudinal reset lines 30 are disconnected from each other within the display area AA. In the present invention, "disconnected from each other" means not connected. The adjacent longitudinal reset lines 30 in the display area AA are disconnected from each other, which shows that the display panel includes at least two longitudinal reset lines 30, and the adjacent longitudinal reset lines 30 are not connected in the display area AA. Adjacent longitudinal reset lines 30 are not electrically connected in the display area AA. A row of pixel circuit rows 10H in embodiments of the present invention is commonly driven by at least two longitudinal reset lines 30.

In fig. 2, one vertical reset line 30 is illustrated to electrically connect three pixel circuit columns 10L, and for one row of pixel circuit rows 10H, one vertical reset line 30 connects three pixel circuits 10 in one row of pixel circuit rows 10H. In the embodiment of the present invention, the number of the pixel circuits 10 in the same row of the pixel circuit row 10H connected to one vertical reset line 30 is not specifically limited. The different schemes will be explained in detail in the following specific examples.

In the prior art, during the same period of driving a row of pixel circuit rows, all the pixel circuits in the row of pixel circuit rows are reset by using a transversely extending reset line, and when a reset signal is written into the pixel circuits by the reset line, a reset current is generated on the reset line, and the reset current causes a voltage drop of the reset signal. This causes the reset lines extending laterally to reset the pixel circuits at different positions in the row of pixel circuits differently, resulting in non-uniform display.

The display panel provided by the embodiment of the invention is provided with the longitudinal reset lines 30, the extending direction of the longitudinal reset lines 30 and the extending direction of the scanning lines 20 are mutually crossed, and the adjacent longitudinal reset lines 30 are mutually disconnected in the display area AA. A row of pixel circuit rows 10H is driven by one scanning line 20, and a row of pixel circuit rows 10H is commonly driven by at least two longitudinal reset lines 30. When the display is performed by driving row by row, in the same period of driving a row of pixel circuit rows 10H, the longitudinal reset lines 30 reset some of the pixel circuits 10 in the row of pixel circuit rows 10H connected thereto, while the number of the pixel circuits 10 reset by one longitudinal reset line 30 is reduced, the voltage drop on the longitudinal reset line 30 is significantly reduced, and the difference in the reset conditions of the pixel circuits 10 connected to the same longitudinal reset line 30 in one row of pixel circuit rows 10H is small. Moreover, the longitudinal reset lines 30 are disconnected from each other in the display area AA, so that the pixel circuits 10 respectively coupled to the adjacent longitudinal reset lines 30 in one pixel circuit row 10H do not affect each other when being reset, and the difference in the reset conditions of the pixel circuits 10 at different positions in the pixel circuit row 10H is small, thereby reducing the difference in the brightness of the light emitting devices driven by the pixel circuits 10 at different positions in the pixel circuit row 10H and improving the problem of uneven display. In addition, the difference in the reset conditions of the pixel circuits 10 connected to the same vertical reset line 30 in the pixel circuit row 10H in one row is small, and the occurrence of insufficient reset of the pixel circuits 10 can be reduced, thereby preventing dark-state light emission.

In some embodiments, fig. 3 is a schematic diagram of a pixel circuit in another display panel according to an embodiment of the present invention. As shown in fig. 3, the pixel circuit includes a driving transistor Tm, a data writing transistor T1, a threshold compensating transistor T2, a first reset transistor T3, a first light emission controlling transistor T4, a second light emission controlling transistor T5, and a storage capacitor Cst. The gate of the driving transistor Tm is connected to the first node N1, the first pole of the driving transistor Tm is connected to the second node N2, and the second pole of the driving transistor Tm is connected to the third node N3. The driving transistor Tm is connected in series between the first light-emitting control transistor T4 and the second light-emitting control transistor T5, gates of the first light-emitting control transistor T4 and the second light-emitting control transistor T5 both receive the light-emitting control signal E, one pole of the first light-emitting control transistor T4 receives the positive power supply signal Pvdd and the other pole is connected to the second node N2, one pole of the second light-emitting control transistor T5 is connected to the third node N3, the other pole is connected to the first electrode of the light-emitting device P, and the second electrode of the light-emitting device P receives the negative power supply signal Pvee. Optionally, the first electrode of the light emitting device P is an anode, and the second electrode is a cathode. The gate of the data writing transistor T1 and the gate of the threshold compensation transistor T2 receive the first scan signal Sc1, one pole of the data writing transistor T1 receives the data signal Vdata, the other pole is connected to the second node N2, and the threshold compensation transistor T2 is connected in series between the first node N1 and the third node N3. The gate of the first reset transistor T3 receives the second scan signal Sc2, one pole of the first reset transistor T3 receives the reset signal Ref, and the other pole is connected to the first node N1.

In some embodiments, the display panel includes a pixel circuit as shown in fig. 3, the first reset transistor T3 is connected to the vertical reset line 30, and the vertical reset line 30 provides the reset signal Ref to the pixel circuit 10.

In other embodiments, fig. 4 is a schematic diagram of a pixel circuit in another display panel according to an embodiment of the present disclosure. Compared with the embodiment of fig. 3, the embodiment of fig. 4 further includes a second reset transistor T6, a gate of the second reset transistor T6 receives the second scan signal Sc2, one pole of the second reset transistor T6 receives the second reset signal Ref2, the other pole is connected to the fourth node N4, and the light emitting device P is connected to the fourth node N4. One pole of the first reset transistor T3 receives the first reset signal Ref1. In this embodiment, the first reset transistor T3 and the second reset transistor T6 each receive a reset signal.

In the embodiments of fig. 3 and 4, the transistors are illustrated as p-type transistors, and optionally, the transistors in the pixel circuit may also be n-type transistors.

In one embodiment, in the circuit diagram of fig. 4, the first reset signal Ref1 and the second reset signal Ref2 are the same signal, and the first reset transistor T3 and the second reset transistor T6 are both connected to the vertical reset line 30. That is, a first pole of the first reset transistor T3 is electrically connected to the gate of the driving transistor Tm, and a second pole of the first reset transistor T3 is electrically connected to the longitudinal reset line 30; a first pole of the second reset transistor T6 is electrically connected to the anode of the light emitting device P, and a second pole of the second reset transistor T6 is electrically connected to the longitudinal reset wire 30.

In another embodiment, the voltage values of the first reset signal Ref1 and the second reset signal Ref2 in the circuit diagram of fig. 4 are different. The first reset transistor T3 is coupled to one of the longitudinal reset lines 30, the second reset transistor T6 is coupled to a row reset line extending in the first direction x, and the row reset line is coupled to all of the pixel circuits 10 in one of the pixel circuit rows 10H. In this embodiment, the longitudinal reset lines 30 provide a first reset signal Ref1 and the row reset lines provide a second reset signal Ref2.

In another embodiment, the voltage values of the first reset signal Ref1 and the second reset signal Ref2 in the circuit diagram of fig. 4 are different. The second reset transistor T6 is first coupled to one of the longitudinal reset lines 30, the first reset transistor T3 is coupled to a row reset line extending along the first direction x, and the row reset line is coupled to all of the pixel circuits 10 in one of the pixel circuit rows 10H. In this embodiment, the longitudinal reset lines 30 provide the second reset signal Ref2, and the row reset lines provide the first reset signal Ref1.

In another embodiment, the voltage values of the first reset signal Ref1 and the second reset signal Ref2 are different. The display panel includes a first reset line providing a first reset signal Ref1 and a second reset line providing a second reset signal Ref2, the first reset transistor T3 is coupled to the first reset line, and the second reset transistor T6 is coupled to the second reset line. The same pixel circuit 10 electrically connects two longitudinal reset lines 30, wherein the first reset line includes one of the two longitudinal reset lines 30, and the second reset line includes the other of the two longitudinal reset lines 30.

In some embodiments, as shown in FIG. 2, the longitudinal reset wires 30 include a first longitudinal reset wire 31. The display panel includes lateral reset lines 40 extending in a first direction x, one lateral reset line 40 being coupled to one first longitudinal reset line 31; one of the horizontal reset lines 40 is coupled to at least two pixel circuits 10 in one row of the pixel circuit row 10H, and the number of the pixel circuits 10 in the same row of the pixel circuit row 10H coupled to the same horizontal reset line 40 is smaller than the total number of the pixel circuits 10 in the pixel circuit row 10H. One lateral reset line 40 is illustrated in fig. 2 coupled to three pixel circuits 10. In the embodiment of the present invention, the transverse reset line 40 is provided and coupled to the first longitudinal reset line 31, the extending direction of the transverse reset line 40 is the same as the extending direction of the scan line 20, the transverse reset line 40 is provided so that the first longitudinal reset line 31 can be coupled to at least two pixel circuits 10 in a row of pixel circuit rows 10H, and the number of pixel circuits 10 belonging to the same row of pixel circuit row 10H to which the first longitudinal reset line 31 is coupled is smaller than the total number of pixel circuits 10 of the pixel circuit row 10H. In the same period of driving a row of pixel circuit rows 10H, a first longitudinal reset line 31 is used to reset some of the pixel circuits 10 in the row of pixel circuit rows 10H connected to the first longitudinal reset line 31, and if the number of the pixel circuits 10 reset by one first longitudinal reset line 31 is small, the voltage drop on the first longitudinal reset line 31 is obviously reduced, and the difference in the reset conditions of the pixel circuits 10 connected to the same first longitudinal reset line 31 in one row of pixel circuit rows 10H is small. The pixel circuit row 10H is driven by at least two longitudinal reset lines 30, so that the difference of the reset conditions of the pixel circuits 10 at different positions in the pixel circuit row 10H is small, the brightness difference of the light emitting devices driven by the pixel circuits 10 at different positions in the pixel circuit row 10H can be reduced, and the problem of uneven display can be solved.

In addition, a transverse reset wire 40 is provided to be coupled with a first longitudinal reset wire 31; and a horizontal reset line 40 is coupled to at least two pixel circuits 10 in a row of pixel circuit rows 10H, which can reduce the number of vertical reset lines 30, save the wiring space in the first direction x, increase the number of pixel circuits 10 arranged in the first direction x, and accordingly increase the number of pixels arranged in a unit area. In some embodiments, when the number of pixels arranged in a unit area is not changed, the arrangement manner of the first vertical reset lines 31 and the horizontal reset lines 40 in the present invention can reduce the number of the vertical reset lines 30, and improve the light transmittance of the display panel to a certain extent.

It should be noted that in fig. 2, the transverse reset line 40 overlaps the pixel circuit 10 to indicate that the transverse reset line 40 is electrically connected to the pixel circuit 10, and the black solid circle at the crossing position of the transverse reset line 40 and the first longitudinal reset line 31 indicates that the transverse reset line 40 is electrically connected to the first longitudinal reset line 31. In the following examples, reference may be made to the following for understanding without specific description.

In some embodiments, fig. 5 is a partial schematic view of another display panel provided by the embodiment of the present invention, and for clarity, the arrangement of the longitudinal reset lines 30 and the transverse reset lines 40 is not shown in fig. 5. As shown in FIG. 5, the first longitudinal reset wire 31 includes a first sub-longitudinal reset wire 31a; the transverse reset line 40 includes a first transverse reset line 41, the first transverse reset line 41 is coupled to the first sub-longitudinal reset line 31a, and the first transverse reset line 41 is disconnected from the longitudinal reset line 30 adjacent to the first sub-longitudinal reset line 31a in the display area AA. The first lateral reset line 41 is disposed such that the first sub-longitudinal reset line 31a is coupled to at least two pixel circuits 10 in one row of pixel circuits 10H, and the first sub-longitudinal reset line 31a and the longitudinal reset line 30 adjacent thereto are not electrically connected within the display area AA. In the same period of driving a row of pixel circuit rows 10H, the first sub-vertical reset line 31a resets a part of the pixel circuits 10 in the row of pixel circuit rows 10H connected thereto, and the number of the pixel circuits 10 reset by the first sub-vertical reset line 31a is smaller, so that the voltage drop on the first sub-vertical reset line 31a is significantly reduced, and the difference in the reset condition of the pixel circuits 10 connected to the first sub-vertical reset line 31a in the row of pixel circuits 10H is smaller. The brightness difference of the light emitting devices driven by the pixel circuits 10 at different positions in the pixel circuit row 10H can be reduced, and the problem of uneven display can be solved.

As shown in FIG. 5, the first longitudinal reset wire 31 further includes a second sub-longitudinal reset wire 31b adjacent to the first sub-longitudinal reset wire 31 a. The lateral reset line 40 includes a second lateral reset line 42, the second lateral reset line 42 being coupled to the second sub-longitudinal reset line 31 b; the first and second horizontal reset lines 41 and 42 are respectively coupled to different pixel circuits 10 in the same row of pixel circuits 10H, and the second and first horizontal reset lines 42 and 41 are disconnected in the display area AA. That is, the second lateral reset line 42 and the first lateral reset line 41 are not connected in the display area AA, so that the first sub-longitudinal reset line 31a and the second sub-longitudinal reset line 31b are not connected in the display area AA. In this embodiment, in the same period of driving one row of the pixel circuit row 10H, the first sub-longitudinal reset line 31a and the second sub-longitudinal reset line 31b respectively reset the pixel circuits 10 connected thereto, and the reset conditions of the pixel circuits 10 by the first sub-longitudinal reset line 31a and the second sub-longitudinal reset line 31b do not affect each other. And the voltage drop on the first sub-longitudinal reset line 31a and the second sub-longitudinal reset line 31b are both significantly reduced, the difference in the reset conditions of the pixel circuits 10 connected to the first sub-longitudinal reset line 31a in one row of the pixel circuit row 10H is small, and the difference in the reset conditions of the pixel circuits 10 connected to the second sub-longitudinal reset line 31b in one row of the pixel circuit row 10H is small, so that the difference in the reset conditions between the pixel circuits 10 connected to the first sub-longitudinal reset line 31a and the pixel circuits 10 connected to the second sub-longitudinal reset line 31b is also small. The embodiment of the invention can reduce the brightness difference of the light-emitting devices driven by the pixel circuits 10 at different positions in the pixel circuit row 10H, and improve the problem of uneven display.

In other embodiments, fig. 6 is a partial schematic view of another display panel according to an embodiment of the present invention, and for clarity, the arrangement of the longitudinal reset lines 30 and the transverse reset lines 40 is not shown in fig. 6. As shown in FIG. 6, the first longitudinal reset line 31 includes a first sub-longitudinal reset line 31a, and the first lateral reset line 41 is coupled to the first sub-longitudinal reset line 31 a. The vertical reset lines 30 include second vertical reset lines 32, and one second vertical reset line 32 is coupled to one pixel circuit 10 in one row of pixel circuits 10H. The first sub-longitudinal reset line 31a is adjacent to the second longitudinal reset line 32, and the first transverse reset line 41 is disconnected from the second longitudinal reset line 32 in the display area AA. In the same period of driving a row of pixel circuit rows 10H, the first sub-longitudinal reset line 31a resets the pixel circuit 10 connected thereto, the second longitudinal reset line 32 resets the pixel circuit 10 connected thereto, the reset conditions of the pixel circuit 10 by the first sub-longitudinal reset line 31a and the second longitudinal reset line 32 do not affect each other, and the voltage drops on the first sub-longitudinal reset line 31a and the second longitudinal reset line 32 are both significantly reduced, so that the difference in the reset conditions of the pixel circuit 10 connected to the first sub-longitudinal reset line 31a in the row of pixel circuit rows 10H is small, and the difference in the reset conditions of the pixel circuit 10 connected to the first sub-longitudinal reset line 31a and the pixel circuit 10 connected to the second longitudinal reset line 32 is also small. This embodiment can reduce the luminance difference of the light emitting devices driven by the pixel circuits 10 at different positions in the pixel circuit row 10H, and improve the problem of display unevenness.

The illustrated longitudinal reset wire 30 of the embodiment of FIG. 6 includes a first longitudinal reset wire 31 and a second longitudinal reset wire 32. The arrangement of the first longitudinal reset wire 31 and the second longitudinal reset wire 32 in the first direction x is not limited in the embodiment of the present invention.

In some embodiments, as shown in fig. 5, the pixel circuits 10 coupled to the first lateral reset lines 41 are sequentially arranged in the first direction x, and the pixel circuits 10 coupled to the second lateral reset lines 42 are sequentially arranged in the first direction x. The first horizontal reset line 41 is coupled to at least two pixel circuits 10 sequentially arranged in a row of pixel circuit rows 10H, and the second horizontal reset line 42 is coupled to at least two pixel circuits 10 sequentially arranged in a row of pixel circuit rows 10H. The embodiment can ensure that the length of the transverse reset line 40 is shortest under the condition that the number of the pixel circuits 10 coupled with the transverse reset line 40 is determined, which is beneficial to reducing the impedance on the transverse reset line 40, and can also reduce the voltage drop of the reset signal on the first longitudinal reset line 31 coupled with the transverse reset line 40, thereby reducing the reset difference between the pixel circuits 10 coupled with one first longitudinal reset line 31 in the same row of pixel circuit rows 10H and improving the problem of uneven display.

In another embodiment, fig. 7 is a partial schematic view of another display panel according to an embodiment of the present invention, and for clearly illustrating a connection relationship between the lateral reset line 40 and the pixel circuit 10, in fig. 7, the lateral reset line 40 overlaps the pixel circuit 10 and has a black solid dot to indicate that the lateral reset line 40 is electrically connected to the pixel circuit 10. As shown in fig. 7, at least one pixel circuit 10 coupled to the first lateral reset line 41 is located between two pixel circuits 10 coupled to the second lateral reset line 42. That is, the pixel circuits 10 connected to the adjacent first and second

sub-vertical reset lines

31a and 31b, respectively, in the same row of the pixel circuit row 10H are alternately arranged. By adopting the design of the embodiment of the present invention, when driving a row of pixel circuit rows 10H, the difference in the reset conditions of the pixel circuits 10 coupled to the first horizontal reset line 41 is substantially the same, the difference in the reset conditions of the pixel circuits 10 coupled to the second horizontal reset line 42 is substantially the same, and the pixel circuits 10 connected to the first sub-vertical reset line 31a and the second sub-vertical reset line 31b adjacent to each other in the pixel circuit row 10H are arranged alternately, so that the reset difference between the plurality of pixel circuits 10 arranged in sequence can be reduced, and the problem of display unevenness can be improved.

In some embodiments, as shown in FIG. 5, the connection point of first longitudinal reset wire 31 and lateral reset wire 40 is first connection point W1; the first connection point W1 is a solid black dot at the crossing position of the first longitudinal reset wire 31 and the lateral reset wire 40 illustrated in fig. 5. The first connection point W1 is a physical connection point of the first longitudinal reset wire 31 and the lateral reset wire 40. The first connection point W1 is also labeled again in the following embodiments relating to circuit layouts. In the embodiment of the present invention, the difference between the numbers of the pixel circuits 10 coupled to the lateral reset line 40 and located on the two sides of the first connection point W1 in the first direction x is less than or equal to a first preset number. When driving one row of pixel circuit rows 10H, the reset signal transmitted from the first vertical reset line 31 is transmitted to the lateral reset line 40 via the first connection point W1, and then the reset signal is transmitted from the first connection line W1 to both left and right ends of the lateral reset line 40 in the first direction x. In the embodiment of the present invention, the difference between the numbers of the pixel circuits 10 coupled to the same horizontal reset line 40 on both sides of the first connection point W1 is limited, so that the difference between the numbers of the pixel circuits 10 coupled to the same horizontal reset line 40 on both sides of the first connection point W1 is not too large, and the difference between the reset conditions of the pixel circuits 10 coupled to the same horizontal reset line 40 on both sides of the first connection point W1 is small, thereby reducing the reset difference between the plurality of pixel circuits 10 coupled to the same first vertical reset line 31 in a row of pixel circuit rows 10H and improving the display unevenness.

Fig. 5 shows that, for the pixel circuits 10 coupled to the same lateral reset line 40, the number of the pixel circuits 10 located on the left side of the first connection point W1 in the first direction x is 1, the number of the pixel circuits 10 located on the right side of the first connection point W1 in the first direction x is 1, and the difference between the numbers of the pixel circuits 10 located on both sides of the first connection point W1 is 0.

In some embodiments, the first predetermined number is 2. That is, the difference in the number of pixel circuits 10 coupled to the lateral reset line 40 and located on the left and right sides of the first connection point W1 is at most 2. The difference between the number of the pixel circuits 10 coupled to the same lateral reset line 40 on both sides of the first connection point W1 is set to be small, so that the reset conditions of the pixel circuits 10 coupled to the same lateral reset line 40 on both sides of the first connection point W1 are substantially the same, the reset difference between the pixel circuits 10 coupled to the same longitudinal reset line 31 in one row of the pixel circuit row 10H can be reduced, and the display unevenness can be improved.

Fig. 5 illustrates that the first vertical reset line 31 overlaps the pixel circuit 10, and the first bit point W1 overlaps one pixel circuit 10, where the overlap of the first bit point W1 and the pixel circuit 10 in the embodiment of the present invention means that the area region enclosed by the first bit point W1 and each transistor in the pixel circuit 10 is overlapped. The pixel circuit 10 overlapping the first bit point W1 at this time does not participate in the calculation of the quantity difference.

In other embodiments, the first connection point W1 does not overlap the pixel circuits 10, and the first connection point W1 is located between adjacent pixel circuits 10.

In another embodiment, fig. 8 is a partial schematic view of another display panel according to an embodiment of the present invention, and as shown in fig. 8, a connection point of the first longitudinal reset wire 31 and the transverse reset wire 40 is a first connection point W1; the first connection point W1 is located between two pixel circuits 10 coupled to the same lateral reset line 40. The horizontal reset line 40 is coupled to the four pixel circuits 10, and the difference between the numbers of the pixel circuits 10 coupled to the horizontal reset line 40 and located at the left and right sides of the first connection point W1 is 0.

In another embodiment, fig. 9 is a partial schematic view of another display panel according to an embodiment of the present invention, and as shown in fig. 9, a connection point of the first longitudinal reset wire 31 and the transverse reset wire 40 is a first connection point W1; the first connection point W1 overlaps the pixel circuit 10. In fig. 9, it is illustrated that the lateral reset line 40 is coupled to four pixel circuits 10 in a row of pixel circuit rows 10H, the number of the pixel circuits 10 located at the left side of the first connection point W1 in the first direction x is 2, the number of the pixel circuits 10 located at the right side of the first connection point W1 in the first direction x is 1, and the difference between the numbers of the pixel circuits 10 located at the two sides of the first connection point W1 is 1.

In some embodiments, fig. 10 is a schematic view of another display panel according to an embodiment of the present invention, and fig. 10 illustrates three pixel circuits 10 arranged in sequence in a row of pixel circuit rows 10H. The connection relationship of the transistors in the pixel circuit 10 can be understood with reference to the embodiment of fig. 4 described above. As shown in fig. 10, the display panel includes a data line 21 and a power line 22 extending in the second direction y, the data line 21 for supplying the data signal Vdata to the pixel circuit 10, and the power line 22 for supplying the positive power signal Pvdd to the pixel circuit 10. The display panel further comprises a light emission control line 23 extending in the first direction x, the light emission control line 23 being adapted to provide a light emission control signal E to the pixel circuit 10. The scan lines 20 extending in the first direction x include a first scan line and a second scan line. Fig. 10 shows that the first scanning line 20a _p, the second scanning line 20b _p, and the second scanning line 20b _p-1,p are positive integers. Illustrated in fig. 10 is the pixel circuit 10 located in the p-th pixel circuit row 10H. The first scanning line 20a _pis coupled to the data writing transistor T1 of the pixel circuit 10 of the p-th pixel circuit row 10H, the second scanning line 20b _pis coupled to the second reset transistor T6 of the pixel circuit 10 of the p-th pixel circuit row 10H, and the first reset transistor T3 of the pixel circuit 10 of the p-th pixel circuit row 10H is coupled to the second scanning line 20b _p-1. This embodiment is different from the circuit of fig. 4 in that the first reset transistor T3 and the second reset transistor T6 belonging to the same pixel circuit 10 receive different scan signals, wherein the first reset transistor T3 of the pixel circuit 10 of the p-th pixel circuit row 10H and the second reset transistor T6 of the pixel circuit 10 of the p-1 th pixel circuit row 10H are controlled by the same second scan line 20b _p-1, and it can be understood that the second reset transistor T6 of the pixel circuit 10 of the p-th pixel circuit row 10H and the first reset transistor T3 of the pixel circuit 10 of the p +1 th pixel circuit row 10H are controlled by the same second scan line 20b _p.

Fig. 10 is a schematic top view of a display panel including a substrate, it being understood that the top view is parallel to a direction perpendicular to a plane of the substrate. As can be seen from fig. 10, at least one first longitudinal reset line 31 and the data line 21 at least partially overlap in a direction perpendicular to the plane of the substrate. The arrangement is such that the first longitudinal reset line 31 and the data line 21 overlap to form a capacitance, and the parasitic capacitance on the first longitudinal reset line 31 can be increased. When the parasitic capacitance on the first longitudinal reset line 31 is large, when the gate of the driving transistor Tm is reset by the reset signal provided by the first longitudinal reset line 31 (that is, when the first node N1 in the pixel circuit is reset, the storage capacitor Cst in the pixel circuit is connected to the first node N1), which is equivalent to charging the small capacitor in the pixel circuit by the large capacitor on the first longitudinal reset line 31, there is almost no current in the first longitudinal reset line 31 and almost no voltage drop on the first longitudinal reset line 31, so that the reset condition of the pixel circuit 10 coupled to the first longitudinal reset line 31 is almost the same, and the display unevenness can be improved. The first vertical reset line 31 in this embodiment can sufficiently reset the pixel circuit 10 coupled thereto, and there is no problem of dark state caused by insufficient reset.

In addition, fig. 10 illustrates a first connecting point W1 at which the first longitudinal reset wire 31 and the lateral reset wire 40 are cross-connected. In this embodiment, the first connection point W1 is located between two adjacent pixel circuits 10, the difference between the numbers of the pixel circuits 10 coupled to the same lateral reset line 40 and located on two sides of the first connection point W1 in the first direction x is 1.

In another embodiment, fig. 11 is a schematic view of another display panel according to an embodiment of the present invention, and the pixel circuit structure and the signal line in fig. 11 can be understood with reference to fig. 10. As shown in fig. 11, at least one of the first longitudinal reset lines 31 and the power supply line 22 at least partially overlap in a direction perpendicular to the plane of the substrate. The arrangement is such that the first longitudinal reset line 31 and the power supply line 22 overlap to form a capacitance, thereby increasing the parasitic capacitance on the first longitudinal reset line 31. When the parasitic capacitance on the first longitudinal reset line 31 is large, the gate of the driving transistor Tm is reset by the reset signal provided by the first longitudinal reset line 31, and therefore, equivalently, the small capacitance in the pixel circuit is charged by the large capacitance on the first longitudinal reset line 31, the first longitudinal reset line 31 has almost no current and almost no voltage drop on the first longitudinal reset line 31, so that the reset conditions of the pixel circuits 10 coupled with the first longitudinal reset line 31 can be the same, the display unevenness can be improved, and the problem of dark state caused by incomplete reset can be avoided.

In addition, fig. 11 illustrates a first connecting point W1 at which the first longitudinal reset wire 31 and the lateral reset wire 40 are cross-connected. The first longitudinal reset line 31 overlaps the 2 nd pixel circuit 10 located in the middle of the 3 pixel circuits 10, and the first longitudinal reset line 31 overlaps the power supply line 22 driving the 2 nd pixel circuit 10. In the embodiment of fig. 11, the difference between the numbers of the pixel circuits 10 coupled to the same lateral reset line 40 and located on both sides of the first connection point W1 in the first direction x is 0.

In some embodiments, at least one lateral reset line 40 is coupled to n pixel circuits 10, n being an odd number greater than 1; n pixel circuits 10 are arranged in the first direction x; that is, the n pixel circuits 10 coupled to the same lateral reset line 40 are located in the same row of pixel circuits 10H. At least one first longitudinal reset line 31 and (n + 1)/2 th pixel circuits 10 of the n pixel circuits 10 at least partially overlap in a direction perpendicular to a plane of the substrate. As shown in fig. 11, n =3, the first longitudinal reset line 31 overlaps the 2 nd pixel circuit 10 among the 3 pixel circuits 10 arranged in the first direction x.

In another embodiment, fig. 12 is a schematic diagram of another display panel according to an embodiment of the present invention, and as shown in fig. 12, a horizontal reset line 40 is coupled to 3 pixel circuits 10 arranged in the first direction x, and a first vertical reset line 31 overlaps with a2 nd pixel circuit 10 of the 3 pixel circuits 10 arranged in the first direction x. Fig. 12 illustrates that the routing direction of the first longitudinal reset line 31 is the second direction y, and the first longitudinal reset line 31 may be a broken line at a local position, so that a structure manufactured in the same layer as the first longitudinal reset line 31 in the pixel circuit 10 can be avoided. For example, in some embodiments, the connection electrode of the pixel circuit connected to the anode of the light emitting device is located at the same layer as the first longitudinal reset line 31, and the first longitudinal reset line 31 is arranged as a broken line at a local position, so that the first longitudinal reset line 31 and the connection electrode are prevented from being short-circuited.

The horizontal reset line 40 is coupled to the odd-numbered pixel circuits 10 arranged in the first direction x in the embodiment of the present invention, and the first vertical reset line 31 is disposed to overlap the pixel circuit 10 located at the middle position among the odd-numbered pixel circuits 10. When driving one row of pixel circuit rows 10H, the reset signal supplied from the first longitudinal reset line 31 is transmitted to both sides of the first longitudinal reset line 31 in the first direction x through the lateral reset line 40. When the first longitudinal reset line 31 is substantially located in the middle of the odd-numbered pixel circuits 10, the distances from the reset signals to the left and right sides of the first longitudinal reset line 31 are substantially the same, so that the reset signals received by the pixel circuits 10 on the two sides of the first longitudinal reset line 31 in the first direction x are substantially the same, and the reset conditions of the pixel circuits 10 on the two sides of the first longitudinal reset line 31 in the first direction x are substantially the same, thereby further improving the problem of display unevenness and improving the display uniformity.

Fig. 11 and 12 are both illustrated with n =3, and in one embodiment, n =5, the first longitudinal reset line 31 is arranged to overlap the 3 rd pixel circuit 10 of the 5 pixel circuits 10 arranged in the first direction x. In one embodiment, n =7, the first longitudinal reset line 31 is disposed to overlap the 7 th pixel circuit 10 of the 7 pixel circuits 10 arranged in the first direction x.

In some embodiments, fig. 13 is a schematic view of another display panel according to an embodiment of the present invention, as shown in fig. 13, the display panel includes a first light emitting device P1, a second light emitting device P2, and a third light emitting device P3 with different emission colors, and only the position of the anode of each light emitting device is illustrated in fig. 13. The pixel circuits 10 in the pixel circuit row include a first pixel circuit 10-1, a second pixel circuit 10-2, and a third pixel circuit 10-3; the first light emitting device P1 is coupled to the first pixel circuit 10-1, the second light emitting device P2 is coupled to the second pixel circuit 10-1, and the third light emitting device P3 is coupled to the third pixel circuit 10-1. As can be seen from fig. 13, the area of the storage capacitor Cst in the first pixel circuit 10-1 is larger than the area of the storage capacitor Cst in the second pixel circuit 10-2, and the area of the storage capacitor Cst in the first pixel circuit 10-1 is larger than the area of the storage capacitor Cst in the third pixel circuit 10-3. That is, the capacitance value of the storage capacitor Cst in the first pixel circuit 10-1 is greater than the capacitance value of the storage capacitor Cst in the second pixel circuit 10-2, and the capacitance value of the storage capacitor Cst in the first pixel circuit 10-1 is greater than the capacitance value of the storage capacitor Cst in the third pixel circuit 10-3. At least one first longitudinal reset line 31 and the first pixel circuit 10-1 at least partially overlap in a direction perpendicular to the plane of the substrate. That is, the first pixel circuit 10-1 is closest to the first longitudinal reset line 31, and the first longitudinal reset line 31 provides the first pixel circuit 10-1 with the shortest distance for transmission of the reset signal.

When the gate of the driving transistor Tm in the pixel circuit 10 is reset by using the first longitudinal reset line 31, the gate of the driving transistor Tm is coupled to the storage capacitor Cst, and the larger the capacitance of the storage capacitor Cst in the pixel circuit 10 is, the larger the reset current generated when the gate of the driving transistor Tm is reset is, the larger the voltage drop on the corresponding first longitudinal reset line 31 is, thereby affecting the reset of the plurality of pixel circuits 10 coupled to the first longitudinal reset line 31 in the same row of pixel circuits 10H. In the embodiment of the present invention, the first vertical reset line 31 is overlapped with the first pixel circuit 10-1 with the largest capacitance value of the storage capacitor Cst, so that the transmission distance of the reset signal provided by the first vertical reset line 31 to the first pixel circuit 10-1 is the shortest. In the same time period for driving one row of pixel circuit row 10H, the first vertical reset line 31 can be used to quickly reset the first pixel circuit 10-1, so as to reduce the influence of the reset current on the voltage drop on the first vertical reset line 31, so as to ensure that the reset conditions of the first vertical reset line 31 on the pixel circuits 10 connected with the first vertical reset line 31 in the same time period are basically the same as much as possible, thereby improving the display unevenness.

In some embodiments, the light emission color of the first light emitting device P1 is red. The light emission colors of the second and third light emitting devices P2 and P3 are one of green and blue, respectively. That is, among the three light emitting color devices, the first pixel circuit 10-1 drives the first light emitting device P1, and the capacitance value of the storage capacitor Cst in the first pixel circuit 10-1 is set to be larger, and the capacitance values of the storage capacitors Cst in the second pixel circuit 10-2 and the third pixel circuit 10-3 are set to be smaller.

In one embodiment, the light emitting color of the second light emitting device P2 is green, and the light emitting color of the third light emitting device P3 is blue. The capacitance value of the storage capacitor Cst in the second pixel circuit 10-2 is set to be smaller, so that the threshold compensation of the driving transistor Tm can be more sufficient when the pixel circuit operates in the threshold compensation stage, and the light emitting brightness of the second light emitting device P2 driven by the second pixel circuit 10-2 is more accurate. Because human eyes are more sensitive to green light, the light-emitting brightness of the second light-emitting device P2 is more accurate, the overall visual effect can be improved, and the problem of uneven display is favorably solved. In addition, the light emitting current required for the third light emitting device P3 emitting blue light is larger than the light emitting currents of the first and second light emitting devices P1 and P2 when the pixel unit composed of the three color light emitting devices emits white light. The data voltage value supplied to the third pixel circuit 10-3 is low when the pixel cell emits white light, thereby resulting in an increase in power consumption. In the embodiment of the present invention, by reducing the capacitance of the storage capacitor Cst in the third pixel circuit 10-3, the data voltage supplied to the third pixel circuit 10-3 can be appropriately increased when the third light emitting device P3 is driven to emit light, so that the data voltage is close to the data voltage supplied to the first pixel circuit 10-1 and the second pixel circuit 10-2, thereby reducing the display power consumption.

In an embodiment, fig. 14 is a schematic diagram of another display panel according to an embodiment of the invention, as shown in fig. 14, a pixel circuit 10 includes a first pixel circuit 10-1, a second pixel circuit 10-2, and a third pixel circuit 10-3; the display panel includes a first light emitting device, a second light emitting device and a third light emitting device having different light emission colors from each other, wherein the first light emitting device is coupled to a first pixel circuit 10-1, the second light emitting device is coupled to a second pixel circuit 10-2, and the third light emitting device is coupled to a third pixel circuit 10-3. The light emitting device is not shown in fig. 14, and the arrangement of the light emitting device is not limited in the embodiment of the present invention. The plurality of first pixel circuits 10-1 are arranged in the second direction y as a first circuit column 10L1, the plurality of second pixel circuits 10-2 are arranged in the second direction y as a second circuit column 10L2, and the plurality of third pixel circuits 10-3 are arranged in the second direction y as a third circuit column 10L3; in the first direction x, the first circuit column 10L1, the second circuit column 10L2, and the third circuit column 10L3 are alternately arranged. In this embodiment mode, the light emitting devices driven by the plurality of pixel circuits 10 in one circuit column emit light of the same color.

Also illustrated in fig. 14 are first longitudinal reset lines 31 extending in the second direction y, and lateral reset lines 40 of a color in the first direction x, one lateral reset line 40 being coupled to each first longitudinal reset line 31. Only one lateral reset line 40 is illustrated in fig. 14 coupling three pixel circuits 10 in a row of pixel circuit rows.

In another embodiment, fig. 15 is a schematic diagram of another display panel according to an embodiment of the invention, and as shown in fig. 15, the pixel circuit 10 includes a first pixel circuit 10-1, a second pixel circuit 10-2, and a third pixel circuit 10-3; the display panel includes a first light emitting device, a second light emitting device and a third light emitting device having different light emission colors from each other, wherein the first light emitting device is coupled to a first pixel circuit 10-1, the second light emitting device is coupled to a second pixel circuit 10-2, and the third light emitting device is coupled to a third pixel circuit 10-3. The light emitting device is not shown in fig. 15, and the arrangement of the light emitting device is not limited in the embodiment of the present invention. The first pixel circuits 10-1 and the second pixel circuits 10-2 are alternately arranged in the second direction y as a fourth circuit column 10L4, and the plurality of third pixel circuits 10-3 are arranged in the second direction y as a fifth circuit column 10L5; in the first direction x, the fourth circuit columns 10L4 and the fifth circuit columns 10L5 are alternately arranged; among them, two pixel circuits 10 belonging to the same pixel circuit row 10H in two adjacent fourth circuit columns 10L4 are one first pixel circuit 10-1 and the other second pixel circuit 10-2. In this embodiment, the first pixel circuits 10-1 and the second pixel circuits 10-2 are alternately arranged in the first direction x in the pixel circuit row 10H with one third pixel circuit 10-3 interposed between the adjacent first pixel circuit 10-1 and second pixel circuit 10-2.

Also illustrated in fig. 15 are first longitudinal reset lines 31 extending in the second direction y, and lateral reset lines 40 of a color in the first direction x, one lateral reset line 40 being coupled to each first longitudinal reset line 31. Only 2 pixel circuits 10 in a row of pixel circuit rows 10H are coupled by one lateral reset line 40 as illustrated in fig. 15.

In some embodiments, as shown in fig. 5 or fig. 6, at least two lateral reset lines 40 are respectively coupled to different pixel circuits 10 in the same row of pixel circuits 10H; the pixel circuits 10 in the pixel circuit row 10H are reset by at least two lateral reset lines 40 in the same period of driving one row of the pixel circuit row 10H. The difference between the numbers of the pixel circuits 10 coupled to the two horizontal reset lines 40 corresponding to the same row of pixel circuit rows 10H is less than or equal to a second preset number. In the same period of driving a row of pixel circuit rows 10H, the difference in reset conditions of the pixel circuits 10 connected to the respective lateral reset lines 40 is small, so that the reset difference between the pixel circuits 10 connected to different lateral reset lines 40 in a row of pixel circuit rows 10H can be reduced, the uniformity of the brightness of the light emitting device driven by the pixel circuit rows 10H can be improved, and the display unevenness can be improved.

In some embodiments, the second predetermined number is 3. That is, the difference in the number of pixel circuits 10 to which the two lateral reset lines 40 corresponding to the same row of pixel circuit rows 10H are coupled is at most 3. As shown in fig. 5, the number of the pixel circuits 10 coupled to the horizontal reset lines 40 is 3, and the difference between the numbers of the pixel circuits 10 coupled to the two horizontal reset lines 40 corresponding to the same row of pixel circuits 10H is 0. In fig. 6, it is shown that the horizontal reset lines 40 corresponding to the same row of pixel circuits 10H include the horizontal reset lines 40 coupled to 2 pixel circuits 10 and also include the horizontal reset lines 40 coupled to 3 pixel circuits 10, and there is a difference of 1 between the numbers of pixel circuits 10 to which two horizontal reset lines 40 are coupled. The embodiment of the present invention limits the second preset number, so that the difference between the numbers of the pixel circuits 10 coupled to the two horizontal reset lines 40 corresponding to the same row of pixel circuit rows 10H is small. In the same period of driving a row of pixel circuit rows 10H, the reset conditions of the pixel circuits 10 connected by the transverse reset lines 40 are not different greatly, so that the reset conditions of the pixel circuits 10 connected by different transverse reset lines 40 in a row of pixel circuit rows 10H are basically the same, the brightness uniformity of the light-emitting device driven by the pixel circuit rows 10H is improved, and the display unevenness is improved.

In some embodiments, as shown in fig. 5, a row of pixel circuit rows 10H is commonly driven by a plurality of horizontal reset lines 40, and the number of pixel circuits 10 coupled to each horizontal reset line 40 corresponding to the same row of pixel circuit row 10H is equal. In the same period of driving a row of pixel circuit rows 10H, each transverse reset line 40 resets the same number of pixel circuits 10, so that the reset conditions between the pixel circuits 10 connected with different transverse reset lines 40 in a row of pixel circuit rows 10H are basically the same, the brightness uniformity of the light-emitting device driven by the pixel circuit rows 10H is improved, and the display unevenness is improved.

In some embodiments, as shown in fig. 5, one first longitudinal reset line 31 is coupled to a plurality of lateral reset lines 40 arranged in the second direction y, and each lateral reset line 40 coupled to the same first longitudinal reset line 31 is coupled to the same number of pixel circuits 10. That is, one first vertical reset line 31 is coupled to the pixel circuits 10 in the plurality of pixel circuit rows 10H, and the number of the pixel circuits 10 in each pixel circuit row 10H to which the first vertical reset line 31 is coupled is equal. When the display is performed by the line-by-line driving, the scanning lines 20 supply scanning signals line by line to drive the plurality of pixel circuit lines 10H line by line, and the first vertical reset line 31 resets the pixel circuits coupled to it in the next pixel circuit line 10H after a period of time after completing the reset of the pixel circuits coupled to it in one pixel circuit line 10H. The first vertical reset line 31 continuously supplies the voltage signal to the first vertical reset line 31 during the time interval in which the pixel circuits in the two rows of pixel circuit rows 10H are reset, and can compensate for the voltage drop on the first vertical reset line 31, so that the first vertical reset line 31 supplies the same reset voltage to the pixel circuits 10 in each pixel circuit row 10H. The transverse reset lines 40 coupled to the same first longitudinal reset line 31 are coupled to the same number of pixel circuits 10, so that the reset conditions of the pixel circuits 10 belonging to different pixel circuit rows 10H coupled to the first longitudinal reset line 31 are substantially the same, thereby further improving the display unevenness and the display uniformity.

In some embodiments, fig. 16 is a schematic view of another display panel according to an embodiment of the invention, as shown in fig. 16, a plurality of pixel circuits 10 are arranged in a first direction x to form a pixel circuit row 10H, and a plurality of pixel circuits 10 are arranged in a second direction y to form a circuit column 10L; the vertical reset lines 30 include second vertical reset lines 32, one second vertical reset line 32 is coupled to one pixel circuit 10 in one row of pixel circuits 10H, and a plurality of pixel circuits 10 in one circuit column 10L are coupled to the same second vertical reset line 32. In the display panel provided by this embodiment, in the same period of driving one row of pixel circuit rows 10H, one second longitudinal reset line 32 only resets one pixel circuit 10, and the parasitic capacitance on the second longitudinal reset line 32 is sufficient to complete resetting the pixel circuit 10, so that there is almost no current and no voltage drop on the second longitudinal reset line 32, and sufficient resetting of the pixel circuit 10 can be realized, and there is no problem of dark state caused by incomplete resetting. The pixel circuits 10 connected to the different second longitudinal reset lines 32 in one row of the pixel circuit row 10H can be sufficiently reset. And the pixel circuits 10 in the circuit column 10L coupled to the second longitudinal reset line 32 can be sufficiently reset when the pixel circuit row 10H is driven row by row. This embodiment can ensure that each pixel circuit 10 is fully reset, effectively improving display unevenness, and improving display uniformity.

In some embodiments, one second longitudinal reset line 32 is coupled to one pixel circuit 10 in one row of pixel circuit rows 10H, a plurality of pixel circuits 10 in one circuit column 10L are coupled to the same second longitudinal reset line 32, and the second longitudinal reset line 32 at least partially overlaps the data line or the power supply line, so that the parasitic capacitance on the second longitudinal reset line 32 can be increased. Which are not illustrated in the drawings.

In some embodiments, the data line 21 and the power line 22 both extend in the second direction y, and the longitudinal reset line 30 is located at a different layer from at least one of the data line 21 and the power line 22. The longitudinal reset line 30 and the data line 21 (or the power line 22) located in a different layer from the longitudinal reset line 30 may be at least partially overlapped to increase the parasitic capacitance on the longitudinal reset line 30, and the pixel circuits are reset by using the large capacitance on the longitudinal reset line 30, so that the longitudinal reset line 30 has almost no current and the longitudinal reset line 30 has almost no voltage drop, and the pixel circuits 10 coupled to the longitudinal reset line 30 can be reset in the same condition, so that each pixel circuit 10 can be fully reset, the display unevenness can be improved, and the problem of dark state luminescence caused by insufficient reset can be avoided.

In one embodiment, the longitudinal reset lines 30 and the data lines 21 are located in different layers. Fig. 17 isbase:Sub>A schematic cross-sectional view taken at the position of linebase:Sub>A-base:Sub>A' of fig. 10. As shown in fig. 17, the display panel includes a semiconductor layer 020, a first metal layer 030, a second metal layer 040, a third metal layer 050, and a fourth metal layer 060 located on the substrate 010 side and sequentially distant from the substrate 010. Fig. 17 illustrates the driving transistor Tm, the active layer of the driving transistor Tm is located on the semiconductor layer 020, the scanning line 20 is located on the first metal layer 030, the first plate of the storage capacitor Cst is located on the first metal layer 030, and the second plate of the storage capacitor Cst is located on the second metal layer 040; the data line 21 and the power line 22 are located on the third metal layer 050; wherein the longitudinal reset wire 30 is located on the fourth metal layer 060. In this embodiment, the longitudinal reset line 30 is located at a different layer from the data line 21 and the power line 22, and the longitudinal reset line 30 at least partially overlaps the data line 21 in a direction e perpendicular to the plane of the substrate 010. Therefore, the parasitic capacitance on the longitudinal reset wire 30 can be increased, and the pixel circuit is reset by using the large capacitance on the longitudinal reset wire 30, so that the longitudinal reset wire 30 has almost no current and the longitudinal reset wire 30 has almost no voltage drop, and the reset condition of the pixel circuit 10 coupled to the longitudinal reset wire 30 can be the same.

In some embodiments, longitudinal reset wires 30 and transverse reset wires 40 are in the same layer, as shown in FIG. 17. The longitudinal reset lines 30 and the lateral reset lines 40 may be fabricated using the same process, and they are directly connected. A region Q1 circled in fig. 17 indicates a connection point where the pixel circuit is connected to the lateral reset line 40. In addition, longitudinal reset wires 30 and transverse reset wires 40 are disposed in the same layer. The longitudinal reset lines 30 and the lateral reset lines 40 can be located more flexibly, and the longitudinal reset lines 30 can be placed to overlap with other signal lines to increase the parasitic capacitance on the longitudinal reset lines 30. In the embodiment of fig. 17, the longitudinal reset line 30 and the data line 21 are arranged to overlap. In another embodiment, as shown in fig. 11, the longitudinal reset lines 30 and the lateral reset lines 40 are in the same layer, and the longitudinal reset lines 30 overlap the power lines 22 in a direction perpendicular to the plane of the substrate 010. The arrangement of the lateral reset lines 40 does not affect the original signal lines of the display panel extending in the first direction x. The provision of the longitudinal reset lines 30 and the lateral reset lines 40 in the same layer can reduce the influence on the wiring space in the display panel.

In some embodiments, the longitudinal reset lines 30 and the transverse reset lines 40 are in different layers. At least one of the vertical reset lines 30 and the horizontal reset lines 40 may be disposed at the same layer as other conductive structures in the display panel, while ensuring that the two are electrically connected through the via holes in the insulating layer. For example, the horizontal reset line 40 and other conductive structures in the display panel are disposed on the same layer, the position of the vertical reset line 30 may also be relatively flexible, and the vertical reset line 30 and the data line 21 or the power line 22 may be overlapped as required, or the vertical reset line 30 may be disposed between adjacent pixel circuits as required. In addition, the longitudinal reset wires 30 and the transverse reset wires 40 are located in different layers, for example, a part of the reset wires extending along the first direction x in the prior art can be reserved as the transverse reset wires 40 in the present invention, and the longitudinal reset wires 30 extending along the second direction y are additionally provided. Thus, the design of the vertical reset lines 30 in the present embodiment can be implemented with relatively little modification to the existing wiring scheme of the display panel.

In an embodiment, fig. 18 is a schematic view of another display panel provided in an embodiment of the invention, and fig. 19 is a schematic cross-sectional view taken at a position of a tangent line B-B' in fig. 18. As seen in conjunction with fig. 18 and 19, the longitudinal reset wires 30 and the transverse reset wires 40 are in different layers. Wherein the longitudinal reset wire 30 is located on the fourth metal layer 060 and the lateral reset wire 40 is located on the second metal layer 040. The longitudinal reset lines 30 and the lateral reset lines 40 are electrically connected by vias that pass through the insulating layer. In the pixel circuit 10, one plate of the storage capacitor Cst is located on the second metal layer 040, and the horizontal reset line 40 is provided on the second metal layer 040, so that the second metal layer 040 can be used. The scan line 20 in the display panel is located on the first metal layer 030, the extending direction of the horizontal reset line 40 is the same as the extending direction of the scan line 20, and the horizontal reset line 40 and the scan line 20 are arranged on different layers, so that the arrangement compactness of routing lines with the same extending direction can be improved, and the space occupied by the pixel circuit can be saved.

In another embodiment, the longitudinal reset wires 30 and the transverse reset wires 40 are in different layers. The longitudinal reset wire 30 is located on the fourth metal layer 060, the lateral reset wire 40 is located on the semiconductor layer 020, and the longitudinal reset wire 30 and the lateral reset wire 40 are electrically connected through a via penetrating through the insulating layer.

In another embodiment, the longitudinal reset wires 30 and the transverse reset wires 40 are in different layers. The longitudinal reset line 30 and the data line 21 are located on the same layer, and the transverse reset line 40 is located on the semiconductor layer 020 or the second metal layer 040.

In another embodiment, the longitudinal reset wires 30 and the transverse reset wires 40 are in different layers. Wherein the longitudinal reset line 30 is located at the same layer as the data line and the power line.

In some embodiments, at least one metal layer is spaced between the film layers of the lateral reset lines 40 and the longitudinal reset lines 30 in a direction perpendicular to the plane of the substrate 010. Fig. 20 is a schematic view of another display panel according to an embodiment of the invention, and fig. 21 is a schematic cross-sectional view taken along line C-C' of fig. 20. As seen in fig. 20 and 21, the display panel further includes a metal pad 50, the lateral reset line 40 is coupled to the metal pad 50 through a via penetrating through the insulating layer, and the metal pad 50 is coupled to the longitudinal reset line 30 through a via penetrating through the insulating layer; metal spacer 50 is located in the metal layer between the film layers in which the lateral reset lines 40 are located and the film layers in which the longitudinal reset lines 30 are located. In this embodiment, the lateral reset wires 40 are shown in a second metal layer 040 and the longitudinal reset wires 30 are shown in a fourth metal layer 060 with a third metal layer 050 spaced between the film layers on which the lateral reset wires 40 are located and the film layers on which the longitudinal reset wires 30 are located, wherein the metal spacer 50 is located on the third metal layer 050. Because there is at least one metal layer at the interval between the rete that horizontal reset wire 40 is located and the rete that vertical reset wire 30 is located, lead to along perpendicular to substrate 010 place plane direction e, the interval distance between horizontal reset wire 40 and the vertical reset wire 30 is great, if directly punch the connection that realizes between the two on the insulating layer, can lead to the depth of punching and punch the hole area great, not only influence the electric connection reliability between horizontal reset wire 40 and the vertical reset wire 30, still can lead to punching to occupy great wiring space. In the embodiment of the invention, the film layer where the transverse reset wire 40 is located and the longitudinal reset wire 30 are realized by arranging the metal cushion block 50, so that the depth of the connecting via hole between the metal cushion block 50 and the transverse reset wire 40 is not too deep, the hole area of the via hole is not too large, the depth of the connecting via hole between the metal cushion block 50 and the longitudinal reset wire 30 is not too deep, and the hole area of the via hole is not too large, thereby ensuring the reliability of the electrical connection between the transverse reset wire 40 and the longitudinal reset wire 30, and reducing the influence of the via hole on the wiring space.

In an embodiment, fig. 22 is a schematic diagram of another display panel according to an embodiment of the present invention, and the pixel circuit 10 illustrated in fig. 22 can be understood by combining the circuit diagram in fig. 4. As shown in fig. 22, the display panel includes a first reset line 25 and a second reset line 26, the first reset line 25 and the second reset line 26 transmit different voltage values; a second pole of the first reset transistor T3 is coupled to a first reset line 25, and a second pole of the second reset transistor T6 is coupled to a second reset line 26; the first reset line 25 supplies a first reset signal Ref1, and the second reset line 26 supplies a second reset signal Ref2. The display panel includes two longitudinal reset lines 30, and the two longitudinal reset lines 30 are a first type of longitudinal reset line 31-1 and a second type of longitudinal reset line 31-2, respectively. Wherein the first reset line 25 comprises a first type of longitudinal reset line 31-1 and the second reset line 26 comprises a second type of longitudinal reset line 31-2. That is, the first reset transistor T3 of the pixel circuit 10 is coupled to the first-type vertical reset line 31-1, and the second reset transistor T6 of the pixel circuit 10 is coupled to the second-type vertical reset line 31-2. The embodiment can respectively reset the first reset transistor T3 and the second reset transistor T6 by using the reset lines transmitting different voltage values, and meets different requirements of the two reset transistors on the voltage value of the reset signal. And two types of longitudinal reset lines are provided, the first reset transistor T3 and the second reset transistor T6 being coupled to their respective longitudinal reset lines, respectively. The two types of longitudinal reset lines are connected with part of the pixel circuits 10 in one row of the pixel circuit row 10H, the number of the pixel circuits 10 reset by the two types of longitudinal reset lines is less in the same time period for driving one row of the pixel circuit row 10H, so that the reset difference among the pixel circuits 10 is smaller, the brightness difference of the light-emitting devices driven by the pixel circuits 10 at different positions in the pixel circuit row 10H can be reduced, and the problem of uneven display is solved.

In addition, FIG. 22 also illustrates that the lateral reset lines 40 include a first type of lateral reset line 40-1 and a second type of lateral reset line 40-2, wherein the first type of lateral reset line 40-1 is coupled to the first type of longitudinal reset line 31-1 and the second type of lateral reset line 40-2 is coupled to the second type of longitudinal reset line 31-2.

In some embodiments, fig. 23 is a schematic diagram of another display panel according to an embodiment of the present invention, and as shown in fig. 23, the non-display area NA includes a reset bus 60; the reset bus 60 is located at one side of the display area AA in the second direction y; the longitudinal reset line 30 is connected to the reset bus 60 after extending from the display area AA to the non-display area NA. In this embodiment, the reset bus 60 is disposed on one side of the display area AA, the reset bus 60 is used to provide a reset signal to the plurality of vertical reset lines 30, and then the lead wires led out from the reset bus 60 are connected to the reset signal ports (the reset signal ports are used for connecting with the display driver chip), so that there is no need to dispose a reset signal port for each vertical reset line 30, the number of reset signal ports disposed in the non-display area NA can be reduced, and the space of the non-display area NA can be saved. The number of output ports provided in the display driver chip can be reduced, and the size of the display driver chip can be reduced.

Compared with the prior art in which the reset bus is arranged around the display area by one circle, the arrangement of the longitudinal reset line 30 and the reset bus 60 in the embodiment of the present invention can also save the space of the non-display area NA on both sides of the display area AA in the first direction x, which is beneficial to narrow the frame.

In the embodiment of the present invention, one vertical reset line 30 is coupled to only a part of the pixel circuits 10 in one row of the pixel circuit rows 10H. In the same period of driving one row of the pixel circuit rows 10H, one vertical reset line 30 resets only the pixel circuits 10 connected thereto, instead of resetting all the pixel circuits 10 in one row of the pixel circuit rows 10H. The voltage drop caused by resetting the pixel circuits 10 by one longitudinal reset line 30 in the same period is small, so that the reset conditions of the pixel circuits 10 coupled to the same longitudinal reset line 30 in one row of the pixel circuit rows 10H can be basically the same. In addition, because the voltage drop generated when one longitudinal reset line 30 resets the pixel circuits 10 in the same period is relatively small, in the time interval of driving two rows of pixel circuit rows 10H row by row, the reset bus 60 can compensate the voltage on the longitudinal reset line 30 to a certain extent, so that the difference in the reset conditions of the pixel circuits 10 in two adjacent rows of pixel circuit rows 10H driven by one longitudinal reset line 30 is relatively small, and the difference in the brightness of the light-emitting devices driven by two rows of pixel circuit rows 10H is relatively small, thereby improving the display uniformity.

In some embodiments, fig. 24 is a schematic view of another display panel according to an embodiment of the present invention, as shown in fig. 24, the display area AA has a notch K, and an edge of the notch K is recessed toward the inside of the display area AA along the second direction y; the display area AA includes a first display area AA1 and a second display area AA2; in the second direction y, the first display area AA1 is located at one side of the gap K; in the first direction x, the second display areas AA2 are located at both sides of the gap K. The longitudinal reset wires 30 include a third sub-longitudinal reset wire 30c and a fourth sub-longitudinal reset wire 30d; within the display area AA: in the second direction y, the length of the third sub-longitudinal reset wire 30c is less than that of the fourth sub-longitudinal reset wire 30d, the third sub-longitudinal reset wire 30c is located in the first display area AA1, and the fourth sub-longitudinal reset wire 30d is located in the second display area AA2.

In the display panel with the gap K in the display area AA, if the reset line is designed conventionally, and the reset line extending along the first direction x is coupled to all the pixel circuits in one row of pixel circuits, the length of the reset line in the display areas on both sides of the gap K is shortened due to the gap K, and the difference between the lengths of the reset line at the long end and the reset line at the short end and the reset lines in other display areas is large, so that the difference between the voltage drop is large, and the difference between the brightness of the display areas on both sides of the gap K and other display areas is large, which may cause a serious display split problem.

With the design of the embodiment of the present invention, the longitudinal reset line 30 extending in the second direction y is disposed in the display panel, and the third sub-longitudinal reset line 30c located in the first display area AA1 and the fourth sub-longitudinal reset line 30d located in the second display area AA2 are disposed according to the position of the display area. In the same period of driving one row of the pixel circuit row 10H, the third sub-vertical reset line 30c and the fourth sub-vertical reset line 30d each reset only the pixel circuit 10 connected thereto, rather than resetting all the pixel circuits 10 in one row of the pixel circuit row 10H. In addition, the third sub-longitudinal reset line 30c and the fourth sub-longitudinal reset line 30d can compensate the voltage on each longitudinal reset line 30 to a certain extent in the time interval of driving two rows of pixel circuit rows 10H row by row, so that the difference of the reset conditions of the pixel circuits 10 in two adjacent rows of pixel circuit rows 10H driven by the third sub-longitudinal reset line 30c is small, and the difference of the reset conditions of the pixel circuits 10 in two adjacent rows of pixel circuit rows 10H driven by the fourth sub-longitudinal reset line 30d is small. Thus, the luminance difference of the light emitting devices driven by the pixel circuit rows 10H on the two sides of the notch K in the first direction x is small, and the luminance difference of the light emitting devices driven by the pixel circuit rows 10H in the two adjacent rows in the second direction y is also small, so that the display uniformity can be improved.

Based on the same inventive concept, an embodiment of the present invention further provides a display apparatus, and fig. 25 is a schematic diagram of the display apparatus provided in the embodiment of the present invention, as shown in fig. 25, the display apparatus includes the display panel 100 provided in any embodiment of the present invention. The structure of the display panel 100 is already described in the above embodiments, and is not described herein again. The display device provided by the embodiment of the invention is any equipment with a display function, such as a mobile phone, a tablet computer, a notebook computer, a television and the like.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, comprising scan lines extending in a first direction and longitudinal reset lines extending in a second direction, the first direction and the second direction being crossed with each other; the display panel includes a display area in which the adjacent longitudinal reset lines are disconnected from each other.

2. The display panel according to claim 1,

the display panel includes a substrate and pixel circuits on one side of the substrate, the pixel circuits being arranged in a pixel circuit row in the first direction;

the longitudinal reset wire comprises a first longitudinal reset wire;

the display panel comprises transverse reset lines extending along the first direction, and one transverse reset line is correspondingly coupled with one first longitudinal reset line; wherein,

one of the horizontal reset lines is coupled to at least two of the pixel circuits in one of the pixel circuit rows, and the number of the pixel circuits in the same pixel circuit row coupled to the same horizontal reset line is smaller than the total number of the pixel circuits in the pixel circuit row.

3. The display panel according to claim 2,

the first longitudinal reset line comprises a first sub-longitudinal reset line;

the transverse reset lines include a first transverse reset line, the first transverse reset line is coupled with the first sub-longitudinal reset line, and the first transverse reset line is disconnected from the longitudinal reset line adjacent to the first sub-longitudinal reset line in the display area.

4. The display panel according to claim 3,

the first longitudinal reset line includes a second sub-longitudinal reset line adjacent to the first sub-longitudinal reset line;

the lateral reset line comprises a second lateral reset line, and the second lateral reset line is coupled with the second sub-longitudinal reset line; wherein,

the first and second horizontal reset lines are respectively coupled to different pixel circuits in the same row of the pixel circuit row, and the second and first horizontal reset lines are disconnected in the display region.

5. The display panel according to claim 4, wherein the pixel circuits coupled to the first horizontal reset lines are sequentially arranged in the first direction, and the pixel circuits coupled to the second horizontal reset lines are sequentially arranged in the first direction.

6. The display panel according to claim 4,

at least one of the pixel circuits coupled to the first lateral reset line is located between two of the pixel circuits coupled to the second lateral reset line.

7. The display panel according to claim 2,

the connection point of the first longitudinal reset wire and the transverse reset wire is a first connection point;

the difference value of the number of the pixel circuits which are coupled with the transverse reset wire and positioned at two sides of the first connecting point in the first direction is less than or equal to a first preset number.

8. The display panel according to claim 7,

the first preset number is 2.

9. The display panel according to claim 2,

the display panel comprises data lines extending along the second direction, and at least one first longitudinal reset line and the data lines at least partially overlap in the direction perpendicular to the plane of the substrate;

or, the display panel comprises a power line extending along the second direction, and at least one of the first longitudinal reset lines and the power line at least partially overlap in a direction perpendicular to the plane of the substrate.

10. The display panel according to claim 2,

at least one of the lateral reset lines is coupled to n of the pixel circuits, n being an odd number greater than 1; n of the pixel circuits are arranged in the first direction;

at least one first longitudinal reset wire and (n + 1)/2 pixel circuits in the n pixel circuits at least partially overlap in a direction perpendicular to a plane of the substrate.

11. The display panel according to claim 2,

the display panel includes a first light emitting device, a second light emitting device, and a third light emitting device having different light emission colors; the pixel circuits in the pixel circuit row include a first pixel circuit, a second pixel circuit, and a third pixel circuit; the first light emitting device is coupled with the first pixel circuit, the second light emitting device is coupled with the second pixel circuit, and the third light emitting device is coupled with the third pixel circuit;

the pixel circuit comprises a storage capacitor, the capacitance value of the storage capacitor in the first pixel circuit is larger than that of the storage capacitor in the second pixel circuit, and the capacitance value of the storage capacitor in the first pixel circuit is larger than that of the storage capacitor in the third pixel circuit;

at least one of the first longitudinal reset lines and the first pixel circuit at least partially overlap in a direction perpendicular to a plane of the substrate.

12. The display panel according to claim 11,

the light emitting color of the first light emitting device is red.

13. The display panel according to claim 2,

a plurality of the first pixel circuits are arranged in a first circuit column in the second direction, a plurality of the second pixel circuits are arranged in a second circuit column in the second direction, and a plurality of the third pixel circuits are arranged in a third circuit column in the second direction;

in the first direction, the first circuit columns, the second circuit columns, and the third circuit columns are alternately arranged.

14. The display panel according to claim 2,

the first pixel circuits and the second pixel circuits are alternately arranged in a fourth circuit column in the second direction, and a plurality of the third pixel circuits are arranged in a fifth circuit column in the second direction; in the first direction, the fourth circuit columns and the fifth circuit columns are alternately arranged;

and one of the two pixel circuits belonging to the same pixel circuit row in the two adjacent fourth circuit columns is the first pixel circuit, and the other one is the second pixel circuit.

15. The display panel according to claim 2, wherein at least two of the lateral reset lines are respectively coupled to different ones of the pixel circuits in a same row of the pixel circuits; wherein,

the difference value of the number of the pixel circuits coupled with the two transverse reset wires corresponding to the same row of the pixel circuits is less than or equal to a second preset number.

16. The display panel according to claim 15,

the second preset number is 3.

17. The display panel of claim 15, wherein the number of the pixel circuits coupled to the respective reset lines corresponding to the same row of the pixel circuits is equal.

18. The display panel according to claim 2,

one of the first vertical reset lines is coupled to a plurality of the horizontal reset lines arranged in the second direction, and each of the horizontal reset lines coupled to the same one of the first vertical reset lines is coupled to the same number of the pixel circuits.

19. The display panel according to claim 1,

the display panel comprises a substrate and pixel circuits located on one side of the substrate, wherein the pixel circuits are arranged in a pixel circuit row in the first direction, and the pixel circuits are arranged in a circuit column in the second direction;

the vertical reset lines include second vertical reset lines, one of the second vertical reset lines is coupled to one of the pixel circuits in one of the pixel circuit rows, and a plurality of the pixel circuits in one of the circuit columns are coupled to the same one of the second vertical reset lines.

20. The display panel according to claim 1,

the display panel comprises a substrate, and a data line and a power line which are positioned on one side of the substrate;

the longitudinal reset line is located at a different layer from at least one of the data line and the power line.

21. The display panel according to claim 2,

the longitudinal reset wire and the transverse reset wire are positioned on the same layer.

22. The display panel according to claim 2,

the longitudinal reset lines and the transverse reset lines are located in different layers.

23. The display panel according to claim 22,

the display panel comprises a semiconductor layer, a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are positioned on one side of the substrate and are sequentially far away from the substrate; the display panel comprises a data line, a scanning line and a power line, and the pixel circuit comprises a transistor and a storage capacitor; the active layer of the transistor is positioned on the semiconductor layer, the scanning line and the first polar plate of the storage capacitor are positioned on the first metal layer, and the second polar plate of the storage capacitor is positioned on the second metal layer; the data line and the power line are positioned on the third metal layer; wherein,

the longitudinal reset wire is located on the fourth metal layer, and the transverse reset wire is located on the second metal layer.

24. The display panel according to claim 22,

at least one metal layer is arranged between the film layer where the transverse reset wire is positioned and the film layer where the longitudinal reset wire is positioned along the direction vertical to the plane of the substrate,

the display panel further comprises a metal cushion block, the transverse reset wire is coupled with the metal cushion block through a through hole penetrating through the insulating layer, and the metal cushion block is coupled with the longitudinal reset wire through a through hole penetrating through the insulating layer; the metal cushion block is positioned in a metal layer between the film layer where the transverse reset wire is positioned and the film layer where the longitudinal reset wire is positioned.

25. The display panel according to claim 1,

the display panel includes a pixel circuit and a light emitting device coupled with the pixel circuit; the pixel circuit comprises a driving transistor, a first reset transistor and a second reset transistor, wherein the first pole of the first reset transistor is electrically connected with the grid electrode of the driving transistor; a first electrode of the second reset transistor is electrically connected with an anode of the light emitting device;

the longitudinal reset wire is electrically connected to at least one of the second pole of the first reset transistor and the second pole of the second reset transistor.

26. The display panel according to claim 25, wherein the display panel comprises a first reset line and a second reset line, and the first reset line and the second reset line transmit different voltage values; a second pole of the first reset transistor is coupled to the first reset line, and a second pole of the second reset transistor is coupled to the second reset line;

and the same pixel circuit is electrically connected with two longitudinal reset wires, the first reset wire comprises one of the two longitudinal reset wires, and the second reset wire comprises the other of the two longitudinal reset wires.

27. The display panel according to claim 1,

the display panel further comprises a non-display area, wherein the non-display area comprises a reset bus; the reset bus is positioned on one side of the display area in the second direction; the longitudinal reset line is connected to the reset bus after extending from the display area to the non-display area.

28. The display panel according to claim 1,

the display area is provided with a notch, and the edge of the notch is sunken towards the inside of the display area along the second direction; the display area comprises a first display area and a second display area;

in the second direction, the first display area is positioned on one side of the notch; in the first direction, the second display areas are positioned on two sides of the notch;

the longitudinal reset wire comprises a third sub-longitudinal reset wire and a fourth sub-longitudinal reset wire;

within the display area: in the second direction, the length of the third sub-longitudinal reset line is smaller than that of the fourth sub-longitudinal reset line, the third sub-longitudinal reset line is located in the first display area, and the fourth sub-longitudinal reset line is located in the second display area.

29. A display device characterized by comprising the display panel according to any one of claims 1 to 28.