CN115215285A

CN115215285A - (111) silicon transfer process based on silicon nitride anodic bonding

Info

Publication number: CN115215285A
Application number: CN202110431854.5A
Authority: CN
Inventors: 叶超展; 孙珂; 杨恒; 李昕欣
Original assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Current assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Priority date: 2021-04-21
Filing date: 2021-04-21
Publication date: 2022-10-21

Abstract

The invention provides a (111) silicon transfer process based on silicon nitride anodic bonding, wherein through a low-stress silicon nitride layer, high-quality anodic bonding can be realized, and meanwhile, a bonding structure is protected from corrosion of a subsequent release process, so that a stable bonding structure is formed; by closing the release groove and corroding the protective layer, a sensitive movable structure which is accurate and controllable in thickness, not limited by crystal orientation and capable of being completely released can be formed, and therefore high-precision and low-cost manufacturing of MEMS devices with any crystal orientation on a (111) crystal face can be achieved.

Description

(111) silicon transfer process based on silicon nitride anodic bonding

Technical Field

The invention belongs to the technical field of micro-nano processing, and relates to a (111) silicon transfer process based on silicon nitride anodic bonding.

Background

Single crystal silicon is a good anisotropic material and has wide applications in micro electro mechanical systems technology. Common silicon wafers can be classified into (100) silicon wafers, (111) silicon wafers and the like according to crystal planes on the surfaces of the silicon wafers. Among them, the (100) silicon wafer is widely used in CMOS integrated circuits and bipolar integrated circuits. As is well known, single crystal silicon is an anisotropic material, and the in-plane crystal orientation of a commonly used (100) silicon wafer is [ nm0 ]]The crystal orientation, there is a clear anisotropy between the crystal orientations. For example [100 ]]Of crystal-oriented siliconYoung's modulus E of 1.31X 10 ¹¹ Pa, shear modulus G of 0.796X 10 ¹¹ Pa, and [110]Young's modulus E of crystal-oriented silicon is 1.7X 10 ¹¹ Pa, shear modulus G of 0.65X 10 ¹¹ Pa, and has obvious difference in mechanical property. And in electrical characteristics, [100 ]]Crystal orientation and [110 ]]There is a significant difference in mobility of crystal orientation. It has been shown in [100 ]]The N-type structure in the crystal direction has the condition of non-linear frequency temperature coefficient and has a point with the frequency temperature coefficient of 0, and the resonance structure can be thermostatted at the point with the frequency temperature coefficient of 0 by the constant temperature control technology according to the phenomenon, so that the low-temperature drift silicon-based resonator is realized. But in the N-type structure this phenomenon only exists for [100 ]]Crystal orientation, N-type [110 ] on the same silicon chip]The temperature coefficient of the crystal orientation structure frequency hardly changes with the doping concentration, and the temperature coefficient of the crystal orientation structure frequency is as high as-29 ppm/DEG C near the normal temperature. A similar phenomenon also exists for P-type (100) silicon wafers. On a P-type (100) silicon wafer, [110 ]]The temperature coefficient of frequency of crystal orientation changes with the change of doping concentration, and when heavily doped, the temperature coefficient of frequency can be reduced to-5 ppm/DEG C. But on the same silicon wafer [100 ]]The temperature coefficient of frequency of crystal orientation hardly changes with the temperature coefficient of frequency. (100) The anisotropy of silicon wafers has no significant adverse effect on general integrated circuits and micro-electro-mechanical systems (MEMS), but for in-plane multi-degree-of-freedom resonant structures, the significant anisotropy can cause significant mismatch of resonant frequency, frequency temperature coefficient and the like among the degrees of freedom.

(111) Silicon wafers are currently used primarily in bipolar integrated circuits and are not typically used in CMOS integrated circuits. (111) Parameters such as Young modulus, frequency temperature coefficient, piezoresistive coefficient and the like of each crystal direction in the silicon wafer surface have quasi-anisotropy characteristics, and the method is suitable for manufacturing an in-plane multi-degree-of-freedom resonance structure.

At present, the MEMS structure on the (111) silicon wafer is generally manufactured by adopting a (111) SOI silicon wafer or an MIS process (micro Inter-etch and Sealing). However, SOI silicon wafers are expensive and it is difficult to realize low-cost commercial manufacturing, and MIS processes and the like are processes for realizing MEMS structures by using the anisotropic wet etching characteristics of silicon, which can process common (111) silicon wafers, and have a processing accuracy comparable to that of SOI processes and a low cost. The main principle of the MIS process is as follows: the corrosion rate of monocrystalline silicon in alkaline corrosion liquid such as KOH, TMAH and the like is different along with the difference of crystal directions, a corrosion slow surface appears at a position with slow corrosion rate at the boundary of a concave angle and a mask, and a corrosion fast surface appears at a position with fast corrosion rate at a convex angle. As shown in fig. 1a to 1c and fig. 2, two square release grooves 1 are etched on a (111) silicon wafer, then an etching protection layer 2 is deposited on the sidewall of the release groove 1, the boundary between the protection layer 2 and the sidewall is regarded as a mask boundary a, and the bottom of the sidewall is regarded as a reentrant corner b, the lower half of each release groove 1 is etched in an etching solution in a hexagonal shape as shown in fig. 1b, and when two unreleased regions of the hexagonal shape are overlapped, a convex corner is formed, where the etching rate is accelerated, and finally a larger hexagonal shape is formed as shown in fig. 1c, and the etching will finally stop at each (111) plane as shown in fig. 2. Therefore, the (111) silicon wafer has the characteristic of lateral corrosion in the corrosive liquid, and the common (111) processing technology is to realize the structure manufacture with uniform thickness and strict limitation on the crystal orientation on the (111) silicon wafer according to the characteristic. The method needs to utilize the anisotropic corrosion characteristic of silicon, and the release window must be manufactured along a specific crystal direction, so that the manufactured structure has definite directivity, and the method has great limitation.

Therefore, it is necessary to provide a new (111) silicon transfer process based on silicon nitride anodic bonding.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a (111) silicon transfer process based on silicon nitride anodic bonding, which is used to solve the above-mentioned series of manufacturing problems encountered in the prior art for fabricating MEMS structures on (111) silicon wafers.

To achieve the above and other related objects, the present invention provides a (111) silicon transfer process based on silicon nitride anodic bonding, comprising the steps of:

providing a (111) silicon wafer;

patterning the (111) silicon wafer, and manufacturing a convex anchor point on the surface of the (111) silicon wafer;

forming a silicon nitride layer covering the anchor points;

forming a first corrosion protection layer, wherein the first corrosion protection layer covers the silicon nitride layer and the surface of the (111) silicon wafer;

patterning the first corrosion protection layer and the (111) silicon wafer to form a first groove, wherein the first groove comprises a structural pattern groove and a closed release groove;

forming a second corrosion protection layer, wherein the second corrosion protection layer covers the side wall and the bottom of the first groove;

removing the second corrosion protection layer at the bottom of the first groove, and etching to form a second groove based on the first groove;

patterning the first corrosion protection layer to expose the silicon nitride layer;

providing a bonding substrate, and carrying out anodic bonding on the bonding substrate and the silicon nitride layer;

performing wet etching by using anisotropic etching liquid to form a through hole based on the second groove;

and removing the first corrosion protection layer and the second corrosion protection layer.

Optionally, the silicon nitride layer is a low-stress silicon nitride layer with tensile stress as internal stress, and the stress is less than 100MPa.

Optionally, the anchor point has a thickness greater than a thickness of the silicon nitride layer; the thickness of the anchor point is less than 2 μm; the thickness of the silicon nitride layer is less than 1 μm.

Optionally, the silicon nitride layer extends to the surface of the (111) silicon wafer, and the extension width is greater than 2 times of the minimum line width of photolithography.

Optionally, the thickness of the first corrosion protection layer is more than 2 times that of the second corrosion protection layer; the first corrosion protection layer comprises a TEOS layer, an LTO layer, a SiC layer and SiO ₂ One or a combination of layers; the second corrosion protection layer comprises a TEOS layer, an LTO layer, a SiC layer and SiO ₂ One or a combination of layers.

Optionally, the bonded substrate comprises a glass bonded substrate.

Optionally, the anisotropic etching solution includes a KOH etching solution or a TMAH etching solution.

Optionally, after exposing the silicon nitride layer and before performing the bonding process, the method further includes a step of forming a first metal layer in the silicon nitride layer, and a step of forming a second metal layer on the surface of the bonding substrate, the second metal layer being disposed corresponding to the first metal layer, so as to achieve electrical connection through the first metal layer and the second metal layer.

Optionally, a step of forming a metal layer on the surface of the (111) silicon wafer is further included, so as to make metal wire electrical connection through the metal layer.

Optionally, the method for forming the silicon nitride layer, the first corrosion protection layer and the second corrosion protection layer includes an LPCVD method.

As described above, the (111) silicon transfer process based on silicon nitride anodic bonding of the present invention has the following beneficial effects:

1) (111) the silicon wafer is laterally corroded in the anisotropic corrosive liquid, and the upper surface and the lower surface with the crystal orientation (111) cannot be corroded, so that the thickness of the sensitive movable structure can be well controlled after the sensitive movable structure is released in the anisotropic corrosive liquid, and a structure with accurate, consistent and controllable thickness is realized;

2) A closed release groove with a closed pattern is formed in the (111) silicon wafer, after anodic bonding is completed, the device is placed in anisotropic etching liquid to be released, and the structural layer is completely released and separated from the (111) silicon wafer by closing the release groove. The process can realize the transfer of the sensitive movable structure to the bonding substrate, and the direction design of the sensitive movable structure on the (111) silicon wafer is not limited by the crystal orientation and can be oriented to any crystal orientation.

3) The low-stress silicon nitride layer is deposited on the (111) silicon wafer to serve as the bonding layer, high-quality anodic bonding can be achieved, and the bulk silicon at the bonding surface can be fully protected from being etched by the anisotropic etching liquid.

Therefore, the invention can realize the transfer of the sensitive movable structure with accurate and controllable thickness and any crystal orientation and the structure, and can realize the high-precision and low-cost manufacture of MEMS devices with any crystal orientation on (111) crystal planes such as silicon-based oscillators, accelerometers, micromechanical gyroscopes and the like.

Drawings

FIGS. 1a to 1c are schematic structural diagrams illustrating the etching of a (111) silicon wafer in an anisotropic etching solution according to the prior art.

FIG. 2 is a schematic cross-sectional view of a (111) silicon wafer etched in an anisotropic etching solution according to the prior art.

FIG. 3 is a flow chart illustrating a (111) silicon transfer process based on silicon nitride anodic bonding according to an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of anchor points fabricated on the surface of a (111) silicon wafer according to an embodiment of the present invention.

Fig. 5 is a schematic structural diagram illustrating a silicon nitride layer formed according to an embodiment of the invention.

FIG. 6 is a schematic structural diagram illustrating a first etching protection layer formed according to an embodiment of the present invention.

Fig. 7 is a schematic structural diagram illustrating the first trench formed in the embodiment of the present invention.

Fig. 8 is a schematic top view of the structure of fig. 7.

FIG. 9 is a schematic structural diagram illustrating a second etching protection layer formed according to an embodiment of the present invention.

Fig. 10 is a schematic structural diagram illustrating the second trench formed in the embodiment of the present invention.

FIG. 11 is a diagram illustrating a structure of a photoresist mask formed according to an embodiment of the present invention.

Fig. 12 is a schematic structural view illustrating the patterned first etching protection layer exposing the silicon nitride layer according to the embodiment of the invention.

Fig. 13 is a schematic structural view of a bonded substrate and a silicon nitride layer after anodic bonding according to an embodiment of the present invention.

Fig. 14 is a schematic structural diagram after forming a through hole in the embodiment of the present invention.

Fig. 15 is a schematic diagram of a sensitive movable structure formed in an embodiment of the present invention.

Fig. 16 is a schematic structural diagram illustrating a first metal layer formed in an embodiment of the invention.

Fig. 17 is a schematic top view of the structure of fig. 16.

Fig. 18 is a schematic structural diagram illustrating a second metal layer formed in the embodiment of the invention.

Fig. 19 is a schematic top view of fig. 18.

Fig. 20 is a schematic structural diagram illustrating a bonded first metal layer and a bonded second metal layer according to an embodiment of the invention.

Fig. 21 is a schematic structural diagram illustrating a metal layer formed on the front surface according to an embodiment of the invention.

Description of the element reference numerals

1. Release slot

2. Protective layer

a mask boundary

b concave angle

100 (111) silicon wafer

100a first surface

100b side wall

100c second surface

101. Anchor point

200. Silicon nitride layer

300. First corrosion protection layer

410. First trench

410a first trench bottom

410b first trench sidewalls

411. First patterned trench

412. First closed release groove

420. Second trench

420a second trench bottom

420b second trench sidewalls

421. Second structure pattern groove

422. Second closure release groove

500. Second corrosion protection layer

600. Photoresist mask

700. Bonded substrate

800. Through hole

910. A first metal layer

920. Second metal layer

930. Metal layer

Q fast etch zone

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.

In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.

It should be noted that the drawings provided in the present embodiment are only for schematically illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

As shown in fig. 3, the present embodiment provides a (111) silicon transfer process based on silicon nitride anodic bonding, comprising the following steps:

providing a (111) silicon wafer;

forming a silicon nitride layer covering the anchor points;

Specifically, the following description will be further made with reference to fig. 4 to 21.

Referring first to fig. 4, a (111) silicon wafer 100 is provided, wherein the deviation of the upper surface of the (111) silicon wafer 100 from the (111) crystal plane is preferably less than ± 1 °.

Next, the (111) silicon wafer 100 may be etched using Deep Reactive Ion Etching (DRIE) to fabricate raised anchors 101 on the (111) silicon wafer 100, such that the (111) silicon wafer 100 has a first surface 100a, sidewalls 100b and a second surface 100c, as shown in fig. 4, so as to avoid bonding of sensitive movable structures with the bonding substrate 700 through the anchors 101 during subsequent anodic bonding, so as to allow only the silicon nitride layer 200 to be bonded with the bonding substrate 700, in preparation for a high-quality bonded structure. The process of fabricating the anchor 101 is not limited thereto, and is not limited herein.

As an example, the anchor 101 has a thickness less than 2 μm, i.e., the height difference between the first surface 100a and the second surface 100c is preferably less than 2 μm, such as 1 μm, 1.5 μm, etc., which may be determined according to the process conditions, the thickness of the silicon nitride layer 200 and the thickness of the first etching protection layer 300 to be formed subsequently, and is not limited herein.

Next, referring to fig. 5, a silicon nitride layer 200 is formed, wherein the silicon nitride layer 200 covers the anchor 101.

As an example, the silicon nitride layer 200 is a low stress silicon nitride layer with tensile stress as internal stress, and the stress is less than 100MPa.

Specifically, the silicon nitride layer 200 may be formed by LPCVD, but is not limited thereto. The silicon nitride layer 200 may be a low-stress silicon nitride layer with a stress of tensile stress and a stress of less than 100MPa, such as 80MPa and 50 MPa. The thickness of the silicon nitride layer 200 may be less than 1 μm, such as 0.5 μm, and the thickness of the silicon nitride layer 200 is smaller than the thickness of the anchor point 101, so as to subsequently pass through the silicon nitride layer 200 on the anchor point 101 as a bonding layer. The silicon nitride layer 200 is formed to completely cover the anchor 101, i.e., the first surface 100a and the sidewall 100b, and extend to the second surface 100 c.

Preferably, the extension width of the silicon nitride layer 200 on the second surface 100c is at least 2 times larger than the minimum line width of photolithography, so that a bonding interface can be formed by anodic bonding of the silicon nitride layer 200 on the first surface 100a and the bonding substrate 700.

Next, referring to fig. 6, a first etching protection layer 300 is formed, wherein the first etching protection layer 300 covers the silicon nitride layer 200 and the surface of the (111) silicon wafer 100.

As an example, the first etching protection layer 300 includes a TEOS layer, an LTO layer, an SiC layer, and SiO ₂ One or a combination of layers.

Specifically, the first etching protection layer 300 may be formed by LPCVD, but is not limited thereto. The material of the first etching protection layer 300 should be able to withstand anisotropic etching solution in the subsequent process, and have good etching selectivity with the silicon nitride layer 200, that is, the anisotropic etching solution may be used to perform wet etching to remove the first etching protection layer 300 without damaging the silicon nitride layer 200. The first etching protection layer 300 may be a TEOS layer, an LTO layer, a SiC layer, or SiO layer ₂ One or a combination of layers, such as TEOS, may be used for the first etching protection layer, and the hydrofluoric acid solution may etch and remove the silicon nitride layer 200 at a very low etching rate, and the TEOS removing process may have a negligible effect on the thickness of the silicon nitride layer 200.

Next, referring to fig. 7, the first etching protection layer 300 and the (111) silicon wafer 100 are patterned to form a first trench 410, wherein the first trench 410 includes a first patterned trench 411 and a first closed release trench 412.

Specifically, the first etching protection layer 300 may be etched to the (111) silicon wafer 100 by RIE, and then the (111) silicon wafer 100 may be etched by DRIE to form the first deep trench 410. Wherein the first closed release trench 412 is in a closed pattern and surrounds the first patterned trench 411, as shown in fig. 8, so that the subsequent transfer of sensitive movable structures to the bonding substrate 700 is ensured by the closed release ring, i.e. the first patterned trench 411, in the process of anodic bonding. Wherein the direction of the first patterned trench 411 is not limited by the crystal orientation, and can be rotated to various angles.

Next, referring to fig. 9, a second etching protection layer 500 is formed, wherein the second etching protection layer 500 covers the sidewalls 410a and the bottom 410b of the first trench 410.

As an example, the second corrosion protection layer 500 includes a TEOS layer, an LTO layer, a SiC layer, and SiO ₂ One or a combination of layers.

Specifically, the second etching protection layer 500 may be formed by LPCVD or SiO by thermal oxidation ₂ Layer, but is not limited to such. The second corrosion protection layer 500 may be a TEOS layer, an LTO layer, a SiC layer, or SiO layer ₂ One or a combination of layers, etc. The thickness of the second corrosion protection layer 500 is smaller than that of the first corrosion protection layer 300, and preferably, the thickness of the first corrosion protection layer 300 is more than 2 times the thickness of the second corrosion protection layer 500. The first corrosion protection layer 300 and the second corrosion protection layer 500 may be made of the same material or different materials, and are not limited herein.

Next, referring to fig. 10, the second etching protection layer 500 at the bottom 410a of the first trench is removed and etched to form a second trench 420 based on the first trench 410.

Specifically, the RIE method may be adopted to etch the second corrosion protection layer 500 at the bottom 410a of the first trench, and since the lateral etching rate of the reactive ion etching is much smaller than the downward etching rate, the second corrosion protection layer 500 at the sidewall 410b of the first trench can be well remained in this etching. Meanwhile, since the thickness of the first corrosion protection layer 300 is greater than that of the second corrosion protection layer 500, the first corrosion protection layer 300 on the surface of the (111) silicon wafer 100 can also remain a certain thickness under the condition of controlling the RIE etching time. Next, the (111) silicon wafer 100 is etched by using deep reactive ions, the etching depth may include 5 μm to 10 μm, such as 5 μm, 8 μm, 10 μm, and the like, and since only the bottom 410a of the first trench is not protected by the second etching protection layer 500, the first trench 410 will be further etched downward to form the second trench 420 based on the first trench 410, that is, including the second structure pattern trench 421 and the second closed release trench 422, as shown in fig. 10.

Next, referring to fig. 11 and 12, the first etching protection layer 300 is patterned to expose the silicon nitride layer 200.

Specifically, front-side lithography is performed to form a photoresist mask 600, and the photoresist mask 600 has a lithography window exposing the anchor point 101, and it is necessary to ensure that the lithography window is smaller than the silicon nitride layer 200. The photoresist may be applied by spraying, but is not limited thereto. The second trench 420 is completely filled with photoresist, and the second trench sidewall 420b is preferably protected by hardening at a low temperature for a long time to prevent the photoresist from being damaged during the subsequent wet etching of the first etching protection layer 300. Next, the first etching protection layer 300 may be removed by using a selective etching method to expose the silicon nitride layer 200, and the photoresist mask 600 is removed to expose the second trench sidewall 420b and the second trench bottom 420a, as shown in fig. 12, thereby forming a sensitive movable structure.

Next, referring to fig. 13, a bonding substrate 700 is provided, and the bonding substrate 700 is anodically bonded to the silicon nitride layer 200. It is preferable that the bonded substrate 700 is a glass bonded substrate, such as a borosilicate glass bonded substrate, but the kind of the bonded substrate 700 is not limited thereto.

Next, referring to fig. 14, an anisotropic etching solution is used to perform a wet etching process to form a through hole 800 based on the second trench 420.

Specifically, the bonded device is placed in an anisotropic etching solution for wet etching, wherein the anisotropic etching solution may include a KOH solution or a TMAH solution. The anisotropic etching solution has extremely low etching speed on the (111) crystal face of the monocrystalline silicon, is only 1/100 of the (100) crystal face, and can be ignored in the actual etching process. Since the surface of the (111) silicon wafer 100 and the bottom 420a of the second trench are both (111) crystal planes, no etching is performed in the anisotropic etching solution, and part of the sidewall of the second trench 420 is protected by the second etching protection layer 500 and is not etched, only the part of the sidewall not covered by the second etching protection layer 500, i.e., the sidewall 420b of the second trench, is not (111) plane, and is not protected by the second etching protection layer 500, so that an etching fast plane is formed, the etching speed is high, etching is performed inward from the sidewall, and a fast etching region Q is formed, so that the second trench 420 is converted into a through hole 800, as shown in fig. 14. When the second structure pattern groove 421 is etched and broken from the bottom, the exposed surface becomes a reentrant corner or a mask boundary, and a slow surface appears at this time, and the etching is finally terminated at the (111) surface, so that based on the second closed release groove 422, under the action of the anisotropic etching liquid, the complete release of the sensitive movable structure can be finally realized, and the sensitive movable structure is anchored on the bonding substrate 700 through anodic bonding, therefore, the transfer process of the sensitive movable structure can be realized, and after the sensitive movable structure is released in the anisotropic etching liquid, the thickness of the sensitive movable structure can be well controlled, and the precise, consistent and controllable thickness can be realized.

Next, referring to fig. 15, the first corrosion protection layer 300 and the second corrosion protection layer 500 are removed.

Specifically, after releasing the sensitive movable structure is completed, for example, a vapor etching method may be used to remove the first corrosion protection layer 300 and the second corrosion protection layer 500, and simultaneously prevent the sensitive movable structure from being adsorbed on the bonding substrate 700 due to surface tension of the liquid, wherein the vapor etching method may use, for example, vapor hydrofluoric acid, and is specifically selected according to the materials of the first corrosion protection layer 300 and the second corrosion protection layer 500, and is not limited herein.

Further, as shown in fig. 16 to 20, in an embodiment, after exposing the silicon nitride layer 200 and before performing the bonding process, a step of forming a first metal layer 910 in the silicon nitride layer 200 and a step of forming a second metal layer 920 on the surface of the bonding substrate 700, the second metal layer 920 corresponding to the first metal layer 910, may be further included to achieve electrical connection through the first metal layer 910 and the second metal layer 920.

Specifically, as shown in fig. 12, after the silicon nitride layer 200 is front-side etched, RIE may be used to etch the silicon nitride layer 200 to the (111) silicon wafer 100 to form a wire window, and a Metal Lift-Off Technology (Metal Lift-Off Technology) is used to fabricate the first Metal layer 910, wherein the thickness of the first Metal layer 910 may be consistent with the thickness of the silicon nitride layer to keep a certain flatness of the bonding surface without affecting the anodic bonding process, as shown in fig. 16 and 17, and a method such as sputtering or evaporation may be used to fabricate the second Metal layer 920 on the bonding substrate 700, and then patterning is performed by front-side lithography, and after ion beam etching, a Metal layer in a bonding region and a Metal layer leading out a wire are used to form the second Metal layer 920, as shown in fig. 18 and 19, alignment bonding is performed to ensure that the first Metal layer 910 and the second Metal layer 920 are compressed, and the bonded device is shown in fig. 20, and the subsequent processes are not repeated here.

Further, referring to fig. 21, in another embodiment, a step of forming a metal layer 930 on the surface of the (111) silicon wafer 100 is further included, so as to make metal wire electrical connection through the metal layer 930.

Specifically, referring to fig. 21, a metal film may be formed on the front surface of the device by sputtering or evaporation, and after the front surface is subjected to photolithography, the metal film is patterned to form the metal layer 930 on the front surface of the sensitive movable structure, so as to make subsequent metal wiring electrical connection through the metal layer 930. The material of the metal layer 930 may be Al, the thickness of the metal layer 930 may be 600nm, and the patterning method may use ion beam etching or metal etching solution to perform wet etching.

In summary, the (111) silicon transfer process based on silicon nitride anodic bonding of the present invention has the following beneficial effects:

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A (111) silicon transfer process based on anodic bonding of silicon nitride, characterized in that it comprises the following steps:

providing a (111) silicon wafer;

forming a silicon nitride layer covering the anchor points;

2. The transfer process according to claim 1, characterized in that: the silicon nitride layer is a low-stress silicon nitride layer with tensile stress as internal stress, and the stress is less than 100MPa.

3. The transfer process according to claim 1, characterized in that: the thickness of the anchor point is larger than that of the silicon nitride layer; the thickness of the anchor point is less than 2 μm; the thickness of the silicon nitride layer is less than 1 μm.

4. The transfer process according to claim 1, characterized in that: the silicon nitride layer extends to the surface of the (111) silicon wafer, and the extending width is larger than 2 times of the minimum line width of photoetching.

5. The transfer process according to claim 1, characterized in that: the thickness of the first corrosion protection layer is more than 2 times of that of the second corrosion protection layer; the first corrosion protection layer comprises a TEOS layer, an LTO layer, a SiC layer and SiO ₂ One or a combination of layers; the second corrosion protection layer comprises a TEOS layer, an LTO layer, a SiC layer and SiO ₂ One or a combination of layers.

6. The transfer process according to claim 1, characterized in that: the bonded substrate comprises a glass bonded substrate.

7. The transfer process according to claim 1, characterized in that: the anisotropic etching solution comprises KOH etching solution or TMAH etching solution.

8. The transfer process according to claim 1, characterized in that: after the silicon nitride layer is exposed and before the bonding process is carried out, the method further comprises the steps of forming a first metal layer in the silicon nitride layer and forming a second metal layer which is arranged corresponding to the first metal layer on the surface of the bonding substrate, so that electric connection is realized through the first metal layer and the second metal layer.

9. The transfer process according to claim 1, characterized in that: the method further comprises the step of forming a metal layer on the surface of the (111) silicon wafer so as to perform metal lead electrical connection through the metal layer.

10. The transfer process according to claim 1, characterized in that: the method for forming the silicon nitride layer, the first corrosion protection layer and the second corrosion protection layer comprises an LPCVD method.