CN115211039A - Bus traffic reduction mechanism and related method of operation - Google Patents

Abstract

Circuits and methods for operating a receiver in a wireless communication system are disclosed. At the front end circuitry, the receiver removes the cyclic prefix, thereby separating the content or symbols associated with the cyclic prefix. The front-end circuitry sends the separated, CP-free content to the signal processing circuitry for further processing.

Description

Bus traffic reduction mechanism and related operation method

cross reference

This application claims priority to US Provisional Patent Application Serial No. 62/982,631, filed February 27, 2020, which is incorporated herein by reference in its entirety.

technical field

The present application relates to the field of communications, and more particularly, to wireless communication methods and devices.

Background technique

The rapid development of computing technology has created a greater demand for data communication. Increased demand, in turn, drives further growth in communication technologies, often requiring additional features, increased processing power, and/or increased resources within a given space. This growth often brings new challenges. For example, an increase in processing speed and/or data volume of inter-circuitry communications (eg, within a user equipment (UE)) increases the power consumption associated with the inter-data communications.

SUMMARY OF THE INVENTION

Embodiments of the present disclosure provide a wireless communication method and apparatus for performing bus traffic reduction. One or more embodiments provide a method for operating a communication device that may include front-end circuitry communicatively coupled to signal processing circuitry. The method may include: receiving a wireless signal at the communication device, wherein the wireless signal includes a content symbol and a corresponding prefix; at a front-end circuit, separating the content symbol based on removing the corresponding prefix; and transmitting the separated content symbols to the signal processing circuit without transmitting the corresponding prefix. Communicating the separated content symbol may include digitally sending a set of bits representing the content symbol to the signal processing circuit. In some embodiments, the front-end circuitry may include a radio frequency front-end (RFFE) chip, and the signal processing circuitry may include a baseband modem.

Additionally or alternatively, the method may include: down-converting the received wireless signal at the front-end circuit; at the front-end circuit, generating a baseband bitstream based on sampling the down-converted wireless signal ; wherein separating the content symbols includes removing or intercepting bits in the bit stream, wherein the removed or intercepted bits correspond to the prefix. Further, the method further comprises: receiving the separated content symbols at the signal processing circuit; and performing a Fourier transform on the separated content symbols at the signal processing circuit.

Additionally or alternatively, the method may further include: at an initial stage, sending a first set of messages from the front-end circuit to the signal processing circuit, wherein the first set of messages includes the first set of messages. a set of content symbols and corresponding plurality of prefixes; and transitioning from the initial stage to a subsequent stage based on a feedback message from the signal processing circuit, wherein the feedback message represents one associated with the plurality of prefixes or more timing details, wherein separating the content symbols and transmitting the separated content symbols may include a subsequent stage; and the separated content symbols include a second set of content symbols following the first set of content symbols . In some embodiments, the method may further include: receiving, at the signal processing circuit, the first set of messages; and, at the signal processing circuit, determining, at the signal processing circuit, a correlation with the plurality of prefixes based on the first set of messages and sending the feedback message to the front-end circuit, wherein the feedback message includes timing of symbol boundaries, set of prefix lengths, current symbol position, symbol length, or a combination thereof.

Additionally or alternatively, the method may further comprise: receiving information about symbol boundaries within the wireless signal from the signal processing circuit, wherein separating the content symbols comprises removing or masking and the symbol boundaries A group of bits that coincide and/or immediately follow the symbol boundary. The method may further include: at the front end circuit, tracking a current symbol position within a communication data unit containing the content symbol; and determining a prefix length based on the current symbol position, wherein removing or Masking the set of bits includes removing or masking the set of bits based on the determined prefix length. The method may further include determining, at the front end circuit, a symbol length based on information from the signal processing circuit, wherein the symbol length represents a duration associated with the content symbol according to a current communication setting, wherein the separation The content symbol includes reserving a set of bits corresponding to the symbol length.

One or more embodiments provide a communication device that may include a front end circuit and a signal processing circuit coupled to the front end circuit. The communication device may be configured to implement one or more aspects/features of the above methods or a combination thereof. The front-end circuit may be configured to: receive a wireless signal including a set of content symbols and a corresponding plurality of prefixes; and separate the set of content symbols based on removing or masking the corresponding plurality of prefixes. The signal processing circuit is configured to: receive the separated set of content symbols; and restore content data based on the separated set of content symbols. The front end circuit and the signal processing circuit are physically separate and electrically coupled to each other by digital connections. In some embodiments, the front-end circuit may include a radio frequency front-end (RFFE) chip; and the signal processing circuit may include a baseband chip. Additionally or alternatively, the digital connection may include a feedback path for conveying information from the signal processing circuit back to the front end circuit. The signal processing circuit may be further configured to: determine information about symbol boundaries; and send the information about symbol boundaries to the front-end circuit through a feedback path. Also, the front end circuitry may be configured to remove a set of bits based on the received information about symbol boundaries, wherein the removed set of bits corresponds to a plurality of prefixes associated with a set of content symbols.

In some implementations, the front-end circuit may include: a downconverter configured to demodulate the received wireless signal to a baseband signal; a sampling circuit coupled to the downconverter configured to sampling the baseband signal; and a prefix remover coupled to the sampling circuit configured to separate sign bits in the sampled baseband signal by removing or masking prefix bits, the sign bits corresponding to the A set of content symbols, the masked prefix bits corresponding to the prefix in the received wireless signal. Additionally or alternatively, the front end circuitry may be configured to receive the wireless signal comprising an initial set of content symbols and prefixes and a subsequent set of content symbols and prefixes, wherein the content symbols and a subsequent set of prefixes includes the separated set of content symbols; sending the initial set of content symbols and prefixes to the signal processing circuit; receiving a feedback message from the signal processing circuit, wherein based on the initial content symbols a set, deriving, at least in part, the feedback message; and separating the set of content symbols in the subsequent set of content symbols and prefixes based on removing or masking a plurality of prefixes in the subsequent set of content symbols and prefixes.

The signal processing circuitry may also be configured to: receive an initial set of content symbols and prefixes from the front end circuitry; determine information about symbol boundaries based on the received initial set of content symbols and prefixes; and send a feedback message to the a front-end circuit for removing subsequent instances of the plurality of prefixes at the front-end circuit. The signal processing circuit may also be configured to: remove prefixes from the initial set of content symbols and prefixes; and perform a Fourier transform on the remaining set of content symbols, wherein the remaining set of content symbols is derived from the content from which the prefixes have been removed an initial set of symbols and prefixes; and performing a Fourier transform directly on the subsequently received set of content symbols without performing a prefix removal process.

One or more embodiments provide a tangible, non-transitory computer-readable medium having stored thereon processor instructions that, when executed by one or more processors, cause the one or more processors to A processor performs one or more aspects/features of the above-described methods, or a combination thereof. The stored processor instructions may be configured to implement the method, the method comprising: receiving a wireless signal at the communication device, wherein the wireless signal includes a content symbol and a corresponding prefix; at the front-end circuit, based on removing the corresponding prefix, separating the content symbols; and passing the separated content symbols to the signal processing circuit without passing the corresponding prefix. Additionally or alternatively, the method and/or communication device may include one or more of the features described herein and/or various combinations thereof.

Description of drawings

In order to describe the technical solutions in the embodiments of the present disclosure more clearly, the accompanying drawings are briefly described below. The drawings illustrate only some aspects or embodiments of the present disclosure, and other drawings can be derived from these drawings by those of ordinary skill in the art without inventive effort.

1 is a schematic diagram of a wireless communication system in accordance with one or more embodiments of the present disclosure.

2 is a block diagram of a mobile communication device in accordance with one or more embodiments of the present disclosure.

3 is a detailed block diagram of a downlink processing circuit in accordance with one or more embodiments of the present disclosure.

4A is a schematic diagram of a first example message in accordance with one or more embodiments of the present disclosure.

4B is a schematic diagram of a second example message in accordance with one or more embodiments of the present disclosure.

4C is a schematic diagram of a data flow before and after processing in accordance with one or more embodiments of the present disclosure.

4D is a table illustrating an example message configuration in accordance with one or more embodiments of the present disclosure.

5 is a flowchart of an example method in accordance with one or more embodiments of the present disclosure.

FIG. 6 is a schematic block diagram of a terminal device according to one or more embodiments of the present disclosure.

7 is a schematic block diagram of a system-on-chip in accordance with one or more embodiments of the present disclosure.

8 is a schematic block diagram of a communication device according to one or more embodiments of the present disclosure.

Detailed ways

The technical solutions in one or more embodiments of the present disclosure are described below. A communication system includes interface circuits configured to reduce the amount of data transferred between adjacent circuits, for example, by reducing the amount of data between radio frequency (RF) circuits (eg, RF chips) and data processing circuits (eg, baseband chips) amount of data transferred between.

Some wireless communication protocols (eg, fourth generation (4G) Long Term Evolution (LTE) standards and/or fifth generation (5G) standards) require a cyclic prefix (CP) to precede each transmitted symbol. The CP can provide a guard interval to cancel intersymbol interference caused by previous transmissions/symbols. In other words, the CP can act as a buffer area to protect subsequent payload or data symbols. The content of the CP may be a repetition of the end-of-symbol portion. Thus, the transmitted messages (eg, content symbols and CPs) can be processed linearly. For example, a linear convolution of a frequency selective multipath channel can be modeled as a circular convolution. Furthermore, some wireless communication protocols may require different lengths of the CP depending on the position/sequence number of the corresponding/surrounding symbols within the communication unit (eg, subframe).

To process content/payload symbols, CPs are removed from transmitted or received data. In conventional systems, at the front-end circuit (eg, RF chip), the received RF signal (eg, the combination of CP and payload symbols) is down-converted and sampled to form a time-domain signal, and passed to processing circuit (eg, baseband modem/chip). Processing circuitry removes the CP or one or more portions of the RF signal, and processes the payload portion, eg, by converting the time domain signal of the remaining symbols to a frequency domain signal (eg, by a Fast Fourier Transform (FFT)).

One or more embodiments of the present disclosure may include circuits and/or processes to remove CP at the front-end circuit, thereby removing CP in digital signals or not including CP in digital signals. Accordingly, the communication system can provide reduced power consumption associated with digital communication between the front end circuitry and the processing circuitry. The amount of data removed and the reduced power consumption can correspond to the length or size of the CP, which can account for up to 25% of the overhead. Given the large number of symbols being transmitted during a communication session (eg, streaming applications and/or voice calls), the removed data can provide significant power savings.

In some embodiments, the front-end circuitry and processing circuitry may operate according to transitions between two or more stages. For example, at an initial stage, the front-end circuitry may perform down-conversion and sampling operations to generate a first set of messages including a plurality of CPs and one or more instances of corresponding payload symbols. Processing circuitry may receive and process the first set of messages to identify at least one symbol boundary (eg, separation between adjacent sets of CP-payload symbol combinations). The processing circuitry may communicate information about the symbol boundaries to the front-end circuitry as feedback during transitions between stages (eg, during a handshake process between the front-end circuitry and the processing circuitry).

For messages processed in subsequent stages, the front-end circuitry can use symbol boundaries to identify the end of each symbol segment in the time-domain signal. The front end circuitry may access a set of registers to identify the appropriate CP length, symbol length, and/or symbol position within a communication unit (eg, subframe). In some embodiments, the processing circuit may provide the CP length, symbol length, and/or symbol position to the front-end circuit during conversion. The front-end circuitry can use the symbol positions to read the appropriate CP length (eg, long CP length for the first symbol and/or middle symbol or normal CP length for other symbols). The front-end circuitry can use the read CP length to remove or mask the corresponding CP portion within the sampled signal. When the corresponding symbol (eg, without the corresponding CP) is passed to the processing circuit, the front-end circuit can update and track the symbol position.

Removing the CP at the front end circuitry rather than the processing circuitry reduces the amount of data transferred to the processing circuitry. The communication device may include a digital connection/bus between the front end circuitry and the processing circuitry. As data rates and bandwidths for wireless communications increase, so do the data rates/data volumes for internal digital communications between front-end circuits and processing circuits. By removing the CP at the front-end circuitry, the communication device can reduce the amount of data transferred internally without additional buffers. In some implementations, the front-end circuitry may adjust the bit rate of the internally transmitted data, eg, by extending the separated bits to fill the period opened by removing the CP. Furthermore, by removing the CP at the front end circuitry, the communication device can reduce the current/power consumed to transmit the CP. Furthermore, by removing the CP at the front end circuitry, the communication device can increase the throughput of the internal interface (eg, up to 25%). Using boundary information from the processing device to identify the CP position in the digital stream and keep track of the symbol/CP length and current symbol position, this provides a relatively simple and fast mechanism/circuit for implementing CP removal at the front-end circuit ( For example, a set of registers, removal/masking circuits, counters, etc.).

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presently described technology. In other implementations, the techniques described herein may be practiced without these specific details. In other instances, well-known features such as specific functions or routines have not been described in detail to avoid unnecessarily obscuring the disclosure. In this specification, references to "an embodiment," "an embodiment," etc. mean that the particular feature, structure, material, or characteristic described is included in at least one embodiment of the described technology. Thus, appearances of such phrases in this specification are not necessarily all referring to the same embodiment. On the other hand, such references are not necessarily mutually exclusive. Furthermore, the particular features, structures, materials or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that the various embodiments shown in the figures are merely illustrative representations and that the figures are not necessarily drawn to scale.

For the sake of clarity, in the following description, several details of structures or processes that are well known and commonly associated with communication systems and subsystems are not described in the following description, but which may unnecessarily obscure the disclosed technology some important aspects. Additionally, while the following disclosure sets forth several implementations of various aspects of the present disclosure, several other implementations may have different configurations or different components than those described in this section. Accordingly, the disclosed technology may have other implementations with additional elements or without several of the elements described below.

Many of the implementations or aspects of the techniques described below may take the form of computer- or processor-executable instructions, including routines executed by a programmable computer or processor. Those skilled in the art will understand that the described techniques may be implemented on computer or processor systems other than those shown and described below. The techniques described herein can be implemented in a special purpose computer or data processor that is specially programmed, configured, or constructed to execute one or more of the computer-executable instructions described below. Thus, the terms "computer" and "processor" are generally used herein to refer to any data processor. Information processed by these computers and processors may be presented on any suitable display medium, including a liquid crystal display (LCD). Instructions for performing computer-executable tasks or processor-executable tasks may be stored in or on any suitable computer-readable medium, including hardware, firmware, or a combination of hardware and firmware. combination. The instructions may be contained in any suitable memory device including, for example, a flash drive and/or other suitable media.

The terms "coupled" and "connected" as used herein, and their derivatives, may be used to describe structural relationships between components. Understandably, these terms are not synonyms for each other. Rather, in certain embodiments, "connected" may be used to indicate that two or more elements are in direct contact with each other. Unless the context clearly defines otherwise, the term "coupled" may be used to indicate that two or more elements are in contact with each other, directly or indirectly (with other intervening elements between them), or that two or more elements cooperate with each other or interact (e.g. in a causal relationship, e.g. for signaling/signaling or for function calls), or both. The term "and/or" in this specification only describes the association relationship between the associated objects, and the term indicates that there can be three kinds of relationships, for example, A and/or B can indicate the following three situations: only A exists, Both A and B exist, but only B exists. Furthermore, the character "/" in this application generally represents an "or" relationship between associated objects.

suitable environment

1 is a schematic diagram of a wireless communication system in accordance with one or more embodiments of the present disclosure. As shown in FIG. 1 , wireless communication system 100 may include network device 110 . The network device 110 may include circuitry configured to provide communication coverage for a particular geographic area. Some examples of network equipment 110 may include: Base Transceiver Station (BTS), Node B (NB), Evolved Node B (eNB or eNodeB), Next Generation Node B (gNB or gNode B), Wireless Fidelity (Wi-Fi) ) Access Point (AP). Additional examples of network devices 110 may include relay stations, access points, in-vehicle devices, wearable devices, and the like. Network devices 110 may include other wireless connectivity devices for communication networks, such as: Global System for Mobile Communications (GSM) networks, Code Division Multiple Access (CDMA) networks, Wideband CDMA (WCDMA) networks, LTE networks, cloud radio access networks (CRAN), Institute of Electrical and Electronics Engineers (IEEE) 802.11-based networks (eg, Wi-Fi networks), Internet of Things (IoT) networks, device-to-device (D2D) networks, next-generation networks (eg, 5G networks), Future Evolved Public Land Mobile Network (PLMN) etc. Alternatively, the 5G system or network may be further referred to as a New Radio (NR) system or network.

Additionally or alternatively, wireless communication system 100 may include terminal device 120 . End device 120 may be an end user device configured to facilitate wireless communication. Terminal device 120 may be configured to wirelessly connect (via, eg, wireless channel 115) to network device 110 in accordance with one or more corresponding communication protocols/standards. Terminal device 120 may be mobile or stationary. Terminal device 120 may be an access terminal, UE, subscriber unit, subscriber station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user equipment. Some examples of end devices 120 may include: cellular phones, smart phones, cordless phones, Session Initiation Protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, A computing device connected to a wireless modem or another processing device connected to a wireless modem, in-vehicle devices, wearable devices, IoT devices, end devices in future 5G networks, end devices in future evolved PLMNs, etc.

For illustrative purposes, FIG. 1 shows a wireless communication system 100 including a network device 110 and a terminal device 120 . It should be understood, however, that the wireless communication system 100 may include additional/other devices, such as additional instances of network devices 110 and/or terminal devices 120, network controllers, mobility management entities, and the like.

Wireless Communication Architecture

2 is a block diagram of a mobile communication device 200 (eg, terminal device 120 of FIG. 1 , network device 110 of FIG. 1 , and/or a portion thereof) in accordance with one or more embodiments of the present disclosure. The mobile communication device 200 may include circuitry configured to transmit line signals to another device. For example, end device 120 (eg, UE) may include mobile communication device 200 configured to exchange wireless signals with network device 110 and/or other wirelessly coupled devices.

The mobile communication device 200 may include an antenna group 212 that includes a set of transmit antennas and/or receiver antennas. Antenna group 212 may be configured to utilize one or more antennas to exchange wireless signals with corresponding devices. In some embodiments, antenna set 212 may be coupled to filter bank 214, which includes a set of frequency-based filters. For example, filter bank 214 may include a set of bandpass filters configured to separate specific frequency ranges used or targeted by the technology, standard and/or context associated with the communication session the specific frequency range.

Mobile communication device 200 may include front-end circuitry 202, such as a transceiver (eg, a radio frequency front-end (RFFE) chip) configured to process various components of a wireless signal. For example, front-end circuitry 202 may include an uplink module 222 (eg, circuitry and/or functionality) configured to mix and synthesize I/Q data from baseband into an RF signal for transmission. Also, the front-end circuitry 202 may include a downlink module 224 (eg, circuits and/or functions) configured to down-convert the input signal/received signal to a complex representation (eg, I/ Q data). As described in detail below, the I/Q data may be processed/trimmed and then forwarded to processing circuitry (eg, a baseband chip) for further processing.

Front end circuitry 202 may communicate baseband data (eg, formatted content data before/after modulation to one or more carrier frequencies) with signal processing circuitry 204 using internal connections 210. Internal connections 210 may include data connections/buses. In some embodiments, the internal connection 210 may be configured to carry digital signals. For example, downlink module 224 may send a down-converted form of the sampled digital stream of the wireless signal to signal processing circuit 204 . The portion of the internal connection 210 configured for downlink signal processing may include a feedback path for conveying information from the signal processing circuit 204 back to the front end circuit 202 . Additionally, signal processing circuitry 204 may send digital baseband data to uplink module 222 for up-conversion and digital-to-analog (D/A) conversion for wireless transmission. The signal processing circuit 204 may be implemented as a physically separate circuit (eg, a separate semiconductor chip).

Signal processing circuitry 204 (eg, a baseband modem/baseband chip) may be configured to process/analyze the baseband data relative to the transmitted/expected content. For example, the signal processing circuitry 204 may analyze the received wireless signal and remove the aspect/effect (eg, inter-symbol interference, inter-carrier interference, inter-device interference) of the wireless channel 115 of FIG. 1 from the received wireless signal , Doppler effects, multipath interference, fading, etc.) and/or noise inside a device to recover the transmitted data. For example, the received wireless signal can be represented as:

Y=HX+N Formula (1).

The received wireless signal may be denoted as 'Y' and the originally transmitted wireless signal may be denoted as 'X'. The noise introduced into the received wireless signal can be denoted as 'N'. The wireless channel 115 or its effect on the transmitted signal may be denoted 'H'. Signal processing circuit 204 may be configured to recover 'X' from 'Y'. Signal processing circuitry 204 may also include circuitry and/or functionality configured to invert transmission processing, eg, constellation mapping, interleaving, encoding, etc., to recover the intended content. For transmission, the signal processing circuit 204 may perform transmission formatting on the content data desired for transmission.

CP removal

3 is a downlink processing circuit (eg, a corresponding portion of the front-end circuit 202 of FIG. 2, eg, the downlink module 224, and/or the signal processing circuit 204 of FIG. 2, in accordance with one or more embodiments of the present disclosure ) detailed block diagram. In some implementations, downlink module 224 may include downconverter 302 and sampling circuit 304 . Downconverter 302 may be configured to demodulate received wireless signals from a carrier frequency to baseband. Sampling circuitry 304 (eg, an analog-to-digital (A/D) converter) may process the downconverted signal/baseband signal to generate a time-domain digital signal for further processing by signal processing circuitry 204 .

In some embodiments, the wireless communication system 100 of FIG. 1 (via, eg, transceiver 216 ), may generate transmission messages according to a transmission scheme (eg, an orthogonal frequency division multiplexing (OFDM) scheme). For example, transceiver 216 may map the transmitted bit sequences to corresponding symbols of the OFDM symbol alphabet. The mapped symbols can be used to generate and transmit a wireless signal ('X'), which represents a sequence of transmitted bits. The wireless communication system 100 may include a CP before each symbol or between each symbol.

Some wireless communication protocols (eg, the 4G LTE standard and/or the 5G standard) require a CP to precede each transmitted symbol. The CP may include a copy of the end portion of the symbol, which may be used to reduce or cancel inter-symbol interference and/or enable linear processing (by using, for example, a circular convolution function).

Downlink module 224 may generate a time-domain digital signal that at least initially includes symbols and digital representations of corresponding CPs. For example, the combination of down-converter 302 and sampling circuit 304 may generate a time-domain digital signal including both symbols and CP, which may be communicated to signal processing circuit 204 as first set of messages 362 during the initial phase , eg, the first set of symbols transmitted during a newly established communication session or after a rate adjustment or synchronization adjustment.

The signal processing circuitry 204 may process the first set of messages 362 using circuitry configured to: (1) process the contents of the first set of messages 362 and (2) coordinate removal of CPs for subsequent messages. For example, the signal processing circuit 204 may include a baseband (BB) boundary identifier 352 configured to identify temporal boundaries between adjacent symbols. In other words, the BB boundary identifier 352 may identify the time at which the CP preceding the corresponding symbol begins and/or the time at which the preceding/previous symbol ends. In some embodiments, the BB boundary identifier 352 may identify a boundary based on detecting a synchronization signal (eg, a primary synchronization signal (PSS) and/or a secondary synchronization signal (SSS)) in the first set of messages 362 . BB boundary identifier 352 may use signal/pattern detection circuitry and/or functionality, such as matched filters.

The signal processing circuit 204 may locally include a BB-CP remover 354 configured to remove the CP from the first set of messages 362 . Thus, the BB-CP remover 354 may separate out the symbols for subsequent processing by the downstream module 358. Downstream module 358 may reverse the transport format, eg, by interleaving, decoding, etc., and recover the content data originally targeted by the sending device.

The signal processing circuit 204 may also include a BB management module 356 configured to perform a transition from an initial stage to a subsequent stage, wherein the signal processing circuit 204 removes the CP, and in the subsequent stage, the front end circuit 202 Remove CP. The BB management module 356 may include circuitry and/or functionality configured to perform a handshake protocol with the front end circuitry 202 to effect phase transitions. For example, BB management module 356 may provide feedback message 364 to downlink module 224 via feedback path 360, feedback message 364 including boundary information (eg, start time and frequency/rate) and/or boundary signals (eg, clock signal/select signal). Additionally, the BB management module 356 may include context information/progress information for the communication in the feedback message 364 . In some embodiments, the BB management module 356 may use the feedback message 364 to provide the downlink module 224 with the sequence or position of the currently processed symbol within the surrounding communication unit (eg, subframe). The BB management module 356 may also use the feedback message 364 to provide the CP length and/or symbol length (eg, duration and/or number of samples) depending on the communication rate/settings of the session.

Downlink module 224 may include circuitry and/or functionality configured to remove CPs during subsequent stages. In some embodiments, downlink module 224 may include RF-boundary identifier 312 . The RF-boundary identifier 312 may include circuitry and/or functionality configured to identify symbol boundaries 332 at the downlink module 224 based on the feedback message 364 . In some embodiments, RF-boundary identifier 312 may include a gating circuit configured to generate an internal gating signal based on boundary information (eg, start time and frequency/rate). Alternatively or additionally, RF-boundary identifier 312 may include interface circuitry configured to receive the strobe signal in feedback message 364 as symbol boundary 332 .

Downlink module 224 may include tracking circuitry 314, which may include circuitry and/or functionality configured to read context information for CP removal. For example, downlink module 224 may include a set of registers configured to store one or more of CP length data (eg, first length 334 and/or second length 336), symbol length 338, symbol position 340 or a combination thereof. In some implementations, the registers may be programmed by the signal processing circuit 204 during phase transitions. In other embodiments, the registers may be preloaded with predetermined values, and the tracking circuit 314 may access the appropriate registers according to selected data in the feedback message 364 (eg, a representation of session settings, such as data rate).

As an illustrative example, during a phase transition, symbol counter 316 may set symbol position 340 based on feedback message 364 . Accordingly, the symbol counter 316 may update/increment the symbol position 340 using the symbol boundary 332 of the subsequent portion of the message. Tracking circuit 314 may use real-time tracked symbol positions 340 to selectively read the appropriate CP length. For example, the tracking circuit 314 may read the first length 334 (eg, a first position and/or an intermediate position) when the symbol position 340 corresponds to one or more predetermined positions (eg, a first position and/or an intermediate position) within a communication unit (eg, a subframe). , representing a long CP). Additionally, the tracking circuit 314 may read the second length 336 when the symbol positions 340 correspond to other positions. The tracking circuit 314 may further read the symbol length 338 corresponding to the communication setting.

Downlink module 224 may include RF-CP remover 318 configured to remove CP from the digitized signal at front end circuitry 202 . RF-CP remover 318 may use read/track values, such as CP length and/or symbol length 338, to identify the bits in the digitized signal that correspond to the CP. The RF-CP remover 318 may remove or mask the identified bits corresponding to the CP (eg, the overload portion). In some embodiments, RF-CP remover 318 may additionally or alternatively remove portions of the symbol that have been repeated in the CP. Thus, RF-CP remover 318 may separate out bits corresponding to symbols (eg, payload/content portions).

In some embodiments, the downlink module 224 (via, eg, the RF-CP remover 318 ), may update the timing, interval, and/or arrangement of the remaining bits. For example, downlink module 224 may combine or multiplex the separated symbol bits to increase overall data throughput. Also, the downlink module 224 may spread the separated symbol bits over time, eg, between symbol boundaries 332 and over the duration/timing corresponding to the removed CP.

The downlink module 224 may include an RF management module 320 configured to supervise and perform stage operations and transitions between stages. RF management module 320 may interact with BB management module 356 to supervise and perform phase operations/phase transitions. For example, RF management module 320 may receive feedback message 364 and initiate transitions between phases. The RF management module 320 may load input values such as symbol boundary information, symbol length 338, CP length, and/or symbol position 340 into the corresponding registers. In response to receiving the feedback message 364, the RF management module 320 may further activate the RF boundary identifier 312, the tracking circuit 314, and/or the RF-CP remover 318 to remove the CP. In some implementations, the RF management module 320 can track and control the stage status 342 . For example, the RF management module 320 may set the phase state 342 at the beginning of the communication session to represent the initial phase. The RF management module 320 may update the stage status 342 based on the transition process/handshake process to indicate subsequent stages. In some implementations, RF management module 320 may update stage status 342 based on a predetermined period of time after first receiving feedback message 364, receiving predetermined feedback content, and/or content targeted in feedback message 364. Accordingly, the downlink module 224 may transition from outputting the first set of messages 362 to outputting the second set of messages 366, which includes the separated sign bits without the CP bits.

message format

4A is a schematic diagram of a first example message (eg, a message/symbol unit in first message set 362) in accordance with one or more embodiments of the present disclosure. For example, first message set 362 may include CP 402 and content 404 . CP 402 may precede corresponding content 404 , which may include symbol portion 412 and/or repeated CP portion 414 .

4B is a schematic diagram of a second example message (eg, a message/symbol unit in the second set of messages 366) in accordance with one or more embodiments of the present disclosure. As described above, the front end circuit 202 can remove the CP 402 from incoming/received messages. Accordingly, the second set of messages 366 may separate out the symbol portion 412 (eg, a set of bits corresponding to the content/OFDM symbol) and remove the CP 402 and/or the repeated CP portion 414.

4C is a schematic diagram of a data flow before and after processing in accordance with one or more embodiments of the present disclosure. The downconverter 302 shown in FIG. 3 and/or the sampling circuit 304 shown in FIG. 3 may generate a first data stream 422 that includes a time domain bit stream representing the transmitted baseband message. The first data stream may correspond to the subsequently transmitted instance in the first set of messages 362 shown in FIG. 3 . In other words, the first data stream 422 may include the CP 402 and the content 404 of each of the first set of messages 362 . The downlink module 224 shown in FIG. 2 may transmit the first data stream 422 to the signal processing circuit 204 shown in FIG. 2 until, at the downlink module 224, the symbol boundary 332 is identified and the CP 402 is removed .

As described above, at the downlink module 224, the downlink module 224 may remove the CP 402 and/or the duplicated CP portion 414. Accordingly, the downlink module 224 may transmit a second data stream 424 comprising a time domain bit stream representing the separated content portions within the transmitted baseband message. In other words, the second data stream 424 may include subsequent transmission instances of the symbols 412 shown in FIG. 4A. The second data stream 424 may be processed according to the symbol boundary 332 . Accordingly, the second data stream 424 may be aligned in time with the symbol boundary 332 .

4D is a table 450 illustrating an example message configuration (eg, CP configuration) in accordance with one or more embodiments of the present disclosure. Table 450 may illustrate example configurations corresponding to different CP lengths and/or different subcarrier spacings (SCSs) associated with wireless communication protocols. For example, each row of table 450 may represent a unique combination of values/settings for channel bandwidth, SCS, frequency band (FR), normal CP length, and/or long CP length. Table 450 further shows the amount of resources (eg, percentage of FFT size) required to process the corresponding CP length. In some implementations, the resources (eg, overhead) required to process the CP may correspond to 7% to 25% of the overall resources. Thus, by removing the CP 402 at the downlink module 224, the signal processing circuit 200 shown in FIG. 2 can reduce a corresponding amount of processing resources/overhead.

control flow

FIG. 5 is a flowchart of an example method 500 in accordance with one or more embodiments of the present disclosure. Method 500 may be used to implement a bus traffic reduction mechanism. The method 500 may be used to operate the terminal device 120 shown in FIG. 1, the network device 110 shown in FIG. 1, the front end circuit 202 shown in FIG. 2, the signal processing circuit 204 shown in FIG. its combination.

At block 502, the front end circuit 202 may receive a wireless signal. For example, antenna group 212 may receive wireless signals ('Y') corresponding to signals ('X') transmitted by peer devices. The received wireless signal may correspond to a wireless communication session (eg, an initial portion of a wireless communication session) between the sending device and the receiving device. Accordingly, front-end circuitry 202 may receive wireless signals that include a set of content symbols and a corresponding set of prefixes. For example, the front end circuitry 202 may receive a set of content symbols and prefixes corresponding to the initial portion of the communication session.

At block 504, the front end circuitry 202 may convert the initially received wireless signal, or a portion thereof, to a baseband format. For example, the down-converter 302 shown in FIG. 3 may down-convert the received wireless signal, eg, by demodulating the wireless signal according to one or more predetermined signals/frequency. In addition, the sampling circuit 304 shown in FIG. 3 can sample the down-conversion result of the wireless signal according to a predetermined sampling rate. Accordingly, the downlink module 224 may generate a baseband bitstream (eg, a time-domain bitstream) that corresponds to downconversion and sampling of the wireless signal.

At block 506 , the front end circuitry 202 may transmit the first message set 362 of FIG. 3 (eg, the converted baseband signals) to the signal processing circuitry 204 . Front-end circuitry 202 may send first set of messages 362 resulting from the conversion to signal processing circuitry 204 . The first set of messages 362 may correspond to an initial phase of an operational and/or communication session.

At block 552, the signal processing circuit 204 may identify boundaries associated with each symbol within the baseband signal. The signal processing circuit 204 may receive the first set of messages 362 from the front end circuit 202 . Signal processing circuitry 204 may determine one or more timing details within first set of messages 362 associated with CP 402 shown in FIG. 4 . For example, as described above, the BB boundary identifier 352 shown in FIG. 3 may determine timing information based on the detection of a synchronization signal (by, eg, a signal/pattern detection circuit/function, eg, a matched filter).

At block 554, the signal processing circuit 204 may process the received baseband signal. Signal processing circuitry 204 may process first set of messages 362 to recover content data (eg, transmitted signal 'X' and/or original content data). As an illustrative example, BB-CP remover 354 shown in FIG. 3 may remove CP 402 from first message set 362 to separate content portion 404 and/or payload symbol 412). Downstream module 358 of FIG. 3 may perform a Fourier transform (eg, FFT) on the separated results (eg, content portion 404 and/or payload symbols 412).

At block 508, the communication device (eg, end device 120) may transition across phases (eg, from an initial phase to a subsequent phase). For example, front end circuitry 202 and signal processing circuitry 204 may interact with each other (eg, handshake processing) to effect conversion. As discussed above, the signal processing circuit 204 may send the feedback message 364 shown in FIG. 3 to the front end circuit 202, the feedback message 364 representing one or more timing details associated with the CP 402 (eg, timing of symbol boundaries, a group prefix length, current symbol position, symbol length, or a combination thereof). Accordingly, the front end circuit 202 may receive information about the symbol boundaries and, based on the feedback message 364, transition from the initial stage to the subsequent stage. Front-end circuitry 202 may remove CP 402 from the received wireless signal at a later stage. The signal processing circuit 404 also transitions to the subsequent stage and directly processes the subsequently received signal (eg, without removing the CP 402 at the signal processing circuit 404).

At block 510, the communication device may set an initial state associated with the phase-based operation. For example, the front-end circuit 202 may configure or set the tracking circuit 314 shown in FIG. 3 to store the first length 334 shown in FIG. 3, the second length 336 shown in FIG. 3, the symbol length 338 shown in FIG. The current symbol position shown 340 or a combination thereof. Furthermore, as described above, the front end circuitry 202 may locally determine the symbol boundaries 332 shown in FIG. 3 .

At block 514, the front end circuit 202 may convert the subsequently received wireless signal or portion of the signal. As described above at block 502, the front-end circuit 202 may receive wireless signals. As described above at block 504, the front-end circuit 202 may continue to convert wireless signals received after the above-described conversion. For example, front-end circuitry 202 may down-convert subsequently received symbols and CPs to baseband. Also, front-end circuitry 202 may sample the down-converted signal to generate a baseband bitstream (eg, a time-domain bitstream).

At block 516, the front end circuitry 202 may identify symbol boundaries of the baseband bitstream. Front end circuitry 202 may identify symbol boundaries based on, for example, strobe signals or timing signals corresponding to symbol boundaries 332 . Accordingly, front-end circuitry 202 may identify separations in the baseband bitstream to determine different symbol-CP groupings within the wireless signal. In other words, front-end circuitry 202 may identify groups of bits, each of which represents a set of content portions 404 and CPs 402 .

At decision block 518, the front end circuitry 202 may determine whether the currently processed symbol corresponds to a long CP. For example, tracking circuit 314 may determine and track symbol position 340 . The tracking circuit 314 and/or the RF-CP remover 318 shown in FIG. 3 can read the appropriate CP length based on the current symbol position 340 . In some embodiments, as represented by block 520, when the current symbol position 340 indicates one or more predetermined positions (eg, the first symbol position and/or the middle symbol position within each subframe), the tracking circuit 314 may read Take the first length 334. For other locations, the tracking circuit 314 may read the second length 336, as represented by block 522.

At block 524, the front end circuit 202 may remove the CP 402 from the subsequently received wireless signal. As an illustrative example, RF-CP remover 318 and/or tracking circuit 314 may determine symbol length 338, eg, by accessing corresponding registers. RF-CP remover 318 may remove CP 402 based on CP length and/or symbol length 338 . RF-CP remover 318 may remove or mask bits that begin for a selected one of first length 334 or second length 336 . RF-CP remover 318 may also retain and separate bits that begin at or after the end of the CP length and continue for symbol length 338, eg, the bits that make up or represent CP 402. Accordingly, RF-CP remover 318 may separate out the bits that make up or represent content portion 404 and/or payload symbol 412 .

At block 526, the front-end circuitry 202 may transmit the second set of messages 366 shown in FIG. 3 (eg, the content portion 404 shown in FIG. 4 and/or the payload detached after removal of the CP 402 shown in FIG. 4 ) symbol 412). Based on the separation of the content portion 404 and/or the payload symbol 412 from within the baseband digital bitstream, the front end circuitry 202 may generate the second set of messages 366 . Front end circuitry 202 may send a second set of messages 366 (eg, a set of bits representing the separated content symbols without corresponding CP 402) to signal processing circuitry 404. Front-end circuitry 202 may transmit to signal processing circuitry 404 via a digital bus (eg, internal bus 210 shown in FIG. 2).

At block 556 , the signal processing circuit 204 may process the second set of messages 336 . The signal processing circuit 204 may receive the second set of messages 336 (eg, separated content symbols). The signal processing circuit 204 may process the second set of messages 336 as described above at block 554 . For example, based on the separated set of content symbols, the signal processing circuit 204 may recover the content data, eg, based on performing a Fourier transform.

At block 528, the front end circuit 202 may update the symbol position (current symbol position 340). The symbol counter 316 may track the current symbol position 340 within a communication data unit (eg, a subframe) that includes content symbols that are processed and sent to the signal processing circuit 204 . For example, the symbol counter 316 may track the current symbol position 340 based on incrementing the current symbol position 340 as each symbol is processed and passed to the signal processing circuit 204 .

At decision block 558, the signal processing circuitry 204 may determine whether the processed message includes a flag or trigger to adjust the timing associated with the wireless communication signal. When the content does not indicate a timing adjustment flag or trigger, the signal processing circuit 204 may continue processing the input signal, as indicated by the feedback loop to block 556 . Furthermore, the signal processing circuit 204 may process the input signal without sending any adjustment instructions to the front end circuit 202 . Accordingly, at decision block 530 , the front end circuit 202 may determine that no timing adjustment feedback has been received from the signal processing circuit 204 . Thus, as represented by the feedback loop to block 514, the front end circuit 202 may continue to convert the received wireless signal, remove the CP 402, and send the separated symbols or content portions to the signal processing circuit 200.

When the content indicates a timing adjustment flag or trigger, as represented by block 560, the signal processing circuit 204 may notify the front end circuit 202 of the timing adjustment. Accordingly, at decision block 530, the front end circuit 202 may determine that timing adjustment feedback has been received. In response to this determination, front end circuitry 202 may perform transitions between stages to achieve the new communication rate. Additionally, after notification, the signal processing circuit 204 may further identify new symbol boundaries based on timing adjustments, as shown by the feedback loop to block 552 . Based on the updated instance of the boundary, the front end circuitry 202 and the signal processing circuitry 204 may perform transitions between stages as described above to perform adjusted timing for subsequently arriving signals.

Example Devices and Systems

FIGS. 6-8 illustrate example devices and systems that include or incorporate variable complexity detectors (eg, front-end circuit 202 shown in FIG. 2 and/or signal processing circuit 204 shown in FIG. 2 ) .

FIG. 6 is a schematic block diagram of a terminal device 600 (eg, the example of the terminal device 120 shown in FIG. 1 ) in accordance with one or more embodiments of the present disclosure. As shown in FIG. 6, terminal device 600 includes a processing unit 610 (eg, digital signal processing (DSP), central processing unit (CPU), graphics processing unit) serving as front end circuit 202, signal processing circuit 204, and/or part thereof (GPU), etc.) and memory 620. The processing unit 610 may be configured to implement instructions corresponding to the method 500 of FIG. 5 and/or other aspects of the above-described embodiments.

7 is a schematic block diagram of a system-on-chip 700 (eg, components within terminal device 120 shown in FIG. 1 and/or components within network device 110 shown in FIG. 1 ) in accordance with one or more embodiments of the present disclosure . The system-on-chip 700 in FIG. 7 includes an input interface 701, an output interface 702, a processor 703, and a memory 704 (eg, a non-transitory computer-readable medium) connectable by an internal communication link, wherein the processor 703 is configured to The code in memory 704 is executed. The memory 704 may include code corresponding to the method 500 of FIG. 5 and/or other aspects of the above-described embodiments. Accordingly, the processor 703 may perform the method 500 and/or other aspects of the above-described embodiments.

FIG. 8 is a schematic block diagram of a communication device 800 (eg, the instance of the terminal device 120 shown in FIG. 1 and/or the instance of the network device 110 shown in FIG. 1 ) in accordance with one or more embodiments of the present disclosure. Communication device 800 may include processor 810 and memory 820 . The memory 820 may store program codes, and the processor 810 may execute the program codes stored in the memory 820 . Memory 820 may include code corresponding to method 500 of FIG. 5 and/or other aspects of the above-described embodiments. Accordingly, processor 810 may implement method 500 and/or other aspects of the above-described embodiments.

Optionally, the communication device 800 may include a transceiver 830 (eg, an instance of the front end circuit 202 shown in FIG. 2 , an instance of the signal processing circuit 204 shown in FIG. 2 , and/or an instance of one or more portions thereof). Transceiver 830 may be configured (by, eg, hardware circuitry, software code from memory 820, and/or firmware) to perform method 600 and/or other aspects of the above-described embodiments.

It should be understood that the processor in embodiments of the present technology may be an integrated circuit chip and have signal processing capabilities. In the implementation process, the steps in the above methods may be implemented by using an integrated logic circuit of hardware in a processor or instructions in the form of software. The processor may be a general purpose processor, a DSP, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or another programmable logic device, a discrete gate or transistor logic device, and discrete hardware components. The methods, steps, and logic block diagrams disclosed in the embodiments of the present technology may be implemented or performed. A general-purpose processor may be a microprocessor, or the processor may alternatively be any conventional processor or the like. The steps in the methods disclosed with reference to the embodiments of the present technology may be performed or completed directly by a decoding processor implemented as hardware, or by using a combination of hardware and software modules in the decoding processor. A software module may reside at random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, or another well-established storage medium in the art. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps in the above method in combination with the hardware in the memory.

It will be appreciated that memory in embodiments of the present technology may be volatile memory or non-volatile memory, or the memory may include both volatile and non-volatile memory. The nonvolatile memory may be read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM) and is used as an external cache. For purposes of illustration and not limitation, many forms of RAM may be used, and are, for example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Synchronous Link Dynamic Random Access Memory (SLDRAM), and Direct Bus Memory Module (Rambus) Random Access Memory ( DR RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but not be limited to, these memories and any other suitable type of memory.

Feedback messages 364, RF-boundary identifiers 312, tracking circuits 314 (eg, registers), symbol counters 316, RF-CP removers 318, corresponding functions, and/or combinations thereof enable CP 402 at front-end circuit 202 actual removal. Based on the removal of the CP 402 at the front end circuit 202, the communication device can reduce the data transferred between the front end circuit 202 and the signal processing circuit 204, increase throughput between the circuits, and reduce power consumption/current consumption associated with internal communication , and/or reduce the error rate by providing longer signal transition durations.

in conclusion

The above detailed description of examples of the disclosed technology is not intended to be exhaustive or to limit the disclosed technology to the precise form disclosed above. Although specific examples of the disclosed technology are described above for illustrative purposes, various equivalent modifications are possible within the scope of the described technology, as those skilled in the relevant art will recognize. For example, although procedures or blocks are presented in a given order, alternative implementations may perform a routine of steps or use a system of blocks in a different order, and some procedures or blocks may be deleted, moved, added, reduced Divide, combine and/or modify to provide alternative embodiments or sub-combinations. Each of these processes or blocks can be implemented in a variety of different ways. Also, although processes or steps are shown as being performed in series in time, these processes or steps may instead be performed or implemented in parallel, or may be performed at different times. Furthermore, any specific numbers mentioned herein are examples only; alternative embodiments may use different values or ranges.

These and other changes can be made to the disclosed technology in light of the foregoing detailed description. While certain examples of the disclosed technology and the best mode contemplated are described in detail, no matter how detailed the above description is presented in the specification, the disclosed technology can be practiced in a variety of ways. The details of the system may vary considerably in its specific implementation while still being encompassed by the technology disclosed herein. As noted above, the use of a specific term when describing certain features or aspects of the disclosed technology should not be construed to imply that the term is hereby redefined to be limited to any specific feature of the disclosed technology to which the term is associated , feature or aspect. Accordingly, the invention is not to be limited except by the appended claims. In general, the terms used in the following claims should not be construed to limit the disclosed technology to the specific examples disclosed in the specification, unless the above Detailed Description section explicitly defines these terms.

Those of ordinary skill in the art can realize that, in conjunction with the examples described in the embodiments disclosed in this specification, the units and algorithm steps may be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may use different methods to implement the described functionality for each particular application, but such implementations should not be considered beyond the scope of this application.

While certain aspects of this invention are presented in certain claim forms below, applicants contemplate various aspects of this invention in any number of claim forms. Accordingly, applicants reserve the right to file additional claims after filing this application to file such additional claims in this or a subsequent application.

Claims (20)

1. A method for operating a communication device comprising a front-end circuit communicatively coupled to a signal processing circuit, the method comprising:

receiving a wireless signal at the communication device, wherein the wireless signal comprises a content symbol and a corresponding prefix;

at a front end circuit, separating the content symbols based on removing the corresponding prefixes; and

the separated content symbols are transmitted to the signal processing circuitry without transmitting the corresponding prefixes.

2. The method of claim 1, wherein transmitting the separated content symbols comprises: a set of bits representing the content symbol is sent over a digital connection to the signal processing circuit.

3. The method of claim 1, wherein the front-end circuit comprises a radio frequency front-end (RFFE) chip and the signal processing circuit comprises a baseband chip.

4. The method of claim 1, further comprising:

at a front-end circuit, down-converting a received wireless signal;

generating, at the front-end circuit, a baseband bitstream based on sampling the down-converted wireless signal; and is

Wherein:

separating the content symbol includes: removing or intercepting bits in the bitstream, wherein the removed or intercepted bits correspond to the prefix.

5. The method of claim 1, further comprising:

receiving the separated content symbols at the signal processing circuit; and

performing, at the signal processing circuit, a Fourier transform on the separated content symbols.

6. The method of claim 1, further comprising:

in an initial stage, sending a first set of messages from the front-end circuitry to the signal processing circuitry, wherein the first set of messages comprises a first group of content symbols and a corresponding plurality of prefixes;

transitioning from the initial stage to a subsequent stage based on a feedback message from the signal processing circuit, wherein the feedback message represents one or more timing details associated with the plurality of prefixes; and is provided with

Wherein:

separating the content symbols and transmitting the separated content symbols are performed during the subsequent phase; and

the separated content symbols include a second set of content symbols following the first set of content symbols.

7. The method of claim 6, further comprising:

receiving, at the signal processing circuit, the first set of messages;

determining, at the signal processing circuit, one or more timing details associated with the plurality of prefixes based on the first set of messages; and

transmitting the feedback message to the front-end circuitry, wherein the feedback message comprises timing of a symbol boundary, a set of prefix lengths, a current symbol position, a symbol length, or a combination thereof.

8. The method of claim 1, further comprising:

receiving information about symbol boundaries within the wireless signal from the signal processing circuitry; and is

Wherein:

separating the content symbols comprises: removing or masking a group of bits that coincide with and/or immediately follow the symbol boundary.

9. The method of claim 8, further comprising:

tracking, at the front end circuitry, a current symbol position within a communication data unit, the communication data unit containing the content symbol;

determining a prefix length based on the current symbol position; and is

Wherein:

removing or masking the set of bits includes: the set of bits is removed or masked based on the determined prefix length.

10. The method of claim 8, further comprising:

determining, at the front end circuitry, a symbol length based on information from the signal processing circuitry, wherein the symbol length represents a duration associated with the content symbol according to a current communication setting; and is

Wherein:

separating the content symbols comprises: a set of bits corresponding to the symbol length is reserved.

11. A communication device, comprising:

a front-end circuit configured to:

receiving a wireless signal comprising a set of content symbols and a corresponding plurality of prefixes;

separating the set of content symbols based on removing or masking the corresponding plurality of prefixes; and

a signal processing circuit coupled to the front-end circuit configured to:

receiving the separated content symbol set; and

and recovering the content data based on the separated content symbol set.

12. The communication device of claim 11, wherein the front-end circuitry and the signal processing circuitry are physically separate and electrically coupled to each other through a digital connection.

13. The communication device of claim 12, wherein:

the front-end circuit comprises a Radio Frequency Front End (RFFE) chip; and

the signal processing circuit comprises a baseband chip.

14. The communication device of claim 12, wherein the digital connection comprises a feedback path to convey information from the signal processing circuit back to the front-end circuit.

15. The communication device of claim 14, wherein:

the signal processing circuit is configured to:

determining information about symbol boundaries;

sending the information about the symbol boundary to a front-end circuit through a feedback path; and

the front-end circuit is configured to: removing a set of bits based on the received information about symbol boundaries, wherein the removed set of bits corresponds to a plurality of prefixes associated with a set of content symbols.

16. The communication device of claim 11, wherein the front-end circuitry comprises:

a down converter configured to demodulate the received wireless signal into a baseband signal;

a sampling circuit coupled to the down-converter configured to sample the baseband signal; and

a prefix remover coupled to the sampling circuit, configured to: separating symbol bits in the sampled baseband signal by removing or masking prefix bits, the symbol bits corresponding to the set of content symbols, the masked prefix bits corresponding to a prefix in the received wireless signal.

17. The communication device of claim 11, wherein the front-end circuitry is configured to:

receiving the wireless signal, the wireless signal comprising an initial set of content symbols and corresponding prefixes and a subsequent set of content symbols and corresponding prefixes, wherein the subsequent set of content symbols and corresponding prefixes comprises the set of separated content symbols;

sending the initial set of content symbols and corresponding prefixes to the signal processing circuitry;

receiving a feedback message from the signal processing circuitry, wherein the feedback message is derived at least in part based on the initial set of content symbols; and

separating the set of content symbols and subsequent sets of corresponding prefixes in the subsequent sets of content symbols and corresponding prefixes based on removing or masking a plurality of prefixes in the subsequent sets of content symbols and corresponding prefixes.

18. The communication device of claim 11, wherein the signal processing circuit is configured to:

receiving an initial set of content symbols and corresponding prefixes from a front-end circuit;

determining information about symbol boundaries based on the received content symbols and an initial set of corresponding prefixes; and

sending a feedback message to the front-end circuitry for removing subsequent instances of the plurality of prefixes at the front-end circuitry.

19. The communication device of claim 18, wherein the signal processing circuit is configured to:

removing the prefixes in the initial set of content symbols and corresponding prefixes;

performing a fourier transform on a set of remaining content symbols, wherein the set of remaining content symbols is from the initial set of content symbols and corresponding prefixes after removal of a prefix; and

the fourier transform is performed directly on the subsequently received set of content symbols without performing a prefix removal process.

20. A non-transitory computer-readable medium storing processor instructions that, when executed by one or more processors, cause the one or more processors to perform a method, the method comprising:

receiving a wireless signal at the communication device, wherein the wireless signal comprises a content symbol and a corresponding prefix;

at a front end circuit, separating the content symbols based on removing the corresponding prefixes; and

the separated content symbols are transmitted to the signal processing circuitry without transmitting the corresponding prefixes.

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